KR102301109B1 - Resistive random access memory and manufacturing method thereof - Google Patents

Abstract

A resistive memory device according to an embodiment of the present invention includes first and second electrodes; and a variable resistor in which a conductive path is formed by oxygen vacancy according to a voltage applied to the first and second electrodes. The variable resistor includes a metal oxide layer in which a first metal is doped with a second metal or in which the first and second metals form a solid solution, and in the metal oxide layer, the first metal is the first metal. and 5 to 15% of the sum of the second metal, and oxygen in the metal oxide layer is in the range of 1 to 2.5 times the sum of the first and second metals. According to the present invention, it is possible to improve the retention characteristics of the resistive memory cell by including the variable resistor that does not need to perform the forming operation. In addition, according to the present invention, a small size conductive path is formed in the variable resistor by controlling an overshooting current caused by the forming operation, and the read margin can be improved by reducing the off current.

Description

Resistive memory device and manufacturing method thereof

The present invention relates to a resistive memory device, and more particularly, to a resistive memory device and a method of manufacturing the same.

A resistive memory device (ReRAM) is a metal/metal oxide/metal (MIM) structure using a metal oxide. When an appropriate electrical signal is applied to the metal oxide, the metal oxide changes from a high resistance state (HRS) to a low resistance state (HRS). A variable resistance characteristic that changes to a low resistance state (LRS) or vice versa appears. Studies on the variable resistance characteristics of resistive memory devices have been conducted for a long time, and as a result, the following conducting filament model has been proposed.

Structural change may occur in the metal oxide to form a conductive path (CP) having a different resistance state from that of the original metal oxide, that is, a conductive filament. According to this model, an electrode metal material is diffused or injected into the thin film by an electrical process (generally referred to as a forming process), or a conductive filament with very high conductivity can be formed by rearrangement of the defect structure in the thin film. This conductive filament is destroyed by joule heating in the local area and is regenerated by factors such as the temperature inside the thin film, the temperature outside the thin film, applied electric field, space charge, etc. may appear.

A resistive memory device having such a variable resistance characteristic has an operation speed much faster than that of a conventional flash memory, operates at a low voltage like DRAM, and can read and write quickly like SRAM. In addition, since the resistive memory device has a relatively simple structure, defects that may occur in a process may be reduced, and manufacturing costs may be lowered. Due to these advantages, the resistive memory device is attracting attention as a memory device replacing the next-generation flash memory.

However, despite these advantages, the resistive memory device has a weakness in reproducibility because the exact switching mechanism has not been identified. In addition, there is a slight variation in operating voltage or durability between resistive memory devices. In addition, when the resistive memory device operates at low power, there is a problem in that retention characteristics are deteriorated.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described technical problem, and an object of the present invention is to provide a resistive memory device and a method of manufacturing the same that reduce deterioration of return characteristics of a memory cell even when operating at low power.

A resistive memory device according to an embodiment of the present invention includes first and second electrodes; and a variable resistor in which a conductive path is formed by oxygen vacancy according to a voltage applied to the first and second electrodes. The variable resistor includes a metal oxide layer in which a first metal is doped with a second metal or in which the first and second metals form a solid solution, and in the metal oxide layer, the first metal is the first metal. and 5 to 15% of the sum of the second metal, and oxygen in the metal oxide layer is in the range of 1 to 2.5 times the sum of the first and second metals.

In an embodiment, the oxygen affinity of the second metal is greater than that of the first metal, and the oxygen vacancy diffusion barrier of the first metal is higher than that of the second metal. The first or second metal atom may be at least one of Al, Si, Ti, Cr, Mn, Ni, Cu, Zn, Y, Zr, Nb, Hf, Ta, and W. In the case of an ALD process, a layer of a first metal oxide and a second metal oxide may be formed into a laminate structure, and in the case of a PVD or CVD process, a layer may be formed of a solid solution structure of the first metal oxide and the second metal oxide. have. The first metal may be Ti, and the second metal may be Al.

Another aspect of a resistive memory device according to an embodiment of the present invention may include: first and second electrodes; and a variable resistor in which a conductive path is formed by oxygen vacancy according to voltages applied to the first and second electrodes, wherein the variable resistor is formed by doping a first metal into a second metal or and a first material layer in which the second metal forms a solid solution; and a second material layer for storing oxygen vacancies moved from the first material layer. In the first material layer, the first metal is in the range of 5 to 15% of the sum of the first and second metals, and oxygen in the first material layer is 1 to 2.5 times the sum of the first and second metals. May be within range tomorrow.

In an embodiment, the second material layer may include a third metal, and the third metal may be selected from among Al, Si, Ti, Cr, Mn, Ni, Cu, Zn, Y, Zr, Nb, Hf, Ta, and W. There may be at least one. The resistive memory device may not perform a separate forming operation in an initial state. A first barrier layer may be included between the first electrode and the first material layer, and a second barrier layer may be included between the second electrode and the second material layer.

Another aspect of the present invention relates to a method of manufacturing a resistive memory device, comprising: forming a first electrode on a substrate; forming a variable resistor on the first electrode; and forming a second electrode on the variable resistor, wherein the forming of the variable resistor includes: forming an oxygen-deficient metal oxide layer for storing oxygen vacancies; and doping a first metal into a second metal or forming an oxygen-rich metal oxide layer in which the first and second metals form a solid solution, wherein the first oxygen-rich metal oxide layer In the first metal is in the range of 5 to 15% of the sum of the first and second metals, and oxygen in the first oxygen-rich metal oxide layer is in the range of 1 to 2.5 times the sum of the first and second metals can tomorrow

According to an embodiment of the present invention, the retention characteristic of the resistive memory cell can be improved by providing the variable resistor that does not need to perform the forming operation. In addition, according to the present invention, a small size conductive path is formed in the variable resistor by controlling an overshooting current caused by the forming operation, and the read margin can be improved by reducing the off current.

1 is a block diagram illustrating a resistive memory device according to the present invention.
2A and 2B are circuit diagrams exemplarily showing the resistive memory cell shown in FIG. 1 .
3 is a cross-sectional view exemplarily illustrating the structure of the resistive memory cell shown in FIG. 2A.
4 is a cross-sectional view illustrating the variable resistor shown in FIG. 3 by way of example.
5 is a graph exemplarily showing a current-voltage curve of the variable resistor shown in FIG. 4 .
6 is a cross-sectional view illustrating an example of a variable resistor of a resistive memory device according to an embodiment of the present invention.
7 and 8 are graphs for explaining the operation characteristics of the resistive memory device shown in FIG. 6 in comparison with the related art.
FIG. 9 is a graph illustrating voltage and 1/resistance characteristics according to time for explaining a program operation of the resistive memory device shown in FIG. 1 .
FIG. 10 is a graph illustrating voltage and 1/resistance characteristics according to time for explaining a refresh operation of the resistive memory device shown in FIG. 1 .
11 is a graph illustrating voltage and 1/resistance characteristics according to time for explaining an erase operation of the resistive memory device shown in FIG. 1 .
12 is a schematic block diagram illustrating a computing system 400 including a resistive memory device according to the present invention.

Hereinafter, embodiments of the present invention will be described clearly and in detail to the extent that those skilled in the art can easily practice the present invention.

1 is a block diagram illustrating a resistive memory device according to the present invention. Referring to FIG. 1 , the resistive memory device 100 includes a memory cell array 110 , an address decoder 120 , a bit line selection circuit 130 , a write driver 140 , a sense amplifier 150 , and a data input/output circuit ( 160 , and a control unit 170 .

The memory cell array 110 may include a plurality of memory cells connected between a plurality of word lines WL1-WLn and a plurality of bit lines BL1-BLm. Each memory cell may be formed of a material (eg, Pt/HfO2/Ta/TiN) capable of storing data using resistance change characteristics. Single-bit data or multi-bit data may be stored in these resistive memory cells. A memory cell capable of storing multi-bit data is referred to as a multi-level memory cell (MLC).

The single level cell SLC may store data 0 or 1 in one memory cell. Meanwhile, the resistive memory cell may have a plurality of intermediate states between the set state and the reset state. Such a multi-level cell (MLC) may store two or more bits of data in one memory cell. The resistive memory cell has any one of multi_states by an MLC program operation. For example, assuming that 2-bit data is stored in one memory cell, the memory cell may have four states (11, 10, 01, 00). The (1,1) state may have the highest resistance value, and the (0,0) state may have the lowest resistance value. In addition, the (1,0) and (0,1) states are first and second intermediate states, respectively, and may have first and second intermediate resistance values. The resistance value of the (1,0) state may be greater than the resistance value of the (0,1) state.

The address decoder 120 is connected to the memory cell array 110 through word lines WL1 to WLn. The address decoder 120 may decode the externally input address ADDR and provide the word line voltage Vw to the selected word line. Also, the address decoder 120 may generate a selection signal Yi for selecting the bit lines BL1 to BLm. The selection signal Yi is provided to the bit line selection circuit 130 .

The bit line selection circuit 130 is connected to the memory cell array 110 through bit lines BL1 to BLm. The bit line selection circuit 130 may select a bit line in response to the selection signal Yi provided from the address decoder 120 . The bit line selection circuit 130 may select a bit line using a plurality of NMOS transistors (not shown). Here, in response to the selection signal Yi, the NMOS transistor connects the bit line BL and the data line DL during a write operation and connects the bit line BL and the sense line SL during a read operation. can

In the example of FIG. 1 , the third word line WL3 is selected by the address decoder 120 , and the third bit line BL3 is selected by the bit line selection circuit 130 . The resistive memory device 100 may select one memory cell 111 commonly connected to the third word line WL3 and the third bit line BL3 through the address ADDR. Hereinafter, a memory cell (eg, 111 ) selected by one word line and one bit line is referred to as a selected memory cell.

The write driver 140 may receive the pulse control signals P_SET and P_RST and provide the program current I_PGM to the data line DL. The pulse control signals P_SET and P_RST may be provided from the control unit 170 . Here, the program current I_PGM is used to program the selected memory cell 111 in one of multi_states. The write driver 140 may provide one or more program currents I_PGM according to the multi-state of the selected memory cell 111 during an MLC program operation.

The sense amplifier 150 detects a difference between the voltage of the sense line SL and the reference voltage Vref during a read operation, so that data stored in the selected memory cell 111 may be read. Here, the reference voltage Vref may be provided from a reference voltage generating circuit (not shown). The sense amplifier 150 may operate in response to a control signal provided from the control unit 170 .

The data input/output circuit 160 may receive or output data from the input/output terminal DQ. The number of input/output terminals DQ may vary according to the type of the resistive memory device 100 . The data input/output circuit 160 may provide the data DI to the write driver 140 in response to the data input/output control signal CON or output the data DO provided from the sense amplifier 150 to the outside. The data input/output control signal CON may be provided from the control unit 170 .

The control unit 170 provides the pulse control signals P_SET and P_RST to the write driver 140 in response to the external control signal CTRL, and provides the data input/output control signal CON to the data input/output circuit 160 . can The control unit 170 may program the selected memory cell 111 by controlling the pulse control signals P_SET and P_RST during the MLC program operation.

2A and 2B are circuit diagrams exemplarily showing the resistive memory cell shown in FIG. 1 . 2A and 2B , the resistive memory cells 111 and 112 may include a memory element (ME) and a select element (SE).

Referring to FIG. 2A , the memory element ME of the resistive memory cell 111 is connected between the bit line BL and the selection element SE, and the selection element SE is connected between the memory element ME and the ground. Connected. The selection element SE may be formed of an NMOS transistor. A word line WL is connected to the gate of the NMOS transistor. When a predetermined voltage is applied to the word line WL, the NMOS transistor is turned on. When the NMOS transistor is turned on, the memory device ME may receive a voltage or a current through the bit line BL. In FIG. 2A , the memory element ME is connected between the bit line BL and the selection element SE. However, the selection element SE may be connected between the bit line BL and the memory element ME.

Referring to FIG. 2B , the memory element ME of the resistive memory cell 112 is connected between the bit line BL and the selection element SE, and the selection element SE is connected to the memory element ME and the word line ( ). WL) is connected between The selection element SE may be formed of a diode D. The memory element ME is connected to the anode of the diode D, and the word line WL is connected to the cathode. When the voltage difference between the anode and the cathode of the diode D becomes higher than the threshold voltage of the diode D, the diode D is turned on. When the diode D is turned on, the memory element ME may be supplied with a voltage or a current through the bit line BL.

2A and 2B , the memory element ME may include a resistive material having a variable resistance characteristic. In the memory element ME, a current flowing according to an applied voltage may form a hysteresis loop. For example, the memory element ME may be TiAlOx. The resistance of the memory element ME may be changed by the generation or disappearance of the conductive path CP. When the conductive path CP is generated, the memory element ME may be in the low resistance state LRS. Conversely, when the conductive path CP disappears, the memory element ME may be in the high resistance state HRS. The memory device ME may include a metal oxide layer in which one or more types of metal atoms are doped or two or more types of metal atoms form a solid solution. The metal atom used in the metal oxide layer may be Al, Si, Ti, Cr, Mn, Ni, Cu, Zn, Y, Zr, Nb, Hf, Ta, W, or the like.

3 is a cross-sectional view exemplarily illustrating the structure of the resistive memory cell shown in FIG. 2A. Referring to FIG. 3 , in the resistive memory cell 111 , an active region 215 may be formed by the isolation region 210 of the semiconductor substrate 205 . A source/drain 220 may be formed in the active region 215 . A gate 230 may be formed on the active region 215 between the source/drain 220 .

A current path may be formed between the source/drain 220 according to a voltage applied to the gate 230 . That is, the selection element SE that is turned on or off according to the word line voltage applied to the gate 230 may be formed. As shown in FIG. 2A , the selection device SE may be an NMOS transistor. The memory element ME may include a variable resistor 260 . The variable resistor 260 may be positioned between the first electrode 250 and the second electrode 280 used as a plating pad.

A conductive first contact 270 may exist between the second electrode 280 and the variable resistor 260 . The first electrode 250 may be connected to the source/drain 220 through the second conductive contact 240 . The first and second electrodes 250 and 280 may be formed of platinum (Pt). Between the second electrode 280 and the semiconductor substrate 205 , the gate 230 , the first and second contacts 240 and 270 , and an insulating layer 290 for insulating each of the first electrodes 250 are provided. can be formed.

4 is a cross-sectional view illustrating the variable resistor shown in FIG. 3 by way of example. Referring to FIG. 4 , the variable resistor 260 is positioned between the first electrode 250 and the second electrode 280 . The variable resistor 260 may be formed of at least one material layer. The variable resistance body 260 may have variable resistance characteristics that change into different resistance states according to voltages or currents supplied through the first and second electrodes 250 and 280 .

The resistance of the variable resistor 260 may be changed by the generation or disappearance of the internal conductive path CP. When the conductive path CP that electrically connects the first electrode 250 and the second electrode 280 is generated, the variable resistor 260 may have a low resistance state LRS. Conversely, when the conductive path CP disappears, the variable resistor 260 may have a high resistance state HRS. The variable resistor 260 may include a metal oxide layer containing a large amount of oxygen vacancy. In this case, the conductive path CP may be formed by the behavior of oxygen vacancies. However, the conductive path CP may be formed in various ways according to the type of the variable resistor 260 , a film structure, and an operating characteristic.

High-pressure hydrogen annealing (HPHA) may be performed to maximize the amount of oxygen vacancy formed in the variable resistor 260 . The variable resistor 260 may be made of a transition metal oxide. The transition metal oxide may consist of HfO ₂ , ZrO ₂ , TiO ₂ , Al ₂ O ₃ or Ta ₂ O ₅ as a stoichiometric oxide film, and AlOx, ZrOx, TiOx, NiOx, ZnOx, MnOx, WOx, It may be made of TaOx, CuOx or HfOx.

High-pressure hydrogen heat treatment (HPHA) may be performed _{for 5-120 minutes in an H 2} atmosphere of 150 to 400° C., 1 to 25 atm, preferably 200° C., in an H ₂ atmosphere of 10 atm for 30 minutes. _{For example, a first insulating layer made of SiO 2} is formed on a substrate made of Si, and a second electrode 280 made of Pt is deposited on the first insulating layer by a sputtering method. Subsequently, the variable resistor 260 may be formed by depositing _{HfO 2} on the second electrode 280 by, for example, an atomic layer deposition (ALD) method. Then, high-pressure hydrogen heat treatment (HPHA) may be performed so that the amount of oxygen vacancies formed in the variable resistor 260 is maximized.

5 is a graph exemplarily showing a current-voltage curve of the variable resistor shown in FIG. 4 . Referring to FIG. 5 , the variable resistor 260 is initially in a high resistance state (HRS), and when the voltage applied to the first electrode (refer to FIG. 3 , 250) reaches a predetermined positive voltage, the variable resistor 260 is A set operation may be performed in which the resistance state of is changed from the high resistance state HRS to the low resistance state LRS. Hereinafter, the voltage during the set operation will be referred to as a set voltage Vset.

The low-resistance state LRS of the variable resistor 260 may be maintained even when the voltage is decreased, and a reset operation may be performed to change the low-resistance state LRS from a predetermined negative voltage back to the high-resistance state HRS. Hereinafter, the voltage during the reset operation will be referred to as a reset voltage Vreset. In this way, the resistance state of the variable resistor 260 may be changed into a high resistance state HRS and a low resistance state LRS.

The variable resistor 260 has one of a low resistance state (LRS) by a set operation and a high resistance state (HRS) by a reset operation, and a set voltage Vset or a reset voltage Vreset is applied. Until then, the previous resistance state can be maintained. Accordingly, the variable resistor 260 may store different data according to the resistance state. Also, the variable resistor 260 may be used as a nonvolatile memory device that retains stored data even when power is removed.

Data stored in the variable resistor 260 may be read through the read voltage Vread. The read voltage Vread may be a voltage between the set voltage Vset and the reset voltage Vreset. During a read operation, since the resistance state of the variable resistor 260 is different according to the previous operation, different data may be read at the same read voltage Vread.

Meanwhile, the resistive memory device 100 (refer to FIG. 1 ) performs a set operation in an initial state, and the initial set operation is referred to as a forming operation. The forming voltage Vforming during the forming operation may be greater than the set voltage Vset. This is because initially generating a conductive path in the variable resistor 260, which will be described later, requires a higher voltage than subsequent operations. In the set operation and the reset operation after the forming operation, each of the set voltage Vset and the reset voltage Vreset may be maintained substantially constant. However, since the forming voltage is a high voltage, the retention characteristics of the variable resistor 260 may be deteriorated. When the resistive memory device 100 operates at low power, a high voltage forming operation may affect characteristics of the resistive memory cell.

In addition, during the forming operation, an excessive overshooting current may occur. The overshooting current may increase the size of the conductive path CP formed in the variable resistor 260 . When the size of the conductive path CP is large, the off-state current of the resistive memory device 100 increases, which may cause a problem of increasing the leakage current. In addition, since the increase in the off current means a decrease in the difference between the on current and the off current, the data read margin of the resistive memory device 100 may be narrowed.

The resistive memory device according to an embodiment of the present invention includes a variable resistor that does not need to perform a forming operation, so that retention characteristics of the resistive memory cell can be improved. In addition, the present invention can provide a resistive memory device capable of forming a small conductive path in a variable resistor by controlling an overshooting current due to a forming operation and improving a read margin by reducing an off current.

6 is a cross-sectional view illustrating an example of a variable resistor of a resistive memory device according to an embodiment of the present invention. Referring to FIG. 6 , the variable resistor 260 includes a first material layer 261 and a second material layer 262 between the first electrode 250 and the second electrode 280 . The first material layer 261 is between the first electrode 250 and the second material layer 262 , and the second material layer 262 is between the first material layer 261 and the second electrode 280 . there may be Meanwhile, the variable resistor 260 further includes a first barrier layer between the first electrode 250 and the first material layer 261 , and the second electrode 280 includes the second material layer 262 . ) may further include a second barrier layer between them. The first and second barrier layers may be formed of a material having a low dielectric constant (eg, AlOx).

The first and second electrodes 250 and 280 are for transmitting voltage or current to both ends of the first material layer 261, and various conductive materials, for example, metal such as W, Al, Ti, Pt, etc., TiN, etc. It may have a single-layer structure or a multi-layer structure including a metal nitride, or a combination thereof. The first and second electrodes 250 and 280 may be substantially the same as the electrodes of FIG. 4 described above.

The first and second material layers 261 and 262 may have a stacked double layer structure. A combination of the first and second material layers 261 and 262 or each of the first and second material layers 261 and 262 may exhibit variable resistance characteristics. For example, the second material layer 262 is an oxygen-poor metal oxide layer that stores a large amount of oxygen vacancy, and the first material layer 261 contains more oxygen than the second material layer 262 . may be an oxygen-rich metal oxide layer. The second material layer 262 may be formed of a material lacking oxygen rather than a stoichiometric ratio, such as TiOx (here, x<2), TaOy (here, y<2.5), or HfOz (here, z<2).

The first material layer 261 may have a variable resistance characteristic. The resistance of the first material layer 261 may be changed by the generation or disappearance of the conductive path CP. When a negative voltage is applied to the first electrode 250 and a positive voltage is applied to the second electrode 280 , oxygen vacancies in the second material layer 262 are injected into the first material layer 261 , so that the first material A conductive path CP by oxygen vacancies may be created in the layer 261 . Accordingly, the variable resistor 260 may be in the low resistance state LRS. Conversely, when a positive voltage is applied to the first electrode 250 and a negative voltage is applied to the second electrode 280 , oxygen vacancies move toward the second material layer 262 , so that the previously created conductive path CP is formed. can be destroyed Accordingly, the variable resistor 260 may be in the high resistance state HRS.

The first material layer 261 may be a metal oxide layer in which one or more types of metal atoms are doped or two or more types of metal atoms form a solid solution. Here, the metal atom used in the first material layer 261 may be Al, Si, Ti, Cr, Mn, Ni, Cu, Zn, Y, Zr, Nb, Hf, Ta, W, or the like. In the case of the ALD process, a layer may be formed in a laminate structure of AOx and BOx. In addition, in the case of a PVD or CVD process, the layer may be formed in a solid solution structure of AOx and BOx. The first material layer 261 may be expressed by the following chemical formula.

The first material layer 261 may be formed by doping metal A into a metal B oxide base (Box base) or forming a solid solution (Aox + Box) of metal A and metal B. Suppose the ratio of metal A is α and the ratio of metal B is β. Here, α+β. As α increases, the resistance level of the resistive memory cell tends to decrease. The first material layer 261 may be formed under the following conditions. First, in the relationship between A and B, the ratio of A can be 5 to 15%. That is, 0.05≤α≤0.15, and α/(α+β) may be 5 to 15%. Next, in the relationship between O and (A+B), the ratio of O may be 1 to 2.5 times that of (A+B). That is, γ/(α+β)=γ/1, 1≦γ≦2.5, and the ratio of O may be 1 to 2.5 times the ratio of metal A+B. Next, in the oxygen affinity, the B atom is greater than the A atom. That is, oxygen affinity may be B-atom > A-atom, and oxygen vacancy diffusion barrier may be AOx > BOx.

For example, the first material layer 261 may be formed _{of Ti α} -Al _β O _γ. Here, Ti may be 4.1, Al may be 36.6, and O may be 59.3. α, β, γ can be calculated as

α=4.1/(41.+36.6)=0.101

β=36.6/(4.1+36.6)=0.899

γ=59.3/(4.1+36.6)=1.457

From the above equation, it can be seen that 0.05≤α≤0.15 and 1≤γ≤2.5. The resistive memory device 100 including the first material layer 261 satisfying these conditions does not require a separate forming operation.

7 and 8 are graphs for explaining the operation characteristics of the resistive memory device shown in FIG. 6 in comparison with the related art. 7 is a graph for explaining a forming operation, and FIG. 8 is a graph for explaining a retention characteristic of a variable resistor. Referring to FIG. 7 , in the related art (a), a forming voltage of a higher voltage than the set voltage is required in the initial state, but in the resistive memory device of the present invention (b) expressed by Formula 1, the forming voltage is almost equal to the set voltage. Therefore, a separate forming operation is not required. Referring to FIG. 8 , it can be seen that the retention characteristic of the resistive memory cell in the resistive memory device of the present invention (b) is improved compared to that of the related art (a).

FIG. 9 is a graph illustrating voltage and 1/resistance characteristics according to time for explaining a program operation of the resistive memory device shown in FIG. 1 . Referring to FIG. 9 , a pulsed word line voltage Vw may be applied to the selection element SE during a program operation. The selection element SE is turned on, and the program voltage Vpgm of the bit line BL may be applied to the memory element ME. The word line voltage Vw is higher than the threshold voltage Vth.

At this time, the conductance (1/R) of the memory element ME or the current through the memory element ME increases while the program voltage Vpgm is applied, and then decreases slowly as the program voltage Vpgm is removed. do. The efficiency of the program operation may be increased by slowing the rate of decrease of the conductance of the memory element ME. At this time, when the conductance of the memory element ME, that is, the current through the memory element ME becomes too low, a refresh operation is required.

FIG. 10 is a graph illustrating voltage and 1/resistance characteristics according to time for explaining a refresh operation of the resistive memory device shown in FIG. 1 . Referring to FIG. 10 , when the conductance of the memory element ME is reduced to a threshold value after the program operation, the refresh operation may be performed by periodically applying the word line voltage Vw to the selection element SE. Through the periodic refresh operation, the conductance of the memory element ME, that is, the current applied to the memory element ME, is maintained above a threshold value to maintain the program state.

11 is a graph illustrating voltage and 1/resistance characteristics according to time for explaining an erase operation of the resistive memory device shown in FIG. 1 . Referring to FIG. 11 , as the pulsed word line voltage Vw is applied to the selection element SE, the program state is entered. Thereafter, in order to erase the program state, an erase voltage Ve is applied to the memory element ME. The erase voltage Ve may be a pulsed negative voltage to increase the erase speed. As the erase voltage Ve is applied, the conductance of the memory element ME, which was slowly decreased, abruptly decreases. Thereafter, the erased state is maintained.

12 is a schematic block diagram illustrating a computing system 400 including a resistive memory device according to the present invention. Referring to FIG. 12 , the computing system 400 according to the present invention includes a flash memory system 410 including a resistive memory device 411 and a memory controller 412 , and a central processing unit electrically connected to a system bus 450 . 430 , a user interface 440 , and a power supply 420 .

Data provided through the user interface 440 or processed by the central processing unit 430 is stored in the resistive memory device 411 through the memory controller 412 . The memory system 410 may be configured as a semiconductor disk device (SSD), and in this case, the booting speed of the computing system 400 will be significantly increased. Although not shown in the drawings, the computing system according to the present invention may further include an application chipset, a camera image processor (CIS), a mobile DRAM, and the like. self-evident to those who

The above are specific embodiments for carrying out the present invention. In addition to the above-described embodiments, the present invention will also include simple design changes or easily changeable embodiments. In addition, the present invention will include techniques that can be easily modified and implemented using the embodiments. Therefore, the scope of the present invention should not be limited to the above-described embodiments, but should be defined by the claims described below as well as the claims and equivalents of the present invention.

100: resistive memory device
110: memory cell array
120: address decoder
130: bit line selection circuit
140: write driver
150: sense amplifier
160: data input/output circuit
170: control unit

Claims (20)

delete delete delete delete delete delete delete A resistive memory device comprising:
first and second electrodes; and
a variable resistor in which a conductive path is formed by oxygen vacancy according to the voltage applied to the first and second electrodes;
The variable resistor is
an oxygen-rich metal oxide layer formed between the first and second electrodes and having a conductive path formed by oxygen vacancies;
an oxygen-poor metal oxide layer formed between the oxygen-rich metal oxide layer and the second electrode and configured to store oxygen vacancies moved in the oxygen-rich metal oxide layer;
a first barrier layer formed between the first electrode and the oxygen-rich metal oxide layer; and
a second barrier layer formed between the second electrode and the oxygen-deficient metal oxide layer;
An initial set voltage (hereinafter referred to as a forming voltage) applied to the first and second electrodes in order to initially create a conductive path in the variable resistor in the initial state of the resistive memory device and a set voltage after the forming voltage are constant doping the first metal into the oxide base of the second metal in the oxygen-rich metal oxide layer or forming a solid solution with the first metal and the second metal, When the ratio of the first metal increases, the resistance level of the variable resistor decreases, the second metal has a greater oxygen affinity than the first metal, and the first metal has oxygen vacancies than the second metal. A diffusion barrier (oxygen vacancy diffusion barrier) is high, the first metal is 5 to 15% of the sum of the first and second metals, and oxygen is 1 to 2.5 times the sum of the first and second metals, so that the resistivity Without performing a separate forming operation in the initial state of the memory device,
The oxygen-deficient metal oxide layer includes a third metal, and the third metal is at least one of Al, Si, Ti, Cr, Mn, Ni, Cu, Zn, Y, Zr, Nb, Hf, Ta, and W A resistive memory device, characterized in that delete 9. The method of claim 8,
The first and second metals are at least one of Al, Si, Ti, Cr, Mn, Ni, Cu, Zn, Y, Zr, Nb, Hf, Ta, and W. 9. The method of claim 8,
In the case of an ALD process, forming a layer of a first metal oxide and a second metal oxide in a laminate structure,
A resistive memory device for forming a layer with a solid solution structure of the first metal oxide and the second metal oxide in the case of a PVD or CVD process. delete delete delete delete delete delete delete delete delete

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