TWI443662B - Nonvolatile memory device - Google Patents
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Description
本發明是有關於一種電子記憶裝置,且特別是有關於適於做為非揮發性記憶裝置的半導體記憶裝置。This invention relates to an electronic memory device, and more particularly to a semiconductor memory device suitable for use as a non-volatile memory device.
電子記憶裝置是眾所周知,見於各種電子系統中。例如,在電腦和其他計算裝置中具有電子記憶裝置(有時稱為電腦記憶體)。很多可移動或獨立的電子記憶裝置例如是記憶卡或固態資料存儲系統已廣為人知。例如,在數位相機中可以使用移動記憶卡來存儲照片或以數位視訊記錄器(digital video recorder)來存儲數位錄影機(digital video recorder)所記錄的電影。Electronic memory devices are well known and found in a variety of electronic systems. For example, there are electronic memory devices (sometimes referred to as computer memory) in computers and other computing devices. Many removable or stand-alone electronic memory devices such as memory cards or solid state data storage systems are well known. For example, in a digital camera, a mobile memory card can be used to store photos or a digital video recorder to store movies recorded by a digital video recorder.
大多數電子記憶裝置可以分類為揮發性或非揮發性。一般來說,揮發性電子記憶裝置需要電力以維持所存儲的訊息。揮發性電子記憶裝置的實例如靜態隨機存取記憶體(Static Random Access Memory,SRAM)或動態隨機存取記憶體(Dynamic Random Access Memory,DRAM),這些電腦記憶裝置只在電腦開機電腦時保留所存儲的資料,並且當電腦關機或斷電時丟失所存儲的資料。相反地,一般來說非揮發性電子記憶裝置能夠在沒有外部電源情況保留所儲存的資料。非揮發性記憶體的實例例如是記憶卡,例如常用在數位相機中的記憶卡。相機可使用這種記憶卡來記錄照片,且即使將記憶卡從相機中移出仍可保留照片資料。Most electronic memory devices can be classified as volatile or non-volatile. In general, volatile electronic memory devices require power to maintain stored messages. Examples of volatile electronic memory devices are static random access memory (SRAM) or dynamic random access memory (DRAM), which are reserved only when the computer is turned on. Stored data and lose stored data when the computer is turned off or powered off. Conversely, in general, non-volatile electronic memory devices are capable of retaining stored data without external power. Examples of non-volatile memory are, for example, memory cards, such as memory cards commonly used in digital cameras. The camera can use this card to record photos and retain photo data even if you remove the card from the camera.
隨著系統中電子記憶裝置功能的增強,資料儲存容量的需求亦隨之增加。舉例來說,功能更強大的電腦和軟體通常會具有更多的隨機存取記憶體(random access memory,RAM)以使其更好操作;具有更大儲存容量記憶卡的高解析度攝影機可以提供更大的圖片和影片檔案。因此,這種趨勢使電子記憶裝置業一直設法增加記憶裝置的資料儲存容量。然而,它不是簡單地增加足夠的容量就可以達成。在資料的儲存容量增加時,通常同樣需要維持令人滿意的記憶裝置的尺寸,甚至還必須使得記憶裝置的尺寸變得更小。因此,另一種趨勢則是在一給定的尺寸下,增加資料的存儲量,也就是,增加位元密度。另一方面,需要考慮的則是成本。舉例來說,當位元密度增加時,仍必須維持或降低電子記憶裝置的成本。換言之,所期望的是能夠降低電子記憶裝置的位元成本(每一位元的成本)。此外,還需要考慮的則是相關的性能表現,例如可以更快的存取電子記憶裝置中的資料。As the functionality of electronic memory devices in the system increases, so does the need for data storage capacity. For example, more powerful computers and software usually have more random access memory (RAM) for better operation; high-resolution cameras with larger storage capacity cards can provide Larger images and video files. Therefore, this trend has led the electronic memory device industry to seek to increase the data storage capacity of memory devices. However, it can be achieved simply by adding enough capacity. As the storage capacity of the data increases, it is generally necessary to maintain a satisfactory size of the memory device, and even the size of the memory device must be made smaller. Therefore, another trend is to increase the amount of data stored at a given size, that is, to increase the bit density. On the other hand, what needs to be considered is the cost. For example, as the bit density increases, the cost of the electronic memory device must still be maintained or reduced. In other words, it is desirable to be able to reduce the bit cost of the electronic memory device (cost per bit). In addition, what needs to be considered is related performance, such as faster access to data in the electronic memory device.
增加位元密度的方法可以透過減少個別記憶胞(memory cell)的尺寸來達成。例如,隨著製造方法的改進,可形成小型結構,從而允許製造更小的記憶胞。然而,一些預測顯示,在未來使用這種方法的位元成本將會增加,這是因為在某些點上,製程成本增加的速度會比記憶胞減小速率來得快。因此,亟需尋找各種替代的方法來增加電子記憶裝置的位元密度。The method of increasing the bit density can be achieved by reducing the size of individual memory cells. For example, as the manufacturing method is improved, a small structure can be formed, thereby allowing a smaller memory cell to be fabricated. However, some predictions show that the cost of bits used in this way will increase in the future, because at some point, the cost of the process will increase faster than the memory cell. Therefore, there is an urgent need to find various alternative methods to increase the bit density of electronic memory devices.
下文描述與記憶裝置有關的記憶裝置與方法。根據本發明所揭露之一方式,記憶裝置可包括記憶胞陣列,其中每一記憶胞各自包括電晶體以及與所述電晶體串聯的電阻值切換裝置(resistance switching device)。所述電晶體與所述電阻值切換裝置可以各自有獨立地儲存一個或多個位元資料的能力。所述電晶體可以包括第一端、第二端以及閘極端,且電晶體可以經配置在各記憶狀態相關聯的多個不同啟始電壓之間切換。所述電阻值切換裝置可以與所述電晶體的所述第一與第二端的其中一個串聯。所述電阻值切換裝置可以經配置在各記憶狀態相關聯的多個不同電阻值之間切換。所述電阻值切換裝置可以包括第一記憶層、第二記憶層以及形成在所述第一記憶層與所述第二記憶層之間的介質層。Memory devices and methods related to memory devices are described below. In accordance with one aspect of the present disclosure, a memory device can include a memory cell array, wherein each memory cell includes a transistor and a resistance switching device in series with the transistor. The transistor and the resistance value switching device each have the ability to independently store one or more bit metadata. The transistor can include a first end, a second end, and a gate terminal, and the transistor can be configured to switch between a plurality of different starting voltages associated with respective memory states. The resistance value switching device may be connected in series with one of the first and second ends of the transistor. The resistance value switching device can be configured to switch between a plurality of different resistance values associated with respective memory states. The resistance value switching device may include a first memory layer, a second memory layer, and a dielectric layer formed between the first memory layer and the second memory layer.
根據本發明所揭露之另一方式,記憶裝置可以包括第一控制線、第二控制線以及與所述第一控制線和所述第二控制線通訊的記憶胞。所述記憶胞包括電晶體以及與此電晶體串連的電阻值切換裝置。所述電晶體與所述電阻值切換裝置可以各自有獨立地儲存一個或多個位元資料的能力。所述電晶體可以包括第一端、第二端以及閘極端。所述電晶體可以經配置在各記憶狀態相關聯的多個不同啟始電壓之間切換。所述電阻值切換裝置可以與所述第一控制線以及所述電晶體的所述第一端串聯。所述電阻值切換裝置可以經配置在各記憶狀態相關聯的多個不同電阻之間切換。所述電阻值切換裝置可以包括第一記憶層、第二記憶層以及形成在所述第一記憶層與所述第二記憶層之間的介質層。According to another aspect of the present disclosure, a memory device can include a first control line, a second control line, and a memory cell in communication with the first control line and the second control line. The memory cell includes a transistor and a resistance value switching device connected in series with the transistor. The transistor and the resistance value switching device each have the ability to independently store one or more bit metadata. The transistor can include a first end, a second end, and a gate terminal. The transistor can be configured to switch between a plurality of different starting voltages associated with respective memory states. The resistance value switching device may be in series with the first control line and the first end of the transistor. The resistance value switching device can be configured to switch between a plurality of different resistors associated with respective memory states. The resistance value switching device may include a first memory layer, a second memory layer, and a dielectric layer formed between the first memory layer and the second memory layer.
根據本發明所揭露之再一方式,提供讀取與寫入記憶胞之方法,用以讀取與寫入至一記憶胞,所述記憶胞包括電晶體以及與所述電晶體串聯的電阻值切換裝置,其中所述電晶體與所述電阻值切換裝置可以各自有獨立地儲存一個或多個位元資料的能力。例如,根據本發明所揭露之一方式,讀取方法可以包括偵測記憶胞的電晶體的啟使電壓,所述電晶體經配置在各記憶狀態相關聯的多個不同啟始電壓之間切換。所述讀取方法也可以包括偵測所述記憶胞的電阻值切換裝置的電阻,所述電阻值切換裝置經配置在各記憶狀態相關聯的多個不同電阻之間切換。所述電阻值切換裝置可以包括第一記憶層、第二記憶層以及形成在所述第一記憶層與所述第二記憶層之間的介質層。在下文題名為「實施方式」中,特舉這些或其他的特徵、方式以及本發明之實施例,作詳細說明如下。According to still another aspect of the present invention, a method for reading and writing a memory cell for reading and writing to a memory cell including a transistor and a resistance value in series with the transistor is provided. A switching device, wherein the transistor and the resistance value switching device each have the ability to independently store one or more bit metadata. For example, in accordance with one aspect of the present disclosure, a reading method can include detecting an enable voltage of a transistor of a memory cell, the transistor being configured to switch between a plurality of different start voltages associated with each memory state . The reading method may also include detecting a resistance of the resistance value switching device of the memory cell, the resistance value switching device being configured to switch between a plurality of different resistances associated with respective memory states. The resistance value switching device may include a first memory layer, a second memory layer, and a dielectric layer formed between the first memory layer and the second memory layer. These and other features, aspects, and embodiments of the present invention are described in detail below as the "embodiments".
圖1為根據本發明實施例所繪示的記憶裝置100之方塊圖。記憶裝置100可以包括記憶體陣列(memory array)102、行解碼器(column decoder)104、感測放大器(sense amplifier)106、列解碼器(row decoder)108、以及源極開關(source switch)110。記憶體陣列102可以包括多個記憶胞112。1 is a block diagram of a memory device 100 in accordance with an embodiment of the invention. The memory device 100 can include a memory array 102, a column decoder 104, a sense amplifier 106, a row decoder 108, and a source switch 110. . Memory array 102 can include a plurality of memory cells 112.
記憶裝置100的配置可使得記憶胞112的排列方式類似具有排列成行和列的字元線(word lines)WL0-WL4、位元線(bit lines)BL0-BL5以及源極線(source lines)SL的NOR快閃記憶體架構。記憶體陣列102的位元線BL0-BL5可以連接至感測放大器106。字元線(word lines)WL0-WL4可以連接至列解碼器108。源極線SL可以連接至源極開關110。在位址/控制線可輸送位址訊號和控制訊號,以將位址訊號和控制訊號輸入記憶裝置100,並連接至行解碼器104、感測放大器106、列解碼器108及源極開關110,並且除此之外,可以用來讀寫存取記憶體陣列102。The memory device 100 is configured such that the memory cells 112 are arranged in a manner similar to word lines WL0-WL4, bit lines BL0-BL5, and source lines SL arranged in rows and columns. The NOR flash memory architecture. Bit lines BL0-BL5 of memory array 102 can be coupled to sense amplifier 106. Word lines WL0-WL4 may be coupled to column decoder 108. The source line SL can be connected to the source switch 110. The address signal and the control signal can be transmitted to the address device and the control signal to input the address signal and the control signal into the memory device 100, and are connected to the row decoder 104, the sense amplifier 106, the column decoder 108, and the source switch 110. And in addition, it can be used to read and write access memory array 102.
行解碼器104可以透過控制和行選擇行選擇線(column select lines)的訊號(column select signal)而連接至感測放大器106。感測放大器106可配置成經由輸入/輸出(I/O)的資料線來接收給記憶體陣列102之輸入資料以及來自記憶體陣列102之輸出資料。Row decoder 104 can be coupled to sense amplifier 106 by controlling and selecting column select lines for the column select lines. The sense amplifier 106 can be configured to receive input data to the memory array 102 and output data from the memory array 102 via input/output (I/O) data lines.
圖2繪示根據本發明實施例的記憶胞112之示意圖。記憶胞112包括電晶體120和電阻值切換裝置122。2 is a schematic diagram of a memory cell 112 in accordance with an embodiment of the present invention. The memory cell 112 includes a transistor 120 and a resistance value switching device 122.
電晶體120可配置成閘極連接至字元線WLn,汲極連接至電阻值切換裝置122,以及源極連接至源極線SL。電晶體120可以是一浮動閘極、n型式電晶體、p型式電晶體或Fin-FET配置成電晶體120的啟始電壓Vt可在兩個值或更多值之間改變,其中啟始電壓Vt的某些數值與各自的記憶胞狀態有關。例如,電晶體120可以是單階記憶胞(single-level cell,SLC)浮置閘極(floating gate)電晶體、多階記憶胞(multi-level cell,MLC)浮置閘極電晶體、奈米晶體快閃(nano-crystal flash)電晶體,或氮化物捕捉裝置(nitride trap device)。The transistor 120 can be configured such that the gate is connected to the word line WLn, the drain is connected to the resistance value switching device 122, and the source is connected to the source line SL. The transistor 120 can be a floating gate, an n-type transistor, a p-type transistor, or a Fin-FET configured such that the starting voltage Vt of the transistor 120 can be varied between two or more values, wherein the starting voltage Some values of Vt are related to the state of the respective memory cells. For example, the transistor 120 can be a single-level cell (SLC) floating gate transistor, a multi-level cell (MLC) floating gate transistor, and a nano-level cell (MLC) floating gate transistor. A nano-crystal flash transistor, or a nitride trap device.
因此,電晶體120可配置成在一或多個位置存儲多個啟始電壓Vt的狀態。例如,在一些實施例中,電晶體120可配置成1位元的記憶裝置,能夠被程式化成兩種不同的啟始電壓Vt的其中之一。這些實施例可以包括電晶體120是單階記憶胞浮置閘極電晶體的實施例。在一些實施例,例如,電晶體120可經配置為2位元的記憶裝置,能夠被程式化在四種不同啟始電壓Vt的其中之一。這些實施例可以包括電晶體120是多階記憶胞浮置閘極電晶體的實施例。電晶體120的實施例包括一個浮置閘極裝置,浮置閘極裝置可以利用熱電子注入來進行程式化以及利用Fowler-Nordheim(FN)電子穿隧(electron tunneling)來進行抹除。Thus, the transistor 120 can be configured to store a plurality of states of the starting voltage Vt at one or more locations. For example, in some embodiments, the transistor 120 can be configured as a 1-bit memory device that can be programmed into one of two different starting voltages Vt. These embodiments may include embodiments in which the transistor 120 is a single-stage memory cell floating gate transistor. In some embodiments, for example, the transistor 120 can be configured as a 2-bit memory device that can be programmed into one of four different starting voltages Vt. These embodiments may include embodiments in which the transistor 120 is a multi-level memory cell floating gate transistor. Embodiments of the transistor 120 include a floating gate device that can be programmed using hot electron injection and Fowler-Nordheim (FN) electron tunneling for erasing.
電阻值切換裝置122可以連接在位線BLn和電晶體120的汲極之間。電阻值切換裝置122可配置成電阻值切換裝置122的電阻在多個電阻值之間改變,其中某些電阻值與各自的記憶胞狀態有關。例如,電阻值切換裝置122可以例如是Lee等人在美國專利第7524722號所描述的電阻式記憶裝置,在此一併納入參考。The resistance value switching device 122 may be connected between the bit line BLn and the drain of the transistor 120. The resistance value switching device 122 can be configured such that the resistance of the resistance value switching device 122 varies between a plurality of resistance values, some of which are related to respective memory cell states. For example, the resistance value switching device 122 can be, for example, a resistive memory device as described in U.S. Patent No. 7,524, 722, the disclosure of which is incorporated herein by reference.
因此,在一些實施例,記憶胞112可配置成存儲一個或多個位元。例如,在一些實施例,電晶體120可配置成在兩種記憶狀態之間切換,且電阻值切換裝置122可配置成在兩種記憶狀態之間切換,使得記憶胞112是2位元的記憶裝置,能夠總共有4種記憶狀態。Thus, in some embodiments, memory cell 112 can be configured to store one or more bits. For example, in some embodiments, the transistor 120 can be configured to switch between two memory states, and the resistance value switching device 122 can be configured to switch between two memory states such that the memory cell 112 is a 2-bit memory. The device can have a total of four memory states.
圖33繪示一實施例之I-V曲線,其中電晶體120可配置為在與各自啟始電壓Vt1 -Vt4 相關的4(2^2)種記憶狀態之間切換。電阻值切換裝置122可配置為在與各自電阻值R1-R4相關的4(2^2)種記憶胞狀態之間的切換。因此,電晶體120能夠儲存兩個位元資料。總共,本實施例的電晶體120與電阻值切換裝置122提供記憶胞112能有總共2^(2+2)=16種記憶胞狀態的能力,因此提供4位元的記憶胞112。33 depicts an IV curve of an embodiment in which the transistor 120 is configurable to switch between 4 (2^2) memory states associated with respective start voltages Vt1 - Vt4 . The resistance value switching device 122 can be configured to switch between 4 (2^2) memory cell states associated with respective resistance values R1-R4. Thus, the transistor 120 is capable of storing two bits of data. In total, the transistor 120 of the present embodiment and the resistance value switching device 122 provide the ability of the memory cell 112 to have a total of 2^(2+2)=16 memory cell states, thus providing a 4-bit memory cell 112.
圖34繪示一實施例之I-V曲線,其中電晶體120可以是多階胞而經配置為與各自啟始電壓相關的16(2^4)種記憶狀態之間切換。啟始電壓包括每一階四個啟始電壓(VtL1 -VtL4 )。電阻值切換裝置122可配置為在與各自電阻值R1-R4相關的4(2^2)種記憶胞狀態之間的切換。因此,電晶體120能夠儲存四個位元資料且電阻值切換裝置122能夠儲存兩個位元資料。總共,本實施例的電晶體120與電阻值切換裝置122提供記憶胞112能有總共2^(4+2)=64種記憶胞狀態的能力,因此提供6位元的記憶胞112。二者擇一地,電阻值切換裝置122可以經配置為8(2^3)種記憶狀態之間切換。上述的實施例,電晶體120與電阻值切換裝置122提供記憶胞112能有總共2^(4+3)=128種記憶胞狀態的能力,因此提供7位元的記憶胞112。Figure 34 depicts an IV curve of an embodiment in which the transistor 120 can be multi-ordered and configured to switch between 16 (2^4) memory states associated with respective start voltages. The starting voltage includes four starting voltages (V tL1 - V tL4 ) for each step. The resistance value switching device 122 can be configured to switch between 4 (2^2) memory cell states associated with respective resistance values R1-R4. Therefore, the transistor 120 can store four bit data and the resistance value switching device 122 can store two bit data. In total, the transistor 120 of the present embodiment and the resistance value switching device 122 provide the ability of the memory cell 112 to have a total of 2^(4+2)=64 memory cell states, thus providing a 6-bit memory cell 112. Alternatively, the resistance value switching device 122 can be configured to switch between 8 (2^3) memory states. In the above embodiment, the transistor 120 and the resistance value switching device 122 provide the ability of the memory cell 112 to have a total of 2^(4+3)=128 memory cell states, thus providing a 7-bit memory cell 112.
進一步實施例可以包括一個電晶體120經配置在一組選定的編號N1啟始電壓與各自的記憶狀態之間進行切換,電阻值切換裝置122經配置在一組選定的編號N2電阻與各自的記憶狀態之間切換,使記憶胞112因而配置成具有一個總數N1+N2的記憶狀態。Further embodiments may include a transistor 120 configured to switch between a set of selected number N1 start voltages and respective memory states, the resistance value switching device 122 being configured in a set of selected number N2 resistors and respective memories The states are switched such that the memory cells 112 are thus configured to have a memory state of a total number N1 + N2.
圖3A繪示電阻值切換裝置122a示意圖,圖3A根據的是電阻值切換裝置122的一些實施例。電阻值切換裝置122a包括基板130、內金屬介電層(intermetal dielectric,IMD)層132,第一電極層134、氧化鎢層136、第一介電層138、第二介電層140和第二電極層142。3A is a schematic diagram of a resistance value switching device 122a, and FIG. 3A is based on some embodiments of a resistance value switching device 122. The resistance value switching device 122a includes a substrate 130, an intermetal dielectric (IMD) layer 132, a first electrode layer 134, a tungsten oxide layer 136, a first dielectric layer 138, a second dielectric layer 140, and a second Electrode layer 142.
基板130可以是矽基板132,並且內金屬介電層132可以是由已知方法,例如透過化學氣相沉積(chemical vapor deposition,CVD)形成在基板130上的氧化層或其他電性絕緣層(electrically-insulating layer)。The substrate 130 may be a germanium substrate 132, and the inner metal dielectric layer 132 may be an oxide layer or other electrically insulating layer formed on the substrate 130 by a known method, such as by chemical vapor deposition (CVD). Electrical-insulating layer).
第一電極134可以由氮化鈦(titanium nitride,TiN)形成,並由CVD或物理氣相沉積(physical vapor deposition,PVD)沈積在IMD層132上。另外,第一電極134的材料可包括摻雜多晶矽(doped polysilicon)、鋁(aluminum)、銅(copper)或氮化鉭(tantalum nitride,TaN)。The first electrode 134 may be formed of titanium nitride (TiN) and deposited on the IMD layer 132 by CVD or physical vapor deposition (PVD). In addition, the material of the first electrode 134 may include doped polysilicon, aluminum, copper, or tantalum nitride (TaN).
氧化鎢層136形成在第一電極134的上方。第一介電層138和第二介電層140位在氧化鎢層136的側面且形成在第一電極134上。介電層138和140可以包含,例如,二氧化矽(SiO2 )、氮化矽(Si3 N4 )或類似的絕緣材料。氧化鎢層136、第一介電層138和第二介電層140所組成的結構的形成方法,可以先在第一電極的上方形成用來做為介電層138和140的連續介電層,其形成的方法例如是化學氣相沉積法。接著,將一部分的連續介質層移除,例如是透過微影和蝕刻,從而在第一介電層138和第二介電層140之間形成間隙(gap)。接下來,可以在第一介電層138和第二介電層140之間的間隙之中形成氧化鎢層(tungsten oxide layer)136。更具體地說,氧化鎢層136的形成方法可以先在第一介電層138和第二介電層140之間的間隙沈積鎢,然後進行氧化製程,使鎢被氧化。例如,可以使用熱氧化方法使得氧擴散到大多數或所有的鎢層,從而造成氧化鎢層136的形成。A tungsten oxide layer 136 is formed over the first electrode 134. The first dielectric layer 138 and the second dielectric layer 140 are located on the side of the tungsten oxide layer 136 and are formed on the first electrode 134. Dielectric layers 138 and 140 may comprise, for example, hafnium oxide (SiO 2 ), tantalum nitride (Si 3 N 4 ) or similar insulating materials. The structure of the tungsten oxide layer 136, the first dielectric layer 138 and the second dielectric layer 140 may be formed by forming a continuous dielectric layer as the dielectric layers 138 and 140 over the first electrode. The method of forming it is, for example, a chemical vapor deposition method. Next, a portion of the continuum dielectric layer is removed, such as by lithography and etching, to form a gap between the first dielectric layer 138 and the second dielectric layer 140. Next, a tungsten oxide layer 136 may be formed in the gap between the first dielectric layer 138 and the second dielectric layer 140. More specifically, the tungsten oxide layer 136 may be formed by depositing tungsten in a gap between the first dielectric layer 138 and the second dielectric layer 140, and then performing an oxidation process to oxidize the tungsten. For example, a thermal oxidation process can be used to diffuse oxygen to most or all of the tungsten layer, resulting in the formation of a tungsten oxide layer 136.
第二電極142可以是氮化鈦(titanium nitride,TiN),可以CVD或PVD法沈積在氧化鎢層136上。同樣地第二電極142可延伸到介電層138和140的上方。第二電極142的材料可選擇性包括摻雜多晶矽、鋁、銅或氮化鉭(TaN)。The second electrode 142 may be titanium nitride (TiN) deposited on the tungsten oxide layer 136 by CVD or PVD. Likewise, the second electrode 142 can extend over the dielectric layers 138 and 140. The material of the second electrode 142 may optionally include doped polysilicon, aluminum, copper or tantalum nitride (TaN).
氧化鎢層136的全部氧化可形成具有可調電阻的第一界面區144和第二界面區146。圖3B繪示第一界面區144和第二界面區146的位置。第一界面區144包括在第一電極134和氧化鎢層136界面的區域。第二界面區146包括在第二電極142和氧化鎢層136界面的區域。The total oxidation of the tungsten oxide layer 136 can form a first interface region 144 and a second interface region 146 having an adjustable resistance. FIG. 3B illustrates the locations of the first interface region 144 and the second interface region 146. The first interface region 144 includes a region at the interface of the first electrode 134 and the tungsten oxide layer 136. The second interface region 146 includes a region at the interface of the second electrode 142 and the tungsten oxide layer 136.
圖4A至圖4E繪示電阻值切換裝置122a的對稱雙態實施例的電阻切換特性。也就是說,在本實施例中,電阻值切換裝置122a包括兩界面區144和146,每一界面區有兩種電阻值(記憶胞狀態),每一界面區至少與另一界面區實質上對稱。在另一實施例中,其包括此處所述的,可以包括未對稱之實施例和/或(and/or)包括每一界面區有兩種以上的電阻值者。4A-4E illustrate the resistance switching characteristics of the symmetric two-state embodiment of the resistance value switching device 122a. That is, in the present embodiment, the resistance value switching device 122a includes two interface regions 144 and 146, each of which has two resistance values (memory cell state), and each interface region is substantially at least substantially different from the other interface region. symmetry. In another embodiment, which includes the embodiments described herein, may include unsymmetric embodiments and/or include more than two resistance values per interface region.
第一電極134和第二電極142兩者之間的電阻可以透過氧化鎢層136而在兩電阻值R1和R2之間調整。電阻值切換裝置122a的電阻值切換行為可以發生在第一界面區144或第二界面區146。如後述參考圖4A至圖4E之詳細記載,電壓脈衝可用於在第一界面區144或第二界面區146兩者間做選擇,以做為以控制電阻值切換裝置122a的切換行為的界面區。這一點很重要,因為將電阻值從R1切換到R2(反之亦然)所需要的電壓,是取決於第一界面區144或第二界面區146是否為目前正在控制電阻值切換裝置122a的切換行為。The electrical resistance between the first electrode 134 and the second electrode 142 can be adjusted between the two resistance values R1 and R2 through the tungsten oxide layer 136. The resistance value switching behavior of the resistance value switching device 122a may occur in the first interface region 144 or the second interface region 146. As described in detail later with reference to FIGS. 4A through 4E, the voltage pulse can be used to select between the first interface region 144 or the second interface region 146 as an interface region for controlling the switching behavior of the resistance value switching device 122a. . This is important because the voltage required to switch the resistance value from R1 to R2 (and vice versa) depends on whether the first interface region 144 or the second interface region 146 is currently switching the resistance value switching device 122a. behavior.
圖4A至圖4E繪示電阻值切換裝置122a的對稱雙狀態實施例的電阻值切換特性。也就是說,在目前的實施例,電阻值切換裝置122a包括兩個界面區144和146,每一界面區有兩種電阻值(記憶狀態),每一界面區至少大致上對稱其他界面區。另一實施例,包括在此所描述者,可以包括非對稱和/或每一界面區包括兩種以上電阻值的實施例。4A to 4E illustrate resistance value switching characteristics of a symmetric two-state embodiment of the resistance value switching device 122a. That is, in the present embodiment, the resistance value switching device 122a includes two interface regions 144 and 146, each of which has two resistance values (memory states), each interface region being at least substantially symmetric with respect to other interface regions. Another embodiment, including those described herein, can include embodiments that are asymmetric and/or that each interface region includes more than two resistance values.
第一電極134和第二電極142兩者之間的電阻可透過氧化鎢層136而調整在兩電阻值R1和R2之間。電阻值切換裝置122a的電阻值切換行為可以發生在第一界面區144或第二界面區146。如後述參考圖4A至圖4E之詳細記載,電壓脈衝可用於在第一界面區144或第二界面區146兩者間做選擇,以做為以控制電阻值切換裝置122a的切換行為的界面區。這一點很重要,因為將電阻值從R1切換到R2(反之亦然)所需要的電壓,是取決於第一界面區144或第二界面區146是否為目前正在控制電阻值切換裝置122a的切換行為。The electrical resistance between the first electrode 134 and the second electrode 142 is adjustable between the two resistance values R1 and R2 through the tungsten oxide layer 136. The resistance value switching behavior of the resistance value switching device 122a may occur in the first interface region 144 or the second interface region 146. As described in detail later with reference to FIGS. 4A through 4E, the voltage pulse can be used to select between the first interface region 144 or the second interface region 146 as an interface region for controlling the switching behavior of the resistance value switching device 122a. . This is important because the voltage required to switch the resistance value from R1 to R2 (and vice versa) depends on whether the first interface region 144 or the second interface region 146 is currently switching the resistance value switching device 122a. behavior.
首先參閱圖4A,該圖繪示當第二界面區146在控制電阻值切換特性時,本實施例電阻值切換裝置122a的電阻值切換特性。在這裡,電阻值切換裝置122a可以被控制成具有重置電阻值(reset resistance)R1或者設定電阻值(set resistance)R2。如電阻值切換裝置122a的電阻值是R1,利用跨越電阻值切換裝置122a施加負電壓V2,如圖3B所示在電壓供應端和接地之間,電阻值可從R1降低到R2。同樣,若電阻值切換裝置122a的電阻值是R2,利用跨越電阻值切換裝置122a施加正電壓V4,電阻值可從R2增加到R1。Referring first to FIG. 4A, the figure shows the resistance value switching characteristic of the resistance value switching device 122a of the present embodiment when the second interface region 146 controls the resistance value switching characteristic. Here, the resistance value switching device 122a may be controlled to have a reset resistance value R1 or a set resistance value R2. If the resistance value of the resistance value switching device 122a is R1, the negative voltage V2 is applied across the resistance value switching device 122a, and the resistance value can be lowered from R1 to R2 between the voltage supply terminal and the ground as shown in FIG. 3B. Similarly, if the resistance value of the resistance value switching device 122a is R2, the positive voltage V4 is applied across the resistance value switching device 122a, and the resistance value can be increased from R2 to R1.
圖4B繪示從第二界面區146切換控制至第一界面區144的程序。具體來說,藉由跨越電阻值切換裝置122a施加負電壓V1,本實施例電阻值切換裝置122a的電阻值切換特性的控制可以從第二界面區146切換至第一界面區144。FIG. 4B illustrates a procedure for switching control from the second interface region 146 to the first interface region 144. Specifically, by applying the negative voltage V1 across the resistance value switching device 122a, the control of the resistance value switching characteristic of the resistance value switching device 122a of the present embodiment can be switched from the second interface region 146 to the first interface region 144.
在圖4B的切換結果如圖4C所示,其中第一界面區146現在正在控制本實施例電阻值切換裝置122a的電阻值切換特性。為了觀察當第一界面區144正在控制時本實施例電阻值切換裝置122a的電阻值切換特性以及當第二界面區146正在控制時本實施例電阻值切換裝置122a的電值阻切換特性兩者之間的差異性,可以將圖4C所示行為與圖4A做比較。現在參閱圖4C,以第一界面區144進行控制,利用跨越電阻值切換裝置122a施加正電壓V3,電阻值可從R1降低到R2,而且藉由跨過電阻值切換裝置122a施加負電壓V1,電阻值可從R2增加到R2。The result of the switching in Fig. 4B is as shown in Fig. 4C, in which the first interface region 146 is now controlling the resistance value switching characteristic of the resistance value switching device 122a of the present embodiment. In order to observe the resistance value switching characteristic of the resistance value switching device 122a of the present embodiment when the first interface region 144 is being controlled and the electrical value resistance switching characteristic of the resistance value switching device 122a of the present embodiment when the second interface region 146 is being controlled The difference between the behavior shown in Figure 4C can be compared to Figure 4A. Referring now to FIG. 4C, control is performed with the first interface region 144, by applying a positive voltage V3 across the resistance value switching device 122a, the resistance value can be lowered from R1 to R2, and by applying a negative voltage V1 across the resistance value switching device 122a, The resistance value can be increased from R2 to R2.
圖4D繪示從第一界面區144切換控制至第二界面區146的流程。具體來說,利用跨越電阻值切換裝置122a施加正電壓V4,本實施例電阻值切換裝置122a的電阻值切換特性的控制可以從第一界面區144切換至第二界面區146。具體來說,利用跨越電阻值切換裝置122a施加正電壓V4,電阻值切換裝置122a之本實施例的電阻值切換特性之控制可以從第一界面區144切換至第二界面區146。FIG. 4D illustrates a flow of switching control from the first interface region 144 to the second interface region 146. Specifically, by applying the positive voltage V4 across the resistance value switching device 122a, the control of the resistance value switching characteristic of the resistance value switching device 122a of the present embodiment can be switched from the first interface region 144 to the second interface region 146. Specifically, by applying the positive voltage V4 across the resistance value switching device 122a, the control of the resistance value switching characteristic of the present embodiment of the resistance value switching device 122a can be switched from the first interface region 144 to the second interface region 146.
在圖4D的切換結果如圖4E所示,與圖4A相同,其中第二界面區146再次控制著本實施例電阻值切換裝置122a的電阻值切換特性。The switching result in Fig. 4D is the same as Fig. 4A, as shown in Fig. 4E, in which the second interface region 146 again controls the resistance value switching characteristic of the resistance value switching device 122a of the present embodiment.
因此,電阻值切換裝置122a可以設定為四種狀態的任何一種,可以做為四種記憶狀態:(1)第一界面控制和電阻值=R1(“R RESET ”狀態);(2)第一界面控制和電阻值=R2(“R SET ”狀態);(3)第二界面控制和電阻值=R1(“RRESET ”狀態);(4)第二界面控制和電阻值=R2(“RSET ”狀態)。R SET 與RSET 之間的狀態很難區分。但是,R RESET 和RRESET 的狀態能夠可靠地互相區分。此外,R RESET 和RRESET 的各狀態能夠可靠地區別於R SET 和RSET 的狀態。因此,根據本實施例,電阻值切換裝置122a可以配置成做為三狀態記憶裝置,其具有如下狀態:(1)R RESET ;(2)RRESET ;(3)R SET 或RSET 。Therefore, the resistance value switching means 122a can be set to any of four states, and can be used as four memory states: (1) the first interface control and the resistance value = R1 (" R RESET "state); (2) the first Interface control and resistance = R2 (" R SET "status); (3) Second interface control and resistance = R1 ("R RESET "status); (4) Second interface control and resistance = R2 ("R SET "state". The state between R SET and R SET is difficult to distinguish. However, the states of R RESET and R RESET can be reliably distinguished from each other. In addition, the states of R RESET and R RESET can be reliably distinguished from the states of R SET and R SET . Therefore, according to the present embodiment, the resistance value switching device 122a can be configured as a three-state memory device having the following states: (1) R RESET ; (2) R RESET ; (3) R SET or R SET .
參考圖5和圖6,根據三狀態記憶裝置之實施例,描述讀取電阻值切換裝置122a的程序。圖5繪示電阻值切換裝置122a的記憶狀態與施加電壓之間的圖形關係,且圖6繪示讀取程序的流程圖。Referring to Figures 5 and 6, the procedure for reading the resistance value switching device 122a will be described in accordance with an embodiment of a three-state memory device. FIG. 5 is a graphical representation of the relationship between the memory state of the resistance value switching device 122a and the applied voltage, and FIG. 6 is a flow chart of the reading process.
首先,在方塊200,電阻值切換裝置122a已經程式化成記憶胞狀態(1)R RESET 、(2)RRESET 、(3)R SET 或RSET 之其中一種。此程序的其餘部分將允許讀取電阻值切換裝置122a,以決定哪個記憶狀態被寫入電阻值切換裝置122a。在方塊202,決定電阻值切換裝置122a的電阻值。如圖5所示,不管第一界面區144和第二界面區146的哪一個在進行控制,電阻值可以預期為較高的電阻值R RESET /RRESET 或較低電阻值R SET /RSET 。若偵測到較低電阻值R SET /RSET ,此程序結束於方塊204,並決定電阻值切換裝置122a的記憶狀態為R SET /RSET 。反之,若偵測到較高電阻值R RESET /RRESET ,此程序繼續進行,以便區分R RESET 記憶狀態和RRESET 記憶狀態。First, at block 200, the resistance value switching device 122a has been programmed into one of the memory cell states (1) R RESET , ( 2 ) R RESET , ( 3 ) R SET or R SET . The remainder of this routine will allow reading of the resistance value switching device 122a to determine which memory state is written to the resistance value switching device 122a. At block 202, the resistance value of the resistance value switching device 122a is determined. As shown in FIG. 5, regardless of which of the first interface region 144 and the second interface region 146 is being controlled, the resistance value can be expected to be a higher resistance value R RESET /R RESET or a lower resistance value R SET /R SET . If a lower resistance value R SET /R SET is detected, the process ends at block 204 and determines that the memory state of the resistance value switching device 122a is R SET /R SET . Conversely, if a higher resistance value R RESET /R RESET is detected, the program continues to distinguish between the R RESET memory state and the R RESET memory state.
利用確定第一界面區144和第二界面區146的哪一個正在進行控制,記憶狀態R RESET 可與RRESET 記憶狀態區分。如圖6所示的程序,這是利用施加電壓VDETERMINE 來實現,為此電阻值切換裝置的行為將有所不同,其取決於第一界面區144和第二界面區146中的哪一個在進行控制。可以做為VDETERMINE 之電壓位準的例子為如圖5所示。在此,電壓位準VDETERMINE 是如圖4A至圖4E所示之電壓位準V3和V4之間的電壓位準。再參考方塊206可知道電阻值位準很高(例如,圖4A至圖4E中的R1),可以理解電阻值切換裝置122a的行為不同於跨越電阻值切換裝置122a施加電壓VDETERMINE 的情形,其取決於第一界面區144和第二界面區146哪一個正在進行控制。例如,根據圖4A若第二界面區146在進行控制,電壓VDETERMINE 的施加不會改變電阻值切換裝置122a的電阻值,而偏離電阻值R1。另一方面,根據圖4D,若第一界面區144在進行控制,電壓VDETERMINE 的施加將改變電阻值切換裝置122a的電阻值,使之從電阻值R1改變至電阻值R2。By determining which of the first interface area 144 and the second interface area 146 is being controlled, the memory state R RESET can be distinguished from the R RESET memory state. As shown in the procedure of Figure 6, this is accomplished using the applied voltage V DETERMINE , for which the behavior of the resistance value switching device will vary depending on which of the first interface region 144 and the second interface region 146 is Take control. An example of a voltage level that can be used as V DETERMINE is shown in FIG. Here, the voltage level V DETERMINE is the voltage level between the voltage levels V3 and V4 as shown in FIGS. 4A to 4E. Referring again to block 206, the resistance value level is high (e.g., R1 in FIGS. 4A-4E). It can be understood that the behavior of the resistance value switching device 122a is different from the case where the voltage V DETERMINE is applied across the resistance value switching device 122a. It depends on which of the first interface area 144 and the second interface area 146 is being controlled. For example, according to FIG. 4A, if the second interface region 146 is under control, the application of the voltage V DETERMINE does not change the resistance value of the resistance value switching device 122a, but deviates from the resistance value R1. On the other hand, according to FIG. 4D, if the first interface region 144 is under control, the application of the voltage V DETERMINE changes the resistance value of the resistance value switching device 122a to change from the resistance value R1 to the resistance value R2.
因此,在方塊206,電壓VDETERMINE 被施加跨越電阻值切換裝置122a,然後在方塊208,測量電阻值切換裝置122a的電阻。若較高電阻值R RESET /RRESET 仍然被偵測到,可以斷定第二界面區146在進行控制,這是因為電阻值沒有受到VDETERMINE 的施加而改變。接著,此程序結束於方塊210,並決定電阻值切換裝置122a的記憶狀態是RRESET 記憶狀態。反之,若偵測到較低電阻值R SET /RSET ,可以判斷第一界面區144在進行控制,因為電阻值受到VDETERMINE 的施加而改變。請注意在這種情況下,VDETERMINE 的施加將控制從第一界面區144切換至第二界面區146。接著,此程序繼續方塊212,其中切換控制被切換回第一界面區144,使得電阻值切換裝置122a的記憶狀態不受目前讀取程序影響。然後,此程序結束於方塊214,並決定此電阻值切換裝置122a之記憶狀態是R RESET 記憶狀態。Thus, at block 206, voltage V DETERMINE is applied across resistance value switching device 122a, and then at block 208, the resistance of resistance value switching device 122a is measured. If the higher resistance value R RESET /R RESET is still detected, it can be concluded that the second interface region 146 is being controlled because the resistance value is not changed by the application of V DETERMINE . Next, the process ends at block 210 and determines that the memory state of the resistance value switching device 122a is the R RESET memory state. On the other hand, if a lower resistance value R SET /R SET is detected, it can be judged that the first interface region 144 is being controlled because the resistance value is changed by the application of V DETERMINE . Note that in this case, the application of V DETERMINE will control switching from the first interface region 144 to the second interface region 146. Next, the process continues to block 212 where the switching control is switched back to the first interface region 144 such that the memory state of the resistance value switching device 122a is unaffected by the current reading program. Then, the process ends at block 214 and determines that the memory state of the resistance value switching device 122a is the R RESET memory state.
圖7至圖9繪示電阻值切換裝置122a的替代實施例的電阻值切換特性。更具體地說,圖7繪示電阻值切換裝置122a的對稱三狀態實施例的切換特性;圖8繪示電阻值切換裝置122a的非對稱雙狀態實施例的切換特性;以及圖9繪示電阻值切換裝置122a的非對稱雙狀態/三狀態實施例的切換特性。藉由改變電極層134和電極層142的組成和/或氧化鎢層136的組成可製造出這些和其他替代實施例。例如,其中的電極層134和電極層142由TiN形成,與RRESET 或R RESET 狀態相關聯的電阻可以增加或減少,端視TiN的氮含量。同樣,RRESET 或R RESET 狀態相關聯的電阻可以增加或減少,其取決於氧化鎢層136的氧含量。7 to 9 illustrate resistance value switching characteristics of an alternative embodiment of the resistance value switching device 122a. More specifically, FIG. 7 illustrates the switching characteristics of the symmetric three-state embodiment of the resistance value switching device 122a; FIG. 8 illustrates the switching characteristics of the asymmetric dual-state embodiment of the resistance value switching device 122a; and FIG. The switching characteristics of the asymmetric dual state/three state embodiment of the value switching device 122a. These and other alternative embodiments can be fabricated by varying the composition of electrode layer 134 and electrode layer 142 and/or the composition of tungsten oxide layer 136. For example, where electrode layer 134 and electrode layer 142 are formed of TiN, the resistance associated with the R RESET or R RESET state can be increased or decreased, depending on the nitrogen content of TiN. Likewise, the resistance associated with the R RESET or R RESET state can be increased or decreased depending on the oxygen content of the tungsten oxide layer 136.
如圖7所示之電阻值切換裝置122a的對稱三狀態實施例的切換特性,其包括每一界面區144/146有三種電阻值(記憶狀態)。對於第一界面區144正在進行控制時的記憶狀態是R SET 、R RESET1 及R RESET2 。對於第二界面區146正在進行控制的記憶狀態是RSET 、RRESET1 及RRESET2 。狀態R SET 及RSET 之間很難區分。但是,狀態R RESET1 、R RESET2 、RRESET1 及RRESET2 能可靠地彼此區分。此外,每一種狀態R RESET1 、R RESET2 、RRESET1 及RRESET2 可以可靠地與狀態R SET 及RSET 區別。因此,根據目前實施例之電阻值切換裝置122a可以設置成五種狀態的記憶裝置,其具有狀態(1)R RESET1 、(2)R RESET2 、(3) RRESET1 、(4) RRESET2 及(5)R SET 或RSET 。The switching characteristic of the symmetric three-state embodiment of the resistance value switching device 122a shown in FIG. 7 includes three resistance values (memory states) for each interface region 144/146. The memory states when the first interface area 144 is being controlled are R SET , R RESET1 , and R RESET2 . The memory states that are being controlled for the second interface region 146 are R SET , R RESET1 , and R RESET2 . It is difficult to distinguish between states R SET and R SET . However, the states R RESET1 , R RESET2 , R RESET1 , and R RESET2 can be reliably distinguished from each other. In addition, each of the states R RESET1 , R RESET2 , R RESET1 , and R RESET2 can be reliably distinguished from the states R SET and R SET . Therefore, the resistance value switching device 122a according to the present embodiment can be set as a memory device of five states having states (1) R RESET1 , (2) R RESET2 , (3) R RESET1 , (4) R RESET2 and ( 5) R SET or R SET .
圖8所示之電阻值切換裝置122a的非對稱雙狀態實施例的切換特性,包括每一界面區144/146有三種電阻值(記憶狀態),其中RRESET 電阻值可與R RESET 電阻值區。對於第一界面區144正在進行控制的記憶狀態是R SET 及R RESET 。對於第二界面區146正在進行控制的記憶狀態是RSET 及RRESET 。狀態R SET 及RSET 之間很難區分。但是,狀態R RESET 及RRESET 能可靠地彼此區分。此外,狀態R RESET 及RRESET 中的每一個可以與狀態R SET 及RSET 可靠地區分。因此,根據目前實施例之電阻值切換裝置122a可以設置成三種狀態的記憶裝置,其具有狀態(1)R RESET 、(2) RRESET 及(3)R SET 或RSET 。The switching characteristic of the asymmetric two-state embodiment of the resistance value switching device 122a shown in FIG. 8 includes three resistance values (memory state) for each interface region 144/146, wherein the R RESET resistance value and the R RESET resistance value region . The memory states that are being controlled for the first interface area 144 are R SET and R RESET . The memory states that are being controlled for the second interface region 146 are R SET and R RESET . It is difficult to distinguish between states R SET and R SET . However, the states R RESET and R RESET can be reliably distinguished from each other. In addition, each of the states R RESET and R RESET can be reliably distinguished from the states R SET and R SET . Therefore, the resistance value switching device 122a according to the present embodiment can be set to a memory device of three states having states (1) R RESET , ( 2 ) R RESET , and ( 3 ) R SET or R SET .
圖10是根據圖8之非對稱實施例所繪示之讀取電阻值切換裝置122a的流程。首先,於方塊300,電阻值切換裝置122a已經程式化成記憶狀態(1)R RESET 、(2) RRESET 及(3)R SET 或RSET 之其中一種。此程序的其餘部分將允許讀取電阻值切換裝置122a,以確定哪一個記憶狀態被寫入電阻值切換裝置122a。在方塊302,確定電阻值切換裝置122a的電阻。如圖8所示,不管第一界面區144和第二界面區146中的哪一個正在進行控制,電阻可以預期為第一電阻R RESET 、第二電阻RRESET 或第三電阻R SET /RSET 的其中之一。若電阻值R SET /RSET 被偵測出,此程序於方塊304結束,並確定電阻值切換裝置122a的記憶狀態為R SET /RSET 。若電阻值RRESET 被偵測出,此流程於方塊306結束,並確定電阻值切換裝置122a的記憶狀態為RRESET 。若電阻值R RESET 被偵測出,此流程於方塊308結束,並確定電阻值切換裝置122a的記憶狀態為R RESET 。FIG. 10 is a flow chart of the read resistance value switching device 122a according to the asymmetric embodiment of FIG. First, at block 300, the resistance value switching device 122a has been programmed into one of the memory states (1) R RESET , ( 2 ) R RESET , and ( 3 ) R SET or R SET . The remainder of this routine will allow reading of the resistance value switching device 122a to determine which memory state is written to the resistance value switching device 122a. At block 302, the resistance of the resistance value switching device 122a is determined. As shown in FIG. 8, regardless of which of the first interface region 144 and the second interface region 146 is being controlled, the resistance can be expected to be the first resistor R RESET , the second resistor R RESET or the third resistor R SET /R SET One of them. If the resistance value R SET /R SET is detected, the process ends at block 304 and the memory state of the resistance value switching device 122a is determined to be R SET /R SET . If the resistance value R RESET is detected, the flow ends at block 306 and it is determined that the memory state of the resistance value switching device 122a is R RESET . If the resistance value R RESET is detected, the flow ends at block 308 and it is determined that the memory state of the resistance value switching device 122a is R RESET .
再次參照圖9,電阻值切換裝置122a的非對稱雙狀態/三狀態實施例的切換特性圖包括兩個與第一界面區144相關聯的電阻值(記憶狀態)以及三個與第二界面區146相關聯的電阻值(記憶狀態)。對於第一界面區144正在進行控制時的記憶狀態為R SET 及R RESET 。對於第二界面區146正在進行控制時的記憶狀態為RSET 、RRESET1 及RRESET2 。狀態R SET 和RSET 之間很難區分。但是,狀態R RESET 、RRESET1 及RRESET2 能可靠地彼此區分。此外,可以可靠地從R SET 及RSET 狀態區別狀態R RESET 、RRESET1 及RRESET2 中的每一個。因此,根據本實施例之電阻值切換裝置122a可以設置成做為四狀態記憶裝置,其具有狀態(1)R RESET 、(2)RRESET1 、(3)RRESET2 及(4)R SET 或RSET 。Referring again to FIG. 9, the switching characteristic diagram of the asymmetric dual state/three state embodiment of the resistance value switching device 122a includes two resistance values (memory states) associated with the first interface region 144 and three and second interface regions. 146 associated resistance value (memory state). The memory states when the first interface area 144 is being controlled are R SET and R RESET . The memory states when the second interface area 146 is being controlled are R SET , R RESET1 , and R RESET2 . It is difficult to distinguish between states R SET and R SET . However, the states R RESET , R RESET1 , and R RESET2 can be reliably distinguished from each other. In addition, each of the states R RESET , R RESET1 , and R RESET2 can be reliably distinguished from the R SET and R SET states. Thus, the resistance value of the present embodiment, the switching device 122a may be configured as a four-state memory device having a state (1) R RESET, (2 ) R RESET1, (3) R RESET2 and (4) R SET or R SET .
圖11是根據電阻值切換裝置122某些實施例所繪示的電阻值切換裝置122b的示意圖。電阻值切換裝置122b包括一個可編程金屬化記憶胞(programmable metallization cell,PMC)。電阻值切換裝置122b包括基板402、金屬層間介電(intermetal dielectric,IMD)層404、第一電極層406、導電插塞層(conductive plug layer)408、第一介電層410、第二介電層412,固態電解質層(solid electrolyte layer)414及第二電極層416。FIG. 11 is a schematic diagram of the resistance value switching device 122b according to some embodiments of the resistance value switching device 122. The resistance value switching device 122b includes a programmable metallization cell (PMC). The resistance value switching device 122b includes a substrate 402, an intermetal dielectric (IMD) layer 404, a first electrode layer 406, a conductive plug layer 408, a first dielectric layer 410, and a second dielectric. Layer 412, a solid electrolyte layer 414 and a second electrode layer 416.
基板402可以是矽基板(silicon substrate),金屬層間介電層404可以藉由已知方法,例如化學氣相沉積(chemical vapor deposition,CVD)法將氧化層或其他電絕緣層形成在基板402上。The substrate 402 may be a silicon substrate. The inter-metal dielectric layer 404 may be formed on the substrate 402 by a known method, such as chemical vapor deposition (CVD). .
第一電極層406之材料可以是氮化鈦(TiN),其位在IMD層404上,可藉由CVD或物理氣相沉積(physical vapor deposition,PVD)法來形成之。或者,第一電極406的材料可包括摻雜多晶矽、鋁、銅或氮化鉭(TaN)。The material of the first electrode layer 406 may be titanium nitride (TiN), which is located on the IMD layer 404 and can be formed by CVD or physical vapor deposition (PVD). Alternatively, the material of the first electrode 406 may include doped polysilicon, aluminum, copper or tantalum nitride (TaN).
導電插塞層408形成在第一電極406上。第一介電層410和第二介電層412位在導電插塞層408的側面且形成在第一電極406上。介電層410和介電層412可以包含,例如,二氧化矽(SiO2 )、氮化矽(Si3 N4 )、或類似的絕緣材料。導電插塞層408可以包含鎢。導電插塞層408、第一介電層410及第二介電層412所組成的結構的形成方法,可以先在第一電極406之上形成用來做為介電層410和412的連續介電層,其形成的方法例如是化學氣相沉積法。接著,將一部分的連續介質層移除,例如透過微影和蝕刻,從而在第一介電層410和第二介電層412之間形成間隙。接下來,可以在第一介電層410和第二介電層412之間的間隙之中形成導電插塞層408。更具體地說,導電插塞層408的形成可以在第一介電層410和第二介電層412之間的間隙之中沈積導電插塞層408的材料。A conductive plug layer 408 is formed on the first electrode 406. The first dielectric layer 410 and the second dielectric layer 412 are located on the side of the conductive plug layer 408 and are formed on the first electrode 406. Dielectric layer 410 and dielectric layer 412 may comprise, for example, hafnium oxide (SiO 2 ), tantalum nitride (Si 3 N 4 ), or a similar insulating material. Conductive plug layer 408 can comprise tungsten. The structure of the conductive plug layer 408, the first dielectric layer 410 and the second dielectric layer 412 can be formed on the first electrode 406 to form a continuous dielectric layer 410 and 412. The electric layer is formed by a chemical vapor deposition method, for example. A portion of the continuum dielectric layer is then removed, such as by lithography and etching, to form a gap between the first dielectric layer 410 and the second dielectric layer 412. Next, a conductive plug layer 408 may be formed in the gap between the first dielectric layer 410 and the second dielectric layer 412. More specifically, the formation of the conductive plug layer 408 can deposit the material of the conductive plug layer 408 in the gap between the first dielectric layer 410 and the second dielectric layer 412.
固態電解質層(solid electrolyte layer)414可透過沈積方式形成在導電插塞層408上。固態電解質層414還可以延伸到介電層410和412上。固態電解質層414可包括過渡金屬氧化物(transition metal oxide)或包含至少一個硫元素的材料。例如,固態電解質層414可以包含GeS/Ag或GeSe/Ag。A solid electrolyte layer 414 can be formed on the conductive plug layer 408 by deposition. The solid electrolyte layer 414 can also extend over the dielectric layers 410 and 412. The solid electrolyte layer 414 may include a transition metal oxide or a material containing at least one sulfur element. For example, the solid electrolyte layer 414 may comprise GeS/Ag or GeSe/Ag.
第二電極層416可在在固態電解質層414上。第二電極層416可以是可氧化電極。第二電極層416可以包含可氧化電極材料,如銀、銅或鋅。The second electrode layer 416 can be on the solid electrolyte layer 414. The second electrode layer 416 may be an oxidizable electrode. The second electrode layer 416 may comprise an oxidizable electrode material such as silver, copper or zinc.
圖11所示的電阻值切換裝置122b的實施例構成一個單一PMC結構。圖12顯示電阻值切換裝置122b之單一PMC實施例在程式化操作和讀取操作的期間所產生的電壓與電流圖。確切的電壓和電流準位可以從圖12所示的內容加以改變。The embodiment of the resistance value switching device 122b shown in Fig. 11 constitutes a single PMC structure. Figure 12 shows a graph of voltage and current generated during a stylized operation and a read operation of a single PMC embodiment of resistance value switching device 122b. The exact voltage and current levels can be varied from what is shown in FIG.
一開始,電阻值切換裝置122b可能沒有程式化,因此可能具有較高的電阻值。若在第二電極層416施加較高的電壓並且在第一電極層406施加較低的電壓,直到被施加一組啟始電壓(V1或可程式化電壓),沒有電流可流過電阻值切換裝置122b。在說明例中,該組啟始電壓V1可以如約0.7伏特。當施加電壓升高超過啟始電壓V1,電流可能流動,直到達到工作電流IW和可被程式化電路所束縛(例如,受限制)。在一個實施例中,電壓也可降低到0伏特,藉此電流降至0安培,從而完成了電阻值切換裝置122b的程式化。Initially, the resistance value switching device 122b may not be programmed and thus may have a higher resistance value. If a higher voltage is applied to the second electrode layer 416 and a lower voltage is applied to the first electrode layer 406 until a set of starting voltages (V1 or programmable voltage) is applied, no current can flow through the resistance value switching. Device 122b. In the illustrated example, the set of starting voltages V1 can be, for example, about 0.7 volts. When the applied voltage rises above the starting voltage V1, the current may flow until the operating current IW is reached and can be tied (eg, limited) by the stylized circuitry. In one embodiment, the voltage can also be reduced to 0 volts, whereby the current is reduced to 0 amps, thereby completing the stylization of the resistance value switching device 122b.
若要偵測或讀取記憶胞狀態時,感測電壓(VS)可施加於電阻值切換裝置122b。該測應電壓VS可能低於啟始電壓V1。在說明例子中,感測電壓VS可以如約0.3伏特。當電阻值切換裝置122b如上所述一般被程式化(設定,SET)並且感測電壓VS施加於電阻值切換裝置122b時,工作電流IW可以流過電阻值切換裝置122b。如電阻值切換裝置122b不是被程式化(重置,RESET),當施加感測電壓VS時,電阻值切換裝置122b只有很少或根本沒有電流流過。To detect or read the memory cell state, a sense voltage (VS) can be applied to the resistance value switching device 122b. The measured voltage VS may be lower than the starting voltage V1. In the illustrated example, the sense voltage VS can be, for example, about 0.3 volts. When the resistance value switching means 122b is generally programmed (set, SET) as described above and the sensing voltage VS is applied to the resistance value switching means 122b, the operating current IW can flow through the resistance value switching means 122b. If the resistance value switching means 122b is not programmed (reset, RESET), when the sensing voltage VS is applied, the resistance value switching means 122b has little or no current flowing.
在一實施例中,一較低的電壓,如負電壓(也稱為重置啟始電壓(reset threshold voltage))可施加於電阻值切換裝置122b,以抹除或重置程式化狀態。在說明的例子中,重置啟始電壓可以如約-0.3伏特。當於重置啟始電壓施加於電阻值切換裝置122b時,負電流可以流過電阻值切換裝置122b。當負電壓下降到低於重置啟始電壓時,電流可能會停止流動(即減少至0安培)。在重置啟始電壓已經施加於電阻值切換裝置122b後,電阻值切換裝置122b可如先前之程式化操作一般,具有相同的高電阻,藉此抹除或重置存儲在電阻值切換裝置122b的值。In one embodiment, a lower voltage, such as a negative voltage (also referred to as a reset threshold voltage), may be applied to the resistance value switching device 122b to erase or reset the stylized state. In the illustrated example, the reset start voltage can be, for example, about -0.3 volts. When the reset start voltage is applied to the resistance value switching device 122b, a negative current can flow through the resistance value switching device 122b. When the negative voltage drops below the reset start voltage, the current may stop flowing (ie, to 0 amps). After the reset start voltage has been applied to the resistance value switching device 122b, the resistance value switching device 122b can have the same high resistance as in the previous stylized operation, whereby the erase or reset is stored in the resistance value switching device 122b. Value.
圖13是根據電阻值切換裝置122的某些實施例所繪示的電阻值切換裝置示意圖。電阻值切換裝置122c包括一個雙PMC(dual-PMC)結構。電阻值切換裝置122c包括基板452、金屬層間介電(IMD)層454,第一電極層456、導電插塞層458、第一介電層460、第二介電層462、第一固態電解質層464、第二電極層466、第二固態電解質層468及第三電極層470。FIG. 13 is a schematic diagram of a resistance value switching device according to some embodiments of the resistance value switching device 122. The resistance value switching device 122c includes a dual PMC (dual-PMC) structure. The resistance value switching device 122c includes a substrate 452, an inter-metal dielectric (IMD) layer 454, a first electrode layer 456, a conductive plug layer 458, a first dielectric layer 460, a second dielectric layer 462, and a first solid electrolyte layer. 464, a second electrode layer 466, a second solid electrolyte layer 468, and a third electrode layer 470.
基板452可以是矽基板,金屬層間介電層454可以藉由已知方法,例如化學氣相沉積(chemical vapor deposition,CVD)法將氧化層或其他電絕緣層形成在基板452上。The substrate 452 may be a germanium substrate, and the metal interlayer dielectric layer 454 may be formed on the substrate 452 by a known method such as chemical vapor deposition (CVD).
第一電極層456之材料可以是氮化鈦(TiN),其位在IMD層454上,可藉由CVD或物理氣相沉積(PVD)法來形成之。或者,第一電極層456的材料可包括摻雜多晶矽、鋁、銅、或氮化鉭(TaN)。The material of the first electrode layer 456 may be titanium nitride (TiN), which is located on the IMD layer 454 and may be formed by CVD or physical vapor deposition (PVD). Alternatively, the material of the first electrode layer 456 may include doped polysilicon, aluminum, copper, or tantalum nitride (TaN).
導電插塞層458形成於第一電極456上。第一介電層460和第二介電層462位於導電插塞層458的側面且形成於第一電極456上。介電層460和462可以包含例如二氧化矽(SiO2 )、氮化矽(Si3 N4 )、或類似的絕緣材料。導電插塞層458可以包含鎢。導電插塞層458、第一介電層460及第二介電層462所組成的結構的形成方法,可以先在第一電極456上形成做為介電層460和462的連續介電層,其形成的方法例如是化學氣相沉積法。接著,將一部分的連續介質層移除,例如透過微影和蝕刻,從而在第一介電層460和第二介電層462之間形成間隙。接下來,可以在第一介電層460和第二介電層462之間的間隙之中沈積導電插塞層458。更具體地說,導電插塞層458的形成方法,可以在第一介電層460和第二介電層462之間的間隙沈積導電插塞層408的材料。A conductive plug layer 458 is formed on the first electrode 456. The first dielectric layer 460 and the second dielectric layer 462 are located on the side of the conductive plug layer 458 and are formed on the first electrode 456. Dielectric layers 460 and 462 may comprise, for example, hafnium oxide (SiO 2 ), tantalum nitride (Si 3 N 4 ), or similar insulating materials. Conductive plug layer 458 can comprise tungsten. A method of forming the structure of the conductive plug layer 458, the first dielectric layer 460, and the second dielectric layer 462 may first form a continuous dielectric layer as the dielectric layers 460 and 462 on the first electrode 456. The method of forming it is, for example, a chemical vapor deposition method. Next, a portion of the continuum dielectric layer is removed, such as by lithography and etching, thereby forming a gap between the first dielectric layer 460 and the second dielectric layer 462. Next, a conductive plug layer 458 can be deposited in the gap between the first dielectric layer 460 and the second dielectric layer 462. More specifically, the conductive plug layer 458 can be formed by depositing a material of the conductive plug layer 408 in a gap between the first dielectric layer 460 and the second dielectric layer 462.
固態電解質層464可透過沈積方式形成在導電插塞層458上。固態電解質層464還可以延伸到介電層460和462上。固態電解質層464可包括過渡金屬氧化物或包含至少一個硫元素的材料。例如,固態電解質層464可以包含GeS/Ag或GeSe/Ag。A solid electrolyte layer 464 can be formed on the conductive plug layer 458 by deposition. The solid electrolyte layer 464 can also extend over the dielectric layers 460 and 462. The solid electrolyte layer 464 can include a transition metal oxide or a material comprising at least one sulfur element. For example, the solid electrolyte layer 464 may comprise GeS/Ag or GeSe/Ag.
第二電極層466可透過沈積方式形成在固態電解質層464上。第二電極層466可以是可氧化電極。第二電極層466可以包含可氧化電極材料,如銀、銅或鋅。The second electrode layer 466 is formed on the solid electrolyte layer 464 by deposition. The second electrode layer 466 can be an oxidizable electrode. The second electrode layer 466 may comprise an oxidizable electrode material such as silver, copper or zinc.
第二固態電解質層468可透過沈積方式形成在第二電極層466上。第二固態電解質層468可包括過渡金屬氧化物或包含至少一個硫元素的材料。例如,第二固態電解質層468可以包含GeS/Ag或GeSe/Ag。The second solid electrolyte layer 468 is formed on the second electrode layer 466 by deposition. The second solid electrolyte layer 468 may include a transition metal oxide or a material containing at least one sulfur element. For example, the second solid electrolyte layer 468 may comprise GeS/Ag or GeSe/Ag.
第三電極層470可透過沈積方式形成在第二固態電解質層468上。第三電極層470可以包含導電或半導電材料,例如是TiN。The third electrode layer 470 is formed on the second solid electrolyte layer 468 by deposition. The third electrode layer 470 may comprise a conductive or semiconductive material such as TiN.
圖13所示之電阻值切換裝置122c的實施例形成了一個雙PMC(dual-PMC)結構,包括上部PMC結構472以及下部PMC結構474。每一個PMC結構472、474能夠被程式化為兩個的記憶狀態,分別對應至各自的電阻值。上部PMC結構472的記憶狀態包括標示為RRESET 和RSET 的記憶狀態,其分別對應於相對高和相對低的電阻值。下部PMC結構474的記憶狀態包括標示為R RESET 和R SET 的記憶胞狀態,其分別對應於相對高和相對低的電阻值。在一些實施例,與RRESET 相關聯的電阻值可以大致上等於與R RESET 相關聯的電阻值,而在另一些實施例中與RRESET 和R RESET 相關聯的各電阻值也可以不相同。同樣,在一些實施例,與RSET 相關聯的電阻值可大致上等於與R SET 相關聯的電阻值,而在另一些實施例中與RSET 和R SET 相關聯的各電阻值也可不相同。The embodiment of the resistance value switching device 122c shown in FIG. 13 forms a dual PMC (dual-PMC) structure including an upper PMC structure 472 and a lower PMC structure 474. Each PMC structure 472, 474 can be programmed into two memory states, each corresponding to a respective resistance value. The memory states of the upper PMC structure 472 include memory states labeled R RESET and R SET , which correspond to relatively high and relatively low resistance values, respectively. The memory states of the lower PMC structure 474 include memory cell states labeled R RESET and R SET , which correspond to relatively high and relatively low resistance values, respectively. In some embodiments, the resistance value associated with R RESET may be substantially equal to the resistance value associated with R RESET , while in other embodiments the respective resistance values associated with R RESET and R RESET may also be different. Also, in some embodiments, the resistance value associated with R SET may be substantially equal to the resistance value associated with R SET , while in other embodiments the resistance values associated with R SET and R SET may also be different. .
圖14至圖16顯示電阻值切換裝置122c的對稱、雙PMC(dual-PMC)實施例的電阻值切換特性圖。更具體地說,圖14顯示上部PMC結構472的電阻值切換特性,圖15顯示下部PMC結構474的電阻值切換特性,圖16顯示由上部PMC結構472和下部PMC結構474形成的雙PMC結構的對稱實施例的整體電阻值切換特性。14 to 16 are diagrams showing resistance value switching characteristics of a symmetric, dual PMC (dual-PMC) embodiment of the resistance value switching device 122c. More specifically, FIG. 14 shows the resistance value switching characteristic of the upper PMC structure 472, FIG. 15 shows the resistance value switching characteristic of the lower PMC structure 474, and FIG. 16 shows the double PMC structure formed by the upper PMC structure 472 and the lower PMC structure 474. The overall resistance value switching characteristic of the symmetric embodiment.
如圖14所示,跨越整個上部PMC結構472之正電壓VS1 會導致上部PMC結構472的電阻值切換到與記憶狀態RRESET 相關聯的電阻值。跨越整個上部PMC結構472之負電壓VS2 會導致上部PMC結構472的電阻值切換到與記憶狀態RSET 相關聯的電阻值。As shown in FIG. 14, across the entire upper structure PMC positive voltage V S1 472 will cause the resistance value of the upper structure 472 is switched to a PMC resistance value R RESET state memory associated. The negative voltage V S2 across the entire upper PMC structure 472 causes the resistance value of the upper PMC structure 472 to switch to the resistance value associated with the memory state R SET .
如圖15所示,跨越整個下部PMC結構474之正電壓VS3 會導致下部PMC結構474的電阻值切換到與記憶狀態R SET 相關聯的電阻值。跨越整個下部PMC結構474之負電壓VS4 會導致下部PMC結構472的電阻值切換到與記憶狀態R RESET 相關聯的電阻值。15, across the lower portion of the structure PMC positive voltage V S3 474 will cause the resistance value of a lower structure 474 is switched to a PMC resistance value of the memory state R SET associated. The negative voltage V S4 across the entire lower PMC structure 474 causes the resistance value of the lower PMC structure 472 to switch to the resistance value associated with the memory state R RESET .
圖14和圖15所示的上部PMC結構472和下部PMC結構474的對稱實施例的組合,導致了記憶裝置能夠有如圖16所示的四種記憶狀態A至D。記憶狀態A至D中的每一種是與上部PMC結構472和下部PMC結構474的記憶狀態的電阻值的各自總和相關聯。當上部PMC結構472的電阻值具有與記憶狀態RSET 相關聯的電阻值以及下部PMC結構474的電阻值具有與記憶狀態R RESET 相關聯的電阻值時,發生記憶狀態A,使得記憶狀態A之雙PMC結構的整體電阻為RSET +R RESET 。當上部PMC結構472的電阻值具有與記憶狀態RRESET 相關聯的電阻值以及下部PMC結構474的電阻值具有與記憶狀態R SET 相關聯的電阻值時,發生記憶狀態D,使得記憶狀態D之雙PMC結構的整體電阻為R SET +RRESET 。當上部PMC結構472的電阻值具有與記憶狀態RRESET 相關聯的電阻值以及下部PMC結構474的電阻值具有與記憶狀態R RESET 相關聯的電阻值時,記憶狀態B和C兩者均發生,使得記憶狀態B和C之雙PMC結構的整體電阻值為RRESET +R RESET 。因此,記憶胞狀態B和C是很難區分,所以電阻值切換裝置122c的雙PMC結構可以以具有記憶狀態的A、B(或C)和D的三狀態記憶裝置來實現。The combination of the symmetric embodiments of the upper PMC structure 472 and the lower PMC structure 474 shown in Figures 14 and 15 results in the memory device being able to have four memory states A through D as shown in Figure 16. Each of the memory states A through D is associated with a respective sum of the resistance values of the memory states of the upper PMC structure 472 and the lower PMC structure 474. When the resistance value of the upper PMC structure 472 has a resistance value associated with the memory state R SET and the resistance value of the lower PMC structure 474 has a resistance value associated with the memory state R RESET , the memory state A occurs such that the memory state A The overall resistance of the dual PMC structure is R SET + R RESET . When the resistance value of the upper PMC structure 472 has a resistance value associated with the memory state R RESET and the resistance value of the lower PMC structure 474 has a resistance value associated with the memory state R SET , the memory state D occurs such that the memory state D The overall resistance of the dual PMC structure is R SET +R RESET . When the resistance value of the upper PMC structure 472 has a resistance value associated with the memory state R RESET and the resistance value of the lower PMC structure 474 has a resistance value associated with the memory state R RESET , both memory states B and C occur, The overall resistance value of the dual PMC structure of memory states B and C is R RESET + R RESET . Therefore, the memory cell states B and C are difficult to distinguish, so the dual PMC structure of the resistance value switching device 122c can be realized by a three-state memory device having A, B (or C) and D in a memory state.
接著參考圖17描述根據實施例之三態、對稱與雙PMC記憶裝置,讀取電阻值切換裝置122c的程序,圖17顯示讀取程序之流程圖。Next, a procedure for reading the resistance value switching means 122c according to the tri-state, symmetrical and dual PMC memory device according to the embodiment will be described with reference to Fig. 17, and Fig. 17 is a flow chart showing the reading procedure.
首先,在方塊500,電阻值切換裝置122c已經被程式化成記憶狀態A、B/C、或D的其中之一。此程序的其餘部分將允許讀取電阻值切換裝置122c,以決定哪一個記憶狀態寫入電阻值切換裝置122c中。在方塊502,決定電阻值切換裝置122c的電阻值。在目前的對稱實施例,相應於與RSET 相關聯的電阻值大致上等於與R SET 相關聯的電阻值,與RRESET 相關聯的電阻值大致等於與R RESET 相關聯的電阻值。因此,電阻值切換裝置122c的電阻值可以預期是一個較高的電阻值R=R RESET +RRESET 或是一個較低的電阻值R=(RRESET +R SET )或(RSET +R RESET )。若較高的電阻值R=R RESET +RRESET 被偵檢,則該程序結束於方塊504,並確定電阻值切換裝置122c的記憶狀態是記憶狀態B/C(R RESET +RRESET )。否則,若偵測到較低電阻值,此程序將繼續,以便區分記憶狀態A(RSET +R RESET )和D(RRESET +R SET )。First, at block 500, the resistance value switching device 122c has been programmed into one of the memory states A, B/C, or D. The remainder of this routine will allow reading of the resistance value switching device 122c to determine which memory state is written into the resistance value switching device 122c. At block 502, the resistance value of the resistance value switching device 122c is determined. In the present embodiment of symmetry corresponding to the resistance value R SET associated with substantially equal resistance value R SET associated with the resistance value R RESET associated with substantially equal resistance value R RESET associated. Therefore, the resistance value of the resistance value switching device 122c can be expected to be a higher resistance value R = R RESET + R RESET or a lower resistance value R = (R RESET + R SET ) or (R SET + R RESET ). If the higher resistance value R = R RESET + R RESET is detected, the routine ends at block 504 and it is determined that the memory state of the resistance value switching device 122c is the memory state B/C ( R RESET + R RESET ). Otherwise, if a lower resistance value is detected, the program will continue to distinguish between memory states A (R SET + R RESET ) and D (R RESET + R SET ).
接著在方塊506中,施加電壓VDETERMINE 於整個電阻值切換裝置122c,然後在方塊508中測量電阻值切換裝置122c的電阻值。在此實施例,VDETERMINE 的電壓為可選擇的,使得若記憶狀態為記憶狀態A時,將會導致上部PMC結構472從RSET 切換至RRESET ,但若記憶狀態為記憶狀態D時,則不會產生任何改變。因此,VDETERMINE 的電壓是介於VS1 和VS3 之間。另外,VDETERMINE 的電壓可以從VS2 和VS4 兩者間選擇時,這使得若記憶狀態是記憶胞狀態D時,將會導致下部PMC結構472從RSET 切換至RRESET ,但若記憶狀態為記憶狀態A時,則不會造成任何改變。Next, in block 506, a voltage V DETERMINE is applied to the overall resistance value switching device 122c, and then the resistance value of the resistance value switching device 122c is measured in block 508. In this embodiment, the voltage of V DETERMINE is selectable, so that if the memory state is the memory state A, the upper PMC structure 472 will be switched from R SET to R RESET , but if the memory state is the memory state D, then No change will happen. Therefore, the voltage of V DETERMINE is between V S1 and V S3 . In addition, when the voltage of V DETERMINE can be selected from between V S2 and V S4 , this causes the lower PMC structure 472 to switch from R SET to R RESET if the memory state is the memory cell state D, but if the memory state When it is in memory state A, it will not cause any change.
假如在方塊508偵測出較低電阻值等於RRESET +R SET (也等於RSET +R RESET ),因為電阻值沒有因為VDETERMINE 的施加而改變,故可確定記憶狀態是記憶狀態D。因此,該程序於方塊510結束,並確定電阻值切換裝置122c的記憶狀態是記憶狀態D。反之,若較高的電阻值R RESET +RRESET 於方塊508被偵測出,因為電阻值藉由VDETERMINE 的施加而改變,故可以確定記憶狀態是記憶狀態A。請注意,在這種情況下,VDETERMINE 的施加將上部PMC結構472的電阻值從RSET 切換至RRESET 。接著,此程序繼續至方塊512,其中上部PMC結構472的電阻值切換回至RSET (例如,利用VS2 的施加),使得電阻值切換裝置122c的記憶狀態不會受到目前讀取程序的擾亂。然後,此程序於方塊514結束,並決定電阻值切換裝置122c的記憶狀態為記憶狀態A。If at block 508 it is detected that the lower resistance value is equal to R RESET + R SET (also equal to R SET + R RESET ), since the resistance value does not change due to the application of V DETERMINE , it can be determined that the memory state is the memory state D. Therefore, the routine ends at block 510 and it is determined that the memory state of the resistance value switching device 122c is the memory state D. Conversely, if the higher resistance value R RESET + R RESET is detected at block 508, since the resistance value is changed by the application of V DETERMINE , it can be determined that the memory state is the memory state A. Note that in this case, the application of V DETERMINE switches the resistance value of the upper PMC structure 472 from R SET to R RESET . Next, the process continues to block 512 where the resistance value of the upper PMC structure 472 is switched back to R SET (eg, with the application of V S2 ) such that the memory state of the resistance value switching device 122c is not disturbed by the current reading process. . Then, the routine ends at block 514 and determines that the memory state of the resistance value switching device 122c is the memory state A.
圖18至圖20等圖顯示一種電阻值切換裝置122c的非對稱、雙PMC的實施例。更具體地說,圖18顯示上部PMC結構472的電阻值切換特性,圖15顯示下部PMC結構474的電阻值切換特性,圖16顯示由上部PMC結構472和下部PMC結構474形成的雙PMC結構的非對稱實施例的整體電阻值切換特性。18 to 20 and the like show an embodiment of an asymmetric, dual PMC of the resistance value switching device 122c. More specifically, FIG. 18 shows the resistance value switching characteristic of the upper PMC structure 472, FIG. 15 shows the resistance value switching characteristic of the lower PMC structure 474, and FIG. 16 shows the double PMC structure formed by the upper PMC structure 472 and the lower PMC structure 474. The overall resistance value switching characteristic of the asymmetric embodiment.
如圖18所示,跨越整個上部PMC結構472之正電壓VS1 會導致上部PMC結構472的電阻值切換到與記憶狀態RRESET 相關聯的電阻值。跨越整個上部PMC結構472之負電壓VS2 會導致上部PMC結構472的電阻值切換到與記憶狀態RSET 相關聯的電阻值。18, across the entire upper structure PMC positive voltage V S1 472 will cause the resistance value of the upper structure 472 is switched to a PMC resistance value R RESET state memory associated. The negative voltage V S2 across the entire upper PMC structure 472 causes the resistance value of the upper PMC structure 472 to switch to the resistance value associated with the memory state R SET .
如圖19所示,跨越整個下部PMC結構474之正電壓VS3 會導致下部PMC結構474的電阻值切換到與記憶狀態R SET 相關聯的電阻值。跨越整個下部PMC結構474之負電壓VS4 會導致下部PMC結構472的電阻值切換到與記憶狀態R RESET 相關聯的電阻值。19, the structure across the entire lower PMC positive voltage V S3 474 will cause the resistance value of a lower structure 474 is switched to a PMC resistance value of the memory state R SET associated. The negative voltage V S4 across the entire lower PMC structure 474 causes the resistance value of the lower PMC structure 472 to switch to the resistance value associated with the memory state R RESET .
如,圖18和圖19所示之上部PMC結構472和下部PMC結構474的非對稱實施例的組合,導致了記憶裝置能夠有圖20所示的四種記憶狀態A至D。記憶狀態A至D中的每一種是與上部PMC結構472和下部PMC結構474之記憶狀態的電阻值的各自總和相關聯。當上部PMC結構472的電阻值具有與記憶狀態RSET 相關聯的電阻值以及下部PMC結構474的電阻值具有與記憶狀態R RESET 相關聯的電阻值時,發生記憶狀態A,使得記憶狀態A之雙PMC結構的整體電阻值為RSET +R RESET 。當上部PMC結構472的電阻值具有與記憶狀態RRESET 相關聯的電阻值以及下部PMC結構474的電阻值具有與記憶胞狀態R SET 相關聯的電阻值時,發生記憶狀態D,使得記憶狀態D之雙PMC結構的整體電阻值為R SET +RRESET 。當上部PMC結構472的電阻值具有與記憶狀態RRESET 相關聯的電阻值以及下部PMC結構474的電阻值具有與記憶狀態R RESET 相關聯的電阻值時,記憶胞狀態B和C兩者均發生,使得記憶狀態B和C之雙PMC結構的整體電阻值為RRESET +R RESET 。因此,記憶狀態B和C是很難區分,所以電阻值切換裝置122c的雙PMC結構可以以具有記憶狀態的A、B(或C)和D的三狀態記憶裝置來實現。For example, the combination of the asymmetric embodiment of the upper PMC structure 472 and the lower PMC structure 474 shown in Figures 18 and 19 results in the memory device being able to have the four memory states A through D shown in Figure 20. Each of the memory states A through D is associated with a respective sum of the resistance values of the memory states of the upper PMC structure 472 and the lower PMC structure 474. When the resistance value of the upper PMC structure 472 has a resistance value associated with the memory state R SET and the resistance value of the lower PMC structure 474 has a resistance value associated with the memory state R RESET , the memory state A occurs such that the memory state A The overall resistance of the dual PMC structure is R SET + R RESET . When the resistance value of the upper PMC structure 472 has a resistance value associated with the memory state R RESET and the resistance value of the lower PMC structure 474 has a resistance value associated with the memory cell state R SET , the memory state D occurs such that the memory state D The overall resistance of the dual PMC structure is R SET +R RESET . When the resistance value of the upper PMC structure 472 has a resistance value associated with the memory state R RESET and the resistance value of the lower PMC structure 474 has a resistance value associated with the memory state R RESET , both the memory cell states B and C occur Thus, the overall resistance value of the dual PMC structure of memory states B and C is R RESET + R RESET . Therefore, the memory states B and C are difficult to distinguish, so the dual PMC structure of the resistance value switching device 122c can be realized by a three-state memory device having A, B (or C) and D in a memory state.
圖21顯示一種讀取電阻值切換裝置122c的替代方法,是根據如圖18至圖20所示具有不對稱電阻性切換特性的不對稱實施例。首先,於方塊600,電阻值切換裝置122c已經被程式化為記憶胞狀態A、B/C、或D之其中一種。此程序的其餘部分將允許讀取電阻值切換裝置122c,以確定記憶狀態A、B/C、或D之其中一種被寫入電阻值切換裝置122c。於方塊602確定電阻值切換裝置122c的電阻。如圖20,電阻值可以預期為與記憶狀態A(RSET +R RESET )、B/C(RRESET +R RESET )、或D(R SET +RRESET )的其中之一相關聯的電阻值。若電阻值RRESET +R RESET 被偵測出,此程序於方塊604,並確定電阻值切換裝置122c的記憶狀態是記憶狀態B/C。若電阻值R SET +RRESET 被偵測出,此程序於方塊606結束,並確定電阻值切換裝置122c的記憶狀態是記憶狀態D。若電阻值RSET +R RESET 被偵測出,此程序於方塊608結束,並確定電阻值切換裝置122c的記憶狀態是記憶狀態A。Figure 21 shows an alternative method of reading the resistance value switching device 122c in accordance with an asymmetric embodiment having asymmetric resistive switching characteristics as shown in Figures 18-20. First, at block 600, the resistance value switching device 122c has been programmed into one of the memory cell states A, B/C, or D. The remainder of this routine will allow reading of the resistance value switching device 122c to determine that one of the memory states A, B/C, or D is written to the resistance value switching device 122c. The resistance of the resistance value switching device 122c is determined at block 602. As shown in Figure 20, the resistance value can be expected as the resistance value associated with one of the memory states A (R SET + R RESET ), B / C (R RESET + R RESET ), or D ( R SET + R RESET ) . If the resistance value R RESET + R RESET is detected, the process proceeds to block 604 and it is determined that the memory state of the resistance value switching device 122c is the memory state B/C. If the resistance value R SET + R RESET is detected, the process ends at block 606 and it is determined that the memory state of the resistance value switching device 122c is the memory state D. If the resistance value R SET + R RESET is detected, the process ends at block 608 and it is determined that the memory state of the resistance value switching device 122c is the memory state A.
除了圖1和圖2所示的電阻值切換裝置122的上述實施例122a、122b和122c,可理解的是電阻值切換裝置122還可以有許多其他實施例。圖22繪示更為一般化的實施例的方塊圖,通常稱為電阻值切換裝置122d。電阻值切換裝置122d包括一上部記憶體結構652和一下部記憶體結構654,其中記憶結構652和654中的每一個包括各自的半導體電阻值切換記憶裝置。例如,上部記憶體結構652可包括PMC、電阻性隨機存取記憶體(Resistive Random Access Memory,RRAM),磁阻性隨機存取記憶體(Magnetoresistive Random Access Memory,MRAM)或鐵電隨機存取記憶體(Ferroelectric Random Access Memory,FRAM)。同樣,下部記憶體結構654可包括PMC、RRAM、MRAM的,或FRAM。另外,上部記憶體結構652和下部記憶體結構654可以包括任何電子記憶裝置,能夠切換兩種電阻值(相當於兩種記憶狀態)。In addition to the above-described embodiments 122a, 122b, and 122c of the resistance value switching device 122 shown in FIGS. 1 and 2, it will be understood that the resistance value switching device 122 can have many other embodiments. Figure 22 depicts a block diagram of a more generalized embodiment, commonly referred to as resistance value switching device 122d. The resistance value switching device 122d includes an upper memory structure 652 and a lower memory structure 654, wherein each of the memory structures 652 and 654 includes a respective semiconductor resistance value switching memory device. For example, the upper memory structure 652 may include a PMC, a resistive random access memory (RRAM), a magnetoresistive random access memory (MRAM), or a ferroelectric random access memory. Ferroelectric Random Access Memory (FRAM). Likewise, the lower memory structure 654 can include PMC, RRAM, MRAM, or FRAM. Additionally, upper memory structure 652 and lower memory structure 654 can include any electronic memory device capable of switching between two resistance values (equivalent to two memory states).
上部記憶體結構652的記憶狀態包括標示為RRESET 和RSET 的記憶狀態,分別對應於相對高和相對低的電阻值。正的重置電壓(+VRESET )可以切換上部記憶體結構652的電阻值至電阻值RRESET ,而負的設定電壓(-VSET )可以切換上部記憶體結構652的電阻值至電阻值RSET 。下部記憶體結構654的記憶狀態包括標示為R RESET 和R SET 的記憶狀態,分別對應於相對高和相對低的電阻值。負的重置電壓(-V RESET )可以切換上部記憶體結構652的電阻值至電阻值R RESET ,而正的設定電壓(+V SET )可以切換上部記憶體結構652的電阻值至電阻值R SET 。對於電阻值切換裝置122d有兩個想要的條件組。第一條件組滿足以下兩個條件(1a)及(1b):The memory states of the upper memory structure 652 include memory states labeled R RESET and R SET , corresponding to relatively high and relatively low resistance values, respectively. The positive reset voltage (+V RESET ) can switch the resistance value of the upper memory structure 652 to the resistance value R RESET , and the negative set voltage (−V SET ) can switch the resistance value of the upper memory structure 652 to the resistance value R. SET . The memory state of the lower memory structure 654 includes memory states labeled R RESET and R SET , corresponding to relatively high and relatively low resistance values, respectively. The negative reset voltage ( -V RESET ) can switch the resistance value of the upper memory structure 652 to the resistance value R RESET , and the positive set voltage (+ V SET ) can switch the resistance value of the upper memory structure 652 to the resistance value R. SET . There are two desired sets of conditions for the resistance value switching device 122d. The first condition group satisfies the following two conditions (1a) and (1b):
(1a) +VRESET >+V SET (1a) +V RESET >+ V SET
(1b) |-VSET |>|-V RESET |(1b) |-V SET |>| -V RESET |
第二條件組滿足以下兩個條件(2a)及(1b):The second condition group satisfies the following two conditions (2a) and (1b):
(2a) +VRESET <+V SET (2a) +V RESET <+ V SET
(2b) |-VSET |<|-V RESET (2b) |-V SET |<| -V RESET
參考圖23至圖26,描述了滿足第一條件組的電阻值切換裝置122d的實施例。參考圖27至圖30,描述了滿足第二條件組的電阻值切換裝置122d的實施例。Referring to Figures 23 to 26, an embodiment of the resistance value switching device 122d that satisfies the first condition set is described. Referring to Figures 27 to 30, an embodiment of the resistance value switching device 122d that satisfies the second condition set is described.
圖23至圖25繪示了滿足條件(1a)和(1b)的第一組的電阻值切換裝置122d實施例的電阻值切換特性的圖式。更具體地說,圖23顯示上部記憶體結構652的電阻值切換特性,圖24顯示下部記憶體結構654的電阻值切換特性,以及圖25顯示根據目前實施例電阻值切換裝置122d的整體電阻值切換特性。23 to 25 are diagrams showing the resistance value switching characteristics of the first group of resistance value switching devices 122d satisfying the conditions (1a) and (1b). More specifically, FIG. 23 shows the resistance value switching characteristic of the upper memory structure 652, FIG. 24 shows the resistance value switching characteristic of the lower memory structure 654, and FIG. 25 shows the overall resistance value of the resistance value switching device 122d according to the current embodiment. Switch characteristics.
如圖23,跨越上部記憶體結構652之正電壓+VRESET 會導致上部記憶體結構652的電阻值切換到與記憶狀態RRESET 相關聯的電阻值。跨越上部記憶體結構652之負電壓-VSET 會導致上部記憶體結構652的電阻值切換到與記憶狀態RSET 相關聯的電阻值。As shown in FIG. 23, a positive voltage +V RESET across the upper memory structure 652 causes the resistance value of the upper memory structure 652 to switch to the resistance value associated with the memory state R RESET . The negative voltage -V SET across the upper memory structure 652 causes the resistance value of the upper memory structure 652 to switch to the resistance value associated with the memory state R SET .
如圖24所示,跨越下部記憶體結構654之正電壓+V SET 會導致下部記憶體結構654的電阻值切換到與記憶狀態R SET 相關聯的電阻值。跨越下部記憶體結構654之負電壓-V RESET 會導致下部記憶體結構654的電阻值切換到與記憶狀態R RESET 相關聯的電阻值。As shown in FIG. 24, a positive voltage + V SET across the lower memory structure 654 causes the resistance value of the lower memory structure 654 to switch to a resistance value associated with the memory state R SET . The negative voltage across the lower memory structure 654 - V RESET causes the resistance value of the lower memory structure 654 to switch to the resistance value associated with the memory state R RESET .
圖23和圖24所示之上部記憶體結構652和下部記憶體結構654的組合,導致記憶裝置具有如圖25所示之四種記憶狀態。記憶狀態A至D中的每一個均與上部記憶體結構652和下部記憶體結構654的記憶狀態的電阻值的各自總和相關聯。當上部記憶體結構652的電阻值具有與記憶狀態RSET 相關聯的電阻值以及下部記憶體結構654的電阻值具有與記憶狀態R RESET 相關聯的電阻值時,發生記憶狀態A,使得記憶狀態A之電阻值切換裝置122d的整體電阻是RSET +R RESET 。當上部記憶體結構652的電阻值具有與記憶狀態RRESET 相關聯的電阻值以及下部記憶體結構654的電阻值具有與記憶狀態R RESET 相關聯的電阻值時,發生記憶狀態B,使得記憶狀態B之電阻值切換裝置122d的整體電阻值是R RESET +RRESET 。當上部記憶體結構652的電阻值具有與記憶狀態RSET 相關聯的電阻值以及下部記憶體結構654的電阻值具有與記憶狀態R SET 相關聯的電阻值時,發生記憶狀態C,使得記憶狀態C之電阻值切換裝置122d的整體電阻值是R SET +RSET 。當上部記憶體結構652的電阻值具有與記憶狀態RRESET 相關聯的電阻值以及下部記憶體結構654的電阻值具有與記憶胞狀態R SET 相關聯的電阻值時,發生記憶狀態D,使得記憶狀態D之電阻值切換裝置122d的整體電阻是R SET +RRESET 。因此,電阻值切換裝置122d可以實現為具有記憶狀態A、B、C和D四種狀態的記憶裝置。The combination of the upper memory structure 652 and the lower memory structure 654 shown in Figures 23 and 24 results in the memory device having four memory states as shown in Figure 25. Each of the memory states A through D is associated with a respective sum of the resistance values of the memory states of the upper memory structure 652 and the lower memory structure 654. When the resistance value of the upper memory structure 652 has a resistance value associated with the memory state R SET and the resistance value of the lower memory structure 654 has a resistance value associated with the memory state R RESET , the memory state A occurs, resulting in a memory state The overall resistance of the resistance value switching device 122d of A is R SET + R RESET . When the resistance value of the upper memory structure 652 has a resistance value associated with the memory state R RESET and the resistance value of the lower memory structure 654 has a resistance value associated with the memory state R RESET , the memory state B occurs, resulting in a memory state The overall resistance value of the resistance value switching device 122d of B is R RESET + R RESET . When the resistance value of the upper memory structure 652 has a resistance value associated with the memory state R SET and the resistance value of the lower memory structure 654 has a resistance value associated with the memory state R SET , the memory state C occurs, resulting in a memory state The overall resistance value of the resistance value switching device 122d of C is R SET + R SET . When the resistance value of the upper memory structure 652 has a resistance value associated with the memory state R RESET and the resistance value of the lower memory structure 654 has a resistance value associated with the memory cell state R SET , the memory state D occurs, causing memory The overall resistance of the resistance value switching device 122d of the state D is R SET + R RESET . Therefore, the resistance value switching device 122d can be realized as a memory device having four states of the memory states A, B, C, and D.
參考圖26,其根據滿足第一組條件(1a)和(1b)之一種四狀態記憶裝置實施例,描述讀取電阻值切換裝置122d的程序。Referring to Fig. 26, a procedure for reading the resistance value switching means 122d will be described based on a four state memory device embodiment which satisfies the first set of conditions (1a) and (1b).
首先,於方塊700,電阻值切換裝置122d已經被程式化為記憶狀態A、B、C、或D之其中一種。此程序的其餘部分將允許讀取電阻值切換裝置122d,以決定記憶狀態A至D之其中一種被寫入電阻值切換裝置122d。在方塊702,決定電阻值切換裝置122d的電阻值。電阻值切換裝置122d的電阻值可以預期為分別與記憶狀態A至D相關聯的四種電阻值的其中之一。若電阻值R=RSET +R SET 被偵測出,此程序結束於方塊704,並確定電阻值切換裝置122d的記憶狀態是記憶狀態C(RSET +R SET )。若電阻值R=RRESET +R RESET 被偵測出,此程序結束於方塊705,並確定電阻值切換裝置122d的記憶狀態是記憶狀態B(RRESET +R RESET )。在目前實施例,與RSET 相關聯的電阻值大致上等於與R SET 相關聯的電阻值,並且與RRESET 相關聯的電阻值大致上等於與R RESET 相關聯的電阻值。因此,於方塊702第三種可能性是電阻值為R=RRESET +R SET =RSET +R RESET 。若這第三種可能性發生,此程序將繼續,以便區分記憶狀態A(RSET +R RESET )和D(RRESET +R SET )。First, at block 700, the resistance value switching device 122d has been programmed into one of the memory states A, B, C, or D. The remainder of this routine will allow reading of the resistance value switching means 122d to determine that one of the memory states A through D is written to the resistance value switching means 122d. At block 702, the resistance value of the resistance value switching device 122d is determined. The resistance value of the resistance value switching device 122d can be expected to be one of four resistance values associated with the memory states A to D, respectively. If the resistance value R = R SET + R SET is detected, the process ends at block 704 and it is determined that the memory state of the resistance value switching device 122d is the memory state C (R SET + R SET ). If the resistance value R = R RESET + R RESET is detected, the routine ends at block 705 and it is determined that the memory state of the resistance value switching device 122d is the memory state B (R RESET + R RESET ). In the present embodiment, the resistance value R SET associated substantially equal resistance value R SET associated and equal to the resistance value R RESET associated with the resistance value R RESET substantially associated. Therefore, a third possibility at block 702 is that the resistance value is R = R RESET + R SET = R SET + R RESET . If this third possibility occurs, the program will continue to distinguish between memory states A (R SET + R RESET ) and D (R RESET + R SET ).
接著在方塊706中,電壓VDETERMINE 施加於整個電阻值切換裝置122d,然後在方塊708中測量電阻值切換裝置122d的電阻值。在此實施例,VDETERMINE 的電壓被選擇,以使若記憶狀態為記憶狀態A時將會導致下部記憶體結構654從R RESET 切換至R SET ,但若記憶狀態為記憶狀態D時不會產生任何改變。因此,VDETERMINE 的電壓是介於+V SET 和+V RESET 之間。Next, in block 706, voltage V DETERMINE is applied to the entire resistance value switching device 122d, and then the resistance value of the resistance value switching device 122d is measured in block 708. In this embodiment, the voltage of V DETERMINE is selected such that if the memory state is memory state A, the lower memory structure 654 will be switched from R RESET to R SET , but if the memory state is memory state D, it will not be generated. Any change. Therefore, the voltage of V DETERMINE is between + V SET and + V RESET .
在方塊708中,再次確定電阻值切換裝置122d的電阻值。若在方塊708偵測到的電阻值為R=RRESET +R SET ,因為電阻值沒有藉由VDETERMINE 的施加而改變,故可確定記憶狀態是記憶狀態D,因此,此程序結束在方塊710,並確定電阻值切換裝置122d的記憶狀態的是記憶狀態D。反之,,若在方塊708偵測到的電阻為R=RRESET +R SET ,因為電阻值藉由VDETERMINE 的施加而改變了,故可以確定記憶狀態為記憶狀態A。請注意在這種情況下,VDETERMINE 的施加將下部記憶體結構654的電阻值從R RESET 切換至R SET 。因此,此程序繼續方塊712,其中下部記憶體結構654的電阻值切換至R RESET (例如,透過-V RESET 的施加),使電阻值切換裝置122d的記憶狀態是不會受目前讀取程序擾亂。然後,此方法於方塊714結束,確定電阻值切換裝置122d的記憶狀態是記憶狀態A。In block 708, the resistance value of the resistance value switching device 122d is again determined. If the resistance value detected at block 708 is R = R RESET + R SET , since the resistance value is not changed by the application of V DETERMINE , it can be determined that the memory state is the memory state D, and therefore, the process ends at block 710. And determining the memory state of the resistance value switching device 122d is the memory state D. Conversely, if the resistance detected at block 708 is R = R RESET + R SET , since the resistance value is changed by the application of V DETERMINE , the memory state can be determined to be memory state A. Note that in this case, the application of V DETERMINE switches the resistance of the lower memory structure 654 from R RESET to R SET . Therefore, the process continues with block 712 where the resistance value of the lower memory structure 654 is switched to R RESET (eg, by the application of -V RESET ) so that the memory state of the resistance value switching device 122d is not disturbed by the current reading program. . Then, the method ends at block 714, and it is determined that the memory state of the resistance value switching device 122d is the memory state A.
圖27至圖29繪示電阻值切換裝置122d實施例的電阻值切換特性圖,其滿足條件(2a)和(2b)的第二組。更具體地說,圖27顯示上部記憶體結構652的電阻值切換特性,圖28顯示下部記憶體結構654的電阻值切換特性,圖29顯示根據本實施例之電阻值切換裝置122d的整體電阻值切換特性。27 to 29 are diagrams showing the resistance value switching characteristic of the embodiment of the resistance value switching device 122d, which satisfies the second group of the conditions (2a) and (2b). More specifically, FIG. 27 shows the resistance value switching characteristic of the upper memory structure 652, FIG. 28 shows the resistance value switching characteristic of the lower memory structure 654, and FIG. 29 shows the overall resistance value of the resistance value switching device 122d according to the present embodiment. Switch characteristics.
如圖27,跨越上部記憶體結構652之正電壓+VRESET 會導致上部記憶體結構652的電阻值切換到與記憶狀態RRESET 相關聯的電阻值。跨越上部記憶體結構652之負電壓-VSET 會導致上部記憶體結構652的電阻值切換到與記憶狀態RSET 相關聯的電阻值。As shown in FIG. 27, a positive voltage +V RESET across the upper memory structure 652 causes the resistance value of the upper memory structure 652 to switch to the resistance value associated with the memory state R RESET . The negative voltage -V SET across the upper memory structure 652 causes the resistance value of the upper memory structure 652 to switch to the resistance value associated with the memory state R SET .
如圖28,跨越下部記憶體結構654之正電壓+V SET 會導致下部記憶體結構654的電阻值切換到與記憶胞狀態R SET 相關聯的電阻值。跨越下部記憶體結構654之負電壓-V RESET 會導致下部記憶體結構654的電阻值切換到與記憶胞狀態R RESET 相關聯的電阻值。As shown in FIG. 28, a positive voltage + V SET across the lower memory structure 654 causes the resistance value of the lower memory structure 654 to switch to a resistance value associated with the memory cell state R SET . The negative voltage across the lower memory structure 654 - V RESET causes the resistance value of the lower memory structure 654 to switch to the resistance value associated with the memory cell state R RESET .
圖27和圖28所示之上部記憶體結構652和下部記憶體結構654的組合,導致記憶裝置具有圖29所示之四種記憶狀態。記憶狀態A至D中的每一個均是與上部記憶體結構652和下部記憶體結構654的記憶狀態的電阻的各自總和相關聯。當上部記憶體結構652的電阻值具有與記憶狀態RSET 相關聯的電阻值以及下部記憶體結構654的電阻值具有與記憶狀態R RESET 相關聯的電阻值時,發生記憶狀態A,使得記憶狀態A之電阻值切換裝置122d的整體電阻值是RSET +R RESET 。當上部記憶體結構652的電阻值具有與記憶狀態RSET 相關聯的電阻值以及下部記憶體結構654的電阻值具有與記憶胞狀態R SET 相關聯的電阻值時,發生記憶胞狀態B,使得記憶狀態B之電阻值切換裝置122d的整體電阻值是R SET +RSET 。當上部記憶體結構652的電阻值具有與記憶狀態RREET 相關聯的電阻值以及下部記憶體結構654的電阻值具有與記憶狀態R REET 相關聯的電阻值時,發生記憶胞狀態C,使得記憶狀態C之電阻值切換裝置122d的整體電阻值是R RESET +RRESET 。當上部記憶體結構652的電阻值具有與記憶狀態RRESET 相關聯的電阻值以及下部記憶體結構654的電阻值具有與記憶狀態RSET 相關聯的電阻值時,發生記憶狀態D,使得記憶狀態D之電阻值切換裝置122d的整體電阻是R S ET +RRESET 。因此,電阻值切換裝置122d可以實現為具有記憶狀態A、B、C和D之四種狀態記憶裝置。The combination of the upper memory structure 652 and the lower memory structure 654 shown in Figures 27 and 28 results in the memory device having the four memory states shown in Figure 29. Each of the memory states A through D is associated with a respective sum of the resistances of the memory states of the upper memory structure 652 and the lower memory structure 654. When the resistance value of the upper memory structure 652 has a resistance value associated with the memory state R SET and the resistance value of the lower memory structure 654 has a resistance value associated with the memory state R RESET , the memory state A occurs, resulting in a memory state The overall resistance value of the resistance value switching device 122d of A is R SET + R RESET . When the resistance value of the upper memory structure 652 has a resistance value associated with the memory state R SET and the resistance value of the lower memory structure 654 has a resistance value associated with the memory cell state R SET , the memory cell state B occurs such that The overall resistance value of the resistance value switching device 122d of the memory state B is R SET + R SET . When the resistance value of the upper memory structure 652 has a resistance value associated with the memory state R REET and the resistance value of the lower memory structure 654 has a resistance value associated with the memory state R REET , the memory cell state C occurs, so that the memory The overall resistance value of the resistance value switching device 122d of the state C is R RESET + R RESET . When the resistance value of the upper memory structure 652 has a resistance value associated with the memory state R RESET and the resistance value of the lower memory structure 654 has a resistance value associated with the memory state R SET , the memory state D occurs, resulting in a memory state The overall resistance of the resistance value switching device 122d of D is R S ET + R RESET . Therefore, the resistance value switching device 122d can be realized as four state memory devices having the memory states A, B, C, and D.
參考圖30,其繪示讀取程序的流程圖,配合圖式與實施例描述讀取電阻值切換裝置122d的方法,該實施例為滿足條件(2a)和(2b)之第二組的四狀態的記憶裝置的實施例。Referring to FIG. 30, a flow chart of a reading program is described, and a method of reading the resistance value switching device 122d is described in conjunction with the drawings and the embodiment, which is a fourth group that satisfies the second group of conditions (2a) and (2b). An embodiment of a state memory device.
首先,於方塊800,電阻值切換裝置122d已經被程式化為記憶狀態A、B、C、或D之其中一種。此程序的其餘部分將允許讀取電阻值切換裝置122d,以決定記憶狀態A至D之其中一種被寫入電阻值切換裝置122d。First, at block 800, the resistance value switching device 122d has been programmed into one of the memory states A, B, C, or D. The remainder of this routine will allow reading of the resistance value switching means 122d to determine that one of the memory states A through D is written to the resistance value switching means 122d.
於方塊802,決定電阻值切換裝置122d的電阻值。電阻值切換裝置122d的電阻值可預期為與記憶狀態A至D分別對應的的四種電阻值之一。若電阻值R=RSET +R SET 被檢出,此程序結束於方塊804,並決定電阻值切換裝置122d的記憶狀態是記憶狀態B(RSET +R SET )。若電阻值R=RRESET +R RESET 被偵檢出,此程序結束於方塊805,並決定電阻值切換裝置122d的記憶狀態是記憶狀態C(RRESET +R RESET )。At block 802, the resistance value of the resistance value switching device 122d is determined. The resistance value of the resistance value switching device 122d can be expected to be one of the four resistance values respectively corresponding to the memory states A to D. If the resistance value R = R SET + R SET is detected, the routine ends at block 804 and it is determined that the memory state of the resistance value switching means 122d is the memory state B (R SET + R SET ). If the resistance value R = R RESET + R RESET is detected, the routine ends at block 805 and determines that the memory state of the resistance value switching means 122d is the memory state C (R RESET + R RESET ).
在目前實施例,與RSET 相關的電阻值大致上等於與R SET 相關的電阻值,並且與RRESET 相關的電阻值大致上等於與R RESET 相關的電阻值。因此,於方塊802第三種可能性是電阻值為R=RRESET +R SET =RSET +R RESET 。若這第三種可能性發生,則此程序將繼續,以便區分記憶狀態A(RSET +R RESET )和記憶狀態D(RRESET +R SET )。In the current embodiment, the resistance value associated with R SET is substantially equal to the resistance value associated with R SET , and the resistance value associated with R RESET is substantially equal to the resistance value associated with R RESET . Therefore, a third possibility at block 802 is that the resistance value is R = R RESET + R SET = R SET + R RESET . If this third possibility occurs, the program will continue to distinguish between memory state A (R SET + R RESET ) and memory state D (R RESET + R SET ).
接著在方塊806中,施加電壓VDETERMINE 於整個電阻值切換裝置122d,然後在方塊808中測量電阻值切換裝置122d的電阻值。在此實施例,VDETERMINE 的電壓是被選擇的,使得若記憶狀態為記憶狀態A時將會導致上部記憶體結構652從RSET 切換至RRESET ,但若記憶狀態為記憶狀態D時則不會產生任何改變。因此,VDETERMINE 的電壓是介於+VRESET 和+VSET 兩者之間。Next, in block 806, voltage V DETERMINE is applied to the entire resistance value switching device 122d, and then the resistance value of the resistance value switching device 122d is measured in block 808. In this embodiment, the voltage of V DETERMINE is selected such that if the memory state is memory state A, the upper memory structure 652 will be switched from R SET to R RESET , but if the memory state is memory state D, then Will make any changes. Therefore, the voltage of V DETERMINE is between +V RESET and +V SET .
在方塊808中,再次決定電阻值切換裝置122d的電阻。若在方塊808偵測到的電阻值為R=RRESET +R SET ,可決定記憶體狀態是記憶狀態D,因為電阻值並沒有因為VDETERMINE 的施加而改變。因此,此程序在方塊810結束並確定電阻值切換裝置122d的記憶狀態的是記憶狀態D。反之,若在方塊808偵測到的電阻值為R=RRESET +R RESET ,可以決定記憶狀態為記憶狀態A,其乃因為電阻值藉由VDETERMINE 的施加而改變。注意在這種情況下,VDETERMINE 的施加將上部記憶體結構652的電阻值從RSET 切換至RRESET 。因此,此程序繼續方塊812,其中上部記憶體結構654的電阻值切換回到RSET (例如,透過-VSET 的施加),使電阻值切換裝置122d的記憶狀態是不會受目前讀取程序擾亂。然後,此程序於方塊814結束,確定電阻值切換裝置122d的記憶狀態是記憶狀態A。In block 808, the resistance of the resistance value switching device 122d is again determined. If the resistance value detected at block 808 is R = R RESET + R SET , it can be determined that the memory state is the memory state D because the resistance value is not changed by the application of V DETERMINE . Therefore, the program ends at block 810 and determines the memory state of the resistance value switching device 122d. Conversely, if the resistance value detected at block 808 is R = R RESET + R RESET , the memory state can be determined to be memory state A because the resistance value is changed by the application of V DETERMINE . Note that in this case, the application of V DETERMINE switches the resistance value of the upper memory structure 652 from R SET to R RESET . Accordingly, the process continues with block 812 where the resistance value of the upper memory structure 654 is switched back to R SET (eg, by the application of -V SET ) so that the memory state of the resistance value switching device 122d is not affected by the current read procedure. disturb. Then, the routine ends at block 814, and it is determined that the memory state of the resistance value switching means 122d is the memory state A.
圖31繪示將記憶胞程式化之程序的流程圖。此程式化程序開始於方塊900,例如包括使用一個寫入致能訊號。在方塊902,判斷目前寫入是否為抹除記憶胞。若是,此程序繼續方塊904,而抹除存儲在電晶體120的資料。例如,若該電晶體120是一個浮置閘極電晶體,透過FN電子穿隧而抹除電晶體120。例如,在此種實施例中,電晶體120可設置具有範圍在-7伏特至-8伏特的抹除閘極電壓Vg,使得在施加抹除閘極電壓Vg期間,RHS位元可以利用施加4.5伏特的汲極電壓和0伏特的源極電壓來進行抹除;LHS位元可以利用施加0伏特的汲極電壓和4.5伏特的源極電壓來進行抹除。Figure 31 is a flow chart showing the procedure for stylizing memory cells. The stylized program begins at block 900 and includes, for example, the use of a write enable signal. At block 902, it is determined if the current write is an erase memory cell. If so, the process continues with block 904 and erases the data stored in transistor 120. For example, if the transistor 120 is a floating gate transistor, the transistor 120 is erased by FN electron tunneling. For example, in such an embodiment, the transistor 120 can be provided with an erase gate voltage Vg ranging from -7 volts to -8 volts such that during application of the erase gate voltage Vg, the RHS bit can utilize 4.5. The drain voltage of volts and the source voltage of 0 volts are erased; the LHS bit can be erased by applying a gate voltage of 0 volts and a source voltage of 4.5 volts.
在方塊906,電晶體120被程式化,在方塊908電阻值切換裝置122被程式化。然後該程式化操作在方塊910結束。At block 906, the transistor 120 is programmed and at block 908 the resistance value switching device 122 is programmed. The stylized operation then ends at block 910.
電晶體120和電阻值切換裝置122設置成電晶體120的程式化電壓不會干擾電阻值切換裝置122的記憶狀態,反之亦然。此外,當電阻值切換裝置122被程式化時,將電晶體120起動的閘極電壓Vg被選定為小於將該電晶體120程式化時的閘極電壓,但大於電晶體120的啟始電壓。這使得電晶體20被啟動,而得以對電阻值切換裝置122進行程式化,而不會影響電晶體120的程式化狀態。The transistor 120 and the resistance value switching device 122 are arranged such that the programmed voltage of the transistor 120 does not interfere with the memory state of the resistance value switching device 122, and vice versa. Further, when the resistance value switching device 122 is programmed, the gate voltage Vg at which the transistor 120 is activated is selected to be smaller than the gate voltage when the transistor 120 is programmed, but larger than the threshold voltage of the transistor 120. This causes the transistor 20 to be activated to program the resistance value switching device 122 without affecting the stylized state of the transistor 120.
一個特定的非限制的例子包括電晶體120,其具有範圍在7伏特至12伏特(500ns)之程式化(PROGRAM)閘極電壓,能夠儲存第一位元和第二位元(RHS位元和LHS位元)。RHS位元可以使用Vd=3.5伏特和Vs=Vb=0伏特來進行程式化;在LHS位元可以使用Vd=Vb=0伏特及Vs=3.5伏特來進行程式化。在這個例子中,抹除(ERASE)閘極電壓的範圍在-7伏特和-8伏特。RHS位元可以使用Vd=4.5伏特和Vs=Vb=0伏特來進行抹除;LHS位元可以使用Vd=Vb=0伏特和Vs=4.5伏特來抹除。電阻值切換裝置122包括RRAM,其中設定(SET)電壓為+/-2伏,而重置(RESET)電壓為+/-3伏特。當施加給電晶體120的閘極電壓小於程式化閘極電壓但大於電晶體120的啟始電壓Vt時,電壓被施加至電阻值切換裝置122。這僅僅是提供了明確用途的一個例子,還可以有許多的其他實施方式。A specific, non-limiting example includes a transistor 120 having a programmable (PROGRAM) gate voltage ranging from 7 volts to 12 volts (500 ns) capable of storing a first bit and a second bit (RHS bit and LHS bit). The RHS bit can be programmed using Vd = 3.5 volts and Vs = Vb = 0 volts; the LHS bit can be programmed using Vd = Vb = 0 volts and Vs = 3.5 volts. In this example, the erase (ERASE) gate voltage ranges from -7 volts to -8 volts. The RHS bit can be erased using Vd = 4.5 volts and Vs = Vb = 0 volts; the LHS bit can be erased using Vd = Vb = 0 volts and Vs = 4.5 volts. The resistance value switching device 122 includes an RRAM in which the set (SET) voltage is +/- 2 volts and the RESET voltage is +/- 3 volts. When the gate voltage applied to the transistor 120 is less than the programmed gate voltage but greater than the start voltage Vt of the transistor 120, the voltage is applied to the resistance value switching device 122. This is just one example of providing a clear use, and there are many other implementations.
圖32繪示讀取記憶胞112之程序的流程圖。讀取程序開始於方塊900,例如包括使用讀取致能訊號(Read Enable signal)。於方塊952,讀取來自電晶體120及電阻值切換裝置的資料,然後該程序於方塊954結束。在方塊952的讀取操作端視所使用的電晶體類型和電阻值切換裝置類型而有所改變。例如,讀取操作可以包括本文所述方法中電阻值切換裝置122的各種實施例。閘極電壓Vg將被設定為一個預定的讀取閘極電壓(predetermined READ gate voltage),則汲極電壓Vd和源極電壓Vs便被設定。透過電阻值切換裝置122的電阻也被測量。32 is a flow chart showing the procedure for reading memory cells 112. The reading process begins at block 900 and includes, for example, the use of a Read Enable signal. At block 952, the data from the transistor 120 and the resistance value switching device is read, and the process ends at block 954. The read operation at block 952 varies depending on the type of transistor used and the type of resistance value switching device. For example, the read operation can include various embodiments of the resistance value switching device 122 in the methods described herein. The gate voltage Vg is set to a predetermined READ gate voltage, and the drain voltage Vd and the source voltage Vs are set. The resistance through the resistance value switching device 122 is also measured.
在上述特定例子中,RHS位元可以利用施加Vd=1.6伏特和Vs=Vb=0伏特而(並且電阻值切換裝置122的電阻值R也被測量);LHS位元可以利用施加Vd=Vb=0伏特和Vs=1.6伏特而讀取(並且電阻值切換裝置122的電阻R也被測量)。In the above specific example, the RHS bit can be applied with Vd = 1.6 volts and Vs = Vb = 0 volts (and the resistance value R of the resistance value switching device 122 is also measured); the LHS bit can be applied with Vd = Vb = 0 volts and Vs = 1.6 volts are read (and the resistance R of the resistance value switching device 122 is also measured).
雖然本發明已以實施例揭露如上,然其並非用以限定本發明,任何所屬技術領域中具有通常知識者,在不脫離本發明之精神和範圍內,當可作些許之更動與潤飾,故本發明之保護範圍當視後附之申請專利範圍所界定者為準。Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.
100...記憶裝置100. . . Memory device
102...記憶體陣列102. . . Memory array
104...行解碼器(column decoder)104. . . Row decoder
106...感測放大器(sense amplifier)106. . . Sense amplifier
108...列解碼器(row decoder)108. . . Row decoder
110...源極開關(source switch)110. . . Source switch
BL0-BL5...位元線BL0-BL5. . . Bit line
SL...源極線SL. . . Source line
WL0-WL4...字元線WL0-WL4. . . Word line
112...記憶胞112. . . Memory cell
120...電晶體120. . . Transistor
122、122a、122b、122c、122d...電阻值切換裝置122, 122a, 122b, 122c, 122d. . . Resistance value switching device
130...基板130. . . Substrate
132...內金屬介電層132. . . Internal metal dielectric layer
134...第一電極層134. . . First electrode layer
136...氧化鎢層136. . . Tungsten oxide layer
138...第一介電層138. . . First dielectric layer
140...第二介電層140. . . Second dielectric layer
142...第二電極層142. . . Second electrode layer
144...第一界面區144. . . First interface area
146...第二界面區146. . . Second interface area
V1、V2...負電壓V1, V2. . . Negative voltage
V3、V4...正電壓V3, V4. . . Positive voltage
R1、R2...電阻R1, R2. . . resistance
R RESET 、RRESET 、R SET 、RSET ...狀態 R RESET , R RESET , R SET , R SET . . . status
VDETERMINE ...電壓V DETERMINE . . . Voltage
200...程式化電阻值切換裝置200. . . Stylized resistance value switching device
202...讀取電阻值202. . . Read resistance value
204...結束(RSET 或R SET )204. . . End (R SET or R SET )
206...施加VDETERMINE 206. . . Apply V DETERMINE
208...讀取電阻值208. . . Read resistance value
210...結束(RRESET )210. . . End (R RESET )
212...重新程式化至R RESET 212. . . Reprogramming to R RESET
214...結束(R RESET )214. . . End ( R RESET )
R RESET1 、RRESET1 、R RESET2 、RRESET2 ...狀態 R RESET1 , R RESET1 , R RESET2 , R RESET2 . . . status
300...程式化電阻值切換裝置300. . . Stylized resistance value switching device
302...讀取電阻值302. . . Read resistance value
304...結束(RSET 或R SET )304. . . End (R SET or R SET )
306...結束(RRESET )306. . . End (R RESET )
308...結束(R RESET )308. . . End ( R RESET )
402...基板402. . . Substrate
404...內金屬介電層404. . . Internal metal dielectric layer
406...第一電極層406. . . First electrode layer
408...導電拴層408. . . Conductive layer
410...第一介電層410. . . First dielectric layer
412...第二介電層412. . . Second dielectric layer
414...固體電解質層414. . . Solid electrolyte layer
416...第二電極層416. . . Second electrode layer
452...基板452. . . Substrate
454...內金屬介電層454. . . Internal metal dielectric layer
456...第一電極層456. . . First electrode layer
458...導電拴層458. . . Conductive layer
460...第一介電層460. . . First dielectric layer
462...第二介電層462. . . Second dielectric layer
464...第一固體電解質層464. . . First solid electrolyte layer
466...第二電極層466. . . Second electrode layer
468...第二固體電解質層468. . . Second solid electrolyte layer
470...第二電極層470. . . Second electrode layer
VS1 、VS3 ...正電壓V S1 , V S3 . . . Positive voltage
VS2 、VS4 ...負電壓V S2 , V S4 . . . Negative voltage
A、B、C、D...記憶狀態A, B, C, D. . . Memory state
500...程式化電阻值切換裝置500. . . Stylized resistance value switching device
502...讀取電阻值502. . . Read resistance value
504...結束(RRESET +R RESET )504. . . End (R RESET + R RESET )
506...施加VDETERMINE 506. . . Apply V DETERMINE
508...讀取電阻值508. . . Read resistance value
510...結束(RRESET +RSET )510. . . End (R RESET +R SET )
512...重新程式化至RSET +RRESET 512. . . Reprogramming to R SET +R RESET
514...結束(RSET +R RESET )514. . . End (R SET + R RESET )
600...程式化電阻值切換裝置600. . . Stylized resistance value switching device
602...讀取電阻值602. . . Read resistance value
604...結束(RRESET +R RESET )604. . . End (R RESET + R RESET )
606...結束(RRESET +R SET )606. . . End (R RESET + R SET )
608...結束(RSET +R RESET )608. . . End (R SET + R RESET )
652...上部記憶體結構652. . . Upper memory structure
654...下部記憶體結構654. . . Lower memory structure
+V SET 、+VRESET ...正電壓+ V SET , +V RESET . . . Positive voltage
-V RESET 、-VSET ...負電壓- V RESET , -V SET . . . Negative voltage
700...程式化電阻值切換裝置700. . . Stylized resistance value switching device
702...讀取電阻值702. . . Read resistance value
704...結束(RSET +R SET )704. . . End (R SET + R SET )
705...結束(RRESET +R RESET )705. . . End (R RESET + R RESET )
706...施加VDETERMINE 706. . . Apply V DETERMINE
708...讀取電阻值708. . . Read resistance value
710...結束(RRESET +R SET )710. . . End (R RESET + R SET )
712...重新程式化至RSET +R RESET 712. . . Reprogramming to R SET + R RESET
714...結束(RSET +R RESET )714. . . End (R SET + R RESET )
800...程式化電阻值切換裝置800. . . Stylized resistance value switching device
802...讀取電阻值802. . . Read resistance value
804...結束(RSET +R SET )804. . . End (R SET + R SET )
805...結束(RRESET +R RESET )805. . . End (R RESET + R RESET )
806...施加VDETERMINE 806. . . Apply V DETERMINE
808...讀取電阻值808. . . Read resistance value
810...結束(RRESET +R SET )810. . . End (R RESET + R SET )
812...重新程式化至RSET +R RESET 812. . . Reprogramming to R SET + R RESET
814...結束(RSET +R RESET )814. . . End (R SET + R RESET )
900...程式化開始900. . . Stylized start
902...抹除狀態?902. . . Erase status?
904...抹除904. . . Erase
906...程式化Vt906. . . Stylized Vt
908...程式化R908. . . Stylized R
910...程式化結束910. . . Stylized end
950...讀取開始950. . . Read start
952...讀取Vt、R952. . . Read Vt, R
954...讀取結束954. . . End of reading
R1~R4...電阻值R1 ~ R4. . . resistance
VtL1 ~VtL4 ...啟始電壓V tL1 ~ V tL4 . . . Starting voltage
圖1為根據本發明實施例所繪示的記憶裝置之方塊圖。FIG. 1 is a block diagram of a memory device according to an embodiment of the invention.
圖2為根據本發明實施例所繪示的記憶胞之示意圖。FIG. 2 is a schematic diagram of a memory cell according to an embodiment of the invention.
圖3A和圖3B為根據圖2所示電阻值切換裝置的某些實施例所繪示的電阻值切換裝置示意圖。3A and 3B are schematic diagrams showing a resistance value switching device according to some embodiments of the resistance value switching device shown in FIG. 2.
圖4A至圖4E為圖3A和圖3B中所示電阻值切換裝置的對稱雙態實施例的電阻值切換特性。4A to 4E are resistance value switching characteristics of a symmetric two-state embodiment of the resistance value switching device shown in Figs. 3A and 3B.
圖5繪示在圖3A和圖3B中所示電阻值切換裝置的對稱雙態實施例的記憶狀態與施加電壓之間的圖形關係。Figure 5 is a graphical representation of the relationship between the memory state and the applied voltage of the symmetric two-state embodiment of the resistance value switching device shown in Figures 3A and 3B.
圖6繪示在圖3A和圖3B所示讀取電阻值切換裝置的對稱雙態實施例的讀取方法之流程圖。6 is a flow chart showing a reading method of the symmetric two-state embodiment of the read resistance value switching device shown in FIGS. 3A and 3B.
圖7繪示在圖3A和圖3B所示電阻值切換裝置的對稱三態實施例的切換特性。Figure 7 is a diagram showing the switching characteristics of the symmetric three-state embodiment of the resistance value switching device shown in Figures 3A and 3B.
圖8繪示在圖3A和圖3B所示電阻值切換裝置的非對稱雙態實施例的切換特性。Figure 8 is a diagram showing the switching characteristics of the asymmetric two-state embodiment of the resistance value switching device shown in Figures 3A and 3B.
圖9繪示在圖3A和圖3B所示電阻值切換裝置的非對稱雙狀態/三狀態實施例的切換特性。Figure 9 is a diagram showing the switching characteristics of the asymmetric dual state/three state embodiment of the resistance value switching device shown in Figures 3A and 3B.
圖10是根據圖8所示非對稱實施例所繪示之讀取電阻值切換裝置的流程。FIG. 10 is a flow chart of the read resistance value switching device according to the asymmetric embodiment shown in FIG.
圖11是根據圖2所示電阻值切換裝置實施例所繪示之電阻值切換裝置示意圖。FIG. 11 is a schematic diagram of a resistance value switching device according to the embodiment of the resistance value switching device shown in FIG. 2.
圖12繪示圖11所示電阻值切換裝置在程式化操作和讀取操作期間電壓與電流的關係。FIG. 12 is a diagram showing the relationship between voltage and current during the staging operation and the reading operation of the resistance value switching device shown in FIG. 11.
圖13是根據圖2所示電阻值切換裝置實施例所繪示之電阻值切換裝置示意圖。FIG. 13 is a schematic diagram of a resistance value switching device according to the embodiment of the resistance value switching device shown in FIG. 2.
圖14是繪示圖13所示電阻值切換裝置的對稱、雙PMC(dual-PMC)實施例的上部PMC結構的電阻切換特性。Fig. 14 is a view showing the resistance switching characteristics of the upper PMC structure of the symmetric, dual PMC (dual-PMC) embodiment of the resistance value switching device shown in Fig. 13.
圖15繪示圖13所示電阻值切換裝置的對稱、雙PMC實施例的下部PMC結構的電阻值切換特性。FIG. 15 is a diagram showing the resistance value switching characteristics of the lower PMC structure of the symmetric, dual PMC embodiment of the resistance value switching device shown in FIG.
圖16是繪示雙PMC結構的電阻值切換關係圖,此雙PMC結構包括具有圖14和圖15分別所示的電阻值切換特性的上部和下部PMC結構。16 is a diagram showing a resistance value switching relationship of a dual PMC structure including upper and lower PMC structures having resistance value switching characteristics shown in FIGS. 14 and 15, respectively.
圖17是繪示根據圖16所示用在電阻值切換裝置中讀取方法之流程圖。Figure 17 is a flow chart showing the reading method used in the resistance value switching device shown in Figure 16.
圖18是繪示圖13所示電阻值切換裝置的非對稱、雙PMC實施例的上部PMC結構的電阻值切換特性。Fig. 18 is a view showing the resistance value switching characteristic of the upper PMC structure of the asymmetric, dual PMC embodiment of the resistance value switching device shown in Fig. 13.
圖19是繪示圖13所示電阻值切換裝置的非對稱、雙PMC實施例的下部PMC結構的電阻值切換特性。Fig. 19 is a view showing the resistance value switching characteristic of the lower PMC structure of the asymmetric, dual PMC embodiment of the resistance value switching device shown in Fig. 13.
圖20繪示雙PMC(dual-PMC)結構的電阻值切換關係圖,此雙PMC結構包括具有圖18和圖19分別所示的電阻值切換特性的上部和下部PMC結構。20 is a diagram showing a resistance value switching relationship of a dual PMC (dual-PMC) structure including upper and lower PMC structures having resistance value switching characteristics shown in FIGS. 18 and 19, respectively.
圖21是根據圖20所示電阻值切換裝置所繪之讀取程序之流程圖。Fig. 21 is a flow chart showing the reading procedure of the resistance value switching device shown in Fig. 20.
圖22是根據圖2所示電阻值切換裝置之數個實施例所繪示之電阻值切換裝置的示意圖。FIG. 22 is a schematic diagram of a resistance value switching device according to several embodiments of the resistance value switching device shown in FIG.
圖23為圖22所示電阻值切換裝置實施例的上部記憶體結構的電阻值切換特性。Fig. 23 is a view showing the resistance value switching characteristic of the upper memory structure of the embodiment of the resistance value switching device shown in Fig. 22.
圖24繪示圖22所示電阻值切換裝置實施例的下部記憶體結構的電阻值切換特性。Figure 24 is a diagram showing the resistance value switching characteristics of the lower memory structure of the embodiment of the resistance value switching device shown in Figure 22.
圖25繪示電阻值切換裝置的電阻值切換特性,此電阻值切換裝置包括具有圖23和圖24分別所示的電阻值切換特性的上部記憶體結構和下部記憶體結構。Fig. 25 is a diagram showing the resistance value switching characteristic of the resistance value switching device including the upper memory structure and the lower memory structure having the resistance value switching characteristics shown in Figs. 23 and 24, respectively.
圖26是根據圖25所示電阻值切換裝置所繪示之讀取程序之流程圖。Figure 26 is a flow chart showing the reading procedure of the resistance value switching device shown in Figure 25.
圖27繪示圖22所示電阻切值換裝置實施例的上部記憶體結構的電阻值切換特性。FIG. 27 is a diagram showing the resistance value switching characteristic of the upper memory structure of the embodiment of the resistor value switching device shown in FIG. 22.
圖28繪示圖22所示電阻值切換裝置實施例的下部記憶體結構的電阻值切換特性。FIG. 28 is a diagram showing the resistance value switching characteristic of the lower memory structure of the embodiment of the resistance value switching device shown in FIG. 22.
圖29繪示電阻值切換裝置的電阻值切換特性,此電阻值切換裝置包括具有圖27和圖28分別所示的電阻值切換特性的上部記憶體結構和下部記憶體結構。Fig. 29 is a diagram showing the resistance value switching characteristic of the resistance value switching device including the upper memory structure and the lower memory structure having the resistance value switching characteristics shown in Figs. 27 and 28, respectively.
圖30是根據圖29所示電阻值切換裝置所繪示之讀取程序之流程圖。Figure 30 is a flow chart showing the reading procedure according to the resistance value switching device shown in Figure 29.
圖31繪示圖2所示記憶胞的程式化程序之流程圖。Figure 31 is a flow chart showing the stylization procedure of the memory cell shown in Figure 2.
圖32繪示圖2所示記憶胞的讀取程序之流程圖。32 is a flow chart showing the reading procedure of the memory cell shown in FIG. 2.
圖33繪示圖2所示記憶胞之一實施例之I-V圖。Figure 33 is a diagram showing an I-V of an embodiment of the memory cell shown in Figure 2.
圖34繪示圖2所示記憶胞之另一實施例之I-V圖。FIG. 34 is a diagram showing an I-V of another embodiment of the memory cell shown in FIG.
100...記憶裝置100. . . Memory device
102...記憶體陣列102. . . Memory array
104...行解碼器(column decoder)104. . . Row decoder
106...感測放大器(sense amplifier)106. . . Sense amplifier
108...列解碼器(row decoder)108. . . Row decoder
110...源極開關(source switch)110. . . Source switch
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