TWI443662B - Nonvolatile memory device - Google Patents

Description

Non-volatile memory device

This invention relates to an electronic memory device, and more particularly to a semiconductor memory device suitable for use as a non-volatile memory device.

Electronic memory devices are well known and found in a variety of electronic systems. For example, there are electronic memory devices (sometimes referred to as computer memory) in computers and other computing devices. Many removable or stand-alone electronic memory devices such as memory cards or solid state data storage systems are well known. For example, in a digital camera, a mobile memory card can be used to store photos or a digital video recorder to store movies recorded by a digital video recorder.

Most electronic memory devices can be classified as volatile or non-volatile. In general, volatile electronic memory devices require power to maintain stored messages. Examples of volatile electronic memory devices are static random access memory (SRAM) or dynamic random access memory (DRAM), which are reserved only when the computer is turned on. Stored data and lose stored data when the computer is turned off or powered off. Conversely, in general, non-volatile electronic memory devices are capable of retaining stored data without external power. Examples of non-volatile memory are, for example, memory cards, such as memory cards commonly used in digital cameras. The camera can use this card to record photos and retain photo data even if you remove the card from the camera.

As the functionality of electronic memory devices in the system increases, so does the need for data storage capacity. For example, more powerful computers and software usually have more random access memory (RAM) for better operation; high-resolution cameras with larger storage capacity cards can provide Larger images and video files. Therefore, this trend has led the electronic memory device industry to seek to increase the data storage capacity of memory devices. However, it can be achieved simply by adding enough capacity. As the storage capacity of the data increases, it is generally necessary to maintain a satisfactory size of the memory device, and even the size of the memory device must be made smaller. Therefore, another trend is to increase the amount of data stored at a given size, that is, to increase the bit density. On the other hand, what needs to be considered is the cost. For example, as the bit density increases, the cost of the electronic memory device must still be maintained or reduced. In other words, it is desirable to be able to reduce the bit cost of the electronic memory device (cost per bit). In addition, what needs to be considered is related performance, such as faster access to data in the electronic memory device.

The method of increasing the bit density can be achieved by reducing the size of individual memory cells. For example, as the manufacturing method is improved, a small structure can be formed, thereby allowing a smaller memory cell to be fabricated. However, some predictions show that the cost of bits used in this way will increase in the future, because at some point, the cost of the process will increase faster than the memory cell. Therefore, there is an urgent need to find various alternative methods to increase the bit density of electronic memory devices.

Memory devices and methods related to memory devices are described below. In accordance with one aspect of the present disclosure, a memory device can include a memory cell array, wherein each memory cell includes a transistor and a resistance switching device in series with the transistor. The transistor and the resistance value switching device each have the ability to independently store one or more bit metadata. The transistor can include a first end, a second end, and a gate terminal, and the transistor can be configured to switch between a plurality of different starting voltages associated with respective memory states. The resistance value switching device may be connected in series with one of the first and second ends of the transistor. The resistance value switching device can be configured to switch between a plurality of different resistance values associated with respective memory states. The resistance value switching device may include a first memory layer, a second memory layer, and a dielectric layer formed between the first memory layer and the second memory layer.

According to another aspect of the present disclosure, a memory device can include a first control line, a second control line, and a memory cell in communication with the first control line and the second control line. The memory cell includes a transistor and a resistance value switching device connected in series with the transistor. The transistor and the resistance value switching device each have the ability to independently store one or more bit metadata. The transistor can include a first end, a second end, and a gate terminal. The transistor can be configured to switch between a plurality of different starting voltages associated with respective memory states. The resistance value switching device may be in series with the first control line and the first end of the transistor. The resistance value switching device can be configured to switch between a plurality of different resistors associated with respective memory states. The resistance value switching device may include a first memory layer, a second memory layer, and a dielectric layer formed between the first memory layer and the second memory layer.

According to still another aspect of the present invention, a method for reading and writing a memory cell for reading and writing to a memory cell including a transistor and a resistance value in series with the transistor is provided. A switching device, wherein the transistor and the resistance value switching device each have the ability to independently store one or more bit metadata. For example, in accordance with one aspect of the present disclosure, a reading method can include detecting an enable voltage of a transistor of a memory cell, the transistor being configured to switch between a plurality of different start voltages associated with each memory state . The reading method may also include detecting a resistance of the resistance value switching device of the memory cell, the resistance value switching device being configured to switch between a plurality of different resistances associated with respective memory states. The resistance value switching device may include a first memory layer, a second memory layer, and a dielectric layer formed between the first memory layer and the second memory layer. These and other features, aspects, and embodiments of the present invention are described in detail below as the "embodiments".

1 is a block diagram of a memory device 100 in accordance with an embodiment of the invention. The memory device 100 can include a memory array 102, a column decoder 104, a sense amplifier 106, a row decoder 108, and a source switch 110. . Memory array 102 can include a plurality of memory cells 112.

The memory device 100 is configured such that the memory cells 112 are arranged in a manner similar to word lines WL0-WL4, bit lines BL0-BL5, and source lines SL arranged in rows and columns. The NOR flash memory architecture. Bit lines BL0-BL5 of memory array 102 can be coupled to sense amplifier 106. Word lines WL0-WL4 may be coupled to column decoder 108. The source line SL can be connected to the source switch 110. The address signal and the control signal can be transmitted to the address device and the control signal to input the address signal and the control signal into the memory device 100, and are connected to the row decoder 104, the sense amplifier 106, the column decoder 108, and the source switch 110. And in addition, it can be used to read and write access memory array 102.

Row decoder 104 can be coupled to sense amplifier 106 by controlling and selecting column select lines for the column select lines. The sense amplifier 106 can be configured to receive input data to the memory array 102 and output data from the memory array 102 via input/output (I/O) data lines.

2 is a schematic diagram of a memory cell 112 in accordance with an embodiment of the present invention. The memory cell 112 includes a transistor 120 and a resistance value switching device 122.

The transistor 120 can be configured such that the gate is connected to the word line WLn, the drain is connected to the resistance value switching device 122, and the source is connected to the source line SL. The transistor 120 can be a floating gate, an n-type transistor, a p-type transistor, or a Fin-FET configured such that the starting voltage Vt of the transistor 120 can be varied between two or more values, wherein the starting voltage Some values of Vt are related to the state of the respective memory cells. For example, the transistor 120 can be a single-level cell (SLC) floating gate transistor, a multi-level cell (MLC) floating gate transistor, and a nano-level cell (MLC) floating gate transistor. A nano-crystal flash transistor, or a nitride trap device.

Thus, the transistor 120 can be configured to store a plurality of states of the starting voltage Vt at one or more locations. For example, in some embodiments, the transistor 120 can be configured as a 1-bit memory device that can be programmed into one of two different starting voltages Vt. These embodiments may include embodiments in which the transistor 120 is a single-stage memory cell floating gate transistor. In some embodiments, for example, the transistor 120 can be configured as a 2-bit memory device that can be programmed into one of four different starting voltages Vt. These embodiments may include embodiments in which the transistor 120 is a multi-level memory cell floating gate transistor. Embodiments of the transistor 120 include a floating gate device that can be programmed using hot electron injection and Fowler-Nordheim (FN) electron tunneling for erasing.

The resistance value switching device 122 may be connected between the bit line BLn and the drain of the transistor 120. The resistance value switching device 122 can be configured such that the resistance of the resistance value switching device 122 varies between a plurality of resistance values, some of which are related to respective memory cell states. For example, the resistance value switching device 122 can be, for example, a resistive memory device as described in U.S. Patent No. 7,524, 722, the disclosure of which is incorporated herein by reference.

Thus, in some embodiments, memory cell 112 can be configured to store one or more bits. For example, in some embodiments, the transistor 120 can be configured to switch between two memory states, and the resistance value switching device 122 can be configured to switch between two memory states such that the memory cell 112 is a 2-bit memory. The device can have a total of four memory states.

33 depicts an IV curve of an embodiment in which the transistor 120 is configurable to switch between 4 (2^2) memory states associated with respective start voltages _Vt1 - _Vt4 . The resistance value switching device 122 can be configured to switch between 4 (2^2) memory cell states associated with respective resistance values R1-R4. Thus, the transistor 120 is capable of storing two bits of data. In total, the transistor 120 of the present embodiment and the resistance value switching device 122 provide the ability of the memory cell 112 to have a total of 2^(2+2)=16 memory cell states, thus providing a 4-bit memory cell 112.

Figure 34 depicts an IV curve of an embodiment in which the transistor 120 can be multi-ordered and configured to switch between 16 (2^4) memory states associated with respective start voltages. The starting voltage includes four starting voltages (V _tL1 - V _tL4 ) for each step. The resistance value switching device 122 can be configured to switch between 4 (2^2) memory cell states associated with respective resistance values R1-R4. Therefore, the transistor 120 can store four bit data and the resistance value switching device 122 can store two bit data. In total, the transistor 120 of the present embodiment and the resistance value switching device 122 provide the ability of the memory cell 112 to have a total of 2^(4+2)=64 memory cell states, thus providing a 6-bit memory cell 112. Alternatively, the resistance value switching device 122 can be configured to switch between 8 (2^3) memory states. In the above embodiment, the transistor 120 and the resistance value switching device 122 provide the ability of the memory cell 112 to have a total of 2^(4+3)=128 memory cell states, thus providing a 7-bit memory cell 112.

Further embodiments may include a transistor 120 configured to switch between a set of selected number N1 start voltages and respective memory states, the resistance value switching device 122 being configured in a set of selected number N2 resistors and respective memories The states are switched such that the memory cells 112 are thus configured to have a memory state of a total number N1 + N2.

3A is a schematic diagram of a resistance value switching device 122a, and FIG. 3A is based on some embodiments of a resistance value switching device 122. The resistance value switching device 122a includes a substrate 130, an intermetal dielectric (IMD) layer 132, a first electrode layer 134, a tungsten oxide layer 136, a first dielectric layer 138, a second dielectric layer 140, and a second Electrode layer 142.

The substrate 130 may be a germanium substrate 132, and the inner metal dielectric layer 132 may be an oxide layer or other electrically insulating layer formed on the substrate 130 by a known method, such as by chemical vapor deposition (CVD). Electrical-insulating layer).

The first electrode 134 may be formed of titanium nitride (TiN) and deposited on the IMD layer 132 by CVD or physical vapor deposition (PVD). In addition, the material of the first electrode 134 may include doped polysilicon, aluminum, copper, or tantalum nitride (TaN).

A tungsten oxide layer 136 is formed over the first electrode 134. The first dielectric layer 138 and the second dielectric layer 140 are located on the side of the tungsten oxide layer 136 and are formed on the first electrode 134. Dielectric layers 138 and 140 may comprise, for example, hafnium oxide (SiO ₂ ), tantalum nitride (Si ₃ N ₄ ) or similar insulating materials. The structure of the tungsten oxide layer 136, the first dielectric layer 138 and the second dielectric layer 140 may be formed by forming a continuous dielectric layer as the dielectric layers 138 and 140 over the first electrode. The method of forming it is, for example, a chemical vapor deposition method. Next, a portion of the continuum dielectric layer is removed, such as by lithography and etching, to form a gap between the first dielectric layer 138 and the second dielectric layer 140. Next, a tungsten oxide layer 136 may be formed in the gap between the first dielectric layer 138 and the second dielectric layer 140. More specifically, the tungsten oxide layer 136 may be formed by depositing tungsten in a gap between the first dielectric layer 138 and the second dielectric layer 140, and then performing an oxidation process to oxidize the tungsten. For example, a thermal oxidation process can be used to diffuse oxygen to most or all of the tungsten layer, resulting in the formation of a tungsten oxide layer 136.

The second electrode 142 may be titanium nitride (TiN) deposited on the tungsten oxide layer 136 by CVD or PVD. Likewise, the second electrode 142 can extend over the dielectric layers 138 and 140. The material of the second electrode 142 may optionally include doped polysilicon, aluminum, copper or tantalum nitride (TaN).

The total oxidation of the tungsten oxide layer 136 can form a first interface region 144 and a second interface region 146 having an adjustable resistance. FIG. 3B illustrates the locations of the first interface region 144 and the second interface region 146. The first interface region 144 includes a region at the interface of the first electrode 134 and the tungsten oxide layer 136. The second interface region 146 includes a region at the interface of the second electrode 142 and the tungsten oxide layer 136.

4A-4E illustrate the resistance switching characteristics of the symmetric two-state embodiment of the resistance value switching device 122a. That is, in the present embodiment, the resistance value switching device 122a includes two interface regions 144 and 146, each of which has two resistance values (memory cell state), and each interface region is substantially at least substantially different from the other interface region. symmetry. In another embodiment, which includes the embodiments described herein, may include unsymmetric embodiments and/or include more than two resistance values per interface region.

The electrical resistance between the first electrode 134 and the second electrode 142 can be adjusted between the two resistance values R1 and R2 through the tungsten oxide layer 136. The resistance value switching behavior of the resistance value switching device 122a may occur in the first interface region 144 or the second interface region 146. As described in detail later with reference to FIGS. 4A through 4E, the voltage pulse can be used to select between the first interface region 144 or the second interface region 146 as an interface region for controlling the switching behavior of the resistance value switching device 122a. . This is important because the voltage required to switch the resistance value from R1 to R2 (and vice versa) depends on whether the first interface region 144 or the second interface region 146 is currently switching the resistance value switching device 122a. behavior.

4A to 4E illustrate resistance value switching characteristics of a symmetric two-state embodiment of the resistance value switching device 122a. That is, in the present embodiment, the resistance value switching device 122a includes two interface regions 144 and 146, each of which has two resistance values (memory states), each interface region being at least substantially symmetric with respect to other interface regions. Another embodiment, including those described herein, can include embodiments that are asymmetric and/or that each interface region includes more than two resistance values.

The electrical resistance between the first electrode 134 and the second electrode 142 is adjustable between the two resistance values R1 and R2 through the tungsten oxide layer 136. The resistance value switching behavior of the resistance value switching device 122a may occur in the first interface region 144 or the second interface region 146. As described in detail later with reference to FIGS. 4A through 4E, the voltage pulse can be used to select between the first interface region 144 or the second interface region 146 as an interface region for controlling the switching behavior of the resistance value switching device 122a. . This is important because the voltage required to switch the resistance value from R1 to R2 (and vice versa) depends on whether the first interface region 144 or the second interface region 146 is currently switching the resistance value switching device 122a. behavior.

Referring first to FIG. 4A, the figure shows the resistance value switching characteristic of the resistance value switching device 122a of the present embodiment when the second interface region 146 controls the resistance value switching characteristic. Here, the resistance value switching device 122a may be controlled to have a reset resistance value R1 or a set resistance value R2. If the resistance value of the resistance value switching device 122a is R1, the negative voltage V2 is applied across the resistance value switching device 122a, and the resistance value can be lowered from R1 to R2 between the voltage supply terminal and the ground as shown in FIG. 3B. Similarly, if the resistance value of the resistance value switching device 122a is R2, the positive voltage V4 is applied across the resistance value switching device 122a, and the resistance value can be increased from R2 to R1.

FIG. 4B illustrates a procedure for switching control from the second interface region 146 to the first interface region 144. Specifically, by applying the negative voltage V1 across the resistance value switching device 122a, the control of the resistance value switching characteristic of the resistance value switching device 122a of the present embodiment can be switched from the second interface region 146 to the first interface region 144.

The result of the switching in Fig. 4B is as shown in Fig. 4C, in which the first interface region 146 is now controlling the resistance value switching characteristic of the resistance value switching device 122a of the present embodiment. In order to observe the resistance value switching characteristic of the resistance value switching device 122a of the present embodiment when the first interface region 144 is being controlled and the electrical value resistance switching characteristic of the resistance value switching device 122a of the present embodiment when the second interface region 146 is being controlled The difference between the behavior shown in Figure 4C can be compared to Figure 4A. Referring now to FIG. 4C, control is performed with the first interface region 144, by applying a positive voltage V3 across the resistance value switching device 122a, the resistance value can be lowered from R1 to R2, and by applying a negative voltage V1 across the resistance value switching device 122a, The resistance value can be increased from R2 to R2.

FIG. 4D illustrates a flow of switching control from the first interface region 144 to the second interface region 146. Specifically, by applying the positive voltage V4 across the resistance value switching device 122a, the control of the resistance value switching characteristic of the resistance value switching device 122a of the present embodiment can be switched from the first interface region 144 to the second interface region 146. Specifically, by applying the positive voltage V4 across the resistance value switching device 122a, the control of the resistance value switching characteristic of the present embodiment of the resistance value switching device 122a can be switched from the first interface region 144 to the second interface region 146.

The switching result in Fig. 4D is the same as Fig. 4A, as shown in Fig. 4E, in which the second interface region 146 again controls the resistance value switching characteristic of the resistance value switching device 122a of the present embodiment.

Therefore, the resistance value switching means 122a can be set to any of four states, and can be used as four memory states: (1) the first interface control and the resistance value = R1 (" R _RESET "state); (2) the first Interface control and resistance = R2 (" R _SET "status); (3) Second interface control and resistance = R1 ("R _RESET "status); (4) Second interface control and resistance = R2 ("R _SET "state". The state between R _SET and R _SET is difficult to distinguish. However, the states of R _RESET and R _RESET can be reliably distinguished from each other. In addition, the states of R _RESET and R _RESET can be reliably distinguished from the states of R _SET and R _SET . Therefore, according to the present embodiment, the resistance value switching device 122a can be configured as a three-state memory device having the following states: (1) R _RESET ; (2) R _RESET ; (3) R _SET or R _SET .

Referring to Figures 5 and 6, the procedure for reading the resistance value switching device 122a will be described in accordance with an embodiment of a three-state memory device. FIG. 5 is a graphical representation of the relationship between the memory state of the resistance value switching device 122a and the applied voltage, and FIG. 6 is a flow chart of the reading process.

First, at block 200, the resistance value switching device 122a has been programmed into one of the memory cell states (1) R _RESET , ( 2 ) R _RESET , ( 3 ) R _SET or R _SET . The remainder of this routine will allow reading of the resistance value switching device 122a to determine which memory state is written to the resistance value switching device 122a. At block 202, the resistance value of the resistance value switching device 122a is determined. As shown in FIG. 5, regardless of which of the first interface region 144 and the second interface region 146 is being controlled, the resistance value can be expected to be a higher resistance value R _RESET /R _RESET or a lower resistance value R _SET /R _SET . If a lower resistance value R _SET /R _{SET is} detected, the process ends at block 204 and determines that the memory state of the resistance value switching device 122a is R _SET /R _SET . Conversely, if a higher resistance value R _RESET /R _{RESET is} detected, the program continues to distinguish between the R _RESET memory state and the R _RESET memory state.

By determining which of the first interface area 144 and the second interface area 146 is being controlled, the memory state R _RESET can be distinguished from the R _RESET memory state. As shown in the procedure of Figure 6, this is accomplished using the applied voltage V _DETERMINE , for which the behavior of the resistance value switching device will vary depending on which of the first interface region 144 and the second interface region 146 is Take control. An example of a voltage level that can be used as V _DETERMINE is shown in FIG. Here, the voltage level V _DETERMINE is the voltage level between the voltage levels V3 and V4 as shown in FIGS. 4A to 4E. Referring again to block 206, the resistance value level is high (e.g., R1 in FIGS. 4A-4E). It can be understood that the behavior of the resistance value switching device 122a is different from the case where the voltage V _DETERMINE is applied across the resistance value switching device 122a. It depends on which of the first interface area 144 and the second interface area 146 is being controlled. For example, according to FIG. 4A, if the second interface region 146 is under control, the application of the voltage V _DETERMINE does not change the resistance value of the resistance value switching device 122a, but deviates from the resistance value R1. On the other hand, according to FIG. 4D, if the first interface region 144 is under control, the application of the voltage V _DETERMINE changes the resistance value of the resistance value switching device 122a to change from the resistance value R1 to the resistance value R2.

Thus, at block 206, voltage V _DETERMINE is applied across resistance value switching device 122a, and then at block 208, the resistance of resistance value switching device 122a is measured. If the higher resistance value R _RESET /R _RESET is still detected, it can be concluded that the second interface region 146 is being controlled because the resistance value is not changed by the application of V _DETERMINE . Next, the process ends at block 210 and determines that the memory state of the resistance value switching device 122a is the R _RESET memory state. On the other hand, if a lower resistance value R _SET /R _{SET is} detected, it can be judged that the first interface region 144 is being controlled because the resistance value is changed by the application of V _DETERMINE . Note that in this case, the application of V _DETERMINE will control switching from the first interface region 144 to the second interface region 146. Next, the process continues to block 212 where the switching control is switched back to the first interface region 144 such that the memory state of the resistance value switching device 122a is unaffected by the current reading program. Then, the process ends at block 214 and determines that the memory state of the resistance value switching device 122a is the R _RESET memory state.

7 to 9 illustrate resistance value switching characteristics of an alternative embodiment of the resistance value switching device 122a. More specifically, FIG. 7 illustrates the switching characteristics of the symmetric three-state embodiment of the resistance value switching device 122a; FIG. 8 illustrates the switching characteristics of the asymmetric dual-state embodiment of the resistance value switching device 122a; and FIG. The switching characteristics of the asymmetric dual state/three state embodiment of the value switching device 122a. These and other alternative embodiments can be fabricated by varying the composition of electrode layer 134 and electrode layer 142 and/or the composition of tungsten oxide layer 136. For example, where electrode layer 134 and electrode layer 142 are formed of TiN, the resistance associated with the R _RESET or R _RESET state can be increased or decreased, depending on the nitrogen content of TiN. Likewise, the resistance associated with the R _RESET or R _RESET state can be increased or decreased depending on the oxygen content of the tungsten oxide layer 136.

The switching characteristic of the symmetric three-state embodiment of the resistance value switching device 122a shown in FIG. 7 includes three resistance values (memory states) for each interface region 144/146. The memory states when the first interface area 144 is being controlled are R _SET , R _{RESET1 ,} and R _RESET2 . The memory states that are being controlled for the second interface region 146 are R _SET , R _{RESET1 ,} and R _RESET2 . It is difficult to distinguish between states R _SET and R _SET . However, the states R _RESET1 , R _RESET2 , R _{RESET1 ,} and R _RESET2 can be reliably distinguished from each other. In addition, each of the states R _RESET1 , R _RESET2 , R _{RESET1 ,} and R _RESET2 can be reliably distinguished from the states R _SET and R _SET . Therefore, the resistance value switching device 122a according to the present embodiment can be set as a memory device of five states having states (1) R _RESET1 , (2) R _RESET2 , (3) R _RESET1 , (4) R _RESET2 and ( 5) R _SET or R _SET .

The switching characteristic of the asymmetric two-state embodiment of the resistance value switching device 122a shown in FIG. 8 includes three resistance values (memory state) for each interface region 144/146, wherein the R _RESET resistance value and the R _RESET resistance value region . The memory states that are being controlled for the first interface area 144 are R _SET and R _RESET . The memory states that are being controlled for the second interface region 146 are R _SET and R _RESET . It is difficult to distinguish between states R _SET and R _SET . However, the states R _RESET and R _RESET can be reliably distinguished from each other. In addition, each of the states R _RESET and R _RESET can be reliably distinguished from the states R _SET and R _SET . Therefore, the resistance value switching device 122a according to the present embodiment can be set to a memory device of three states having states (1) R _RESET , ( 2 ) R _{RESET ,} and ( 3 ) R _SET or R _SET .

FIG. 10 is a flow chart of the read resistance value switching device 122a according to the asymmetric embodiment of FIG. First, at block 300, the resistance value switching device 122a has been programmed into one of the memory states (1) R _RESET , ( 2 ) R _{RESET ,} and ( 3 ) R _SET or R _SET . The remainder of this routine will allow reading of the resistance value switching device 122a to determine which memory state is written to the resistance value switching device 122a. At block 302, the resistance of the resistance value switching device 122a is determined. As shown in FIG. 8, regardless of which of the first interface region 144 and the second interface region 146 is being controlled, the resistance can be expected to be the first resistor R _RESET , the second resistor R _RESET or the third resistor R _SET /R _SET One of them. If the resistance value R _SET /R _SET is detected, the process ends at block 304 and the memory state of the resistance value switching device 122a is determined to be R _SET /R _SET . If the resistance value R _RESET is detected, the flow ends at block 306 and it is determined that the memory state of the resistance value switching device 122a is R _RESET . If the resistance value R _RESET is detected, the flow ends at block 308 and it is determined that the memory state of the resistance value switching device 122a is R _RESET .

Referring again to FIG. 9, the switching characteristic diagram of the asymmetric dual state/three state embodiment of the resistance value switching device 122a includes two resistance values (memory states) associated with the first interface region 144 and three and second interface regions. 146 associated resistance value (memory state). The memory states when the first interface area 144 is being controlled are R _SET and R _RESET . The memory states when the second interface area 146 is being controlled are R _SET , R _{RESET1 ,} and R _RESET2 . It is difficult to distinguish between states R _SET and R _SET . However, the states R _RESET , R _{RESET1 ,} and R _RESET2 can be reliably distinguished from each other. In addition, each of the states R _RESET , R _{RESET1 ,} and R _RESET2 can be reliably distinguished from the R _SET and R _SET states. Thus, the resistance value of the present embodiment, the switching device 122a may be configured as a four-state memory device having a state _{(1) R RESET, (2} ) R RESET1, (3) R RESET2 and (4) R _SET or R _SET .

FIG. 11 is a schematic diagram of the resistance value switching device 122b according to some embodiments of the resistance value switching device 122. The resistance value switching device 122b includes a programmable metallization cell (PMC). The resistance value switching device 122b includes a substrate 402, an intermetal dielectric (IMD) layer 404, a first electrode layer 406, a conductive plug layer 408, a first dielectric layer 410, and a second dielectric. Layer 412, a solid electrolyte layer 414 and a second electrode layer 416.

The substrate 402 may be a silicon substrate. The inter-metal dielectric layer 404 may be formed on the substrate 402 by a known method, such as chemical vapor deposition (CVD). .

The material of the first electrode layer 406 may be titanium nitride (TiN), which is located on the IMD layer 404 and can be formed by CVD or physical vapor deposition (PVD). Alternatively, the material of the first electrode 406 may include doped polysilicon, aluminum, copper or tantalum nitride (TaN).

A conductive plug layer 408 is formed on the first electrode 406. The first dielectric layer 410 and the second dielectric layer 412 are located on the side of the conductive plug layer 408 and are formed on the first electrode 406. Dielectric layer 410 and dielectric layer 412 may comprise, for example, hafnium oxide (SiO ₂ ), tantalum nitride (Si ₃ N ₄ ), or a similar insulating material. Conductive plug layer 408 can comprise tungsten. The structure of the conductive plug layer 408, the first dielectric layer 410 and the second dielectric layer 412 can be formed on the first electrode 406 to form a continuous dielectric layer 410 and 412. The electric layer is formed by a chemical vapor deposition method, for example. A portion of the continuum dielectric layer is then removed, such as by lithography and etching, to form a gap between the first dielectric layer 410 and the second dielectric layer 412. Next, a conductive plug layer 408 may be formed in the gap between the first dielectric layer 410 and the second dielectric layer 412. More specifically, the formation of the conductive plug layer 408 can deposit the material of the conductive plug layer 408 in the gap between the first dielectric layer 410 and the second dielectric layer 412.

A solid electrolyte layer 414 can be formed on the conductive plug layer 408 by deposition. The solid electrolyte layer 414 can also extend over the dielectric layers 410 and 412. The solid electrolyte layer 414 may include a transition metal oxide or a material containing at least one sulfur element. For example, the solid electrolyte layer 414 may comprise GeS/Ag or GeSe/Ag.

The second electrode layer 416 can be on the solid electrolyte layer 414. The second electrode layer 416 may be an oxidizable electrode. The second electrode layer 416 may comprise an oxidizable electrode material such as silver, copper or zinc.

The embodiment of the resistance value switching device 122b shown in Fig. 11 constitutes a single PMC structure. Figure 12 shows a graph of voltage and current generated during a stylized operation and a read operation of a single PMC embodiment of resistance value switching device 122b. The exact voltage and current levels can be varied from what is shown in FIG.

Initially, the resistance value switching device 122b may not be programmed and thus may have a higher resistance value. If a higher voltage is applied to the second electrode layer 416 and a lower voltage is applied to the first electrode layer 406 until a set of starting voltages (V1 or programmable voltage) is applied, no current can flow through the resistance value switching. Device 122b. In the illustrated example, the set of starting voltages V1 can be, for example, about 0.7 volts. When the applied voltage rises above the starting voltage V1, the current may flow until the operating current IW is reached and can be tied (eg, limited) by the stylized circuitry. In one embodiment, the voltage can also be reduced to 0 volts, whereby the current is reduced to 0 amps, thereby completing the stylization of the resistance value switching device 122b.

To detect or read the memory cell state, a sense voltage (VS) can be applied to the resistance value switching device 122b. The measured voltage VS may be lower than the starting voltage V1. In the illustrated example, the sense voltage VS can be, for example, about 0.3 volts. When the resistance value switching means 122b is generally programmed (set, SET) as described above and the sensing voltage VS is applied to the resistance value switching means 122b, the operating current IW can flow through the resistance value switching means 122b. If the resistance value switching means 122b is not programmed (reset, RESET), when the sensing voltage VS is applied, the resistance value switching means 122b has little or no current flowing.

In one embodiment, a lower voltage, such as a negative voltage (also referred to as a reset threshold voltage), may be applied to the resistance value switching device 122b to erase or reset the stylized state. In the illustrated example, the reset start voltage can be, for example, about -0.3 volts. When the reset start voltage is applied to the resistance value switching device 122b, a negative current can flow through the resistance value switching device 122b. When the negative voltage drops below the reset start voltage, the current may stop flowing (ie, to 0 amps). After the reset start voltage has been applied to the resistance value switching device 122b, the resistance value switching device 122b can have the same high resistance as in the previous stylized operation, whereby the erase or reset is stored in the resistance value switching device 122b. Value.

FIG. 13 is a schematic diagram of a resistance value switching device according to some embodiments of the resistance value switching device 122. The resistance value switching device 122c includes a dual PMC (dual-PMC) structure. The resistance value switching device 122c includes a substrate 452, an inter-metal dielectric (IMD) layer 454, a first electrode layer 456, a conductive plug layer 458, a first dielectric layer 460, a second dielectric layer 462, and a first solid electrolyte layer. 464, a second electrode layer 466, a second solid electrolyte layer 468, and a third electrode layer 470.

The substrate 452 may be a germanium substrate, and the metal interlayer dielectric layer 454 may be formed on the substrate 452 by a known method such as chemical vapor deposition (CVD).

The material of the first electrode layer 456 may be titanium nitride (TiN), which is located on the IMD layer 454 and may be formed by CVD or physical vapor deposition (PVD). Alternatively, the material of the first electrode layer 456 may include doped polysilicon, aluminum, copper, or tantalum nitride (TaN).

A conductive plug layer 458 is formed on the first electrode 456. The first dielectric layer 460 and the second dielectric layer 462 are located on the side of the conductive plug layer 458 and are formed on the first electrode 456. Dielectric layers 460 and 462 may comprise, for example, hafnium oxide (SiO ₂ ), tantalum nitride (Si ₃ N ₄ ), or similar insulating materials. Conductive plug layer 458 can comprise tungsten. A method of forming the structure of the conductive plug layer 458, the first dielectric layer 460, and the second dielectric layer 462 may first form a continuous dielectric layer as the dielectric layers 460 and 462 on the first electrode 456. The method of forming it is, for example, a chemical vapor deposition method. Next, a portion of the continuum dielectric layer is removed, such as by lithography and etching, thereby forming a gap between the first dielectric layer 460 and the second dielectric layer 462. Next, a conductive plug layer 458 can be deposited in the gap between the first dielectric layer 460 and the second dielectric layer 462. More specifically, the conductive plug layer 458 can be formed by depositing a material of the conductive plug layer 408 in a gap between the first dielectric layer 460 and the second dielectric layer 462.

A solid electrolyte layer 464 can be formed on the conductive plug layer 458 by deposition. The solid electrolyte layer 464 can also extend over the dielectric layers 460 and 462. The solid electrolyte layer 464 can include a transition metal oxide or a material comprising at least one sulfur element. For example, the solid electrolyte layer 464 may comprise GeS/Ag or GeSe/Ag.

The second electrode layer 466 is formed on the solid electrolyte layer 464 by deposition. The second electrode layer 466 can be an oxidizable electrode. The second electrode layer 466 may comprise an oxidizable electrode material such as silver, copper or zinc.

The second solid electrolyte layer 468 is formed on the second electrode layer 466 by deposition. The second solid electrolyte layer 468 may include a transition metal oxide or a material containing at least one sulfur element. For example, the second solid electrolyte layer 468 may comprise GeS/Ag or GeSe/Ag.

The third electrode layer 470 is formed on the second solid electrolyte layer 468 by deposition. The third electrode layer 470 may comprise a conductive or semiconductive material such as TiN.

The embodiment of the resistance value switching device 122c shown in FIG. 13 forms a dual PMC (dual-PMC) structure including an upper PMC structure 472 and a lower PMC structure 474. Each PMC structure 472, 474 can be programmed into two memory states, each corresponding to a respective resistance value. The memory states of the upper PMC structure 472 include memory states labeled R _RESET and R _SET , which correspond to relatively high and relatively low resistance values, respectively. The memory states of the lower PMC structure 474 include memory cell states labeled R _RESET and R _SET , which correspond to relatively high and relatively low resistance values, respectively. In some embodiments, the resistance value associated with R _RESET may be substantially equal to the resistance value associated with R _RESET , while in other embodiments the respective resistance values associated with R _RESET and R _RESET may also be different. Also, in some embodiments, the resistance value associated with R _SET may be substantially equal to the resistance value associated with R _SET , while in other embodiments the resistance values associated with R _SET and R _SET may also be different. .

14 to 16 are diagrams showing resistance value switching characteristics of a symmetric, dual PMC (dual-PMC) embodiment of the resistance value switching device 122c. More specifically, FIG. 14 shows the resistance value switching characteristic of the upper PMC structure 472, FIG. 15 shows the resistance value switching characteristic of the lower PMC structure 474, and FIG. 16 shows the double PMC structure formed by the upper PMC structure 472 and the lower PMC structure 474. The overall resistance value switching characteristic of the symmetric embodiment.

As shown in FIG. 14, across the entire upper structure PMC positive voltage V _S1 472 will cause the resistance value of the upper structure 472 is switched to a PMC resistance value R _RESET state memory associated. The negative voltage V _S2 across the entire upper PMC structure 472 causes the resistance value of the upper PMC structure 472 to switch to the resistance value associated with the memory state R _SET .

15, across the lower portion of the structure PMC positive voltage V _S3 474 will cause the resistance value of a lower structure 474 is switched to a PMC resistance value of the memory state R _SET associated. The negative voltage V _S4 across the entire lower PMC structure 474 causes the resistance value of the lower PMC structure 472 to switch to the resistance value associated with the memory state R _RESET .

The combination of the symmetric embodiments of the upper PMC structure 472 and the lower PMC structure 474 shown in Figures 14 and 15 results in the memory device being able to have four memory states A through D as shown in Figure 16. Each of the memory states A through D is associated with a respective sum of the resistance values of the memory states of the upper PMC structure 472 and the lower PMC structure 474. When the resistance value of the upper PMC structure 472 has a resistance value associated with the memory state R _SET and the resistance value of the lower PMC structure 474 has a resistance value associated with the memory state R _RESET , the memory state A occurs such that the memory state A The overall resistance of the dual PMC structure is R _SET + R _RESET . When the resistance value of the upper PMC structure 472 has a resistance value associated with the memory state R _RESET and the resistance value of the lower PMC structure 474 has a resistance value associated with the memory state R _SET , the memory state D occurs such that the memory state D The overall resistance of the dual PMC structure is R _SET +R _RESET . When the resistance value of the upper PMC structure 472 has a resistance value associated with the memory state R _RESET and the resistance value of the lower PMC structure 474 has a resistance value associated with the memory state R _RESET , both memory states B and C occur, The overall resistance value of the dual PMC structure of memory states B and C is R _RESET + R _RESET . Therefore, the memory cell states B and C are difficult to distinguish, so the dual PMC structure of the resistance value switching device 122c can be realized by a three-state memory device having A, B (or C) and D in a memory state.

Next, a procedure for reading the resistance value switching means 122c according to the tri-state, symmetrical and dual PMC memory device according to the embodiment will be described with reference to Fig. 17, and Fig. 17 is a flow chart showing the reading procedure.

First, at block 500, the resistance value switching device 122c has been programmed into one of the memory states A, B/C, or D. The remainder of this routine will allow reading of the resistance value switching device 122c to determine which memory state is written into the resistance value switching device 122c. At block 502, the resistance value of the resistance value switching device 122c is determined. In the present embodiment of symmetry corresponding to the resistance value R _SET associated with substantially equal resistance value R _SET associated with the resistance value R _RESET associated with substantially equal resistance value R _RESET associated. Therefore, the resistance value of the resistance value switching device 122c can be expected to be a higher resistance value R = R _RESET + R _RESET or a lower resistance value R = (R _RESET + R _SET ) or (R _SET + R _RESET ). If the higher resistance value R = R _RESET + R _RESET is detected, the routine ends at block 504 and it is determined that the memory state of the resistance value switching device 122c is the memory state B/C ( R _RESET + R _RESET ). Otherwise, if a lower resistance value is detected, the program will continue to distinguish between memory states A (R _SET + R _RESET ) and D (R _RESET + R _SET ).

Next, in block 506, a voltage V _{DETERMINE is} applied to the overall resistance value switching device 122c, and then the resistance value of the resistance value switching device 122c is measured in block 508. In this embodiment, the voltage of V _DETERMINE is selectable, so that if the memory state is the memory state A, the upper PMC structure 472 will be switched from R _SET to R _RESET , but if the memory state is the memory state D, then No change will happen. Therefore, the voltage of V _DETERMINE is between V _S1 and V _S3 . In addition, when the voltage of V _DETERMINE can be selected from between V _S2 and V _S4 , this causes the lower PMC structure 472 to switch from R _SET to R _RESET if the memory state is the memory cell state D, but if the memory state When it is in memory state A, it will not cause any change.

If at block 508 it is detected that the lower resistance value is equal to R _RESET + R _SET (also equal to R _SET + R _RESET ), since the resistance value does not change due to the application of V _DETERMINE , it can be determined that the memory state is the memory state D. Therefore, the routine ends at block 510 and it is determined that the memory state of the resistance value switching device 122c is the memory state D. Conversely, if the higher resistance value R _RESET + R _RESET is detected at block 508, since the resistance value is changed by the application of V _DETERMINE , it can be determined that the memory state is the memory state A. Note that in this case, the application of V _DETERMINE switches the resistance value of the upper PMC structure 472 from R _SET to R _RESET . Next, the process continues to block 512 where the resistance value of the upper PMC structure 472 is switched back to R _SET (eg, with the application of V _S2 ) such that the memory state of the resistance value switching device 122c is not disturbed by the current reading process. . Then, the routine ends at block 514 and determines that the memory state of the resistance value switching device 122c is the memory state A.

18 to 20 and the like show an embodiment of an asymmetric, dual PMC of the resistance value switching device 122c. More specifically, FIG. 18 shows the resistance value switching characteristic of the upper PMC structure 472, FIG. 15 shows the resistance value switching characteristic of the lower PMC structure 474, and FIG. 16 shows the double PMC structure formed by the upper PMC structure 472 and the lower PMC structure 474. The overall resistance value switching characteristic of the asymmetric embodiment.

18, across the entire upper structure PMC positive voltage V _S1 472 will cause the resistance value of the upper structure 472 is switched to a PMC resistance value R _RESET state memory associated. The negative voltage V _S2 across the entire upper PMC structure 472 causes the resistance value of the upper PMC structure 472 to switch to the resistance value associated with the memory state R _SET .

19, the structure across the entire lower PMC positive voltage V _S3 474 will cause the resistance value of a lower structure 474 is switched to a PMC resistance value of the memory state R _SET associated. The negative voltage V _S4 across the entire lower PMC structure 474 causes the resistance value of the lower PMC structure 472 to switch to the resistance value associated with the memory state R _RESET .

For example, the combination of the asymmetric embodiment of the upper PMC structure 472 and the lower PMC structure 474 shown in Figures 18 and 19 results in the memory device being able to have the four memory states A through D shown in Figure 20. Each of the memory states A through D is associated with a respective sum of the resistance values of the memory states of the upper PMC structure 472 and the lower PMC structure 474. When the resistance value of the upper PMC structure 472 has a resistance value associated with the memory state R _SET and the resistance value of the lower PMC structure 474 has a resistance value associated with the memory state R _RESET , the memory state A occurs such that the memory state A The overall resistance of the dual PMC structure is R _SET + R _RESET . When the resistance value of the upper PMC structure 472 has a resistance value associated with the memory state R _RESET and the resistance value of the lower PMC structure 474 has a resistance value associated with the memory cell state R _SET , the memory state D occurs such that the memory state D The overall resistance of the dual PMC structure is R _SET +R _RESET . When the resistance value of the upper PMC structure 472 has a resistance value associated with the memory state R _RESET and the resistance value of the lower PMC structure 474 has a resistance value associated with the memory state R _RESET , both the memory cell states B and C occur Thus, the overall resistance value of the dual PMC structure of memory states B and C is R _RESET + R _RESET . Therefore, the memory states B and C are difficult to distinguish, so the dual PMC structure of the resistance value switching device 122c can be realized by a three-state memory device having A, B (or C) and D in a memory state.

Figure 21 shows an alternative method of reading the resistance value switching device 122c in accordance with an asymmetric embodiment having asymmetric resistive switching characteristics as shown in Figures 18-20. First, at block 600, the resistance value switching device 122c has been programmed into one of the memory cell states A, B/C, or D. The remainder of this routine will allow reading of the resistance value switching device 122c to determine that one of the memory states A, B/C, or D is written to the resistance value switching device 122c. The resistance of the resistance value switching device 122c is determined at block 602. As shown in Figure 20, the resistance value can be expected as the resistance value associated with one of the memory states A (R _SET + R _RESET ), B / C (R _RESET + R _RESET ), or D ( R _SET + R _RESET ) . If the resistance value R _RESET + R _RESET is detected, the process proceeds to block 604 and it is determined that the memory state of the resistance value switching device 122c is the memory state B/C. If the resistance value R _SET + R _RESET is detected, the process ends at block 606 and it is determined that the memory state of the resistance value switching device 122c is the memory state D. If the resistance value R _SET + R _RESET is detected, the process ends at block 608 and it is determined that the memory state of the resistance value switching device 122c is the memory state A.

In addition to the above-described embodiments 122a, 122b, and 122c of the resistance value switching device 122 shown in FIGS. 1 and 2, it will be understood that the resistance value switching device 122 can have many other embodiments. Figure 22 depicts a block diagram of a more generalized embodiment, commonly referred to as resistance value switching device 122d. The resistance value switching device 122d includes an upper memory structure 652 and a lower memory structure 654, wherein each of the memory structures 652 and 654 includes a respective semiconductor resistance value switching memory device. For example, the upper memory structure 652 may include a PMC, a resistive random access memory (RRAM), a magnetoresistive random access memory (MRAM), or a ferroelectric random access memory. Ferroelectric Random Access Memory (FRAM). Likewise, the lower memory structure 654 can include PMC, RRAM, MRAM, or FRAM. Additionally, upper memory structure 652 and lower memory structure 654 can include any electronic memory device capable of switching between two resistance values (equivalent to two memory states).

The memory states of the upper memory structure 652 include memory states labeled R _RESET and R _SET , corresponding to relatively high and relatively low resistance values, respectively. The positive reset voltage (+V _RESET ) can switch the resistance value of the upper memory structure 652 to the resistance value R _RESET , and the negative set voltage (−V _SET ) can switch the resistance value of the upper memory structure 652 to the resistance value R. _SET . The memory state of the lower memory structure 654 includes memory states labeled R _RESET and R _SET , corresponding to relatively high and relatively low resistance values, respectively. The negative reset voltage ( -V _RESET ) can switch the resistance value of the upper memory structure 652 to the resistance value R _RESET , and the positive set voltage (+ V _SET ) can switch the resistance value of the upper memory structure 652 to the resistance value R. _SET . There are two desired sets of conditions for the resistance value switching device 122d. The first condition group satisfies the following two conditions (1a) and (1b):

(1a) +V _RESET >+ V _SET

(1b) |-V _SET |>| -V _RESET |

The second condition group satisfies the following two conditions (2a) and (1b):

(2a) +V _RESET <+ V _SET

(2b) |-V _SET |<| -V _RESET

Referring to Figures 23 to 26, an embodiment of the resistance value switching device 122d that satisfies the first condition set is described. Referring to Figures 27 to 30, an embodiment of the resistance value switching device 122d that satisfies the second condition set is described.

23 to 25 are diagrams showing the resistance value switching characteristics of the first group of resistance value switching devices 122d satisfying the conditions (1a) and (1b). More specifically, FIG. 23 shows the resistance value switching characteristic of the upper memory structure 652, FIG. 24 shows the resistance value switching characteristic of the lower memory structure 654, and FIG. 25 shows the overall resistance value of the resistance value switching device 122d according to the current embodiment. Switch characteristics.

As shown in FIG. 23, a positive voltage +V _RESET across the upper memory structure 652 causes the resistance value of the upper memory structure 652 to switch to the resistance value associated with the memory state R _RESET . The negative voltage -V _SET across the upper memory structure 652 causes the resistance value of the upper memory structure 652 to switch to the resistance value associated with the memory state R _SET .

As shown in FIG. 24, a positive voltage + V _SET across the lower memory structure 654 causes the resistance value of the lower memory structure 654 to switch to a resistance value associated with the memory state R _SET . The negative voltage across the lower memory structure 654 - V _RESET causes the resistance value of the lower memory structure 654 to switch to the resistance value associated with the memory state R _RESET .

The combination of the upper memory structure 652 and the lower memory structure 654 shown in Figures 23 and 24 results in the memory device having four memory states as shown in Figure 25. Each of the memory states A through D is associated with a respective sum of the resistance values of the memory states of the upper memory structure 652 and the lower memory structure 654. When the resistance value of the upper memory structure 652 has a resistance value associated with the memory state R _SET and the resistance value of the lower memory structure 654 has a resistance value associated with the memory state R _RESET , the memory state A occurs, resulting in a memory state The overall resistance of the resistance value switching device 122d of A is R _SET + R _RESET . When the resistance value of the upper memory structure 652 has a resistance value associated with the memory state R _RESET and the resistance value of the lower memory structure 654 has a resistance value associated with the memory state R _RESET , the memory state B occurs, resulting in a memory state The overall resistance value of the resistance value switching device 122d of B is R _RESET + R _RESET . When the resistance value of the upper memory structure 652 has a resistance value associated with the memory state R _SET and the resistance value of the lower memory structure 654 has a resistance value associated with the memory state R _SET , the memory state C occurs, resulting in a memory state The overall resistance value of the resistance value switching device 122d of C is R _SET + R _SET . When the resistance value of the upper memory structure 652 has a resistance value associated with the memory state R _RESET and the resistance value of the lower memory structure 654 has a resistance value associated with the memory cell state R _SET , the memory state D occurs, causing memory The overall resistance of the resistance value switching device 122d of the state D is R _SET + R _RESET . Therefore, the resistance value switching device 122d can be realized as a memory device having four states of the memory states A, B, C, and D.

Referring to Fig. 26, a procedure for reading the resistance value switching means 122d will be described based on a four state memory device embodiment which satisfies the first set of conditions (1a) and (1b).

First, at block 700, the resistance value switching device 122d has been programmed into one of the memory states A, B, C, or D. The remainder of this routine will allow reading of the resistance value switching means 122d to determine that one of the memory states A through D is written to the resistance value switching means 122d. At block 702, the resistance value of the resistance value switching device 122d is determined. The resistance value of the resistance value switching device 122d can be expected to be one of four resistance values associated with the memory states A to D, respectively. If the resistance value R = R _SET + R _SET is detected, the process ends at block 704 and it is determined that the memory state of the resistance value switching device 122d is the memory state C (R _SET + R _SET ). If the resistance value R = R _RESET + R _RESET is detected, the routine ends at block 705 and it is determined that the memory state of the resistance value switching device 122d is the memory state B (R _RESET + R _RESET ). In the present embodiment, the resistance value R _SET associated substantially equal resistance value R _SET associated and equal to the resistance value R _RESET associated with the resistance value R _RESET substantially associated. Therefore, a third possibility at block 702 is that the resistance value is R = R _RESET + R _SET = R _SET + R _RESET . If this third possibility occurs, the program will continue to distinguish between memory states A (R _SET + R _RESET ) and D (R _RESET + R _SET ).

Next, in block 706, voltage V _{DETERMINE is} applied to the entire resistance value switching device 122d, and then the resistance value of the resistance value switching device 122d is measured in block 708. In this embodiment, the voltage of V _DETERMINE is selected such that if the memory state is memory state A, the lower memory structure 654 will be switched from R _RESET to R _SET , but if the memory state is memory state D, it will not be generated. Any change. Therefore, the voltage of V _DETERMINE is between + V _SET and + V _RESET .

In block 708, the resistance value of the resistance value switching device 122d is again determined. If the resistance value detected at block 708 is R = R _RESET + R _SET , since the resistance value is not changed by the application of V _DETERMINE , it can be determined that the memory state is the memory state D, and therefore, the process ends at block 710. And determining the memory state of the resistance value switching device 122d is the memory state D. Conversely, if the resistance detected at block 708 is R = R _RESET + R _SET , since the resistance value is changed by the application of V _DETERMINE , the memory state can be determined to be memory state A. Note that in this case, the application of V _DETERMINE switches the resistance of the lower memory structure 654 from R _RESET to R _SET . Therefore, the process continues with block 712 where the resistance value of the lower memory structure 654 is switched to R _RESET (eg, by the application of -V _RESET ) so that the memory state of the resistance value switching device 122d is not disturbed by the current reading program. . Then, the method ends at block 714, and it is determined that the memory state of the resistance value switching device 122d is the memory state A.

27 to 29 are diagrams showing the resistance value switching characteristic of the embodiment of the resistance value switching device 122d, which satisfies the second group of the conditions (2a) and (2b). More specifically, FIG. 27 shows the resistance value switching characteristic of the upper memory structure 652, FIG. 28 shows the resistance value switching characteristic of the lower memory structure 654, and FIG. 29 shows the overall resistance value of the resistance value switching device 122d according to the present embodiment. Switch characteristics.

As shown in FIG. 27, a positive voltage +V _RESET across the upper memory structure 652 causes the resistance value of the upper memory structure 652 to switch to the resistance value associated with the memory state R _RESET . The negative voltage -V _SET across the upper memory structure 652 causes the resistance value of the upper memory structure 652 to switch to the resistance value associated with the memory state R _SET .

As shown in FIG. 28, a positive voltage + V _SET across the lower memory structure 654 causes the resistance value of the lower memory structure 654 to switch to a resistance value associated with the memory cell state R _SET . The negative voltage across the lower memory structure 654 - V _RESET causes the resistance value of the lower memory structure 654 to switch to the resistance value associated with the memory cell state R _RESET .

The combination of the upper memory structure 652 and the lower memory structure 654 shown in Figures 27 and 28 results in the memory device having the four memory states shown in Figure 29. Each of the memory states A through D is associated with a respective sum of the resistances of the memory states of the upper memory structure 652 and the lower memory structure 654. When the resistance value of the upper memory structure 652 has a resistance value associated with the memory state R _SET and the resistance value of the lower memory structure 654 has a resistance value associated with the memory state R _RESET , the memory state A occurs, resulting in a memory state The overall resistance value of the resistance value switching device 122d of A is R _SET + R _RESET . When the resistance value of the upper memory structure 652 has a resistance value associated with the memory state R _SET and the resistance value of the lower memory structure 654 has a resistance value associated with the memory cell state R _SET , the memory cell state B occurs such that The overall resistance value of the resistance value switching device 122d of the memory state B is R _SET + R _SET . When the resistance value of the upper memory structure 652 has a resistance value associated with the memory state R _REET and the resistance value of the lower memory structure 654 has a resistance value associated with the memory state R _REET , the memory cell state C occurs, so that the memory The overall resistance value of the resistance value switching device 122d of the state C is R _RESET + R _RESET . When the resistance value of the upper memory structure 652 has a resistance value associated with the memory state R _RESET and the resistance value of the lower memory structure 654 has a resistance value associated with the memory state R _SET , the memory state D occurs, resulting in a memory state The overall resistance of the resistance value switching device 122d of D is R _{S ET} + R _RESET . Therefore, the resistance value switching device 122d can be realized as four state memory devices having the memory states A, B, C, and D.

Referring to FIG. 30, a flow chart of a reading program is described, and a method of reading the resistance value switching device 122d is described in conjunction with the drawings and the embodiment, which is a fourth group that satisfies the second group of conditions (2a) and (2b). An embodiment of a state memory device.

First, at block 800, the resistance value switching device 122d has been programmed into one of the memory states A, B, C, or D. The remainder of this routine will allow reading of the resistance value switching means 122d to determine that one of the memory states A through D is written to the resistance value switching means 122d.

At block 802, the resistance value of the resistance value switching device 122d is determined. The resistance value of the resistance value switching device 122d can be expected to be one of the four resistance values respectively corresponding to the memory states A to D. If the resistance value R = R _SET + R _SET is detected, the routine ends at block 804 and it is determined that the memory state of the resistance value switching means 122d is the memory state B (R _SET + R _SET ). If the resistance value R = R _RESET + R _RESET is detected, the routine ends at block 805 and determines that the memory state of the resistance value switching means 122d is the memory state C (R _RESET + R _RESET ).

In the current embodiment, the resistance value associated with R _SET is substantially equal to the resistance value associated with R _SET , and the resistance value associated with R _RESET is substantially equal to the resistance value associated with R _RESET . Therefore, a third possibility at block 802 is that the resistance value is R = R _RESET + R _SET = R _SET + R _RESET . If this third possibility occurs, the program will continue to distinguish between memory state A (R _SET + R _RESET ) and memory state D (R _RESET + R _SET ).

Next, in block 806, voltage V _{DETERMINE is} applied to the entire resistance value switching device 122d, and then the resistance value of the resistance value switching device 122d is measured in block 808. In this embodiment, the voltage of V _DETERMINE is selected such that if the memory state is memory state A, the upper memory structure 652 will be switched from R _SET to R _RESET , but if the memory state is memory state D, then Will make any changes. Therefore, the voltage of V _DETERMINE is between +V _RESET and +V _SET .

In block 808, the resistance of the resistance value switching device 122d is again determined. If the resistance value detected at block 808 is R = R _RESET + R _SET , it can be determined that the memory state is the memory state D because the resistance value is not changed by the application of V _DETERMINE . Therefore, the program ends at block 810 and determines the memory state of the resistance value switching device 122d. Conversely, if the resistance value detected at block 808 is R = R _RESET + R _RESET , the memory state can be determined to be memory state A because the resistance value is changed by the application of V _DETERMINE . Note that in this case, the application of V _DETERMINE switches the resistance value of the upper memory structure 652 from R _SET to R _RESET . Accordingly, the process continues with block 812 where the resistance value of the upper memory structure 654 is switched back to R _SET (eg, by the application of -V _SET ) so that the memory state of the resistance value switching device 122d is not affected by the current read procedure. disturb. Then, the routine ends at block 814, and it is determined that the memory state of the resistance value switching means 122d is the memory state A.

Figure 31 is a flow chart showing the procedure for stylizing memory cells. The stylized program begins at block 900 and includes, for example, the use of a write enable signal. At block 902, it is determined if the current write is an erase memory cell. If so, the process continues with block 904 and erases the data stored in transistor 120. For example, if the transistor 120 is a floating gate transistor, the transistor 120 is erased by FN electron tunneling. For example, in such an embodiment, the transistor 120 can be provided with an erase gate voltage Vg ranging from -7 volts to -8 volts such that during application of the erase gate voltage Vg, the RHS bit can utilize 4.5. The drain voltage of volts and the source voltage of 0 volts are erased; the LHS bit can be erased by applying a gate voltage of 0 volts and a source voltage of 4.5 volts.

At block 906, the transistor 120 is programmed and at block 908 the resistance value switching device 122 is programmed. The stylized operation then ends at block 910.

The transistor 120 and the resistance value switching device 122 are arranged such that the programmed voltage of the transistor 120 does not interfere with the memory state of the resistance value switching device 122, and vice versa. Further, when the resistance value switching device 122 is programmed, the gate voltage Vg at which the transistor 120 is activated is selected to be smaller than the gate voltage when the transistor 120 is programmed, but larger than the threshold voltage of the transistor 120. This causes the transistor 20 to be activated to program the resistance value switching device 122 without affecting the stylized state of the transistor 120.

A specific, non-limiting example includes a transistor 120 having a programmable (PROGRAM) gate voltage ranging from 7 volts to 12 volts (500 ns) capable of storing a first bit and a second bit (RHS bit and LHS bit). The RHS bit can be programmed using Vd = 3.5 volts and Vs = Vb = 0 volts; the LHS bit can be programmed using Vd = Vb = 0 volts and Vs = 3.5 volts. In this example, the erase (ERASE) gate voltage ranges from -7 volts to -8 volts. The RHS bit can be erased using Vd = 4.5 volts and Vs = Vb = 0 volts; the LHS bit can be erased using Vd = Vb = 0 volts and Vs = 4.5 volts. The resistance value switching device 122 includes an RRAM in which the set (SET) voltage is +/- 2 volts and the RESET voltage is +/- 3 volts. When the gate voltage applied to the transistor 120 is less than the programmed gate voltage but greater than the start voltage Vt of the transistor 120, the voltage is applied to the resistance value switching device 122. This is just one example of providing a clear use, and there are many other implementations.

32 is a flow chart showing the procedure for reading memory cells 112. The reading process begins at block 900 and includes, for example, the use of a Read Enable signal. At block 952, the data from the transistor 120 and the resistance value switching device is read, and the process ends at block 954. The read operation at block 952 varies depending on the type of transistor used and the type of resistance value switching device. For example, the read operation can include various embodiments of the resistance value switching device 122 in the methods described herein. The gate voltage Vg is set to a predetermined READ gate voltage, and the drain voltage Vd and the source voltage Vs are set. The resistance through the resistance value switching device 122 is also measured.

In the above specific example, the RHS bit can be applied with Vd = 1.6 volts and Vs = Vb = 0 volts (and the resistance value R of the resistance value switching device 122 is also measured); the LHS bit can be applied with Vd = Vb = 0 volts and Vs = 1.6 volts are read (and the resistance R of the resistance value switching device 122 is also measured).

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

100. . . Memory device

102. . . Memory array

104. . . Row decoder

106. . . Sense amplifier

108. . . Row decoder

110. . . Source switch

BL0-BL5. . . Bit line

SL. . . Source line

WL0-WL4. . . Word line

112. . . Memory cell

120. . . Transistor

122, 122a, 122b, 122c, 122d. . . Resistance value switching device

130. . . Substrate

132. . . Internal metal dielectric layer

134. . . First electrode layer

136. . . Tungsten oxide layer

138. . . First dielectric layer

140. . . Second dielectric layer

142. . . Second electrode layer

144. . . First interface area

146. . . Second interface area

V1, V2. . . Negative voltage

V3, V4. . . Positive voltage

R1, R2. . . resistance

R _RESET , R _RESET , R _SET , R _SET . . . status

V _DETERMINE . . . Voltage

200. . . Stylized resistance value switching device

202. . . Read resistance value

204. . . End (R _SET or R _SET )

206. . . Apply V _DETERMINE

208. . . Read resistance value

210. . . End (R _RESET )

212. . . Reprogramming to R _RESET

214. . . End ( R _RESET )

R _RESET1 , R _RESET1 , R _RESET2 , R _RESET2 . . . status

300. . . Stylized resistance value switching device

302. . . Read resistance value

304. . . End (R _SET or R _SET )

306. . . End (R _RESET )

308. . . End ( R _RESET )

402. . . Substrate

404. . . Internal metal dielectric layer

406. . . First electrode layer

408. . . Conductive layer

410. . . First dielectric layer

412. . . Second dielectric layer

414. . . Solid electrolyte layer

416. . . Second electrode layer

452. . . Substrate

454. . . Internal metal dielectric layer

456. . . First electrode layer

458. . . Conductive layer

460. . . First dielectric layer

462. . . Second dielectric layer

464. . . First solid electrolyte layer

466. . . Second electrode layer

468. . . Second solid electrolyte layer

470. . . Second electrode layer

V _S1 , V _S3 . . . Positive voltage

V _S2 , V _S4 . . . Negative voltage

A, B, C, D. . . Memory state

500. . . Stylized resistance value switching device

502. . . Read resistance value

504. . . End (R _RESET + R _RESET )

506. . . Apply V _DETERMINE

508. . . Read resistance value

510. . . End (R _RESET +R _SET )

512. . . Reprogramming to R _SET +R _RESET

514. . . End (R _SET + R _RESET )

600. . . Stylized resistance value switching device

602. . . Read resistance value

604. . . End (R _RESET + R _RESET )

606. . . End (R _RESET + R _SET )

608. . . End (R _SET + R _RESET )

652. . . Upper memory structure

654. . . Lower memory structure

+ V _SET , +V _RESET . . . Positive voltage

- V _RESET , -V _SET . . . Negative voltage

700. . . Stylized resistance value switching device

702. . . Read resistance value

704. . . End (R _SET + R _SET )

705. . . End (R _RESET + R _RESET )

706. . . Apply V _DETERMINE

708. . . Read resistance value

710. . . End (R _RESET + R _SET )

712. . . Reprogramming to R _SET + R _RESET

714. . . End (R _SET + R _RESET )

800. . . Stylized resistance value switching device

802. . . Read resistance value

804. . . End (R _SET + R _SET )

805. . . End (R _RESET + R _RESET )

806. . . Apply V _DETERMINE

808. . . Read resistance value

810. . . End (R _RESET + R _SET )

812. . . Reprogramming to R _SET + R _RESET

814. . . End (R _SET + R _RESET )

900. . . Stylized start

902. . . Erase status?

904. . . Erase

906. . . Stylized Vt

908. . . Stylized R

910. . . Stylized end

950. . . Read start

952. . . Read Vt, R

954. . . End of reading

R1 ~ R4. . . resistance

V _tL1 ~ V _tL4 . . . Starting voltage

FIG. 1 is a block diagram of a memory device according to an embodiment of the invention.

FIG. 2 is a schematic diagram of a memory cell according to an embodiment of the invention.

3A and 3B are schematic diagrams showing a resistance value switching device according to some embodiments of the resistance value switching device shown in FIG. 2.

4A to 4E are resistance value switching characteristics of a symmetric two-state embodiment of the resistance value switching device shown in Figs. 3A and 3B.

Figure 5 is a graphical representation of the relationship between the memory state and the applied voltage of the symmetric two-state embodiment of the resistance value switching device shown in Figures 3A and 3B.

6 is a flow chart showing a reading method of the symmetric two-state embodiment of the read resistance value switching device shown in FIGS. 3A and 3B.

Figure 7 is a diagram showing the switching characteristics of the symmetric three-state embodiment of the resistance value switching device shown in Figures 3A and 3B.

Figure 8 is a diagram showing the switching characteristics of the asymmetric two-state embodiment of the resistance value switching device shown in Figures 3A and 3B.

Figure 9 is a diagram showing the switching characteristics of the asymmetric dual state/three state embodiment of the resistance value switching device shown in Figures 3A and 3B.

FIG. 10 is a flow chart of the read resistance value switching device according to the asymmetric embodiment shown in FIG.

FIG. 11 is a schematic diagram of a resistance value switching device according to the embodiment of the resistance value switching device shown in FIG. 2.

FIG. 12 is a diagram showing the relationship between voltage and current during the staging operation and the reading operation of the resistance value switching device shown in FIG. 11.

FIG. 13 is a schematic diagram of a resistance value switching device according to the embodiment of the resistance value switching device shown in FIG. 2.

Fig. 14 is a view showing the resistance switching characteristics of the upper PMC structure of the symmetric, dual PMC (dual-PMC) embodiment of the resistance value switching device shown in Fig. 13.

FIG. 15 is a diagram showing the resistance value switching characteristics of the lower PMC structure of the symmetric, dual PMC embodiment of the resistance value switching device shown in FIG.

16 is a diagram showing a resistance value switching relationship of a dual PMC structure including upper and lower PMC structures having resistance value switching characteristics shown in FIGS. 14 and 15, respectively.

Figure 17 is a flow chart showing the reading method used in the resistance value switching device shown in Figure 16.

Fig. 18 is a view showing the resistance value switching characteristic of the upper PMC structure of the asymmetric, dual PMC embodiment of the resistance value switching device shown in Fig. 13.

Fig. 19 is a view showing the resistance value switching characteristic of the lower PMC structure of the asymmetric, dual PMC embodiment of the resistance value switching device shown in Fig. 13.

20 is a diagram showing a resistance value switching relationship of a dual PMC (dual-PMC) structure including upper and lower PMC structures having resistance value switching characteristics shown in FIGS. 18 and 19, respectively.

Fig. 21 is a flow chart showing the reading procedure of the resistance value switching device shown in Fig. 20.

FIG. 22 is a schematic diagram of a resistance value switching device according to several embodiments of the resistance value switching device shown in FIG.

Fig. 23 is a view showing the resistance value switching characteristic of the upper memory structure of the embodiment of the resistance value switching device shown in Fig. 22.

Figure 24 is a diagram showing the resistance value switching characteristics of the lower memory structure of the embodiment of the resistance value switching device shown in Figure 22.

Fig. 25 is a diagram showing the resistance value switching characteristic of the resistance value switching device including the upper memory structure and the lower memory structure having the resistance value switching characteristics shown in Figs. 23 and 24, respectively.

Figure 26 is a flow chart showing the reading procedure of the resistance value switching device shown in Figure 25.

FIG. 27 is a diagram showing the resistance value switching characteristic of the upper memory structure of the embodiment of the resistor value switching device shown in FIG. 22.

FIG. 28 is a diagram showing the resistance value switching characteristic of the lower memory structure of the embodiment of the resistance value switching device shown in FIG. 22.

Fig. 29 is a diagram showing the resistance value switching characteristic of the resistance value switching device including the upper memory structure and the lower memory structure having the resistance value switching characteristics shown in Figs. 27 and 28, respectively.

Figure 30 is a flow chart showing the reading procedure according to the resistance value switching device shown in Figure 29.

Figure 31 is a flow chart showing the stylization procedure of the memory cell shown in Figure 2.

32 is a flow chart showing the reading procedure of the memory cell shown in FIG. 2.

Figure 33 is a diagram showing an I-V of an embodiment of the memory cell shown in Figure 2.

FIG. 34 is a diagram showing an I-V of another embodiment of the memory cell shown in FIG.

100. . . Memory device

102. . . Memory array

104. . . Row decoder

106. . . Sense amplifier

108. . . Row decoder

110. . . Source switch

Claims (33)

A memory device includes a memory cell array, wherein at least one memory cell comprises: a transistor having a first end, a second end, and a gate terminal, the starting voltage of the transistor being associated with each memory state Switching between different starting voltages; and a resistance value switching device connected in series with one of the first end and the second end of the transistor, the resistance value switching device being associated with each memory state Switch between multiple different resistance values. The memory device of claim 1, wherein the resistance value switching device comprises a first interface region and a second interface region, the first interface region and the second interface region each having different resistance values Switch characteristics. The memory device of claim 2, wherein at least one of the first interface region and the second interface region comprises at least a portion of the dielectric layer. The memory device of claim 3, wherein the dielectric layer comprises a tungsten oxide layer. The memory device of claim 2, wherein the resistance value switching characteristic of the first interface region is symmetrical with the resistance value switching characteristic of the second interface region. The memory device of claim 2, wherein the resistance value switching characteristic of the first interface region and the resistance value switching characteristic of the second interface region are asymmetric. The memory device of claim 1, wherein the resistance value switching device comprises a first programmable metallized memory cell. The memory device of claim 7, wherein the resistance value switching device comprises a second programmable metallized memory cell. The memory device of claim 8, wherein the first programmable metallized memory cell comprises a first memory layer, and the first memory layer is used as a first solid electrolyte layer, and The second programmable metalized memory cell includes a second memory layer and the second memory layer serves as a second solid electrolyte layer. The memory device of claim 9, wherein the resistance value switching device comprises a dielectric layer formed between the first memory layer and the second memory layer, and the dielectric layer comprises An oxidizable electrode layer between the first solid electrolyte layer and the second solid electrolyte layer. The memory device of claim 8, wherein the first programmable metallization memory cell and the second programmable metallization memory cell each have different resistance value switching characteristics. The memory device of claim 11, wherein the resistance value switching characteristic of the first programmable metallized memory cell and the resistance value switching characteristic of the second programmable metallized memory cell are symmetrical . The memory device of claim 11, wherein the resistance value switching characteristic of the first programmable metallized memory cell and the resistance value switching characteristic of the second programmable metallized memory cell are asymmetric . A memory device as described in claim 1 of the patent application, wherein The resistance value switching device includes a first memory structure and a second memory structure. The memory device of claim 14, wherein the first memory structure comprises a resistive random access memory (RRAM), a magnetoresistive random access memory (MRAM), and a ferroelectric random access memory. One of the bodies (FRAM). The memory device of claim 1, wherein the transistor comprises a floating gate. A memory device includes: a first control line; a second control line; a memory cell communicating with the first control line and the second control line, the memory cell comprising: a transistor having a first end, a second end and a gate terminal, a starting voltage of the transistor being switched between a plurality of different starting voltages associated with a memory state; and a resistance value switching device, the first of the transistors One end of the end and the second end are connected in series, and the resistance value switching device switches between a plurality of different resistance values associated with the memory state. The memory device of claim 17, wherein the gate terminal is connected to the second control line. The memory device of claim 17, wherein the first control line and the second control line are controlled to store data in the transistor and to store data in the resistance value switching device. A memory device as described in claim 17 of the patent application, wherein The first control line and the second control line are controlled to read data of the transistor and read data of the resistance value switching device. The memory device of claim 17, wherein the resistance value switching device comprises a first interface region and a second interface region, the first interface region and the second interface region having respective different resistance values Switch characteristics. The memory device of claim 21, wherein at least one of the first interface region and the second interface region comprises at least a portion of the dielectric layer. The memory device of claim 22, wherein the dielectric layer comprises a tungsten oxide layer. The memory device of claim 17, wherein the resistance value switching device comprises a first programmable metalized memory cell. The memory device of claim 24, wherein the resistance value switching device comprises a second programmable metalized memory cell. The memory device of claim 25, wherein the first programmable metallized memory cell comprises a first memory layer, and the first memory layer is used as a first solid electrolyte layer, and The second programmable metalized memory cell includes a second memory layer and the second memory layer serves as a second solid electrolyte layer. The memory device of claim 26, wherein the resistance value switching device comprises a dielectric layer formed between the first memory layer and the second memory layer, and the dielectric layer comprises An oxidizable electrode between the first solid electrolyte layer and the second solid electrolyte layer Floor. The memory device of claim 17, wherein the resistance value switching device comprises a first memory structure and a second memory structure. The memory device of claim 28, wherein the first memory structure comprises one of a resistive random access memory, a magnetoresistive random access memory, and a ferroelectric random access memory. The memory device of claim 17, wherein the transistor comprises a floating gate. A method of reading a memory cell of a semiconductor memory device, the method comprising: detecting a starting voltage of a transistor of the memory cell, the starting voltage of the transistor being in a plurality of different states associated with each memory state Switching between initial voltages; and detecting a resistance value of the resistance value switching device of the memory cell, the resistance value switching device being connected in series with the transistor, the resistance value switching device being associated with a plurality of memory states Switch between resistance values. The method of claim 31, wherein the detecting the threshold voltage of the transistor comprises applying a first voltage at a gate terminal of the transistor and applying a second voltage to the memory cell, When the first voltage exceeds the current programmed starting voltage of the transistor, current is caused to flow through the resistance value switching device. The method of claim 31, wherein the step of detecting the resistance value of the resistance value switching device comprises allowing a current to flow through the transistor.