TWI682280B - 半導體裝置、半導體系統以及系統晶片 - Google Patents

半導體裝置、半導體系統以及系統晶片 Download PDF

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Publication number
TWI682280B
TWI682280B TW104127599A TW104127599A TWI682280B TW I682280 B TWI682280 B TW I682280B TW 104127599 A TW104127599 A TW 104127599A TW 104127599 A TW104127599 A TW 104127599A TW I682280 B TWI682280 B TW I682280B
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TW
Taiwan
Prior art keywords
data
memory
cache memory
semiconductor device
processor
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TW104127599A
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English (en)
Chinese (zh)
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TW201608373A (zh
Inventor
禹敦志
金寬浩
金美卿
李範宇
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南韓商三星電子股份有限公司
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Publication of TW201608373A publication Critical patent/TW201608373A/zh
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0842—Multiuser, multiprocessor or multiprocessing cache systems for multiprocessing or multitasking
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0891—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using clearing, invalidating or resetting means
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0893—Caches characterised by their organisation or structure
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1673—Details of memory controller using buffers
TW104127599A 2014-08-29 2015-08-25 半導體裝置、半導體系統以及系統晶片 TWI682280B (zh)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US201462043595P 2014-08-29 2014-08-29
US62/043,595 2014-08-29
KR10-2014-0143553 2014-10-22
KR1020140143553A KR102261591B1 (ko) 2014-08-29 2014-10-22 반도체 장치, 반도체 시스템 및 시스템 온 칩

Publications (2)

Publication Number Publication Date
TW201608373A TW201608373A (zh) 2016-03-01
TWI682280B true TWI682280B (zh) 2020-01-11

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TW104127599A TWI682280B (zh) 2014-08-29 2015-08-25 半導體裝置、半導體系統以及系統晶片

Country Status (3)

Country Link
JP (1) JP6641120B2 (ko)
KR (1) KR102261591B1 (ko)
TW (1) TWI682280B (ko)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11868818B2 (en) * 2016-09-22 2024-01-09 Advanced Micro Devices, Inc. Lock address contention predictor
KR102526499B1 (ko) * 2020-09-28 2023-05-02 고려대학교 산학협력단 Fpga 기반 캐시 무효화 방법 및 이를 수행하는 장치

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004258935A (ja) * 2003-02-26 2004-09-16 Matsushita Electric Ind Co Ltd 半導体装置
US20080005465A1 (en) * 2006-06-30 2008-01-03 Matthews Jeanna N Write ordering on disk cached platforms
TWI312966B (en) * 2005-10-31 2009-08-01 Sigmatel Inc Direct memory access module, integrated circuit, and method of processing a memory request
TW201234263A (en) * 2010-12-12 2012-08-16 Russell Hamilton Fish Iii CPU in memory cache architecture

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004258935A (ja) * 2003-02-26 2004-09-16 Matsushita Electric Ind Co Ltd 半導体装置
TWI312966B (en) * 2005-10-31 2009-08-01 Sigmatel Inc Direct memory access module, integrated circuit, and method of processing a memory request
US20080005465A1 (en) * 2006-06-30 2008-01-03 Matthews Jeanna N Write ordering on disk cached platforms
TW201234263A (en) * 2010-12-12 2012-08-16 Russell Hamilton Fish Iii CPU in memory cache architecture

Also Published As

Publication number Publication date
KR102261591B1 (ko) 2021-06-04
JP2016051471A (ja) 2016-04-11
KR20160026599A (ko) 2016-03-09
JP6641120B2 (ja) 2020-02-05
TW201608373A (zh) 2016-03-01

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