TWI682280B - Semiconductor device, semiconductor system and system on chip - Google Patents

Abstract

At least one example embodiment discloses a semiconductor device including a direct memory access (DMA) system configured to directly access a memory to write first data to an address of the memory, wherein the DMA system includes an initializer configured to set a data transfer parameter for writing the first data to the memory during a flushing period of second data from a cache to the address by a processor, a creator configured to create the first data based on the set data transfer parameter, and a transferer configured to write the first data to the address of the memory after the flushing period based on the data transfer parameter.

Description

Semiconductor device, semiconductor system and system chip

This application claims the priority of Provisional Application No. 62/043,595 filed on August 29, 2014 and Korean Patent Application No. 10-2014-0143553 filed with the Korean Intellectual Property Office on October 22, 2014, As well as all rights and interests arising from 35U.SC §119, the contents of the application are incorporated herein by reference.

At least some example embodiments relate to a semiconductor device, a semiconductor system, and a system wafer.

The direct memory access (DMA) method is that the controller of the input/output (I/O) device controls the data transfer from the peripheral device to the main memory without using a central processing unit (CPU) Data transmission method of the execution program. The DMA method can increase the data input/output speed and can reduce the speed difference between the CPU and peripheral devices. If the input/output device requests DMA, the CPU transfers control of the main memory. Whenever the CPU cycle is ended, the CPU may permit this operation.

However, when the peripheral device processing unit with built-in DMA to be used will When the updated data is sent to the specific address of the system memory, the existing data received from the specific address of the system memory and stored in the cache memory is not valid, so that the cache memory is first invalidated (for example, Clear) to start the DMA function.

At least some example embodiments provide a semiconductor device that can improve overall performance by performing a DMA function while failing (ie, flushing) the cache memory.

At least some example embodiments also provide a semiconductor system that can improve overall performance by performing a DMA function while disabling (ie, flushing) the cache memory.

At least some example embodiments also provide a system chip that can improve overall performance by performing DMA functions while failing (ie, flushing) the cache memory.

These and other objectives of example embodiments will be described in or will be apparent from the following description of at least some example embodiments.

According to at least one example embodiment, a semiconductor device is provided that includes a direct memory access (DMA) system configured to directly access memory to write first data to an address of the memory, wherein the DMA system Contains: an initializer configured to set data transfer parameters during the data removal cycle of the second data from the cache to the address by the processor, the data transfer parameters used to write the first data To memory; builder, configured to build based on the data transfer parameters set Establish the first data; and the transmitter is configured to write the first data to the address of the memory after the data removal cycle based on the data transmission parameters.

The first data is different from the second data.

The builder is configured to receive the first data from an external device or directly create the first data.

The builder is configured to perform at least one of a read operation and a write operation on the external device.

The semiconductor device further includes a buffer configured to store the first data.

The builder is configured to store the first data in the buffer.

The transmitter is configured to transmit the first data stored in the buffer to the memory.

The data transmission parameters include the size of the first data, the address of the buffer storing the first data, and the address of the memory.

The initializer is configured to receive information related to the data transfer parameters and information related to the clearing of the cache memory from the processor.

The transmitter is configured to receive information related to the clearing of the cache memory from the initializer, and the transmitter is disabled during the data removal cycle.

The transmitter is configured to operate after the data removal cycle.

The transmitter is configured to receive information about the clearing of the cache memory from the processor.

The transmitter is configured to receive information about the clearing of the cache memory from the cache memory.

The processor includes a central processing unit (central processing unit; CPU).

The memory includes dynamic random access memory (DRAM).

The creator is configured to create the first data after the initializer sets the data transfer parameters.

The creator is configured to create the first data during the data removal cycle.

The transmitter is configured to send the first data to the address of the memory after the creator creates the first data.

The builder is configured to perform at least one of a read operation and a write operation on the memory.

The semiconductor device further includes a buffer configured to store the first data, where the first data includes third data and fourth data.

The address of the memory includes a first address and a second address. The transmitter is configured to perform the first transmission of the third data to the first address and the fourth data to the first address after the first transmission The second transmission of the two addresses, and the transmitter performs the first transmission while the creator creates the fourth data.

The creator is configured to create third data during the data removal cycle, and create fourth data after the data removal cycle.

According to at least one example embodiment, a semiconductor device is provided that includes a direct memory access (DMA) system configured to directly access memory, and configured to store first data to be transferred to memory and A buffer for the second data, wherein the DMA system includes: an initializer configured to set data transfer parameters during a data removal cycle of the third data from the cache to the first address of the memory, the data The transmission parameters are used to transfer the first data and the second data to the memory; the builder is configured to perform the first creation and the second creation in sequence, and the builder is configured to create the first by based on the data transmission parameters Data and storing the first data in the buffer during the data removal cycle to perform the first creation, and the creator Configured to perform the second creation by creating the second data and storing the second data in the buffer; and the transmitter, configured to perform the first transmission and the second transmission in sequence, the transmitter is configured To perform the first transfer such that the first data stored in the buffer is transferred to the first address of the memory after the data removal period and during the second creation based on the data transfer parameters, and the transmitter is configured to execute The second transfer causes the second data stored in the buffer to be transferred to the second address of the memory.

The builder is configured to perform the first build after the initializer completes the setting of the data transfer parameters.

The transmitter is configured to perform the second transmission after completing the second establishment.

According to at least one example embodiment, a semiconductor system is provided that includes: a cache memory connected to the memory via a bus; a first processor configured to store the cache memory during a data removal cycle The first data in is arranged to the address of the memory; and the second processor is configured to create a second data different from the first data and send the second data to the address of the memory, wherein the second The processor includes a buffer configured to store the second data and a direct memory access (DMA) system configured to set the second data to the memory during the data removal cycle The data transfer parameters of and the second data stored in the buffer to the address of the memory based on the data transfer parameters after the data removal period.

The first processor is configured to perform at least one of a read operation and a write operation on the cache memory.

The DMA system includes: an initializer configured to set data transfer parameters for transferring the second data to the memory; a builder configured to create second data to be transferred to the memory based on the data transfer parameters; and Transmitter, configured to be based on The data transmission parameter transmits the second data to the address of the memory.

The initializer is configured to receive information related to the data transfer parameters and information related to the clearing of the cache memory from the processor.

The first and second processors are connected to each other via a bus.

According to at least one example embodiment, a semiconductor system is provided that includes: a cache memory connected to the memory via a bus; a first processor configured to store the cache memory during a data removal cycle The first data in is cleared to the address of the memory; and the second processor is configured to create a second data different from the first data and send the second data to the address of the memory via the bus, The second processor includes a buffer configured to store the second data and a direct memory access (DMA) system configured to transfer the second data stored in the buffer to the memory Address, and wherein the DMA system includes: an initializer configured to set data transfer parameters for transferring the second data to the memory during the data removal cycle and receiving data transfer parameters from the first processor Information and information related to the clearing of cache memory; a builder configured to create second data to be sent to memory based on data transfer parameters and store the second data in a buffer; and a transmitter , Configured to transfer the second data stored in the buffer to the address of the memory after the data removal cycle based on the data transfer parameters.

According to at least one example embodiment, a semiconductor system is provided that includes: a cache memory connected to the memory via a bus; a first processor configured to store the cache memory during a data removal cycle The first data in is sorted to the address of the memory; the second processor includes a first buffer configured to store second data different from the first data; and the third processor includes Direct memory access (DMA) system with direct access memory, where the second processor is configured To create the second data and store the second data in the first buffer, and the DMA system includes: an initializer configured to set the data transfer for transferring the second data to the memory during the data removal cycle Parameters; a builder configured to receive the second data stored in the first buffer based on the data transmission parameters; and a transmitter configured to transmit the second data to the second data after the data removal cycle based on the data transmission parameters The address of the memory.

The initializer is configured to receive information related to data transfer parameters and information related to the clearing of the cache memory from the first processor.

The third processor further includes a second buffer configured to store the received second data.

The builder is configured to store the second data received from the first buffer in the second buffer.

The transmitter is configured to transmit the second data stored in the second buffer to the address of the memory.

The builder is configured to receive the second data after setting the data transmission parameters.

The second processor is configured to create second data and store the second data in the first buffer during the data removal cycle.

The builder unit is configured to receive the second data during the data removal cycle.

The transmitter is configured to transmit the second data to the address after the creator receives the second data.

The first to third processors are connected to each other via a bus.

The third processor is configured to receive data transfer parameters from the initializer, and Create the second data based on the data transfer parameters.

According to at least one example embodiment, there is provided a system chip including: a memory; a cache memory connected to the memory; a first processor configured to store the cache memory during a data removal cycle Retrieve the first data in the memory to the address of the memory; the second processor, including a first buffer configured to store second data different from the first data; and the third processor, including A direct memory access (DMA) system configured to directly access memory, in which the memory and the first to third processors comply with the AMBA advanced eXtensible interface (AXI) protocol The buses are connected to each other, the second processor is configured to create the second data and store the second data in the first buffer, and the DMA system includes: an initializer configured to set the data removal cycle Data transmission parameters for transmitting the second data to the memory; a builder configured to receive the second data stored in the first buffer based on the data transmission parameters; and a transmitter configured to transmit the data based on the data transmission parameters After the data removal cycle, the second data is sent to the address of the memory.

At least one example embodiment discloses a memory system including: a memory; a processor configured to drain the first data in the cache to the memory during a data removal cycle Address; a direct memory access system that includes an initializer configured to operate during the data removal cycle and create the second data, and configured to be outside the data removal cycle The transmitter that sends the second data to the address of the memory.

In an example embodiment, the initializer is configured to generate data transfer parameters during the data removal cycle, and the transmitter is configured to transfer second data based on the data transfer parameters.

In an example embodiment, the transmitter is configured to transmit the second data to the address after the data removal cycle.

In an example embodiment, the memory system is configured to deactivate the transmitter before the data removal cycle.

In an example embodiment, the memory system is configured to enable the transmitter when the data removal cycle ends.

In an example embodiment, the memory includes a three-dimensional memory array.

In example embodiments, the three-dimensional memory includes non-volatile memory formed monolithically in one or more physical levels of memory cells having active regions disposed above a silicon substrate.

In an example embodiment, the three-dimensional memory array includes a plurality of memory cells, and each of the memory cells includes a charge trapping layer.

In an example embodiment, at least one of word lines and bit lines in the three-dimensional memory array is shared between levels.

100‧‧‧Semiconductor device

110,440,540‧‧‧DMA module

115, 442, 542‧‧‧ setting unit

120, 445, 545‧‧‧ building unit

125, 447, 547‧‧‧ transmission unit

160, 450‧‧‧ buffer

200‧‧‧Memory

250‧‧‧ processor

300, 420, 520 ‧‧‧ cache memory

350‧‧‧External device

400、500‧‧‧Semiconductor system

410, 510‧‧‧ First processor

430, 530‧‧‧ second processor

470, 595‧‧‧bus

550‧‧‧External memory

560‧‧‧First buffer

580‧‧‧ Third processor

590‧‧‧second buffer

1200‧‧‧ Tablet PC

1300‧‧‧Note PC

1400‧‧‧Smartphone

S100, S105, S107, S110, S113, S115, S117, S120, S122, S125, S127, S130, S200, S205, S207, S210, S213, S215, S217, S220, S222, S225, S227, S230, S300, S305, S307, S310, S313, S314, S315, S317, S320, S322, S325, S327, S330

_{t 1, t 2, t 3} , t 4, t 5, t 1 ', t 2', t 3 ', t 4', t 5 ', t 6' ‧‧‧ time

The above and other features and advantages of the example embodiments will become more apparent by describing at least some example embodiments thereof in detail with reference to the drawings, in which:

FIG. 1 is a block diagram of a semiconductor device according to an embodiment.

FIG. 2 is a block diagram of the DMA module shown in FIG. 1.

3 and 4 are schematic diagrams for explaining the operation of the semiconductor device shown in FIG. 1.

5 is a block diagram of a semiconductor system according to an embodiment.

6 is a block diagram of the second processor shown in FIG. 5.

7 is a block diagram of a semiconductor system according to another embodiment.

FIG. 8 is a block diagram of the second and third processors shown in FIG. 7.

9 is a diagram illustrating the semiconductor system depicted in FIG. 7 implemented as a system wafer.

10 to 12 illustrate an electronic system according to at least some example embodiments to which a semiconductor system can be applied.

13 and 14 are diagrams illustrating the operation method of the semiconductor device illustrated in FIG. 1.

15 and 16 are diagrams illustrating the operation method of the semiconductor system illustrated in FIG. 5.

17 and 18 are diagrams illustrating the operation method of the semiconductor system illustrated in FIG. 7.

The advantages, features, and implementation methods of the inventive concept can be more easily understood by referring to the following detailed description of example embodiments and accompanying drawings. However, the inventive concept can be embodied in many different forms and should not be interpreted as being limited to the embodiments set forth herein. On the contrary, example embodiments are provided so that the content of the present disclosure will be thorough and complete, and will fully convey the concept of the inventive concept to those skilled in the art, and the inventive concept will only be defined by the scope of the attached patent application. Throughout this description, similar reference numbers refer to similar elements.

The terminology used herein is for the purpose of describing particular embodiments only, and It is not intended to limit the inventive concept. As used herein, the singular forms "a" and "said" are also intended to include the plural forms unless the context clearly indicates otherwise. It should be further understood that the term "comprises and/or comprising" when used in this specification specifies the presence of stated features, integers, steps, operations, elements and/or components, but does not exclude one or more other The presence or addition of features, integers, steps, operations, elements, components, and/or groups thereof.

It should be understood that when an element or layer is referred to as being “on”, “connected to” or “coupled to” another element or layer, it can be directly on the other element or layer, connected or Coupled to other elements or layers, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers present. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

It should be understood that although the terms first, second, etc. may be used herein to describe various elements, components, regions, layers and/or sections, such elements, components, regions, layers and/or sections should not be affected by These terms are limited. These terms are only used to distinguish one element, component, region, layer or section from another region, layer or section. Therefore, without departing from the teachings of the inventive concept, the first element, component, region, layer, or section discussed below may be referred to as the second element, component, region, layer, or section.

For ease of description, spatial relative terms such as "below", "below", "lower", "above", "upper", and the like can be used in this article to describe The relationship between one element or feature and another element or feature described. It should be understood that spatial relative terms are intended to cover different orientations of the device in use or operation than those depicted in the figures. For example, if the device in the figure Elements described as "below" or "beneath" other elements or features would be oriented "above" the other elements or features. Thus, the exemplary term "below" can encompass both orientations above and below. The device can be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art to which the general inventive concept belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology and this specification, and should not be interpreted in an idealized or excessively formal sense, unless in this context So clearly defined.

Hereinafter, a semiconductor device according to example embodiments will be described with reference to FIGS. 1 to 4.

1 is a block diagram of a semiconductor device according to at least one example embodiment, FIG. 2 is a block diagram of the module illustrated in FIG. 1, and FIGS. 3 and 4 are diagrams for explaining the semiconductor device illustrated in FIG. Schematic diagram of operation.

As used herein, "unit" or "module" refers to a hardware component such as a processor or a field-programmable gate array (FPGA) or an application-specific integrated circuit (FPGA) Application Specific Integrated Circuit (ASIC) hardware components execute software components that perform predetermined and/or desired functions. However, a unit or module does not always have a meaning limited to software or hardware. The module may be constructed to be stored in an addressable storage medium or to execute one or more processors. Therefore, modules include, for example, software components, object-oriented software components, class components or task components, processing sequences, functions, properties, procedures, sub-components Routines, code segments, drivers, firmware, microcode, circuits, data, databases, data structures, tables, arrays, and parameters. The components and functions provided by the module can be combined into a smaller number of components or modules or can be divided into a larger number of components or modules.

When the module is hardware, the existing hardware may include one or more central processing units (Central Processing Unit; CPU), digital signal processors (DSP), application-specific-integrated-circuit ; ASIC), field programmable gate array (FPGA) computer or similar configured as a dedicated machine to perform the function of the module. As stated above, CPU, DSP, ASIC, and FPGA may be commonly referred to as processing devices.

In the case where the module executes software for the processor, the processor is configured as a dedicated machine to execute the software stored in the storage medium to perform the function of the module.

Referring to FIG. 1, the semiconductor device 100 may include a DMA module 110 and a buffer 160.

The DMA module 110 can directly access the memory 200.

In detail, the DMA module 110 can directly create data or can receive data from an external device to store it in the buffer 160, and can transfer the data stored in the buffer 160 to the memory 200.

In addition, the DMA module 110 may perform a read operation or a write operation on the memory 200.

The buffer 160 can store data received from the DMA module 110. Here, when the DMA module 110 transmits data, it may not occupy the bus (not shown). Therefore, the buffer 160 may have a size large enough to allow the DMA module 110 to operate without deteriorating performance.

In detail, the buffer 160 may have a transfer rate from the DMA module 110 at a time. The storage area with the largest amount of data sent to the memory 200 is large.

In addition, the memory 200 may include, for example, DRAM, but example embodiments are not limited thereto. In addition, the memory 200 may include a data area for storing general data and a spherical area. Each area of the memory 200 may include multiple memory blocks.

The non-volatile memory may be a two-dimensional (2D) or three-dimensional (3D) memory array. The 3D memory array is monolithically formed in the physical level of the array of memory cells with active regions disposed above the silicon substrate and the circuits associated with the operation of their memory cells, regardless of the associated The circuit is above or inside this substrate. The term "monolithic" means that the layer of each level of the array is deposited directly on the layer of each underlying level of the array.

The 3D memory array includes vertical NAND strings that are vertically oriented so that at least one memory cell is located on another memory cell. At least one memory cell may include a charge trapping layer.

The following patent documents incorporated herein by reference describe suitable configurations for three-dimensional memory arrays, where the three-dimensional memory array is configured into multiple levels, where word lines and/or bit lines are shared between the levels : US Patent No. 7,679,133; 8,553,466; 8,654,587; 8,559,235; and US Patent Application Publication No. 2011/0233648.

Yet another detailed configuration of the memory 200 is known to those skilled in the art, and a detailed description thereof will not be given.

Referring to FIG. 2, the DMA module 110 may include a setting unit (initializer) 115, a establishing unit (establisher) 120, and a transmitting unit (transmitter) 125.

The setting unit 115 may set the data transfer parameter DP for writing the first data to the memory 200.

In detail, the setting unit 115 can receive information (DP.I) related to the data transfer parameter DP from the processor 250, and can set the data transfer parameter DP. Here, the data transmission parameter DP may include, for example, the size of the first data to be transmitted to the memory 200, the address of the buffer 160 storing the first data to be transmitted to the memory 200, and the first data to be transmitted to The predetermined and/or selected location of the memory 200 of the example, but the example embodiment is not limited thereto. The first data is data to be transmitted to the memory 200.

Here, the processor 250 may include, for example, a central processing unit (CPU), but example embodiments are not limited thereto. In addition, the first data may include updated data to be stored in the predetermined and/or selected address of the memory 200.

The setting unit 115 can receive information related to data transfer parameters (DP.I) and information related to cache memory failure (also known as flushing) from the processor 250 (CI.I), and can start based on receiving The information related to cache memory clearing (CI.I) sets the data transfer parameter DP. That is, the data transfer parameter DP can be set based on the information related to the data transfer parameter (DP.I) received from the processor 250, and the setting can be determined based on the information related to the cache memory clearing received from the processor 250. The start time of the operation.

In the illustrated example embodiment, information related to cache memory clearing (CI.I) is provided from the processor 250 to the setting unit 115, but the example embodiment is not limited thereto. In more detail, the information related to the clearing of the cache memory provided first from the processor 250 to the setting unit 115 and then from the setting unit 115 to the transmission unit 125 is described, but the example embodiments are not limited thereto. That is, the information related to cache memory clearing (CI.I) can also be provided directly from the processor 250 to the transmission unit 125 without passing through the setting unit 115, and once the clearing of the cache memory 300 begins , The cache memory 300 can create information (CI.I) related to cache memory clearance in itself and can It is provided to the transfer unit 125. However, for convenience, in the following description, it is assumed by way of example that information related to cache memory clearing (CI.I) is provided from the processor 250 to the setting unit 115.

While the processor 250 arranges the second data stored in the cache memory 300 to the predetermined and/or selected address of the memory 200, the setting unit 115 is executed to set the data transfer parameter DP. Here, the second data is existing data that is different from the first data that is updated data (ie, unupdated data). In addition to the clearing of the cache memory 300, the processor 250 can also perform a read operation or a write operation on the cache memory 300.

The setting unit 115 may provide the set data transmission parameter DP to the establishment unit 120 and the transmission unit 125. In addition, the setting unit 115 may provide information related to cache memory clearing (CI.I) to the transmission unit 125, which will be described in more detail later.

The establishing unit 120 may create the first data to be transmitted to the memory 200 based on the set data transmission parameter DP.

In detail, the establishment unit 120 can receive the data transmission parameter DP from the setting unit 115 and can create the first data based on the data transmission parameter DP. Here, the expression "the creation unit 120 creates data" may mean that the creation unit 120 may receive (read) the data from the external device 350 or may directly create the data in itself. In addition, the establishing unit 120 may store (write) the created first data in the buffer 160.

Here, the external device 350 may include, for example, a multi-media card (MMC), but example embodiments are not limited thereto.

That is, the creation unit 120 creates the first data according to the data size indicated by the data transfer parameter DP, and can store the created first data in the data transfer parameter The address of the buffer 160 indicated by the number DP.

The establishment unit 120 may perform a read operation or a write operation on the external device 350. As described above, the creation unit 120 can receive (read) the first data from the external device 350 to create the first data. In addition to the reading operation, the establishing unit 120 can also perform a data writing operation on the external device 350.

The transmission unit 125 may write the first data to a predetermined and/or selected address of the memory 200 based on the data transmission parameter DP.

In detail, the transmission unit 125 may receive the data transmission parameter DP from the setting unit 115 or may transmit the first data to the predetermined and/or selected location of the memory 200 based on the data transmission parameter DP. Here, the transmission unit 125 may transmit the first data stored in the buffer 160 to the memory 200.

That is, the transmission unit 125 can read the first data stored in the address of the buffer 160 indicated by the data transmission parameter DP, and can transmit (write) the first data to the memory indicated by the data transmission parameter DP The predetermined and/or selected location of the body 200.

After the clearing of the cache memory 300 is completed, the transmission unit 125 may transmit the first data to the predetermined and/or selected location of the memory 200.

In addition, the transmission unit 125 may receive the cache-related information (CI.I) from the setting unit 115 when the cache memory 300 is cleared and then deactivate the cache memory 300 (for example, signaling the cache (Information on the clearing of the memory 300). Here, the transmission unit 125 may be deactivated before the clearing of the cache memory 300 starts, at the same time as the clearing of the cache memory 300 starts, or in all cases after the clearing of the cache memory 300 starts.

After the clearing of the cache memory 300 is completed, the transmission unit 125 may set itself The setting unit 115 receives information related to clearing (CI.I) of the cache memory 300 to be activated next (for example, information to signal completion of clearing of the cache memory 300).

The transmission unit 125 may perform a read operation or a write operation on the memory 200. As described above, the transmission unit 125 can transmit (write) the first data to the predetermined and/or selected address of the memory 200. In addition to the writing operation, the transmission unit 125 can also perform the data reading operation from the memory 200.

Referring to FIG. 2 and FIG. 3, the operation of the DMA module starts after the failure operation (ie, clearing) of the cache memory is completed. Specifically, FIG. 3 illustrates a case where the semiconductor device 100 according to example embodiments is not applied.

That is, the operation of the DMA module can be blocked during a cache memory failure period (corresponding to a time period ranging from t ₁ to t ₂ ) in which the processor clears the cache memory. If the operation of the DMA module is not blocked during the cache memory data removal cycle (t ₁ to t ₂ ), the address of the memory to which the cache memory is flushed and the DMA module intends to transfer data to When the memory addresses are the same as each other, the data (ie, unupdated data or existing data) cleared by the cache memory can be overwritten on the updated data to be transmitted by the DMA module.

Therefore, the DMA function can be blocked during the cache memory data removal period (t ₁ to t ₂ ), and the initial setting operation of the DMA module (that is, the operation of the setting unit to set the data transfer parameters) can automatically complete the cache memory The time t _{2 for the} removal of the body begins.

If the initial setting operation of the DMA module is completed at time t ₃ , the first data creation operation (data creation 1) (that is, the operation of the creation unit creating the first data) may start from time t ₃ .

In addition, if the first data creation operation (data creation 1) is completed at time t ₄ , the second data creation operation (data creation 2) (ie, the creation unit creates the second data of the updated data, the second data Different from the first data) and the first data transmission operation (data transmission 1) (that is, the operation of the transmission unit transmitting the first data to the memory) can start from time t ₄ at the same time. That is, the operations of the transmission unit and the establishment unit of the DMA module can be executed in a pipelined manner.

Next, if the second data creation operation (data creation 2) and the first data transfer operation (data transfer 1) are completed at time t ₅ , the second data transfer operation (data transfer 2) (that is, the transfer unit data transmission to the memory operation) may start at time t _5.

Here, the address of the memory to which the second data is transferred and the address of the memory to which the first data is transferred may be different from each other.

As shown in Figure 3, it is possible to prevent the data (that is, unupdated data or existing data) cleared by the cache memory from being overwritten on the updated data, but the execution time of the DMA module may be The cache memory drain time (cache failure) is extended, thereby reducing overall performance.

At the same time, referring to FIG. 2 and FIG. 4, the operation of the DMA module starts at the same time as the failure operation (ie, clearing) of the cache memory. Specifically, FIG. 4 illustrates a case where the semiconductor device 100 is applied.

The following description will focus on the difference between the situations depicted in FIGS. 3 and 4.

That is, in the cache memory failure cycle in which the processor clears the cache memory (cache memory failure) corresponding to the time period ranging from t ₁ to t ₂ , unlike the DMA module in FIG. 3 Is not blocked.

In detail, while the clearing of the cache memory starts at time t ₁ ′, the transfer unit of the DMA module is disabled (data transfer disabled). As described above, the transfer unit of the DMA module may be disabled before the flushing of the cache memory, at the same time as the flushing of the cache memory starts, or after the flushing of the cache memory is started. However, for convenience, the following description will be made regarding the case of FIG. 4 in which the transfer unit of the DMA module is deactivated at the beginning of the flushing of the cache memory.

Here, the deactivation period of the transmission unit may continue until time t ₄ ′, that is, until the time when the clearing of the cache memory is completed. This is to prevent data cleared by the cache memory (ie, unupdated data or existing data) from being overwritten on the updated data.

DMA module initial setting operation (i.e., operation information setting unit sets the transmission parameter DP) in the emptying time can cache backward starting t ₁ 'a little time t _2' starts.

That is, the operation of the DMA module 110 may be performed during the cycle of clearing the cache memory 300. Therefore, unlike in FIG. 3, the execution time of the DMA module may be extended due to the clearing time of the cache memory 300 (cache memory failure).

If the initial setting operation of the DMA module 110 is completed at time t ₃ ′, the first data creation operation (data creation 1) (that is, the operation of the creation unit to create the first data) may start from time t ₃ ′. Here, the first data creation operation (data creation 1) and the clearing time of the cache memory 300 can be pipelined.

In detail, the first data creation operation (data creation 1) starts during the clearing time of the cache memory 300 (ie, between t ₁ ′ and t ₄ ′), and can be completed after the cache memory 300 is completed. Before the clearing, the clearing of the cache memory 300 is completed at the same time or after the clearing of the cache memory 300 is completed.

Further, if the time t ₄ 'complete emptying of the cache memory, the time may be at t _4' is enabled after the DMA transfer unit module (data transmission enabled). Therefore, if the first data creation operation (data creation 1) is completed at time t ₅ ', the second data creation operation (data creation 2) (that is, the creation unit creates the second data different from the first data, the first A data is the updated data) and the first data transmission operation (data transmission 1) (ie, the operation of the transmission unit transmitting the first data to the memory) can start at time t ₅ ′.

That is, the operations of the transfer unit 125 and the establishment unit 120 of the DMA module 110 can be performed in a pipelined manner.

Next, if the second data creation operation (data creation 2) and the first data transfer operation (data transfer 1) are completed at time t ₆ ', the second data transfer operation (data transfer 2) (that is, the transfer unit 2. The operation of transferring data to the memory) can start at time t ₆ '.

In the semiconductor device 100, the deactivation cycle of the transmission unit 125 continues until the time when the clearing of the cache memory 300 is completed, thereby preventing data cleared by the cache memory (ie, unupdated data or existing data ) Is overwritten on the updated data, and the execution time of the DMA module 110 is accelerated due to the clearing time of the cache memory 300, and finally the overall performance is improved.

In addition, in at least some example embodiments, the setting unit 115, the establishment unit 120, and the transfer unit 125 are implemented in hardware, but the example embodiments are not limited thereto. That is, the setting unit 115, the establishing unit 120, and the transmitting unit 125 may also be implemented in a processor configured to execute software stored in the DMA module 110 in a code format.

Hereinafter, a semiconductor system according to example embodiments will be described with reference to FIGS. 5 and 6. In the following description, the same contents as the previous example embodiments will not be repeatedly described.

5 is a block diagram of a semiconductor system according to an example embodiment, and FIG. 6 It is a block diagram of the second processor shown in FIG. 5.

Referring to FIG. 5, the semiconductor system 400 may include a first processor 410, a cache memory 420, a second processor 430 and a bus 470.

The first processor 410 may clear the data stored in the cache memory 420 (for example, existing data, that is, unupdated data) to a predetermined and/or selected location of the memory 200.

In detail, in addition to the clearing of the cache memory 420, the first processor 410 can also perform a read operation or a write operation on the cache memory 420. In addition, the first processor 410 may provide information related to the data transfer parameter DP and information related to the failure or clearing of the cache memory 420 to the second processor 430.

Here, the first processor 410 may include, for example, a central processing unit (CPU), and the memory 200 may include, for example, DRAM, but example embodiments are not limited thereto.

The cache memory 420 can be cleared by the first processor 410.

In detail, the cache memory 420 can be cleared by the first processor 410 to the predetermined and/or selected location of the memory 200. In addition, the cache memory 420 can be connected to the memory 200 via a bus 470.

The second processor 430 may create data (updated data) different from the data stored in the cache memory 420, and may transmit the created data to the predetermined and/or selected location of the memory 200.

Here, the second processor 430 can directly create data in itself or can receive data from the external device 350.

The bus 470 may connect the first processor 410, the second processor 430, and the cache memory 420 to each other, and may interconnect the semiconductor system 400 and the memory 200 connection.

In detail, the first processor 410 provides information related to the data transfer parameter DP and information related to the failure or clearing of the cache memory 420 to the second processor 430, and the cache memory 420 is cleared to The predetermined and/or selected address of the memory 200 and the predetermined and/or selected address of the second processor 430 to transmit data to the memory 200 may all be executed through the bus 470.

In addition, the semiconductor system 400 including the first processor 410, the cache memory 420, the second processor 430, and the bus 470 is illustrated in FIG. 5, but example embodiments are not limited thereto. That is, the semiconductor system 400 may also include the memory 200 and the external device 350.

Referring to FIG. 6, the second processor 430 may include a DMA module 440 and a buffer 450. Here, the second processor 430 may be the semiconductor device 100 shown in FIG. 2.

Therefore, the DMA module 440 can directly access the memory 200 via the bus 470.

In detail, the DMA module 440 can set data transfer parameters DP for transferring data to the memory 200 and can create data to be transferred to the memory 200 based on the data transfer parameters DP to then store them in the buffer 450. In addition, the DMA module 440 can transfer the data stored in the buffer 450 to a predetermined and/or selected address of the memory 200. Here, the DMA module 440 can directly create data to be transferred to the memory 200 in itself or can receive data from the external device 350.

In addition, the DMA module 440 may include a setting unit 442, a setting unit 445, and a transfer unit 447, which are the same as described above, and a detailed description will not be given.

In addition, in the illustrated example embodiment, it will be related to the cache memory (CI.I) is provided from the first processor 410 to the second processor 430 (for example, the setting unit 442 of the second processor 430), but the example embodiments are not limited thereto. In more detail, the information related to cache memory clearing (CI.I) provided first from the first processor 410 to the setting unit 442 and then from the setting unit 442 to the transmission unit 447, but an example embodiment Not limited to this. That is, information related to cache memory clearing (CI.I) can also be directly provided from the first processor 410 to the transmission unit 447 via the bus 470 without passing through the setting unit 442, and once cached When the clearing of the memory 420 is started, the cache memory 420 can create information (CI.I) related to the clearing of the cache memory in itself and can provide it to the transmission unit 447 via the bus 470.

Hereinafter, a semiconductor system according to another example embodiment will be described with reference to FIGS. 7 and 8. In the following description, the same content as the previous embodiment will not be repeatedly described.

7 is a block diagram of a semiconductor system according to another example, and FIG. 8 is a block diagram of the second and third processors shown in FIG. 7.

Referring to FIG. 7, the semiconductor system 500 may include a first processor 510, a cache memory 520, a second processor 530, a third processor 580, and a bus 595.

The first processor 510 may arrange the data stored in the cache memory 520 (for example, existing data, that is, unupdated data) to a predetermined and/or selected location of the memory 200.

In detail, in addition to the clearing of the cache memory 520, the first processor 510 can also perform a read operation or a write operation on the cache memory 520. In addition, the first processor 510 may provide information related to the data transfer parameter DP and information related to the failure or clearing of the cache memory 520 to the second processor 530.

Here, the first processor 510 may include, for example, a central processing unit (CPU), and the memory 200 may include, for example, DRAM, but example embodiments are not limited thereto.

The cache memory 520 can be cleared by the first processor 510.

In detail, the cache memory 520 can be cleared by the first processor 510 to a predetermined and/or selected address of the memory 200. In addition, the cache memory 520 can be connected to the memory 200 via a bus 595.

The second processor 530 may transmit data (updated data) different from the data stored in the cache memory 520 to a predetermined and/or selected address of the memory 200.

Here, the second processor 530 may receive (ie, read) the data stored in the third processor 580, and may transmit the received data to the memory 200.

The third processor 580 can receive data to be transmitted to the memory 200 from the external device 350, and can store the received data.

The bus 595 may connect the first processor 510, the second processor 530, the third processor 580, and the cache memory 520, and may connect the semiconductor system 500 and the memory 200 to each other.

In detail, the first processor 510 provides information related to the data transfer parameter DP and information related to the failure or removal of the cache memory 520 to the second processor 530, and the second processor 530 transfers the data transfer parameter DP is provided to the third processor 580, the second processor 530 receives the data stored in the third processor 580, the predetermined and/or selected location of the cache memory 520 to the memory 200 and the second processing The predetermined and/or selected location of the data sent from the device 530 to the memory 200 may be performed via the bus 595.

Referring to FIG. 8, the second processor 530 may include a DMA module 540 and a first buffer 560.

In detail, the DMA module 540 may include a setting unit 542, a establishing unit 545, and a transmitting unit 547.

The setting unit 542 can set the data transfer parameter DP for writing the first data to the memory 200.

In detail, the setting unit 542 can receive information related to the data transfer parameter DP from the first processor 510 via the bus 595, and can set the data transfer parameter DP. Here, the data transmission parameter DP may include, for example, the size of the first data to be transmitted to the memory 200, the address of the first buffer 560 storing the first data to be transmitted to the memory 200, and the storage to be transmitted to The address of the second buffer 590 of the first data of the memory 200 and the predetermined and/or selected address of the memory 200 to which the first data is to be transferred, but example embodiments are not limited thereto. In addition, the first data may include updated data to be transmitted to the memory 200.

The setting unit 542 can receive information related to data transfer parameters (DP.I) and information related to cache memory failure (also called flushing) from the processor 250 (CI.I), and can start to receive The information related to cache memory clearing (CI.I) sets the data transfer parameter DP. That is, the data transfer parameter DP can be set based on the information (DP.I) received from the first processor 510, and can be based on the cache clearing received from the first processor 510 Information to determine the start time of the set operation.

In the illustrated example embodiment, information related to cache memory clearing (CI.I) is provided from the first processor 510 to the second processor 530 (eg, the setting unit 542 of the second processor 530) , But the example embodiments are not limited to this. In more detail In other words, information related to cache memory clearing (CI.I) is firstly provided from the first processor 510 to the setting unit 542 and then from the setting unit 542 to the transmission unit 547, but the example embodiments are not limited thereto. That is, information related to cache memory clearing (CI.I) can also be provided directly from the first processor 510 to the transmission unit 547 via the bus 595 without passing through the setting unit 542, and once the cache is cached When the clearing of the body 520 starts, the cache memory 520 can create information about the cache memory clearing (CI.I) in itself and can provide it to the transmission unit 547 via the bus 595. However, for convenience, in the following description, it is assumed by way of example that information related to cache memory clearing (CI.I) is provided from the first processor 510 to the setting unit 542.

The first processor 510 may arrange the second data stored in the cache memory 520 to a predetermined and/or selected address of the memory 200 while executing the setting unit 542 to set the data transfer parameter DP. Here, the second data may be existing data (ie, unupdated data), which is different from the first data that is updated data.

The setting unit 542 may provide the set data transmission parameter DP to the establishment unit 545 and the transmission unit 547. In addition, the setting unit 542 may provide information (CI.I) related to cache memory clearing to the transmission unit 547.

The establishing unit 545 may create the first data to be transmitted to the memory 200 based on the set data transmission parameter DP.

In detail, the establishment unit 545 may receive the data transfer parameter DP from the setting unit 542 or may receive the first data stored in the second buffer 590 of the third processor 580 based on the data transfer parameter DP. In addition, the establishment unit 545 can be executed to clear the cache memory 520 while receiving the first data.

Here, the establishment unit 545 may receive data from the second buffer 590 of the third processor 580 via the bus 595, or may directly create data in itself.

In addition, the establishing unit 545 may store the first data in the address of the first buffer 560 indicated by the data transfer parameter DP.

The transmission unit 547 may write the first data to a predetermined and/or selected address of the memory 200 based on the data transmission parameter DP.

In detail, the transmission unit 547 may receive the data transmission parameter DP from the setting unit 542 or may transmit the first data to the predetermined and/or selected location of the memory 200 based on the data transmission parameter DP. Here, the transmission unit 547 may transmit the first data stored in the first buffer 560 to the memory 200.

That is, the transmission unit 547 can read the first data stored in the address of the first buffer 560 indicated by the data transmission parameter DP, and can transmit (write) the first data to the data indicated by the data transmission parameter DP The predetermined and/or selected location of the memory 200 of

After the clearing of the cache memory 520 is completed, the transmission unit 547 may be executed to transmit the first data to the predetermined and/or selected location of the memory 200.

In addition, the transmission unit 547 may receive the cache-related information (CI.I) from the setting unit 542 when the cache 520 is cleared from the setting unit 542 (for example, signaling the cache (The information of the start of clearing of the memory 520). Here, the transfer unit 547 may be deactivated before the clearing of the cache memory 520 starts, at the same time as the clearing of the cache memory 520 starts, or in all cases after the clearing of the cache memory 520 starts.

After the clearing of the cache memory 520 is completed, the transmitting unit 547 may receive the cache-related information (CI.I) from the setting unit 542 and then activate the clearing memory 520 (for example, signaling the cache (The information of the completion of the clearing of the memory 520).

The transmission unit 547 may perform a read operation or a write operation on the memory 200. As described above, the transmission unit 547 can transmit (write) the first data to the predetermined and/or selected address of the memory 200. In addition to the writing operation, the transmission unit 547 can also perform the data reading operation from the memory 200.

The third processor 580 may include a second buffer 590.

In detail, the third processor 580 can create the first data and can store the created first data in the second buffer 590. That is, the third processor 580 may receive the data transfer parameter DP from the setting unit 542 and may receive the first data from the external device 350 based on the received data transfer parameter DP or may create the first data in itself.

That is, in the semiconductor system 500 shown in FIG. 8, unlike the semiconductor system 400 shown in FIG. 6, the processor (ie, the third processor 580) that receives data from the external device 350 is provided separately from the semiconductor system 500 shown in FIG. 6. The data received from the external device 350 is transmitted to the processor (ie, the second processor 530) of the memory 200.

In addition, the semiconductor systems 400 and 500 shown in FIGS. 6 and 8 can be integrated into the system together with the memory 200. In an example embodiment, the semiconductor system 400 or 500 and the memory 200 can be integrated into the system to form a memory card. The semiconductor system 400 or 500 and the memory 200 may be integrated into the system, and examples thereof may include PC cards, such as personal computer memory card international association (PCMCIA) cards, compact flash memory (compact) flash; CF) card, smart media card (for example, SM or SMC), memory stick, multimedia card (for example, MMC, RS-MMC, or MMCmicro), SD card (for example, SD, miniSD, and SDHC) or general flash Memory storage (universal flash storage; UFS).

The semiconductor system 400 or 500 and the memory 200 can be integrated into the system to form a solid state drive or solid state disk (solid state drive or solid state disk; SSD).

9 is a diagram illustrating the semiconductor system depicted in FIG. 7 implemented as a system wafer.

Referring to FIG. 9, a semiconductor system 500 according to another example embodiment may include a first processor 510, a cache memory 520, a second processor 530, and a third processor 580, which may be implemented as a system on chip ; SoC) and can be connected to each other via an internal bus incorporated into the SoC (for example, a bus that complies with the AMBA Advanced Extensible Interface (AXI) protocol). In addition, in at least some example embodiments, the SoC may be implemented as an application processor (AP) installed on the mobile terminal. In at least some example embodiments, the SoC may further include the memory 200 and the external memory 550.

The semiconductor system 400 shown in FIG. 5 and the semiconductor system 500 shown in FIG. 7 can also be implemented as a system on chip (SoC), and a detailed description thereof will not be given.

In addition, the semiconductor systems 400 and 500 according to at least some example embodiments may be installed by various types of packages. For example, the semiconductor systems 400 and 500 can be mounted by various types of packages such as (but not limited to): package on package (PoP), ball grid array (BGA), wafer level Package (chip scale package; CSP), plastic leaded chip carrier (PLCC), plastic dual in-line package (PDIP), crystals and crystals in Wolver components Round mid-grain form, chip on board (COB), ceramic dual in-line package (CERDIP), plastic metric quad flat pack (MQFP), thin square flat Thin quad flat pack (TQFP), small outline (SOIC), shrinkable small outline seal Shrink small outline package (SSOP), thin small outline (TSOP), system in package (SIP), multi-chip package (MCP), wafer-level manufacturing package (wafer) -level fabricated package; WFP), wafer-level processed stack package (WSP), and mounting type.

10 to 12 illustrate an electronic system according to at least some example embodiments to which a semiconductor system can be applied.

Specifically, FIG. 10 illustrates a tablet PC 1200, FIG. 11 illustrates a notebook computer 1300, and FIG. 12 illustrates a smartphone 1400. At least one of the semiconductor systems 400 and 500 can be used by the tablet PC 1200, the notebook computer 1300, and the smartphone 1400.

In addition, it is obvious to those skilled in the art that at least one of the semiconductor systems 400 and 500 may be other integrated circuits not described herein. That is, in the above example embodiment, as at least one of the electronic systems, only the tablet PC 1200, the notebook computer 1300, and the smart phone 1400 are exemplified, but the example embodiment is not limited thereto. In at least some example embodiments, the electronic system may be implemented as a computer, ultra mobile personal computer (UMPC), workstation, netbook, personal digital assistants (PDA), portable computer, network tablet Computer (web tablet), wireless phone, mobile phone, smart phone, e-book, portable multimedia player (PMP), portable game console, navigation device, black box, digital camera, 3D TV, Digital audio recorder, digital audio player, digital video recorder, digital video player, etc.

Hereinafter, the semiconductor illustrated in FIG. 1 will be described with reference to FIGS. 13 and 14 Method of operation of the device. In the following description, the same contents as the example embodiment illustrated in FIG. 1 will not be repeatedly described.

13 and 14 are diagrams illustrating the operation method of the semiconductor device illustrated in FIG. 1.

Referring to FIGS. 2, 13 and 14, first, information related to data transfer parameters (DP.I) and information related to cache memory clearing (CI.I) are provided (S100).

In detail, the setting unit 115 can receive information related to data transfer parameters (DP.I) and information related to cache memory clearing (CI.I) from the processor 250.

The clear start signal is provided to the cache memory 300 (S105).

In detail, the processor 250 may provide a failure (ie, clear) start signal to the cache memory 300.

The data transfer operation of the DMA module 110 is disabled (S107).

In detail, the setting unit 115 can provide information (CI.I) related to cache memory clearing to the transmission unit 125. In addition, the transmission unit 125 may receive information (CI.I) related to the cache memory clearing that will be disabled (for example, information to signal the start of clearing of the cache memory 300).

The clearing of the cache memory 300 starts (S110).

In detail, the second data (existing data, that is, unupdated data) stored in the cache memory 300 can be cleared to a predetermined and/or selected location of the memory 200.

In the illustrated example embodiment, S100, S105, S107, and S110 are sequentially performed, but the example embodiment is not limited thereto. That is, after the processor 250 provides the clear start signal to the cache memory 300 (S105), the data transfer parameters can be The related information (DP.I) and information related to cache memory clearing (CI.I) are provided to the setting unit 115 (S100).

Therefore, in all cases before the clearing of the cache memory 300 starts, at the same time as the clearing of the cache memory 300 starts, or after the clearing of the cache memory 300 starts, the transmission unit 125 ( S107).

After the clearing of the cache memory 300 starts, the setting unit 115 may set the data transfer parameter DP based on the information (DP.I) related to the data transfer parameter received from the processor 250. In addition, the setting unit 115 can set the data transfer parameter DP and can provide it to the establishing unit 120 (S113).

Next, the data is created (S115).

In detail, the establishing unit 120 may create the first data (ie, the updated data of the predetermined and/or selected location to be transmitted to the memory 200) based on the received data transmission parameter DP. The establishment unit 120 can directly create the first data in itself or can receive the first data from the external device 350.

The data is stored in the buffer 160 (S117).

In detail, the establishing unit 120 may store the first data in the address of the buffer 160 indicated by the data transfer parameter DP.

If the clearing of the cache memory 300 is completed (S120), the processor 250 may send information (CI.I) related to the clearing of the cache memory (for example, signaling the completion of the clearing of the cache memory 300)的信息) providing to the setting unit 115. However, if the clearing of the cache memory 300 is not completed, the disabled state of the transfer unit 125 (ie, the data transfer disabled state of the DMA module 110 may be maintained) may be maintained (S122).

The data transfer operation of the DMA module 110 is enabled (S125).

In detail, if the processor 250 receives a signal to notify the cache If the information of 300 is cleared, the setting unit 115 may provide the received information to the transmission unit 125.

The transmission unit 125 may receive information that the activation of the cache memory 300 is then signaled to be completed.

The data stored in the buffer 160 is read (S127).

In detail, the transmission unit 125 may read the first data stored in the buffer 160 based on the data transmission parameter DP.

Send the data to the memory 200 (S130).

In detail, the transmission unit 125 may transmit the first data to the predetermined and/or selected location of the memory 200 based on the data transmission parameter DP.

Hereinafter, the operation method of the semiconductor system illustrated in FIG. 5 will be described with reference to FIGS. 15 and 16. In the following description, the same content as the example embodiment illustrated in FIG. 5 will not be described repeatedly.

15 and 16 are diagrams illustrating the operation method of the semiconductor system illustrated in FIG. 5.

Referring to FIG. 6, FIG. 15 and FIG. 16, first, information related to data transfer parameters (DP.I) and information related to cache memory clearing (CI.I) are provided (S200).

In detail, the setting unit 442 of the DMA module 440 of the second processor 430 can receive information related to data transfer parameters (DP.I) and information related to cache memory clearing from the first processor 410 ( CI.I).

The clear start signal is provided to the cache memory 420 (S205).

In detail, the first processor 410 may provide a failure (ie, clear) start signal to the cache memory 420.

The data transfer operation of the DMA module 440 is disabled (S207).

In detail, the setting unit 442 can provide information (CI.I) related to cache memory clearing to the transmission unit 447. In addition, the transmission unit 447 may receive information (CI.I) related to the cache memory clearing that will be disabled (for example, information to signal the start of clearing of the cache memory 420).

The clearing of the cache memory 420 starts (S210).

In detail, the second data (existing data, that is, unupdated data) stored in the cache memory 420 can be cleared to a predetermined and/or selected location of the memory 200.

In the illustrated example embodiment, S200, S205, S207, and S210 are sequentially executed, but the example embodiment is not limited thereto. That is, after the first processor 410 provides the clear start signal to the cache memory 420 (S205), the information related to the data transfer parameters (DP.I) and the information related to the cache memory clear can be provided Information (CI.I) is provided to the setting unit 442 (S200).

Therefore, the transmission can be disabled before the start of the clearing of the cache memory 420 (S210), at the same time or after the start of the clearing of the cache memory 420 (S210) Unit 447 (S207).

After the clearing of the cache memory 420 starts, the setting unit 442 may set the data transfer parameter DP based on the information (DP.I) related to the data transfer parameter received from the first processor 410. In addition, the setting unit 442 can set the data transfer parameter DP and can provide it to the establishing unit 445 (S213).

Next, the data is created (S215).

In detail, the establishing unit 445 may establish the first data (ie, the scheduled and/or selected location address to be transmitted to the memory 200 based on the received data transmission parameter DP Updates). The establishing unit 445 may directly create the first data in itself or may receive the first data from the external device 350.

The data is stored in the buffer 450 (S217).

In detail, the establishing unit 445 may store the first data in the address of the buffer 450 indicated by the data transfer parameter DP.

If the clearing of the cache memory 420 is completed (S220), the first processor 410 may send information (CI.I) related to the clearing of the cache memory (for example, signaling the clearing of the cache memory 420 The completed information is provided to the setting unit 442. However, if the clearing of the cache memory 420 is not completed, the disabled state of the transfer unit 447 (ie, the disabled data transfer state of the DMA module 440) may be maintained (S222).

The data transfer operation of the DMA module 440 is enabled (S225).

In detail, if the first processor 410 receives information signaling completion of the clearing of the cache memory 420, the setting unit 442 may provide the received information to the transmission unit 447.

The transmission unit 447 may receive information that the activation of the cache memory 420 is then signaled to be completed.

The data stored in the buffer 450 is read (S227).

In detail, the transmission unit 447 can read the first data stored in the buffer 450 based on the data transmission parameter DP.

Send the data to the memory 200 (S230).

In detail, the transmission unit 447 may transmit the first data to the predetermined and/or selected location of the memory 200 based on the data transmission parameter DP.

Hereinafter, the operation method of the semiconductor system illustrated in FIG. 7 will be described with reference to FIGS. 17 and 18. In the following description, implementation with previous examples will not be described repeatedly Examples of the same content.

17 and 18 are diagrams illustrating the operation method of the semiconductor system shown in FIG. 7.

Referring to FIG. 7, FIG. 17 and FIG. 18, first, information related to data transfer parameters (DP.I) and information related to cache memory clearing (CI.I) are provided (S300).

In detail, the setting unit 542 of the DMA module 540 of the second processor 530 can receive information related to data transfer parameters (DP.I) and information related to cache memory clearing from the first processor 510 ( CI.I).

The clear start signal is provided to the cache memory 520 (S305).

In detail, the first processor 510 may provide a failure (ie, clear) start signal to the cache memory 520.

The data transfer operation of the DMA module 540 is disabled (S307).

In detail, the setting unit 542 may provide information (CI.I) related to cache memory clearing to the transmission unit 547. In addition, the transmission unit 547 may receive information (CI.I) related to the cache memory clearing which will be deactivated (for example, information to signal the start of the clearing of the cache memory 520).

The clearing of the cache memory 520 starts (S310).

In detail, the second data (existing data, that is, unupdated data) stored in the cache memory 520 can be cleared to a predetermined and/or selected location of the memory 200.

In the illustrated example embodiment, S300, S305, S307, and S310 are sequentially performed, but the example embodiment is not limited thereto. That is, after the first processor 510 provides the clear start signal to the cache memory 520 (S305), it Information related to data (DP.I) and information related to cache memory clearing (CI.I) are provided to the setting unit 542 (S300).

Therefore, the transmission can be disabled before the start of the clearing of the cache memory 520 (S310), at the same time or after the start of the clearing of the cache memory 520 (S310) Unit 547 (S307).

After the clearing of the cache memory 520 starts, the setting unit 542 may set the data transfer parameter DP based on the information (DP.I) related to the data transfer parameter received from the first processor 510. Although not shown, the third processor 580 may receive the data transmission parameters from the setting unit 542, and may receive the first data from the external device 350 based on the received data transmission parameters, or may directly create the first data (S313).

The setting unit 542 can set the data transfer parameter DP, and can provide it to the establishing unit 545 (S314).

In FIG. 18, the third processor 580 can be executed before the establishment unit 545 receives the data transmission parameter DP from the setting unit 542 (S314) and the first data is established from the setting unit 542 (S313), but the example embodiment Not limited to this.

That is, before the third processor 580 receives the data transmission parameter DP from the setting unit 542, the third processor 580 receives the data transmission parameter DP from the setting unit 542 at the same time or receives the data from the third processor 580 from the setting unit 542 After transmitting the parameter DP, the execution establishing unit 545 receives the data transmission parameter DP from the setting unit 542.

The data is read from the second buffer 590 (S315).

In detail, the establishing unit 545 may read the first data (ie, the updated data of the predetermined and/or selected location to be transmitted to the memory 200) from the second buffer 590 based on the received data transmission parameter DP. The establishing unit 545 may directly establish the first material in itself. However, for convenience, in the following description, it is assumed that The stand-up unit 545 receives the first data stored in the second buffer 590.

The data is stored in the first buffer 560 (S317).

In detail, the establishing unit 545 may store the first data in the address of the first buffer 560 indicated by the data transfer parameter DP.

If the clearing of the cache memory 520 is completed (S320), the first processor 510 may send information (CI.I) related to the clearing of the cache memory (for example, signaling the clearing of the cache memory 520 The completed information is provided to the setting unit 542. However, if the clearing of the cache memory 520 is not completed, the disabled state of the transfer unit 547 (ie, the disabled state of the data transfer of the DMA module 540) may be maintained (S322).

The data transfer operation of the DMA module 540 is enabled (S325).

In detail, if the first processor 510 receives information signaling completion of the clearing of the cache memory 520, the setting unit 542 may provide the received information to the transmission unit 547.

The transmission unit 547 may receive information that the activation of the cache memory 520 is then signaled to be completed.

The data stored in the first buffer 560 is read (S327).

In detail, the transmission unit 547 may read the first data stored in the first buffer 560 based on the data transmission parameter DP.

Send the data to the memory 200 (S330).

In detail, the transmission unit 547 may transmit the first data to the predetermined and/or selected location of the memory 200 based on the data transmission parameter DP.

Although at least some example embodiments have been specifically illustrated and described, those of ordinary skill in the art will understand that forms can be made therein without departing from the spirit and scope of the example embodiments as defined by the scope of the following patent applications With details Various changes. Therefore, it is required that the example embodiments are regarded as illustrative and non-limiting in all aspects, and reference is made to the scope of the attached patent application rather than the foregoing description to indicate the scope of the example embodiments.

100‧‧‧Semiconductor device

110‧‧‧DMA module

160‧‧‧Buffer

200‧‧‧Memory

Claims (20)

A semiconductor device includes: a direct memory access (DMA) system configured to directly access a memory to write first data to an address of the memory, the direct memory access system includes , An initializer configured to set data transfer parameters during a data removal cycle of the second data from the cache to the address by the processor, the data transfer parameters used to apply the first Data is written to the memory; a builder configured to create the first data based on the set data transfer parameters; and a transmitter configured to store data in the data based on the data transfer parameters After the removal cycle, the first data is written to the address of the memory. The semiconductor device according to item 1 of the patent application scope, wherein the first data is different from the second data. The semiconductor device according to item 1 of the patent application scope, wherein the builder is configured to perform one of the following operations: receiving the first data from an external device and directly creating the first data. The semiconductor device according to item 3 of the patent application range, wherein the builder is configured to perform at least one of a read operation and a write operation on the external device. The semiconductor device as described in item 1 of the patent application further includes a buffer configured to store the first data. The semiconductor device as described in item 5 of the patent application scope, wherein the The stand is configured to store the first data in the buffer. The semiconductor device according to item 6 of the patent application range, wherein the transmitter is configured to transfer the first data stored in the buffer to the memory. The semiconductor device according to item 5 of the patent application scope, wherein the data transfer parameter includes the size of the first data, the address of the buffer storing the first data, and the memory of the memory Address. The semiconductor device according to item 1 of the patent application scope, wherein the initializer is configured to receive information related to the data transfer parameter and information related to the clearing of the cache memory from the processor News. The semiconductor device according to item 9 of the patent application scope, wherein the transmitter is configured to receive the information related to the clearing of the cache memory from the initializer, and the transmission The device is disabled during the data removal cycle. The semiconductor device of claim 10, wherein the transmitter is configured to operate after the data removal cycle. The semiconductor device according to item 1 of the patent application scope, wherein the transmitter is configured to receive information related to the clearing of the cache memory from the processor. The semiconductor device according to item 1 of the patent application scope, wherein the transmitter is configured to receive information related to the clearing of the cache memory from the cache memory. The semiconductor device according to item 1 of the patent scope, wherein the creator is configured to create the first data after the initializer sets the data transfer parameters. The semiconductor device according to item 14 of the patent scope, wherein the creator is configured to create the first data during the data removal period. The semiconductor device according to item 15 of the patent application scope, wherein the transmitter is configured to transmit the first data to the bit of the memory after the creator creates the first data site. The semiconductor device according to item 1 of the patent application range, wherein the builder is configured to perform at least one of a read operation and a write operation on the memory. The semiconductor device as described in item 1 of the patent application further includes: a buffer configured to store the first data, wherein the first data includes third data and fourth data. The semiconductor device of claim 18, wherein the address of the memory includes a first address and a second address, and the transmitter is configured to perform transmission of the third data A first transmission to the first address and a second transmission to transmit the fourth data to the second address after the first transmission, and the transmitter establishes the location at the creator The first transmission is performed when the fourth material is described. The semiconductor device of claim 18, wherein the creator is configured to create the third data during the data removal period and the fourth after the data removal period data.

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