KR20160026599A - Semiconductor device, semiconductor system and system on chip - Google Patents

Abstract

The present invention provides a semiconductor device, a semiconductor system and a system on a chip. The semiconductor device comprises a DMA module to directly access a memory to write first data on a predetermined address of the memory. The DMA module comprises: a setting unit to set a transmission parameter for writing the first data on the memory; a generation unit to generate the first data to be transmitted to the memory based on the set transmission parameter; and a transmission unit to write the first data on the predetermined address of the memory based on the transmission parameter. The setting unit sets the transmission parameter during a course where a processor flushes second data stored in a cache to the predetermined address of the memory. The transmission unit transmits the first data to the predetermined address of the memory after flushing is completed.

Description

TECHNICAL FIELD [0001] The present invention relates to a semiconductor device, a semiconductor system, and a system-on-chip (SEMICONDUCTOR DEVICE, SEMICONDUCTOR SYSTEM AND SYSTEM ON CHIP)

The present invention relates to a semiconductor device, a semiconductor system, and a system-on-a-chip.

DMA (Direct Memory Access) means that an input / output device controller can move data without executing a program by a CPU (Central Processing Unit). With this method, the input / output speed can be improved and the speed difference between the CPU and the peripheral device can be reduced. When an input / output device requests a DMA, the CPU passes control of the main memory, and the CPU can allow this operation every time the CPU cycle ends.

However, when the latest data is to be transferred to a specific address in the system memory using a peripheral processing unit having a built-in DMA, the old data stored in the cache received from the specific address of the memory is invalid, (E. G., Flushing) the DMA and then starts DMA.

A problem to be solved by the present invention is to provide a semiconductor device with improved performance by performing a DMA function simultaneously with a cache invalidation (i.e., flushing) process.

Another problem to be solved by the present invention is to provide a semiconductor system with improved performance by performing a DMA function simultaneously with a cache invalidation (i.e., flushing) process.

Another problem to be solved by the present invention is to provide a system on chip which improves the performance by performing the DMA function simultaneously with the invalidation (i.e., flushing) of the cache.

The problems to be solved by the present invention are not limited to the above-mentioned problems, and other matters not mentioned can be clearly understood by those skilled in the art from the following description.

According to an aspect of the present invention, there is provided a semiconductor device including a DME module for directly accessing a memory and writing first data to a predetermined address of the memory, A setting unit for setting a transfer parameter for writing the first data into the memory; a generation unit for generating first data to be transferred to the memory based on the set transfer parameter; Wherein the setting unit sets the transmission parameter during a period in which the processor flushes the second data stored in the cache to a predetermined address in the memory, The transmission of the generated first data to a predetermined address of the memory is performed after the flushing is completed.

The first data may be data different from the second data.

The generation unit may generate the first data by allowing the generation unit to receive or directly generate the first data from the external device.

The generating unit may perform a read operation or a write operation to an external device.

And a buffer in which the first data is stored.

The generating unit may generate and store the first data in a buffer.

The transmitting unit may transmit the first data stored in the buffer to the memory.

The transmission parameter may include a size of the first data or an address of a buffer where the first data is stored or a predetermined address of the memory.

The setting unit can be provided with information relating to transmission parameters from the processor and information relating to flushing of the cache.

The transfer unit may be deactivated during a period in which the cache is flushed by receiving information related to flushing of the cache from the setting unit.

The transmission unit can be activated after the flushing of the cache is completed.

The sending unit may be provided with information relating to flushing of the cache from the processor.

The sending unit may be provided with information related to flushing of the cache from the cache.

The processor may include a central processing unit (CPU).

The memory may comprise a DRAM.

The generation unit may generate the first data after the setting unit has completed setting the transmission parameter.

The generation unit may generate the first data during the interval during which the cache is flushed.

The transmitting unit may transmit the generated first data to a predetermined address of the memory after the generating unit is finished generating the first data.

The transmission unit may perform a read operation or a write operation to the memory.

And a buffer for storing the first data, wherein the first data includes third and fourth data, and the generating unit generates a third data by generating and storing the third data in a buffer, And stores it in a buffer, and the generating unit can perform the second generating operation after completing the first generating operation.

The predetermined address includes a first address and a second address, and the transmission unit performs a first transmission operation for transmitting the third data to the first address and a second transmission operation for transmitting the fourth data to the second address The transmission unit performs the second transmission operation after completing the first transmission operation, and the first transmission operation can be performed during the interval in which the second generation operation is performed.

The first generating operation may be performed during a period in which the cache is flushed, and the second generating operation may be performed after the flushing of the cache is completed.

According to another aspect of the present invention, there is provided a semiconductor device comprising: a DME module for directly accessing a memory; And a buffer for storing first and second data to be transferred to the memory, wherein the DMA module comprises: a setting unit for setting transfer parameters for transferring the first and second data to and from the memory; A generation unit that sequentially performs a first generation operation of generating 1 data and storing the data in a buffer and a second generation operation of generating a second data and storing the second data in a buffer, And a second transmission operation for sequentially transmitting the first data to the first address of the memory and the second data stored in the buffer to the second address of the memory, wherein the setting unit sets transmission parameters Is performed during a period in which the processor flushes the third data stored in the cache to the first address, and the first generating operation is performed during a period in which the cache is flushed The second generating operation is performed after the flushing of the cache is completed, and the first transmitting operation is performed during the period in which the second generating operation is performed after the flushing of the cache is completed.

The generating unit may perform the first generating operation after the setting unit has completed setting the transmission parameter.

The second transmission operation may be performed after the second generation operation is completed.

According to another aspect of the present invention, there is provided a semiconductor system comprising: a cache connected to a memory via a bus; A first processor for flushing the first data stored in the cache to a predetermined address in the memory; And a second processor for generating second data different from the first data and transmitting the second data to a predetermined address of the memory, wherein the second processor comprises: a buffer for storing the generated second data; And a DMA module for setting a transmission parameter for transmitting the second data stored in the buffer to a predetermined address based on the transmission parameter, wherein the DMA module sets the transmission parameter in such a manner that the first processor is stored in the cache Flushing the first data to a predetermined address, and the DMA module transmits the second data to the predetermined address after the flushing is completed.

The first processor may perform a read operation or a write operation to the cache.

The DME module includes a setting unit for setting a transfer parameter for transferring second data to a memory, a generation unit for generating second data to be transferred to the memory based on the transfer parameter, And a transmission unit for transmitting the second data to the determined address.

The setting unit can be provided with information relating to transmission parameters from the first processor and information relating to flushing of the cache.

The first and second processors may be connected to each other via a bus.

According to another aspect of the present invention, there is provided a semiconductor system comprising: a cache connected to a memory via a bus; A first processor for flushing the first data stored in the cache to a predetermined address in the memory; And a second processor for generating second data different from the first data and transmitting the generated second data to a predetermined address of the memory via the bus, wherein the second processor comprises: a buffer for storing the second data; Wherein the DMA module sets transfer parameters for transferring the second data to the memory and transfers information relating to the transfer parameter from the first processor and information relating to the flushing of the cache A generation unit for generating second data to be transmitted to the memory based on the transmission parameter and storing the second data in a buffer based on the transmission parameter and a transmission unit for transmitting the second data stored in the buffer to a predetermined address in the memory based on the transmission parameter, Unit, and the setting unit sets the transmission parameter is the number of times during which the cache is flushing. And, sending unit to send the second data to a predetermined address in memory, is carried out after flushing is complete.

According to another aspect of the present invention, there is provided a semiconductor system comprising: a cache connected to a memory via a bus; A first processor for flushing the first data stored in the cache to a predetermined address in the memory; A second processor including a first buffer for storing second data different from the first data; And a third processor including a DME module for directly accessing the memory, wherein the second processor generates and stores the second data in a first buffer, the DME module comprising: A generating unit receiving second data stored in the first buffer based on the transmission parameter, and a transmitting unit transmitting the second data to a predetermined address of the memory based on the transmission parameter However, the setting unit sets transmission parameters during the period in which the cache is flushed, and the transmitting unit transmits the second data to the predetermined address in the memory after the flushing is completed.

The setting unit can be provided with information relating to transmission parameters and flushing of the cache from the first processor.

The third processor may further include a second buffer for storing the second data received.

The generating unit may store the data provided from the first buffer in the second buffer.

The transmission unit may transmit the data stored in the second buffer to a predetermined address in the memory.

The receiving of the second data by the generating unit can be started after the setting unit has completed setting the transmission parameters.

The second processor may generate the second data and store the second data in the first buffer during the interval during which the cache is flushed.

The receiving of the second data by the generating unit may be performed during a period in which the cache is flushed.

The transmitting unit may transmit the second data to a predetermined address after the generating unit is finished receiving the second data.

The first to third processors may be connected to each other via a bus.

The third processor may receive the transmission parameter from the setting unit and generate the second data based on the transmission parameter.

According to another aspect of the present invention, there is provided a system-on-chip comprising: a memory; A cache associated with memory; A first processor for flushing the first data stored in the cache to a predetermined address in the memory; A second processor including a first buffer for storing second data different from the first data; And a third processor including a DME module for directly accessing the memory, wherein the memory and the first to third processors are connected to each other via a bus conforming to the AMBI Advanced Extensible Interface (AXI) protocol, 2 data and stores the data in the first buffer. The DME module includes a setting unit for setting a transmission parameter for transmitting the second data to the memory, and a setting unit for providing second data stored in the first buffer based on the transmission parameter And a transmission unit for transmitting the second data to a predetermined address of the memory based on the transmission parameter, wherein the setting unit sets transmission parameters for a period during which the cache is flushed, The transmission of the second data to the predetermined address of the second memory is performed after the flushing is completed.

Other specific details of the invention are included in the detailed description and drawings.

1 is a block diagram illustrating a semiconductor device according to an embodiment of the present invention.
2 is a block diagram for explaining the DME module of FIG.
3 and 4 are schematic views for explaining the operation of the semiconductor device of FIG.
5 is a block diagram illustrating a semiconductor system according to one embodiment of the present invention.
FIG. 6 is a block diagram illustrating the second processor of FIG. 5. FIG.
7 is a block diagram illustrating a semiconductor system according to another embodiment of the present invention.
8 is a block diagram illustrating the second and third processors of FIG.
Figure 9 is a diagram illustrating the semiconductor system of Figure 7 implemented as a system on chip.
10 through 12 are exemplary electronic systems to which a semiconductor system according to some embodiments of the present invention may be applied.
13 and 14 are views for explaining a method of operating the semiconductor device of FIG.
FIGS. 15 and 16 are views for explaining a method of operating the semiconductor system of FIG.
17 and 18 are views for explaining a method of operating the semiconductor system of FIG.

BRIEF DESCRIPTION OF THE DRAWINGS The advantages and features of the present invention and the manner of achieving them will become apparent with reference to the embodiments described in detail below with reference to the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Is provided to fully convey the scope of the invention to those skilled in the art, and the invention is only defined by the scope of the claims. The dimensions and relative sizes of the components shown in the figures may be exaggerated for clarity of description. Like reference numerals refer to like elements throughout the specification and "and / or" include each and every combination of one or more of the mentioned items.

It is to be understood that when an element or layer is referred to as being "on" or " on "of another element or layer, All included. On the other hand, a device being referred to as "directly on" or "directly above " indicates that no other device or layer is interposed in between.

The terms spatially relative, "below", "beneath", "lower", "above", "upper" May be used to readily describe a device or a relationship of components to other devices or components. Spatially relative terms should be understood to include, in addition to the orientation shown in the drawings, terms that include different orientations of the device during use or operation. For example, when inverting an element shown in the figures, an element described as "below" or "beneath" of another element may be placed "above" another element. Thus, the exemplary term "below" can include both downward and upward directions. The elements can also be oriented in different directions, so that spatially relative terms can be interpreted according to orientation.

The terminology used herein is for the purpose of illustrating embodiments and is not intended to be limiting of the present invention. In the present specification, the singular form includes plural forms unless otherwise specified in the specification. The terms " comprises "and / or" comprising "used in the specification do not exclude the presence or addition of one or more other elements in addition to the stated element.

Although the first, second, etc. are used to describe various elements or components, it is needless to say that these elements or components are not limited by these terms. These terms are used only to distinguish one element or component from another. Therefore, it is needless to say that the first element or the constituent element mentioned below may be the second element or constituent element within the technical spirit of the present invention.

Unless defined otherwise, all terms (including technical and scientific terms) used herein may be used in a sense commonly understood by one of ordinary skill in the art to which this invention belongs. Also, commonly used predefined terms are not ideally or excessively interpreted unless explicitly defined otherwise.

Hereinafter, a semiconductor device according to an embodiment of the present invention will be described with reference to FIGS. 1 to 4. FIG.

1 is a block diagram illustrating a semiconductor device according to an embodiment of the present invention. 2 is a block diagram for explaining the DME module of FIG. 3 and 4 are schematic views for explaining the operation of the semiconductor device of FIG.

The term "sub-unit" or "module" as used herein refers to a hardware component such as software or an FPGA or ASIC, and a sub-unit or module performs certain roles. However, " part " or " module " is not meant to be limited to software or hardware. The term " part " or " module " may be configured to reside on an addressable storage medium and configured to play one or more processors. Thus, by way of example, 'a' or 'module' is intended to be broadly interpreted as encompassing any type of process, including features such as software components, object-oriented software components, class components and task components, Microcode, circuitry, data, databases, data structures, tables, arrays, and variables, as used herein, Or " modules " or " modules " or " modules " or " modules " Can be further separated.

Referring to FIG. 1, a semiconductor device 100 according to an embodiment of the present invention may include a DIA module 110 and a buffer 160.

The DME module 110 can access the memory 200 directly.

Specifically, the DME module 110 may generate data directly or may receive data from an external device, store the data in the buffer 160, and transmit the data stored in the buffer 160 to the memory 200. [

The DME module 110 may also perform a read or write operation to the memory 200. [

The buffer 160 may store data provided by the DMA module 110. In this case, the DMA module 110 may not be able to occupy a bus (not shown) when data is transferred. In this case, the DMA module 110 may buffer a buffer (not shown) 160) is secured.

More specifically, the buffer 160 preferably has a free space larger than the maximum amount of data that the DME module 110 can transfer to the memory 200 at one time.

In addition, the memory 200 may include, but is not limited to, a DRAM, for example. Also, the memory 200 may include a data area and a spare area for storing general data. Each of the areas of the memory 200 may be composed of a plurality of memory blocks. The detailed configuration of the memory 200 is well known to those skilled in the art, and thus a detailed description thereof will be omitted.

Referring to FIG. 2, the DMI module 110 may include a setting unit 115, a generating unit 120, and a transmitting unit 125.

The setting unit 115 can set the transfer parameter DP for writing the first data in the memory 200. [

Specifically, the setting unit 115 can receive the information (DP.I) related to the transmission parameter DP from the processor 250 and set the transmission parameter DP. Here, the transmission parameter DP includes, for example, the size of the first data to be transmitted to the memory 200, the address of the buffer 160 in which the first data to be transmitted to the memory 200 is stored, May include a predetermined address of the memory 200 to be transmitted, but the present invention is not limited thereto. The first data is data to be transferred to the memory 200.

Here, the processor 250 may include, but is not limited to, a Central Processing Unit (CPU), for example. Also, the first data may include the latest data to be stored in a predetermined address of the memory 200.

The setting unit 115 can receive information (CI.I) related to invalidation of the cache (hereinafter referred to as flushing) as well as information (DP.I) related to the transmission parameter from the processor 250, The setting operation of the transmission parameter DP can be started based on the information (CI.I) related to the flushing of the cache. That is, the transmission parameter DP is set based on the information DP.I related to the transmission parameter provided from the processor 250, and the starting point of the setting operation is related to the flushing of the cache provided from the processor 250 Information (CI.I).

Here, information (CI.I) related to the flushing of the cache is shown to be provided from the processor 250 to the setting unit 115, but is not limited thereto. More specifically, information (CI.I) associated with flushing of the cache is shown to be provided to the sending unit 125 in the setting unit 115 after being provided to the setting unit 115 first in the processor 250, But is not limited thereto. That is, the information (CI.I) associated with the flushing of the cache may be provided to the transfer unit 125 directly by the processor 250 without going through the setting unit 115, and when the flushing of the cache 300 begins, (CI. I) related to the flushing of the cache itself, and may provide it to the transfer unit 125. [0050] However, for convenience of explanation, it is assumed that the information (CI.I) related to the flushing of the cache from the processor 250 to the setting unit 115 is provided.

The setting unit 115 may set the transmission parameter DP while the processor 250 flushes the second data stored in the cache 300 to a predetermined address in the memory 200. [ Here, the second data may be old data (i.e., un-updated data), and may be data different from the first data which is the latest data. The processor 250 may also perform a read or write operation to the cache 300 in addition to flushing the cache 300.

The setting unit 115 can provide the set transmission parameters DP to the generating unit 120 and the transmitting unit 125. [ Further, the setting unit 115 can provide information (CI.I) related to the flushing of the cache to the transfer unit 125, and a detailed description thereof will be described later.

The generating unit 120 may generate first data to be transmitted to the memory 200 based on the set transmission parameters DP.

Specifically, the generating unit 120 can receive the transmission parameter DP from the setting unit 115 and can generate the first data based on the transmission parameter DP. Here, generation unit 120 generates data may include generation unit 120 receiving (or leading) data from external device 350 directly. The generating unit 120 may also store (write) the generated first data in the buffer 160. [

Here, the external device 350 may include, but is not limited to, for example, a Multi-Media Card (MMC).

That is, the generating unit 120 may generate the first data according to the size of the data indicated by the transmission parameter DP, and store the generated first data at the address of the buffer 160 indicating the transmission parameter DP .

The generation unit 120 can perform a read or write operation to the external device 350. [ As described above, the generating unit 120 may receive the first data from the external device 350 to generate the first data, and the generating unit 120 may perform the read operation in addition to the external device 350 ) Can also be performed.

The transmission unit 125 can write the first data to a predetermined address of the memory 200 based on the transmission parameter DP.

Specifically, the transmission unit 125 can receive the transmission parameter DP from the setting unit 115 and can transmit the first data to the predetermined address of the memory 200 based on the transmission parameter DP . Here, the transfer unit 125 can transfer the first data stored in the buffer 160 to the memory 200. [

That is, the transfer unit 125 reads the first data stored in the address of the buffer 160 indicated by the transfer parameter DP and transfers the first data to a predetermined address of the memory 200 indicated by the transfer parameter DP (Write).

The transmission unit 125 may transmit the first data to the predetermined address of the memory 200 after the flushing of the cache 300 is completed.

The transfer unit 125 also receives information (CI.I) related to the flushing of the cache 300 from the setting unit 115 (e.g., information indicating that the flushing of the cache 300 starts) Lt; / RTI > may be deactivated during the period in which it is flushed. Here, the point in time when the transfer unit 125 is inactivated is possible before or simultaneously with the start of flushing of the cache 300, or both.

After the flushing of the cache 300 is completed, the transfer unit 125 sends information (CI.I) related to the flushing of the cache (for example, information indicating that flushing of the cache 300 is completed) to the setting unit 115 And can be activated.

The transmission unit 125 can perform a read or write operation to the memory 200. [ As described above, it is assumed that the transfer unit 125 can transfer the first data to a predetermined address of the memory 200, and the transfer unit 125 reads data from the memory 200 in addition to the write operation Operation can also be performed.

Referring to FIGS. 2 and 3, the operation of the DMA module is shown after the invalidation (i.e., flush) of the cache is completed. 3 is a case in which the semiconductor device 100 according to the embodiment of the present invention is not applied.

That is, the operation of the DMA module may be blocked during a period in which the processor flushes the cache (Cache Invalidation) (time t1 to t2). If the operation of the DMA module is not blocked during the period (time t1 to t2) during which the cache is flushed, if the address of the memory where the cache is flushed and the address of the memory to which the DMA module transmits data is the same, (I.e., un-updated data or old data) may be overwritten on the latest data even though the data to be transmitted is the latest data.

Accordingly, the operation of the DMA module is blocked during the period (time t1 to t2) during which the cache is flushed, and the initial setup of the DMA module (Initial Setup) Transmission parameter setting) can be started.

When the initial setting operation of the DME module is completed at the time t3, a data creation operation (Data Creation 1) (i.e., the generation unit generates the first data) can be started from the time t3.

At the time t4, when the generation of the first data is completed, the generation of the second data (Data Creation 2) from the time t4 (i.e., the generation unit generates the second data which is the latest data different from the first data) And data transfer 1 of the first data (i.e., the transfer unit transfers the first data to the memory) can be started at the same time. That is, the operation of the transmission unit of the DME module and the operation of the generation unit can be pipelined.

Subsequently, when the generation of the second data and the transfer of the first data are completed at the time t5, the transfer of the second data (Data transfer 2) (i.e., the transfer unit transfers the second data to the memory Can be started.

Here, the address of the memory to which the second data is transmitted may be different from the address of the memory to which the first data is transmitted.

3, it is possible to prevent the data flushed by the cache (i.e., the un-updated data or the old data) from being overwritten on the latest data. However, The execution time is slowed down, which may lead to a total performance degradation problem.

On the other hand, referring to FIGS. 2 and 4, the operation of the DMA module starts at the same time as invalidation (i.e., flushing) of the cache. 3 is a case to which the semiconductor device 100 according to the embodiment of the present invention is applied.

The difference from the above-described FIG. 3 will be mainly described.

That is, unlike FIG. 3, it can be seen that the operation of the DMI module 110 is not blocked during a period in which the processor 250 flushes the cache 300 (Cache Invalidation) (time t1 to t2).

Concretely, at the time t1, the flushing of the cache 300 is started, and the transfer unit 125 of the DMA module 110 can be disabled (Data Transfer Disable). Of course, the timing at which the transfer unit 125 of the DMA module 110 is deactivated is possible before or at the start of flushing of the cache 300 as described above, or after the start of flushing of the cache 300. However, In FIG. 4, it will be described that the flushing of the cache 300 starts and proceeds at the same time.

Here, the inactivation period of the transfer unit 125 may be continued until time t4, that is, the flushing of the cache 300 is completed. This is to prevent data (i.e., un-updated data or old data) that has been flushed by the cache 300 from being overwritten on the latest data.

The initial setting operation (initial setting) of the DMA module 110 (that is, the setting unit 115 sets the transfer parameter DP) at a time t2 elapsing from the time t1 at which the flushing of the cache 300 starts, Can be started.

That is, the operation of the DMA module 110 may be performed during a period in which the cache 300 is flushed. Accordingly, unlike FIG. 4 described above, it is possible to prevent the overall performance degradation caused by delaying the execution time of the DMA module by the flushing time of the cache 300. In other words, the execution time of the DMA module 110 is advanced by the flushing time of the cache 300 as shown in FIG. 4, thereby improving the overall performance.

When the initial setting operation of the DME module 110 is completed at time t3, a data creation operation (Data Creation 1) (i.e., the generation unit may generate the first data) may be started from time t3. Here, the generation of the first data may be pipelined with the flushing interval of the cache 300.

Specifically, the generation of the first data is started during the flushing interval of the cache 300 (i.e., starting from time t1 to time t4), before or after the end of the flushing interval of the cache, Can be terminated.

When the flushing of the cache 300 is completed at time t4, the transfer unit 125 of the DMA module 110 may be enabled (Data Transfer Enable) after time t4. Thus, when the generation of the first data is completed at the time t5, the generation of the second data (Data Creation 2) (i.e., the generation unit 120 generates the second data as the latest data different from the first data from the time t5) (I.e., the transfer unit 125 transfers the first data to the memory 200) can be started at the same time.

That is, the operation of the transmission unit 125 of the DME module 110 and the operation of the generation unit 120 may be pipelined.

Subsequently, at the time t6, when the generation of the second data and the transfer of the first data are completed, the transfer of the second data (Data transfer 2) (i.e., the transfer unit 125 transfers the second data to the memory (E.g., transmitting to the base station 200).

The semiconductor device 100 according to the embodiment of the present invention can maintain the deactivation period of the transfer unit 125 until the flushing of the cache 300 is completed, Updated data or old data) can be prevented from being overwritten on the latest data and the overall performance can be improved by advancing the execution time of the DMA module 110 by the flushing time of the cache 300. [

Further, in some embodiments of the present invention, the setting unit 115, the generating unit 120, and the transmitting unit 125 are implemented in hardware, but the present invention is not limited thereto. That is, the setting unit 115, the generating unit 120, and the transmitting unit 125 may be implemented in software and stored in the form of a code in the DMI module 110. [

Hereinafter, a semiconductor system according to an embodiment of the present invention will be described with reference to FIG. 5 and FIG. The contents overlapping with those of FIGS. 1 and 2 described above will be omitted.

5 is a block diagram illustrating a semiconductor system according to one embodiment of the present invention. FIG. 6 is a block diagram illustrating the second processor of FIG. 5. FIG.

5, a semiconductor system 400 according to an embodiment of the present invention may include a first processor 410, a cache 420, a second processor 430, and a bus 470.

The first processor 410 may flush the data stored in the cache 420 (e.g., old data, i.e., un-updated data) to a predetermined address in the memory 200. [

In particular, the first processor 410 may perform a read or write operation to the cache 420 in addition to flushing the cache 420. [ The first processor 410 may also provide information related to the flushing of the cache 420 and information related to the transmission parameters DP to the second processor 430.

Here, the first processor 410 may include, for example, a CPU (Central Processing Unit), and the memory 200 may include a DRAM, but the present invention is not limited thereto.

The cache 420 may be flushed by the first processor 410.

Specifically, the cache 420 may be flushed to a predetermined address of the memory 200 by the first processor 410. The cache 420 may also be coupled to the memory 200 via a bus 470.

The second processor 430 may generate data (latest data) different from the data stored in the cache 420 and transmit the generated data to a predetermined address of the memory 200.

Here, the second processor 430 internally generates data directly or can be provided from the external device 350. [

The bus 470 connects the first processor 410, the second processor 430 and the cache 420 as well as the semiconductor system 400 and the memory 200.

Specifically, the first processor 410 may provide information relating to the transmission parameters DP and information related to the flushing of the cache 420 to the second processor 430, And the second processor 430 may transfer the data to the pre-stored address of the memory 200 via the bus 470. [0050]

5, semiconductor system 400 is illustrated as including but not limited to a first processor 410, a cache 420, a second processor 430, and a bus 470. That is, the semiconductor system 400 may also include the memory 200 and the external device 350.

Referring to FIG. 6, the second processor 430 may include a DMA module 440 and a buffer 450. Here, the second processor 430 may be the semiconductor device 100 of FIG.

Accordingly, the DME module 440 can directly access the memory 200 through the bus 470. [

Specifically, the DMA module 440 sets a transfer parameter DP for transferring data to the memory 200, generates data to be transferred to the memory 200 based on the transfer parameter DP, (450). The DME module 440 may also transmit the data stored in the buffer 450 to a predetermined address of the memory 200. Here, the DME module 440 internally generates data to be transferred to the memory 200 directly or may be provided from the external device 350.

Also, as described above, the DME module 440 may include a setting unit 442, a generating unit 445, and a transmitting unit 447, and a detailed description thereof will be omitted.

In addition, information (CI.I) related to flushing the cache is provided to the second processor 430 (e.g., the configuration unit 442 of the second processor 430) But is not limited thereto. More specifically, information (CI.I) relating to flushing of the cache is shown to be provided to the setting unit 442 in the first processor 410 and then to the sending unit 447 in the setting unit 442 However, the present invention is not limited thereto. That is, information (CI.I) related to flushing of the cache may be provided to the transfer unit 447 directly via the bus 470 without passing through the setting unit 442 in the first processor 410, The cache 420 itself may generate information (CI.I) related to the flushing of the cache and provide it to the transfer unit 447 via the bus 470. [

Hereinafter, a semiconductor system according to another embodiment of the present invention will be described with reference to FIGS. 7 and 8. FIG. The contents overlapping with those of the above-described embodiments will be omitted.

7 is a block diagram illustrating a semiconductor system according to another embodiment of the present invention. 8 is a block diagram illustrating the second and third processors of FIG.

7, a semiconductor system 500 according to another embodiment of the present invention includes a first processor 510, a cache 520, a second processor 530, a third processor 580, a bus 595, . ≪ / RTI >

The first processor 510 may flush the data stored in the cache 520 (e.g., old data, i.e., un-updated data) to a predetermined address in the memory 200. [

Specifically, the first processor 510 may perform a read or write operation to the cache 520 in addition to flushing the cache 520. [ The first processor 510 may also provide information related to the flushing of the cache 520 and information related to the transmission parameters DP to the second processor 530.

Herein, the first processor 510 may include, for example, a CPU (Central Processing Unit), and the memory 200 may include a DRAM, but the present invention is not limited thereto.

The cache 520 may be flushed by the first processor 510.

Specifically, the cache 520 may be flushed to a predetermined address of the memory 200 by the first processor 510. The cache 520 may also be coupled to the memory 200 via a bus 595.

The second processor 530 may transmit data stored in the cache 520 and other data (latest data) to a predetermined address in the memory 200. [

Here, the second processor 530 may receive (i.e., read) the data stored in the third processor 580 and transmit the data to the memory 200. [

The third processor 580 can receive data to be transferred from the external device 350 to the memory 200 and store the received data.

The bus 595 connects the first processor 510, the second processor 530, the third processor 580 and the cache 520 as well as connects the semiconductor system 500 and the memory 200 .

Specifically, the first processor 510 provides the second processor 530 with information relating to the transmission parameters DP and information relating to the flushing of the cache 520, the second processor 510 providing information relating to the flushing of the cache 520, The second processor 530 is provided with data stored in the third processor 580; the cache 520 is flushed to a pre-stored address of the memory 200; And the second processor 530 transfers data to the pre-stored address of the memory 200 via the bus 595. [

Referring to FIG. 8, the second processor 530 may include a DMA module 540 and a first buffer 560.

Specifically, the DME module 540 may include a setting unit 542, a generating unit 545, and a transmitting unit 547. [

The setting unit 542 can set the transfer parameter DP for writing the first data in the memory 200. [

Specifically, the setting unit 542 can receive the information related to the transmission parameter DP from the first processor 510 via the bus 595, and set the transmission parameter DP. Here, the transmission parameter DP includes, for example, the size of the first data to be transmitted to the memory 200, the address of the first buffer 560 storing the first data to be transmitted to the memory 200, The address of the second buffer 590 storing the first data to be transmitted to the first memory 200, and the predetermined address of the memory 200 to which the first data is to be transmitted, but the present invention is not limited thereto. In addition, the first data may include the latest data to be transmitted to the memory 200.

The setting unit 542 also provides information (CI.I) related to invalidation of the cache (hereinafter referred to as flushing) as well as information related to the transmission parameter DP from the first processor 510 via the bus 595 And can start the setting operation of the transmission parameter DP based on the information (CI.I) related to the flushing of the provided cache. That is, the transmission parameter DP is set based on the information related to the transmission parameter DP provided from the first processor 510, and the starting point of the setting operation is the flushing of the cache provided from the first processor 510 RTI ID = 0.0 > (CI. I) < / RTI >

Herein, the information (CI.I) related to the flushing of the cache is provided from the first processor 510 to the second processor 530 (for example, the setting unit 542 of the second processor 530) But is not limited thereto. More specifically, information (CI.I) relating to flushing of the cache is shown to be provided to the setting unit 542 in the first processor 510 and then to the sending unit 547 in the setting unit 542 However, the present invention is not limited thereto. That is, information (CI.I) relating to flushing of the cache may be provided to the transfer unit 547 directly via the bus 595, without the setting unit 542 at the first processor 510, The cache 520 may itself generate information (CI.I) relating to flushing of the cache and provide it to the transfer unit 547 via the bus 595. [ However, for convenience of explanation, it is assumed that information (CI.I) related to the flushing of the cache is provided from the first processor 510 to the setting unit 542. [

The setting unit 542 may set the transmission parameter DP while the first processor 510 flushes the second data stored in the cache 520 to a predetermined address of the memory 200. [ Here, the second data may be old data (i.e., un-updated data), and may be data different from the first data which is the latest data.

The setting unit 542 can provide the set transmission parameters DP to the generating unit 545 and the transmitting unit 547. [ The setting unit 542 may also provide to the transfer unit 547 information (CI.I) relating to the flushing of the cache.

The generating unit 545 may generate first data to be transmitted to the memory 200 based on the set transmission parameters DP.

More specifically, the generation unit 545 can receive the transmission parameter DP from the setting unit 542, and can generate the transmission parameter DP based on the transmission parameter DP stored in the second buffer 590 of the third processor 580 1 data can be provided. Also, the receiving unit 545 may be provided with the first data for a period during which the cache 520 is flushed.

Here, the generating unit 545 may receive data from the second buffer 590 of the third processor 580 via the bus 595, or may internally generate data directly.

The generating unit 545 may also store the first data at the address of the first buffer 560 pointed to by the transmission parameter DP.

The transmission unit 547 can write the first data to a predetermined address of the memory 200 based on the transmission parameter DP.

Specifically, the transmission unit 547 can receive the transmission parameter DP from the setting unit 542 and can transmit the first data to the predetermined address of the memory 200 based on the transmission parameter DP . Here, the transfer unit 547 may transfer the first data stored in the first buffer 560 to the memory 200. [

That is, the transfer unit 547 reads the first data stored in the address of the first buffer 560 indicated by the transfer parameter DP and transfers the first data to the predetermined address of the memory 200 indicated by the transfer parameter DP Data can be transmitted (written).

The transmission unit 547 may transmit the first data to the predetermined address of the memory 200 after the flushing of the cache 520 is completed.

The transfer unit 547 also receives information (CI.I) related to the flushing of the cache 520 from the setting unit 542 (e.g., information indicating that the flushing of the cache 520 starts) Lt; / RTI > may be deactivated during the period in which it is flushed. Here, the point in time at which the transfer unit 547 is deactivated is possible before or simultaneously with the start of flushing of the cache 520, or both.

After the flushing of the cache 520 is completed, the transfer unit 547 sends information (CI.I) related to the flushing of the cache (e.g., information indicating that flushing of the cache 520 is completed) to the setting unit 542 And can be activated.

The transfer unit 547 can perform a read or write operation to the memory 200. [ As described above, the transfer unit 547 is capable of transferring the first data to a predetermined address of the memory 200, and the transfer unit 547 reads data to the memory 200 in addition to the write operation Operation can also be performed.

The third processor 580 may include a second buffer 590.

Specifically, the third processor 580 may generate and store the first data in the second buffer 590. That is, the third processor 580 can receive the transmission parameter from the setting unit 542, receive the first data from the external device 350 based on the received transmission parameter, or internally generate the first data .

That is, the semiconductor system 500 shown in FIG. 8 differs from the semiconductor system 400 shown in FIG. 6 in that a processor (that is, a third processor 580) receiving data from the external device 350 and a processor It can be seen that there is a separate processor (i.e., the second processor 530) that transfers the data provided from the device 350 to the memory 200. [

The semiconductor systems 400 and 500 shown in FIGS. 6 and 8 may also be integrated together with the memory 200 into one system. Illustratively, semiconductor system 400 or 500 and memory 200 may be integrated into one system to form a memory card. For example, the semiconductor system 400 or 500 and the memory 200 may be integrated into a single system and may be a PC card (PCMCIA), a compact flash card (CF), a smart media card (SM, SMC ), A memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), and a universal flash memory device (UFS). In addition, the semiconductor system 400 or 500 and the memory 200 may be integrated into a single system to form a solid state drive (SSD).

9, a semiconductor system 500 according to another embodiment of the present invention includes a first processor 510, a cache 520, a second processor 530, and a third processor 580, These may be implemented as a single System on Chip 600, and each of these elements may be interconnected via an internal bus in the system-on-chip, e.g., a bus conforming to the AXI Advanced Extensible Interface (AXI) protocol. Also in some embodiments of the invention. The system-on-chip may be implemented as an application processor installed in the terminal. In some embodiments of the present invention, the system-on-chip may be implemented to include memory 200 and external device 350 as well.

Of course, not only the semiconductor system 500 of FIG. 7 but also the semiconductor system 400 of FIG. 5 may be implemented as a system-on-chip, and a detailed description thereof will be omitted.

Additionally, the semiconductor system 400 or 500 may be implemented in various types of packages. For example, the semiconductor system 400 or 500 may include a package on package (PoP), ball grid arrays (BGAs), chip scale packages (CSPs), plastic leaded chip carriers (PLCC) Die in Waffle Pack, Die in Wafer Form, Chip On Board (COB), Ceramic Dual In Line Package (CERDIP), Plastic Metric Quad Flat Pack (MQFP), Thin Quad Flatpack (TQFP) (SSOP), Thin Small Outline (TSOP), Thin Quad Flatpack (TQFP), System In Package (SIP), Multi Chip Package (MCP), Wafer-level Fabricated Package WSP), etc. Figures 10-12 are exemplary electronic systems to which a semiconductor system according to some embodiments of the present invention may be applied.

Fig. 10 shows a tablet PC 1200, Fig. 11 shows a notebook 1300, and Fig. 12 shows a smartphone 1400. Fig. Semiconductor systems 400, 500 in accordance with some embodiments of the present invention may be used with such tablet PC 1200, notebook 1300, smartphone 1400, and the like.

It is also apparent to those skilled in the art that the semiconductor system 400, 500 according to some embodiments of the present invention may also be applied to other integrated circuit devices not illustrated. That is, although only the tablet PC 1200, the notebook computer 1300, and the smartphone 1400 are described as examples of the electronic system according to the present embodiment, the electronic system according to the present embodiment is not limited thereto. In some embodiments of the invention, the electronic system may be a computer, an Ultra Mobile PC (UMPC), a workstation, a netbook, a Personal Digital Assistant (PDA), a portable computer, a wireless phone, A mobile phone, an e-book, a portable multimedia player (PMP), a portable game machine, a navigation device, a black box, a digital camera, A digital audio recorder, a digital audio recorder, a digital picture recorder, a digital picture player, a digital video recorder, ), A digital video player, or the like.

Hereinafter, an operation method of the semiconductor device of FIG. 1 will be described with reference to FIG. 13 and FIG. The contents overlapping with those of FIG. 1 described above will be omitted.

13 and 14 are views for explaining a method of operating the semiconductor device of FIG.

Referring to FIGS. 2, 13 and 14, information (DP.I) related to transmission parameters and information (CI.I) related to flushing of a cache are provided (SlOO).

Specifically, the setting unit 115 may be provided with information (DP.I) related to transmission parameters and information (CI.I) related to flushing of the cache from the processor 250.

And provides a flushing start signal of the cache 300 (S105).

Specifically, the processor 250 may provide a flushing start signal to the cache 300.

The data transfer operation of the DMA module 110 is inactivated (S107).

Specifically, the setting unit 115 may provide the transfer unit 125 with information (CI.I) related to the flushing of the cache. Also, the transfer unit 125 may be deactivated by receiving information (CI.I) associated with flushing of the cache (e.g., information indicating that flushing of the cache 300 is to begin).

Flushing of the cache 300 is started (S110).

In particular, the second data (old data, i.e., un-updated data) stored in the cache 300 may be flushed to a predetermined address of the memory 200. [

In the present invention, S100, S105, S107, and S110 are sequentially generated, but the present invention is not limited thereto. That is, the processor 250 provides the flushing start signal to the cache 300 (S105), and then transmits to the setting unit 115 information (DP.I) related to the transmission parameter and information (CI.I (S100).

Thus, the point in time at which the transfer unit 125 is deactivated (S107) may be before, at the same time, or after the point in time at which the flushing of the cache 300 starts (S110).

After the flushing of the cache 300 is started, the setting unit 115 can set the transmission parameter DP based on the information DP.I related to the transmission parameter provided from the processor 250. [ The setting unit 115 may set the transmission parameter DP and provide it to the generating unit 120 (S113).

Data is generated (S115).

Specifically, the generating unit 120 may generate the first data (i.e., the latest data to be transmitted to a predetermined address of the memory 200) based on the supplied transmission parameters DP. The generating unit 120 may directly generate the first data internally or may receive the first data from the external device 350. [

The data is stored in the buffer 160 (S117).

Specifically, the generating unit 120 may store the first data at the address of the buffer 160 indicated by the transmission parameter DP.

The processor 250 determines whether information (CI.I) related to flushing of the cache (e.g., information indicating that the flushing of the cache 300 is complete) to the setting unit 115 ). ≪ / RTI > However, if the flushing of the cache 300 has not ended, the deactivation state of the transfer unit 125 can be maintained (i.e., the data transfer operation of the DMA module is deactivated) (S122).

The data transfer operation of the DMA module 110 is activated (S125).

Specifically, when the setting unit 115 is informed from the processor 250 that the flushing of the cache 300 is completed, the setting unit 115 can provide the information to the transfer unit 125. [

The transmission unit 125 is informed that the flushing of the cache 300 is completed, and can be activated.

The data stored in the buffer 160 is read (S127).

Specifically, the transmission unit 125 can read the first data stored in the buffer 160 based on the transmission parameter DP.

Data is transmitted to the memory 200 (S130).

Specifically, the transmission unit 125 may transmit the first data to a predetermined address of the memory 200 based on the transmission parameter DP.

Hereinafter, an operation method of the semiconductor system of Fig. 5 will be described with reference to Figs. 15 and 16. Fig. The contents overlapping with those of FIG. 5 described above will be omitted.

FIGS. 15 and 16 are diagrams illustrating a method of operating the semiconductor system of FIG.

Referring to FIGS. 6, 15, and 16, information related to a transmission parameter and information (CI.I) related to flushing of a cache are provided (S200).

Specifically, the configuration unit 442 included in the DMA module 440 of the second processor 430 receives from the first processor 410 information relating to transmission parameters and information (CI.I) relating to flushing of the cache Can be provided.

And provides a flushing start signal of the cache 420 (S205).

Specifically, the first processor 410 may provide an invalidation (i.e., flush) start signal to the cache.

The data transfer operation of the DMA module 440 is inactivated (S207).

Specifically, the setting unit 442 can provide the transfer unit 447 with information (CI.I) related to the flushing of the cache. The transfer unit 447 may also be deactivated by receiving information (CI.I) associated with flushing of the cache (e.g., information indicating that flushing of the cache 420 is to begin).

Flushing of the cache 420 is started (S210).

In particular, the second data (old data, i.e., un-updated data) stored in the cache 420 may be flushed to a predetermined address of the memory 200. [

In the present invention, S200, S205, S207, and S210 are sequentially generated, but the present invention is not limited thereto. That is, after the first processor 410 provides the flushing start signal to the cache 420 (S205), the first processor 410 provides the setting unit 442 with information related to transmission parameters and information (CI.I) related to flushing of the cache (S200).

Thus, the point in time at which the transfer unit 447 is deactivated (S207) may be earlier, at the same time, or later than the point in time at which the flushing of the cache 420 starts (S210).

After the flushing of the cache 420 is started, the setting unit 442 can set the transmission parameter DP based on the information related to the transmission parameter provided from the first processor 410. [ The setting unit 442 may set the transmission parameter DP and provide it to the generating unit 445 (S213).

Data is generated (S215).

Specifically, the generating unit 445 may generate the first data (i.e., the latest data to be transmitted to the predetermined address of the memory 200) based on the supplied transmission parameters DP. The generating unit 445 may directly generate the first data internally or may receive the first data from the external device 350.

The data is stored in the buffer 450 (S217).

Specifically, the generating unit 445 may store the first data at the address of the buffer 450 indicated by the transmission parameter DP.

When the flushing of the cache 420 is terminated (S220), the first processor 410 determines whether information (CI.I) related to the flushing of the cache (e.g., flushing of the cache 420) Quot;). ≪ / RTI > However, if the flushing of the cache 420 has not ended, the deactivation state of the transfer unit 447 can be maintained (i.e., the data transfer operation inactivated state of the DMA module) (S222).

The data transfer operation of the DMA module 440 is activated (S225).

Specifically, when the setting unit 442 is informed from the first processor 410 that the flushing of the cache 420 is completed, the setting unit 442 can provide the information to the transfer unit 447.

The transfer unit 447 is informed that the flushing of the cache 420 is completed and can be activated.

The data stored in the buffer 450 is read (S227).

Specifically, the transfer unit 447 can read the first data stored in the buffer 450 based on the transfer parameter DP.

And transfers the data to the memory 200 (S230).

Specifically, the transmission unit 447 can transmit the first data to the predetermined address of the memory 200 based on the transmission parameter DP.

Hereinafter, an operation method of the semiconductor system of FIG. 7 will be described with reference to FIGS. 17 and 18. FIG. The contents overlapping with those of FIG. 7 described above will be omitted.

17 and 18 are views for explaining a method of operating the semiconductor system of FIG.

Referring to FIGS. 7, 17 and 18, information relating to transmission parameters and information (CI.I) related to flushing of the cache are provided (S300).

Specifically, the setting unit 542 included in the DMA module 540 of the second processor 530 receives from the first processor 510 information relating to transmission parameters and information (CI.I) relating to flushing of the cache Can be provided.

And provides a flushing start signal of the cache 520 (S305).

Specifically, the first processor 510 may provide an invalidation (i.e., flush) start signal to the cache.

The data transfer operation of the DMA module 540 is deactivated (S307).

Specifically, the setting unit 542 may provide the transfer unit 547 with information (CI.I) related to the flushing of the cache. The transfer unit 547 may also be deactivated by receiving information (CI.I) related to flushing of the cache (e.g., information that flushing of the cache 520 is to begin).

Flushing of the cache 520 is started (S310).

In particular, the second data (old data, i.e., un-updated data) stored in the cache 520 may be flushed to a predetermined address of the memory 200. [

In the present invention, S300, S305, S307, and S310 are sequentially generated, but the present invention is not limited thereto. That is, after providing the flushing start signal to the cache 520 (S305), the first processor 510 provides the setting unit 542 with information related to the transmission parameter and information (CI.I) related to the flushing of the cache (S300).

Therefore, the time point S307 at which the transfer unit 547 is deactivated may be before, coincident with, or after the time point S310 at which the flushing of the cache 520 starts.

After the flushing of the cache 520 is started, the setting unit 542 can set the transmission parameter DP based on the information related to the transmission parameter provided from the first processor 510. [ Although not shown in the figure, the third processor 580 may be provided with transmission parameters from the setting unit 542, and may receive the first data from the external device 350 based on the received transmission parameters, (S313).

The setting unit 542 may set the transmission parameter DP and provide it to the generating unit 545 (S314).

18 shows a case where the third processor 580 receives the transmission parameter from the setting unit 542 and generates the first data at step S313 when the generating unit 545 receives the transmission parameter DP from the setting unit 542, (S314), but the present invention is not limited thereto.

That is, the time when the generation unit 545 receives the transmission parameter DP from the setting unit 542 is earlier than the time when the third processor 580 receives the transmission parameter from the setting unit 542, Lt; / RTI >

Data is read from the second buffer 590 (S315).

Specifically, the generation unit 545 reads the first data (i.e., the latest data to be transmitted to the predetermined address of the memory 200) from the second buffer 590 based on the supplied transmission parameter DP . Although the generating unit 545 may directly generate the first data internally, the first data stored in the second buffer 590 will be described as an example for convenience of explanation.

The data is stored in the first buffer 560 (S317).

Specifically, the generating unit 545 may store the first data at the address of the first buffer 560 indicated by the transmission parameter DP.

The first processor 510 determines if the flushing of the cache 520 is complete (S320) and if the information (CI.I) related to flushing the cache (e.g., flushing the cache 520) Quot;). ≪ / RTI > However, if the flushing of the cache 520 has not ended, the deactivation state of the transfer unit 547 can be maintained (i.e., the data transfer operation inactivated state of the DMA module) (S322).

The data transfer operation of the DMA module 540 is activated (S325).

Specifically, when the setting unit 542 is informed from the first processor 510 that the flushing of the cache 520 is completed, the setting unit 542 can provide it to the transfer unit 547. [

The transfer unit 547 can be informed that flushing of the cache 520 is completed and can be activated.

The data stored in the first buffer 560 is read (S327).

Specifically, the transfer unit 547 can read the first data stored in the first buffer 560 based on the transfer parameter DP.

The data is transmitted to the memory 200 (S330).

Specifically, the transmission unit 547 may transmit the first data to a predetermined address of the memory 200 based on the transmission parameter DP.

While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, It is to be understood that the invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. It is therefore to be understood that the above-described embodiments are illustrative in all aspects and not restrictive.

Claims (20)

And a DMA module for directly accessing the memory and writing the first data to a predetermined address of the memory,
The DME module includes:
A setting unit for setting a transfer parameter for writing the first data in the memory;
A generating unit for generating first data to be transmitted to the memory based on the set transmission parameters;
And a transmission unit for writing the generated first data to the predetermined address of the memory based on the transmission parameter,
The setting unit setting the transmission parameter is performed during a period in which the processor flushes the second data stored in the cache to the predetermined address of the memory, Wherein the transmitting of the first data is performed after the flushing is completed. The method according to claim 1,
Wherein the first data is data different from the second data. The method according to claim 1,
Wherein the generating unit generates the first data by causing the generating unit to receive or directly generate the first data from an external device. The method according to claim 1,
And a buffer in which the first data is stored. 5. The method of claim 4,
Wherein the transmission parameter includes a size of the first data or an address of the buffer where the first data is stored or the predetermined address of the memory. The method according to claim 1,
Wherein the setting unit is provided with information relating to the transmission parameter and information relating to flushing of the cache from the processor. The method according to claim 1,
Wherein the transfer unit is provided with information related to flushing of the cache from the processor. The method according to claim 1,
Wherein the transfer unit is provided with information related to flushing of the cache from the cache. The method according to claim 1,
Wherein said generation unit generates said first data after said setting unit has finished setting said transmission parameter. 10. The method of claim 9,
Wherein the generation unit generates the first data during a period in which the cache is flushed. 11. The method of claim 10,
Wherein the transmitting unit starts transmitting the generated first data to the predetermined address of the memory after the generating unit is finished generating the first data. The method according to claim 1,
And a buffer in which the first data is stored,
Wherein the first data comprises third and fourth data,
Wherein the generating unit performs a first generating operation of generating the third data and storing the third data in the buffer and a second generating operation of generating the second data and storing the second data in the buffer,
Wherein the generating unit performs the second generating operation after completing the first generating operation. 13. The method of claim 12,
Wherein the predetermined address includes a first address and a second address,
The transmission unit performs a first transmission operation for transmitting the third data to the first address and a second transmission operation for transmitting the fourth data to the second address,
Wherein the transmission unit performs the second transmission operation after completing the first transmission operation,
Wherein the first transfer operation is performed during a period in which the second generation operation is performed. 13. The method of claim 12,
Wherein the first generating operation is performed during a period in which the cache is flushed,
Wherein the second generating operation is performed after the flushing of the cache is completed. A DMA module for directly accessing the memory; And
And a buffer for storing first and second data to be transmitted to the memory,
The DME module includes:
A setting unit for setting transmission parameters for transmitting the first and second data to the memory;
A generation unit configured to sequentially generate a first data generation operation for generating the first data based on the transmission parameter and storing the first data in the buffer and a second generation operation for generating the second data and storing the generated second data in the buffer;
A first transmission operation for transmitting the first data stored in the buffer to a first address of the memory based on the transmission parameter and a second transmission for transmitting the second data stored in the buffer to a second address of the memory, And a transmission unit for sequentially performing operations,
Wherein the setting unit sets the transmission parameter during a period in which the processor flushes third data stored in the cache to the first address and the first generating operation is performed during a period in which the cache is flushed Wherein the second generating operation is performed after the flushing of the cache is completed, and the first transmitting operation is performed during a period during which the second generating operation is performed after the flushing of the cache is completed. A cache connected to the memory via a bus;
A first processor for flushing the first data stored in the cache to a predetermined address in the memory; And
And a second processor for generating second data different from the first data and transmitting the second data to the predetermined address of the memory,
Wherein the second processor comprises:
A buffer for storing the generated second data,
And a DMA module for setting a transmission parameter for transmitting the second data to the memory and transmitting the second data stored in the buffer to the predetermined address based on the transmission parameter,
Wherein the setting of the transmission parameter by the DMA module is performed during a period in which the first processor flushes the first data stored in the cache to the predetermined address,
Wherein the DMA module transfers the second data to the predetermined address after the flushing is completed. A cache connected to the memory via a bus;
A first processor for flushing the first data stored in the cache to a predetermined address in the memory; And
And a second processor for generating second data different from the first data and transmitting the second data to the predetermined address of the memory via the bus,
Wherein the second processor comprises:
A buffer for storing the second data,
And a DMA module for transmitting the second data stored in the buffer to the predetermined address,
The DME module includes:
A setting unit configured to set a transmission parameter for transmitting the second data to the memory, and receive from the first processor information related to the transmission parameter and information related to flushing of the cache;
A generating unit for generating the second data to be transmitted to the memory based on the transmission parameter and storing the generated second data in the buffer;
And a transmission unit for transmitting the second data stored in the buffer to the predetermined address of the memory based on the transmission parameter,
The setting unit is configured to set the transmission parameter during a period in which the cache is flushed, and the transmitting unit transmitting the second data to the predetermined address in the memory is a state in which the flushing is completed Lt; / RTI > A cache connected to the memory via a bus;
A first processor for flushing the first data stored in the cache to a predetermined address in the memory;
A second processor including a first buffer for storing second data different from the first data; And
And a third processor including a DME module for directly accessing the memory,
The second processor generates the second data and stores the second data in the first buffer,
The DME module includes:
A setting unit for setting a transmission parameter for transmitting the second data to the memory;
A generating unit receiving the second data stored in the first buffer based on the transmission parameter;
And a transmission unit for transmitting the second data to the predetermined address of the memory based on the transmission parameter,
The setting unit setting the transmission parameter is performed during a period in which the cache is flushed, and the transmitting unit transmitting the second data to the predetermined address in the memory is performed after the completion of the flushing system. 19. The method of claim 18,
And the third processor further comprises a second buffer for storing the second data. 19. The method of claim 18,
And the first to third processors are connected to each other via the bus.

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