TWI681699B - Circuit design method and circuit design system - Google Patents

Abstract

A circuit design method and a circuit design system are provided. The circuit design method includes: providing a transmission line on a circuit board; providing a test signal to a main transmission line; obtaining the test signal and a first transmission time through the first via wire and the first branch transmission line via a first branch transmission line of the transmission line, and obtaining a test signal and a second transmission time via a second branch transmission line of the transmission line; obtaining the transmission time difference according to the first transmission time and the second transmission time; obtains the compensation distance according to the transmission time difference; and compensating the length of the first branch transmission line or the second branch transmission line by the compensation distance.

Description

Circuit wiring design method and circuit wiring design system

The invention relates to a circuit wiring design method and a circuit wiring design system for designing transmission lines in a circuit board.

In order to reduce the test signal multiple reflections on at least two branch transmission lines at different layers in the printed circuit board due to different electrical transmission lengths, the current T-topology wiring design is By making multiple branch transmission lines of the same layer of the printed circuit board mutually symmetrical in wiring, the signals transmitted by the at least two branch transmission lines can reach the receiving end of each branch transmission line at a similar time point.

However, this design only considers the length of the transmission line of the single-layer wiring design of the printed circuit board to be the same length, but does not consider that the printed circuit board in the multilayer wiring design, the branch transmission line between multiple layers may have different Guide hole height. Therefore, without considering the different via heights, the interference caused by the above-mentioned multiple reflection of the signal will not be reduced, thereby causing interference to the components of the receiving end of the branch transmission line, causing the transmitted signal to be severely damaged.

The invention provides a circuit wiring design method and a circuit wiring design system, which can be used to reduce the interference caused by multiple reflections of signals due to the different transmission time of different transmission lines during multilayer wiring.

The circuit wiring design method of the present invention. Used for circuit wiring design of circuit board. The circuit board includes a first via structure and a second via structure. The circuit design method includes: providing a transmission line on the circuit board. The transmission line includes a main transmission line, a first branch transmission line, and a second branch transmission line. The main transmission line connects one end of the first via structure and one end of the second via structure. One end is connected to the other end of the first via hole structure, one end of the second branch transmission line is connected to the other end of the second via hole structure; the test signal is provided to the main transmission line; the other end of the first branch transmission line is passed through the first via hole structure and The test signal of the first branch transmission line and obtain the first transmission time for passing the test signal, and the other end of the second branch transmission line obtains the test signal passing through the second via structure and the second branch transmission line and obtains the test signal passing The second transmission time; the transmission time difference is obtained according to the first transmission time and the second transmission time; the compensation distance is obtained according to the transmission time difference; and the length of the first branch transmission line or the second branch transmission line is compensated by the compensation distance to pass the test signal The first transmission time of the first via structure, the first branch transmission line and the second via structure and the second branch transmission line are equal to the second transmission time.

The circuit wiring design system of the present invention is installed on a circuit board. The circuit board includes a first via structure and a second via structure. Circuit wiring design system including transmission Line, driver, first receiver, second receiver, and processor. The transmission line includes a main transmission line, a first branch transmission line, and a second branch transmission line. The main transmission line connects one end of the first via structure and one end of the second via structure, and one end of the first branch transmission line connects to the other end of the first via structure. One end of the second branch transmission line is connected to the other end of the second via structure. The driver is used to provide test signals to the main transmission line. The first receiver is connected to the other end of the first branch transmission line. The first receiver is used to obtain a test signal output from the driver and pass through the first via structure and the first branch transmission line and obtain the first transmission time for the test signal to pass. The second receiver is connected to the other end of the second branch transmission line. The second receiver is used to obtain the test signal output from the driver and pass through the second via structure and the second branch transmission line and obtain the second transmission time for the test signal to pass. The processor is coupled to the first receiver and the second receiver. The processor is used to obtain the transmission time difference according to the first transmission time and the second transmission time, and obtain the compensation distance according to the transmission time difference. The compensation distance is used to compensate the length of the first branch transmission line or the second branch transmission line, so that the test signal passes through the first via structure and the first branch transmission line and the second via structure and the second branch transmission line The first transmission time is equal to the second transmission time.

Based on the above, the transmission time difference is obtained according to the first transmission time and the second transmission time. Next, the compensation distance is obtained according to the transmission time difference, and the distance of the first branch transmission line or the second branch transmission line is compensated by the compensation distance. The first transmission time is equal to the second transmission time, so that when the test signal passes through the first branch transmission line and when the test signal passes through the second branch transmission line, interference caused by multiple reflections of the signal will not occur.

In order to make the above-mentioned features and advantages of the present invention more obvious and understandable, the embodiments are specifically described below in conjunction with the accompanying drawings for detailed description as follows.

100‧‧‧ circuit wiring design system

110‧‧‧Drive

120_1‧‧‧First receiver

120_2‧‧‧Second receiver

130‧‧‧ processor

BL1‧‧‧The first branch transmission line

BL2‧‧‧Second branch transmission line

C1, C2‧‧‧ waveform

H1‧‧‧First guide hole structure

H2‧‧‧Second guide hole structure

LV1, LV2‧‧‧ Height

LL1, LL2‧‧‧Length

m1‧‧‧ First transmission time

m2‧‧‧Second transmission time

ML1‧‧‧Main transmission line

S210, S220, S230, S240, S250, S260

S242, S244, S252, S254, S256, S262, S264

TS‧‧‧Test signal

VREF‧‧‧Reference voltage level

FIG. 1 is a schematic diagram of a circuit wiring design system according to an embodiment of the invention.

2 is a flowchart of a circuit wiring design method according to an embodiment of the invention.

FIG. 3 is a waveform diagram of a test signal according to an embodiment of the invention.

FIG. 4 is a flowchart of a circuit wiring design method according to steps S230, S240, and S250.

Please refer to FIG. 1, which is a schematic diagram of a circuit wiring design system according to an embodiment of the invention. The circuit wiring design system is provided on a circuit board (not shown). The circuit board includes a first via structure H1 and a second via structure H2. In this embodiment, the circuit wiring design system 100 includes a transmission line, a driver 110, a first receiver 120_1, a second receiver 120_2, and a processor 130. The transmission line of this embodiment includes a main transmission line ML1, a first branch transmission line BL1, and a second branch transmission line BL2. The main transmission line ML1 connects the first end of the first via structure H1 and the first end of the second via structure H2. The first end of the first branch transmission line BL1 is connected to the The second end of the first via structure H1 and the first end of the second branch transmission line BL2 are connected to the second end of the second via structure H2. The driver 110 is used to provide a test signal TS to the main transmission line ML1. The first receiver 120_1 is connected to the second end of the first branch transmission line BL1. The first receiver 120_1 obtains the test signal TS output from the driver 110 through the second end of the first branch transmission line BL1 and passes through the first via hole structure H1 and the first branch transmission line BL1 and obtains the test signal TS through the first via hole structure H1 And the first transmission time m1 of the first branch transmission line BL1. The second receiver 120_2 is connected to the second end of the second branch transmission line BL2. The second receiver 120_2 obtains the test signal TS output from the driver 110 through the second end of the second branch transmission line BL2 and passes through the second via structure H2 and the second branch transmission line BL2 and obtains the test signal TS through the second via structure H2 And the second transmission time of the second branch transmission line BL2. The processor 130 is coupled to the first receiver 120_1 and the second receiver 120_2. The processor 130 is used to obtain a transmission time difference according to the first transmission time and the second transmission time, and obtain a compensation distance according to the transmission time difference. The compensation distance is used to compensate the length of the first branch transmission line BL1 or the second branch transmission line BL2, so that the first transmission time is equal to the second transmission time. The processor 130 may be, for example, a central processing unit (Central Processing Unit, CPU), or other programmable general-purpose or special-purpose microprocessor (Microprocessor), digital signal processor (DSP), or Programmable controllers, application specific integrated circuits (Application Specific Integrated Circuits, ASIC), programmable logic devices (Programmable Logic Device, PLD), or other similar devices or combinations of these devices can load and execute computer programs. The number of branch transmission lines of the present invention There may be multiple, and the number of receivers may also be multiple, which is not limited to this embodiment.

In the case where the main transmission line ML1, the first branch transmission line BL1 and the second branch transmission line BL2 are respectively laid out on different layers of the circuit board, the height LV1 of the first via structure H1 and the height LV2 of the second via structure H2 may have different. The first branch transmission line BL1 has a length LL1, and the first via structure H1 has a height LV1. Therefore, the path length formed by the first branch transmission line BL1 and the first via structure H1 is LV1+LL1. Similarly, the second branch transmission line BL2 has a length LL2, and the second via structure H2 has a height LV2, that is, the path length formed by the second branch transmission line BL2 and the first via structure H1 is LV2+LL2.

The circuit wiring design system 100 uses the processor 130 to obtain the transmission time difference according to the first transmission time and the second transmission time. In the case of the length of the first branch transmission line BL1 and the length of the second branch transmission line BL2, the processor 130 can learn the test signal TS in the first via hole structure H1 and the second via hole according to the first transmission time and the second transmission time The transmission time difference of structure H2. The difference in transmission time can reflect the difference in the actual transmission time of the test signal TS on the first via structure H1 and the second via structure H2. The processor 130 obtains the compensation distance according to the transmission time difference. In this way, the compensation distance is used to compensate the shorter of the first branch transmission line BL1 and the second branch transmission line BL2 to reduce the actual transmission time difference between the first branch transmission line BL1 and the second branch transmission line BL2. The time when the signal reaches the first receiver 120_1 and the second receiver 120_2 can be consistent, so as to eliminate the interference caused by the multiple reflection of the signal.

Material 1 on the first branch transmission line BL1 and the second branch transmission line BL2 In the case of a consistent and symmetrical design, the compensation distance can be regarded as being used to compensate for the difference between the height LV1 of the first via structure H1 and the height LV2 of the second via structure H2.

Specifically, please refer to FIG. 1 and FIG. 2 at the same time. FIG. 2 is a flowchart of a circuit wiring design method according to an embodiment of the invention. As described in step S210: the transmission line ML1 is provided. In step S210, the transmission line ML1 is provided on the circuit board. The main transmission line ML1 connects one end of the first via structure H1 and one end of the second via structure H2. One end of the first branch transmission line BL1 is connected to the other end of the first via hole structure H1, and one end of the second branch transmission line BL2 is connected to the other end of the second via hole structure H2. As described in step S220: a test signal TS is provided to the main transmission line ML1. In step S220, the driver 110 provides a test signal TS that rises from a first voltage level to a second voltage level to the input terminal of the main transmission line ML1. The first voltage level is different from the second voltage level. In this embodiment, the second voltage level is greater than the first voltage level. In some embodiments, the first voltage level is greater than the second voltage level. The test signal TS may be realized by a pulse signal of at least one cycle, a step signal or a ramp signal of at least one cycle.

As described in step S230: the test signal and the first transmission time are obtained through the other end of the first branch transmission line BL1, and the test signal and the second transmission time are obtained through the other end of the second branch transmission line BL2. In an embodiment, the first receiver 120_1 obtains the test signal TS passing through the first via structure H1 and the first branch transmission line BL1 at the second end of the first branch transmission line BL1, so as to obtain the test signal TS from the first voltage The first transmission time when the level rises to the second voltage level. And the second receiver 120_2 also obtains a pass through the second end of the second branch transmission line BL2 The via signal structure H2 and the test signal TS of the second branch transmission line BL2 are used to obtain a second transmission time for the test signal TS to rise from the first voltage level to the second voltage level.

In another embodiment, a reference voltage level VREF may be set between the first voltage level and the second voltage level. The first receiver 120_1 may receive the test signal TS at the second end of the first branch transmission line BL1, and use the time point when the test signal TS rises from the first voltage level to the reference voltage level VREF as the first transmission time. Similarly, the second receiver 120_2 can also receive the test signal TS at the second end of the second branch transmission line BL2, and take the time point when the test signal TS rises from the first voltage level to the reference voltage level VREF as the first 2. Transmission time. In this embodiment, the voltage value of the reference voltage level VREF is the average of the voltage value of the first voltage level and the voltage value of the second voltage level. In other embodiments, in the case where the voltage value of the second voltage level is greater than the voltage value of the reference voltage level VREF, the voltage value of the reference voltage level VREF may be set to 10 of the voltage value of the second voltage level %~90%. In other embodiments, when the test signal TS is that the first voltage level is greater than the second voltage level, that is, the voltage value of the first voltage level is greater than the voltage value of the reference voltage level VREF The voltage value of the reference voltage level VREF may be set to be higher than the voltage value of the first voltage level by 10% to 90%.

Specifically, please refer to FIG. 1 and FIG. 3 at the same time. FIG. 3 is a waveform diagram of the test signal TS according to an embodiment of the present invention. In this embodiment, in FIG. 3, the first receiver 120_1 receives at the second end of the first branch transmission line BL1 The waveform to the test signal TS is represented by the waveform C1. The waveform of the test signal TS received by the second receiver 120_2 at the second end of the second branch transmission line BL2 is represented by the waveform C2. In this embodiment, the voltage value of the first voltage level is 0 volts (V), and the voltage value of the second voltage level is 1.5V. The voltage value of the reference voltage level VREF is the average of the voltage value of the first voltage level and the voltage value of the second voltage level. Therefore, the voltage value of the reference voltage level VREF is 0.75V. The time when the first receiver 120_1 receives the received test signal TS from the first voltage level to the reference voltage level VREF is taken as the first transmission time m1. In FIG. 3, the first transmission time m1 is 1.041 nanoseconds (nsec). The time point when the second receiver 120_2 receives the received test signal TS from the first voltage level to the reference voltage level VREF is taken as the second transmission time m2. In FIG. 3, the second transmission time m2 is 1.054 nanoseconds.

Please return to FIG. 1 and FIG. 2, after obtaining the first transmission time and the second transmission time in step S230 of the circuit wiring design system 100, proceed to step S230.

As described in step S240: the transmission time difference is obtained according to the first transmission time and the second transmission time. In step S240, the processor 130 receives the first transmission time from the first receiver 120_1 and the second transmission time from the second receiver 120_2. The processor 130 obtains the transmission time difference according to the first transmission time and the second transmission time.

As described in step S250: the compensation distance is obtained according to the transmission time difference. In step S240, the processor 130 determines based on the above-mentioned transmission time difference, and obtains the compensation distance based on the result of the determination. After obtaining the compensation distance, enter the step S250. As described in step S260: the length of the first branch transmission line BL1 or the second branch transmission line BL2 is compensated by the compensation distance so that the first transmission time is equal to the second transmission time.

To further explain, please refer to FIG. 1, FIG. 2 and FIG. 4 at the same time. FIG. 4 is a flowchart of the circuit wiring design method shown in steps S240, S250, and S260 in FIG. In this embodiment, step S240 further includes steps S242 and S244. Step S250 further includes steps S252, S254, and S256. Step S260 further includes steps S262 and S264.

As described in step S242: the transmission time difference is obtained according to the first transmission time and the second transmission time. In step S242, the processor 130 compares the first transmission time with the second transmission time to obtain a transmission time difference. For example, taking FIG. 3 as an example, the first transmission time m1 is 1.041 nanoseconds, and the second transmission time m2 is 1.054 nanoseconds. Therefore, the processor 130 may perform a subtraction operation on the first transmission time m1 and the second transmission time m2 to obtain the transmission time difference between the first transmission time m1 and the second transmission time m2. After subtraction, the transmission time difference = m1-m2 = -0.013 nanoseconds = -13 picoseconds (psec). The processor 130 may further determine the result of the transmission time difference in step S244. In this embodiment, the processor 130 may determine that the first transmission time is shorter than, longer than, or equal to the second transmission time based on the result of the transmission time difference. According to the above example, the result of the transmission time difference being -13 picoseconds indicates that the first transmission time is shorter than the second transmission time by about 13 picoseconds. In other words, the test signal TS is transmitted to the first receiver 120_1 via the first via hole structure H1 and the first branch transmission line BL1 in a shorter time than the test signal TS via the second via hole structure H2 And the length of time that the second branch transmission line BL2 is transmitted to the second receiver 120_2. Therefore, the processor 130 proceeds to step S252 and obtains the compensation distance according to the transmission time difference.

As described in step S252: the first compensation distance is obtained according to the transmission speed of the test signal TS on the first branch transmission line BL1. If the first transmission time is shorter than the second transmission time, the processor 130 will obtain the transmission speed of the test signal TS on the first branch transmission line BL1 in step S252. For example, the processor 130 may learn from the database that the transmission speed of the test signal TS on the first branch transmission line BL1 is 153.217 picoseconds/inch (psec/inch), that is, 0.153217 psec/mil. Therefore, the processor 130 will obtain the first compensation distance according to the transmission time difference generated by the first transmission time being shorter than the second transmission time and the above-mentioned transmission speed. According to the above example, when the transmission time difference is equal to -13 picoseconds and the transmission speed of the test signal TS in the first layer transmission line TL1 is 0.153217 psec/mil, the processor 130 can divide the absolute value of the transmission time difference by the test signal The transmission speed of TS on the first layer transmission line TL1 to obtain the first compensation distance, that is, the first compensation distance is 13÷0.153217=84.846mil. Then, it progresses to step S262.

As described in step S262: the length of the first branch transmission line BL1 is increased by the first compensation distance. After the processor 130 obtains the first compensation distance, the processor 130 can output the first compensation distance to provide to the layout software, and the layout software increases the length of the first branch transmission line BL1 by the first compensation distance. Further, the layout software increases the length of the first branch transmission line BL1 by the first compensation distance, thereby increasing the length of the first branch transmission line BL1 by 84.846 mil. When the length of the first branch transmission line BL1 is increased, the test signal TS will be extended to the first receiver 120_1 time, so the first transmission time can be delayed. In this way, the first transmission time can be close to the second transmission time, so as to reduce the interference caused by the multiple reflection of the signal.

Please return to step S244. In some embodiments, the difference in transmission time obtained based on the first transmission time and the second transmission time may also be greater than zero. Such a result indicates that the second transmission time is shorter than the first transmission time. That is, the test signal TS is transmitted to the second receiver 120_2 through the second via hole structure H2 and the second branch transmission line BL2 in a shorter time than the test signal TS is received through the first via hole structure H1 and the first branch transmission line BL1 The length of time transmitted to the first receiver 120_1. The processor 130 proceeds to step S254 and obtains the compensation distance according to the transmission time difference.

As described in step S254: the second compensation distance is obtained according to the transmission speed of the test signal TS on the second branch transmission line BL2. If the second transmission time is shorter than the first transmission time, the processor 130 will obtain the transmission speed of the test signal TS on the second branch transmission line BL2 in step S254. Therefore, the processor 130 obtains the second compensation distance according to the transmission time difference generated by the second transmission time being shorter than the first transmission time and the transmission speed of the second branch transmission line BL2.

As described in step S264: the length of the second branch transmission line BL2 is increased by the second compensation distance. After the processor 130 obtains the second compensation distance in step S254, the processor 130 can output the second compensation distance to provide to the layout software, and the layout software increases the length of the second branch transmission line BL2 by the second compensation distance. Further, the layout software increases the length of the second branch transmission line BL2 by the second compensation distance degree. In the case where the length of the second branch transmission line BL2 is increased, the transmission time of the test signal TS to the second receiver 120_2 is extended, so the second transmission time can be delayed. In this way, the second transmission time can be close to the first transmission time, thereby reducing interference caused by multiple reflections of the signal.

Please return to step S244 again. In some other embodiments, the transmission time difference may have a result equal to 0. Such a result indicates that the first transmission time is equal to the second transmission time. That is, the test signal TS is transmitted to the second receiver 120_2 through the second via hole structure H2 and the second branch transmission line BL2 equal to the test signal TS being transmitted through the first via hole structure H1 and the first branch transmission line BL1 The length of time to the first receiver 120_1. Therefore, the processor 130 proceeds to step S256 and does not generate the compensation distance.

In summary, the present invention is the first transmission time for receiving the test signal at the second end of the first branch transmission line, and the second transmission time for receiving the test signal at the second end of the second branch transmission line. The transmission time difference is obtained according to the first transmission time and the second transmission time. Obtain the compensation distance according to the transmission time difference. The transmission time difference can reflect the actual difference between the transmission time of the test signal through the first via structure and the first branch transmission line and the transmission time through the second via structure and the second branch transmission line. Next, the compensation distance is obtained according to the transmission time difference. In this way, the compensation distance is used to compensate one of the first branch transmission line and the second branch transmission line to reduce the difference in actual transmission time between the first branch transmission line and the second branch transmission line, so that the first transmission time and the second The transmission time can be the same to eliminate the interference caused by the multiple reflection of the signal.

Although the present invention has been disclosed as above with examples, it is not intended to limit the present invention. Any person with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention shall be subject to the scope defined in the appended patent application.

S210, S220, S230, S240, S250, S260

Claims (12)

A circuit wiring design method for circuit wiring design of a circuit board, the circuit board includes a first via structure and a second via structure, the circuit wiring design method includes: providing a transmission line on the circuit board, The transmission line includes a main transmission line, a first branch transmission line and a second branch transmission line, the main transmission line connects one end of the first via structure and one end of the second via structure, and one end of the first branch transmission line connects to the The other end of the first via structure, one end of the second branch transmission line is connected to the other end of the second via structure; a test signal is provided to the main transmission line; the other end of the first branch transmission line is passed through the first The via structure and the test signal of the first branch transmission line and obtain a first transmission time for the test signal to pass, and the second via transmission structure and the second branch transmission line are obtained through the other end of the second branch transmission line The test signal and obtain a second transmission time through which the test signal passes; obtain a transmission time difference based on the first transmission time and the second transmission time; obtain a compensation distance based on the transmission time difference; and compensate by the compensation distance The length of the first branch transmission line or the second branch transmission line, so that the test signal passes through the first via structure and the first branch transmission line and the second via structure and the first transmission of the second branch transmission line The time is equal to the second transmission time. The circuit wiring design method as described in item 1 of the patent application scope, wherein the step of obtaining the compensation distance according to the transmission time difference includes: judging that the first transmission time is shorter or longer than the second transmission time according to the transmission time difference; and when When the first transmission time is shorter than the second transmission time, a first compensation distance is obtained according to the transmission speed of the first branch transmission line, and the length of the first branch transmission line is increased according to the first compensation distance. The circuit wiring design method as described in item 2 of the patent application scope, wherein the step of determining that the first transmission time is shorter or longer than the second transmission time according to the transmission time difference further includes: when it is determined that the second transmission time is shorter than At the first transmission time, a second compensation distance is obtained according to the transmission speed of the second branch transmission line, and the length of the second branch transmission line is increased according to the second compensation distance. The circuit wiring design method as described in item 1 of the patent application scope, wherein the test signal is an electrical signal that rises from a first voltage level to a second voltage level, wherein the first transmission time and the The step of the second transmission time includes: receiving the test signal from the other end of the first branch transmission line to use the time point when the first voltage level reaches the second voltage level as the first transmission time; and The other end of the second branch transmission line receives the test signal to use the time point when the first voltage level reaches the second voltage level as the second transmission time. The circuit wiring design method as described in item 4 of the patent application scope, wherein the step of obtaining the first transmission time and the second transmission time includes: providing a reference voltage level, wherein the reference voltage level is located at the first Between the voltage level and the second voltage level; receiving the test signal from the other end of the first branch transmission line to use the time point when the first voltage level reaches the reference voltage level as the first transmission Time; and receiving the test signal from the other end of the second branch transmission line to use the time point when the first voltage level reaches the reference voltage level as the second transmission time. The circuit wiring design method as described in item 5 of the patent application range, wherein the voltage value of the reference voltage level is the average value of the voltage value of the first voltage level and the voltage value of the second voltage level. A circuit wiring design system is provided on a circuit board including a first via structure and a second via structure. The circuit wiring design system includes: a transmission line provided on the circuit board, including a main A transmission line, a first branch transmission line and a second branch transmission line, the main transmission line connects one end of the first via structure and one end of the second via structure, and one end of the first branch transmission line connects the first via structure The other end of the second branch transmission line is connected to the other end of the second via structure; a driver for providing a test signal to the main transmission line; a first receiver connected to the other of the first branch transmission line At one end, the first receiver is used to obtain the test signal output from the driver and pass through the first via structure and the first branch transmission line and obtain a first transmission time for the test signal to pass; a second receiver, Connected to the other end of the second branch transmission line, the second receiver is used to obtain the test signal output from the driver and pass through the second via structure and the second branch transmission line and obtain a second transmission through which the test signal passes Time; and a processor, coupled to the first receiver and the second receiver, for obtaining a transmission time difference according to the first transmission time and the second transmission time, and obtaining a compensation distance according to the transmission time difference Where the compensation distance is used to compensate for the length to the first branch transmission line or the second branch transmission line so that the test signal passes through the first via structure and the first branch transmission line and the second via structure and the The first transmission time and the second transmission time of the second branch transmission line are equal. The circuit wiring design system as described in item 7 of the patent application scope, wherein: wherein the processor is further used for: judging that the first transmission time is shorter or longer than the second transmission time based on the transmission time difference; and when it is determined that the When the first transmission time is shorter than the second transmission time, a first compensation distance is obtained according to the transmission speed of the first branch transmission line, and the length of the first branch transmission line is increased according to the first compensation distance. The circuit wiring design system as described in item 8 of the patent application scope, wherein: the processor is further used to obtain the transmission speed of the second branch transmission line when the second transmission time is determined to be shorter than the first transmission time A second compensation distance increases the length of the second branch transmission line according to the second compensation distance. The circuit wiring design system as described in item 7 of the patent application scope, wherein: the test signal is an electrical signal that rises from a first voltage level to a second voltage level, and the first receiver The other end of a branch transmission line receives the test signal to use the time point when the first voltage level reaches the second voltage level as the first transmission time, and the second receiver receives the test signal from the second branch transmission line. One end receives the test signal to use the time point when the first voltage level reaches the second voltage level as the second transmission time. The circuit wiring design system as described in item 10 of the patent application scope, wherein: the test signal is an electrical signal that rises from a first voltage level to a second voltage level, and the first receiver The other end of a branch transmission line receives the test signal to use the time point from when the first voltage level reaches a reference voltage level as the first transmission time, wherein the reference voltage level is located at the first voltage level Between the second voltage level, the second receiver receives the test signal from the other end of the second branch transmission line to use the time point when the first voltage level reaches the reference voltage level as the first 2. Transmission time. The circuit wiring design system as described in item 11 of the patent application range, wherein the voltage value of the reference voltage level is the average of the voltage value of the first voltage level and the voltage value of the second voltage level.

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