TWI681693B - Upper electrode element, reaction chamber and semiconductor processing device - Google Patents
Upper electrode element, reaction chamber and semiconductor processing device Download PDFInfo
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- TWI681693B TWI681693B TW107112447A TW107112447A TWI681693B TW I681693 B TWI681693 B TW I681693B TW 107112447 A TW107112447 A TW 107112447A TW 107112447 A TW107112447 A TW 107112447A TW I681693 B TWI681693 B TW I681693B
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- H—ELECTRICITY
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- H—ELECTRICITY
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- H—ELECTRICITY
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- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
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- H—ELECTRICITY
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- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
- H01J37/32—Gas-filled discharge tubes
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Abstract
本發明提供一種上電極元件及反應腔室。該上電極元件包括線圈,該線圈中設置有n個功率饋入點,其中,n為大於等於1的整數;並且該線圈中設置有n+1個接地端點,該功率饋入點和該接地端點的排布關係遵循以下規律:對於每一該功率饋入點而言,沿線圈的纏繞方向在該功率饋入點的上游和下游分別設置有一個接地端點,該功率饋入點和其上游接地端點之間的線圈構成第一線圈分部,該功率饋入點和其下游接地端點之間的線圈構成第二線圈分部,該第一線圈分部和第二線圈分部並聯在該功率饋入點和地之間。本發明提供的上電極元件和反應腔室,可以減小線圈上存在的電位分佈差異,從而可以提高電漿的分佈均勻性,進而可以提高製程均勻性。 The invention provides an upper electrode element and a reaction chamber. The upper electrode element includes a coil, where n power feeding points are provided in the coil, where n is an integer greater than or equal to 1; and n+1 grounding endpoints are provided in the coil, the power feeding point and the The arrangement relationship of the grounding terminals follows the following rules: for each of the power feeding points, a grounding terminal is provided upstream and downstream of the power feeding point along the winding direction of the coil, and the power feeding point The coil between its upstream grounding terminal constitutes the first coil section, and the coil between the power feed point and its downstream grounding terminal constitutes the second coil section, the first coil section and the second coil section The part is connected in parallel between the power feed point and ground. The upper electrode element and the reaction chamber provided by the present invention can reduce the difference in potential distribution existing on the coil, thereby improving the distribution uniformity of the plasma and further improving the process uniformity.
Description
本發明涉及半導體製造技術領域,具體地,涉及一種上電極元件、反應腔室及半導體加工裝置。 The present invention relates to the technical field of semiconductor manufacturing, and in particular, to an upper electrode element, a reaction chamber, and a semiconductor processing device.
在半導體製造製程中,電感耦合電漿(ICP,Inductive Coupled Plasma)發生裝置可以在較低的工作氣壓下獲得高密度的電漿,而且結構簡單,造價低,因此廣泛應用於電漿蝕刻(IC)、物理氣相沉積(PVD)、電漿化學氣相沉積(CVD)、微電子機械系統(MEMS)和發光二極體(LED)等製程中。 In the semiconductor manufacturing process, Inductive Coupled Plasma (ICP, Inductive Coupled Plasma) generators can obtain high-density plasma under a low working pressure, and the structure is simple and the cost is low, so it is widely used in plasma etching (IC ), physical vapor deposition (PVD), plasma chemical vapor deposition (CVD), micro-electromechanical system (MEMS) and light-emitting diode (LED) and other processes.
在進行製程的過程中,為了提高產品的品質,在實施沉積製程之前,首先要對晶片進行預清洗(Preclean),以去除晶片表面的氧化物等雜質。一般的預清洗腔室的基本原理是:將通入清洗腔室內的諸如氬氣、氦氣或氫氣等的清洗氣體激發形成電漿,對晶片進行化學反應和物理轟擊,從而可以去除晶片表面的雜質。 During the process, in order to improve the quality of the product, before performing the deposition process, the wafer must first be pre-cleaned (Preclean) to remove impurities such as oxides on the surface of the wafer. The basic principle of the general pre-cleaning chamber is to excite the cleaning gas, such as argon, helium or hydrogen, into the plasma to form a plasma, chemically react and physically bombard the wafer, so that the surface of the wafer can be removed. Impurities.
第1圖為現有的一種預清洗腔室的剖視圖。請參閱第1圖,預清洗腔室包括腔體1,在該腔體1的頂部設置有介電質襯筒2,且在該介電質襯筒2的周圍環繞設置有射頻線圈3,該射頻線圈3通過上匹配器4與上射頻電源5電連接,上射頻電源5用於向射頻線圈3載入射頻功率,由射頻線圈3產生的電磁場
能夠通過介電質襯筒2饋入至腔體1中,以激發腔體1中的製程氣體形成電漿。並且,在腔體1中還設置有基座6,用於承載晶片7。並且,基座6通過下匹配器8和下射頻電源9電連接,下射頻電源9用於向基座6載入射頻負偏壓,以吸引電漿蝕刻襯底表面。
Figure 1 is a cross-sectional view of a conventional pre-cleaning chamber. Please refer to FIG. 1, the pre-cleaning chamber includes a
如第2圖所示,上述射頻線圈3的輸入端用作功率饋入點與上匹配器4電連接,上述射頻線圈3的輸出端接地。這會存在以下問題:由於高頻的駐波效應,射頻線圈3的每一匝的電位分佈存在較大的差異,而且射頻線圈3的不同匝之間的電位也存在較大的差異,這種差異會造成由射頻線圈3產生的電磁場在反應腔室內分佈不均勻,從而造成電漿的分佈均勻性較低,進而影響製程均勻性。
As shown in FIG. 2, the input end of the above-mentioned
本發明旨在至少解決先前技術中存在的技術問題之一,提出了一種上電極元件及反應腔室,其可以減小線圈上存在的電位分佈差異,從而可以提高電漿的分佈均勻性,進而可以提高製程均勻性。 The present invention aims to solve at least one of the technical problems existing in the prior art, and proposes an upper electrode element and a reaction chamber, which can reduce the potential distribution difference existing on the coil, thereby improving the uniformity of the plasma distribution, and Can improve process uniformity.
為實現本發明的目的而提供一種上電極元件,包括線圈,該線圈中設置有n個功率饋入點,其中,n為大於等於1的整數;並且該線圈中設置有n+1個接地端點,該功率饋入點和該接地端點的排布關係遵循以下規律:對於每一該功率饋入點而言,沿線圈的纏繞方向在該功率饋入點的上游和下游分別設置有一個接地端點,該功率饋入點和其上游接地端點之間的線圈構成第一線圈分部,該功率饋入點和其下游接地端點之間的線圈構成第二線圈分部,該第一線圈分部和第二線圈分部並聯在該功率饋入點和地之間。 To achieve the object of the present invention, an upper electrode element is provided, including a coil, where n power feeding points are provided in the coil, where n is an integer greater than or equal to 1; and n+1 ground terminals are provided in the coil Point, the arrangement relationship between the power feeding point and the grounding end point follows the following rules: for each of the power feeding points, there are respectively one upstream and downstream of the power feeding point along the winding direction of the coil The ground terminal, the coil between the power feed point and its upstream ground terminal constitutes the first coil section, and the coil between the power feed point and its downstream ground terminal constitutes the second coil section, the first A coil section and a second coil section are connected in parallel between the power feed point and ground.
其中,該線圈為多匝柱狀螺旋立體線圈。 Among them, the coil is a multi-turn cylindrical spiral three-dimensional coil.
其中,對於每一該功率饋入點來說,該第一線圈分部和第二線圈分部二者其一的長度與二者之和的總長度的比值的取值範圍在0.5/5.5~2.5/5.5之間;進一步,該第一線圈分部和第二線圈分部二者其一的長度與二者之和的總長度的比值的取值範圍在0.7/5.5~1.5/5.5之間;更進一步地,該第一線圈分部和第二線圈分部二者其一的長度與二者之和的總長度的比值的取值範圍在0.9/5.5~1.1/5.5之間。例如,該第一線圈分部和第二線圈分部二者其一的長度與二者之和的總長度的比值為2.5/5.5、2.0/5.5、1.8/5.5、1.5/5.5、1.4/5.5、1.3/5.5、1.2/5.5、1.1/5.5、1.05/5.5、1.02/5.5、1/5.5、0.97/5.5、0.95/5.5、0.9/5.5、0.8/5.5、0.7/5.5、0.6/5.5或者0.5/5.5。 For each of the power feed points, the ratio of the length of one of the first coil section and the second coil section to the total length of the sum of the two ranges from 0.5/5.5 to Between 2.5/5.5; further, the ratio of the length of one of the first coil part and the second coil part to the total length of the sum of the two ranges from 0.7/5.5 to 1.5/5.5 Further, the ratio of the length of one of the first coil part and the second coil part to the total length of the sum of the two ranges from 0.9/5.5 to 1.1/5.5. For example, the ratio of the length of one of the first coil part and the second coil part to the total length of the sum of the two is 2.5/5.5, 2.0/5.5, 1.8/5.5, 1.5/5.5, 1.4/5.5 , 1.3/5.5, 1.2/5.5, 1.1/5.5, 1.05/5.5, 1.02/5.5, 1/5.5, 0.97/5.5, 0.95/5.5, 0.9/5.5, 0.8/5.5, 0.7/5.5, 0.6/5.5 or 0.5 /5.5.
其中,該線圈為單匝線圈。 Among them, the coil is a single-turn coil.
其中,對於每一該功率饋入點而言,其上游接地端點和下游接地端點中的至少一個通過阻抗配置裝置接地,通過設定不同的該阻抗配置裝置的阻抗大小,來使兩個該第一線圈分部和第二線圈分部的電流方向相同或相反。 For each of the power feeding points, at least one of the upstream ground terminal and the downstream ground terminal is grounded through the impedance configuration device, and by setting different impedance sizes of the impedance configuration device, the two The current directions of the first coil section and the second coil section are the same or opposite.
其中,該阻抗配置裝置包括可調電容,該可調電容的容值範圍為0~2000pF。 Wherein, the impedance configuration device includes an adjustable capacitor, and the capacitance of the adjustable capacitor ranges from 0 to 2000pF.
其中,該上電極元件還包括匹配器和功率源,該功率源經由該匹配器而與該功率饋入點電連接;並且,該阻抗配置裝置和該匹配器整合於同一個殼體中或者分別設置在不同的殼體中。 Wherein, the upper electrode element further includes a matching device and a power source, and the power source is electrically connected to the power feeding point via the matching device; and, the impedance configuration device and the matching device are integrated in the same housing or separately Set in different housings.
其中,該上電極元件還包括介電質襯筒,該線圈環繞該介電質襯筒而設置在該介電質襯筒的週邊。 Wherein, the upper electrode element further includes a dielectric liner barrel, and the coil is disposed around the dielectric liner barrel around the dielectric liner barrel.
作為另一個方面,本發明還提供一種反應腔室,其包括前述任意一方案所述的上電極元件,該上電極元件還包括介電質襯筒,該線圈環繞該介電質襯筒而設置在該介電質襯筒的週邊;該反應腔室還包括法拉第遮罩件,該法拉第遮罩件環繞設置在該介電質襯筒的內側,並且該法拉第遮罩件包括導電環體,在該導電環體上形成有開縫;該開縫包括第一子開縫,該第一子開縫沿該導電環體的圓周方向設置,且與該導電環體的軸線之間形成夾角,用以通過增加電磁場在該導電環體的圓周方向上的電場分量的耦合效率,來增加該電磁場的總耦合效率。 As another aspect, the present invention also provides a reaction chamber, which includes the upper electrode element according to any one of the foregoing solutions, the upper electrode element further includes a dielectric liner barrel, and the coil is disposed around the dielectric liner barrel At the periphery of the dielectric lining cylinder; the reaction chamber further includes a Faraday shield member disposed around the inside of the dielectric lining cylinder, and the Faraday shield member includes a conductive ring body, A slit is formed on the conductive ring body; the slit includes a first sub-slot, the first sub-slot is provided along the circumferential direction of the conductive ring body, and forms an angle with the axis of the conductive ring body, To increase the coupling efficiency of the electromagnetic field by increasing the coupling efficiency of the electric field component of the electromagnetic field in the circumferential direction of the conductive ring body.
其中,該法拉第遮罩件的上端面高於該介電質襯筒的上端面;該法拉第遮罩件的下端面低於該介電質襯筒的下端面。 Wherein, the upper end surface of the Faraday shield member is higher than the upper end surface of the dielectric liner cylinder; the lower end surface of the Faraday shield member is lower than the lower end surface of the dielectric liner cylinder.
其中,該反應腔室為預清洗腔室。 Wherein, the reaction chamber is a pre-cleaning chamber.
作為再一個方面,本發明還提供一種半導體加工裝置,其包括前述任意一方案所述的反應腔室。 As still another aspect, the present invention also provides a semiconductor processing apparatus including the reaction chamber described in any one of the foregoing solutions.
本發明具有以下有益效果: 本發明提供的上電極元件,其將功率饋入點設置在線圈的除端點之外的位置處,且該線圈的端點接地,以將線圈自該功率饋入點形成相互並聯的複數線圈分部,使得線圈的整體阻抗降低,相應地,線圈的整體電壓也降低,從而可以減小線圈上的電位分佈差異,提高電漿的分佈均勻性,進而提高製程均勻性。進一步地,在上電極元件包括介電質襯筒的情況下,由於線圈的整體電壓被降低,因而可以減少電漿中的離子對介電質襯筒的轟擊,從而減少了反應腔室內的顆粒污染。 The invention has the following beneficial effects: The upper electrode element provided by the invention has a power feeding point set at a position other than the end point of the coil, and the end point of the coil is grounded to form a plurality of parallel coils from the power feeding point The division reduces the overall impedance of the coil, and accordingly, the overall voltage of the coil also decreases, which can reduce the difference in the potential distribution on the coil, improve the uniformity of the plasma distribution, and thus improve the uniformity of the process. Further, in the case where the upper electrode element includes a dielectric liner barrel, since the overall voltage of the coil is reduced, the bombardment of the dielectric liner barrel by ions in the plasma can be reduced, thereby reducing particles in the reaction chamber Pollution.
本發明提供的反應腔室及半導體加工裝置,其通過採用本發明提供的上述上電極元件,可以提高電漿的分佈均勻性,從而可以提高製程均勻性。The reaction chamber and the semiconductor processing device provided by the present invention can improve the uniformity of plasma distribution by using the above-mentioned upper electrode element provided by the present invention, thereby improving the process uniformity.
為使本領域的技術人員更好地理解本發明的技術方案,下面結合附圖來對本發明提供的上電極元件、反應腔室及半導體加工裝置進行詳細描述。 In order to enable those skilled in the art to better understand the technical solution of the present invention, the upper electrode element, the reaction chamber and the semiconductor processing device provided by the present invention will be described in detail below with reference to the drawings.
請參閱第3A圖,本實施例提供的上電極元件包括線圈10,在該線圈10上設置有功率饋入點103,其位於線圈10的除端點(第一端101和第二端102)之外的位置處。並且,線圈10的端點接地,由此,上述線圈10自功率饋入點103形成相互並聯的複數線圈分部。射頻電源12通過匹配器11與上述功率饋入點103電連接,用於通過該功率饋入點103向線圈10載入射頻功率。
Please refer to FIG. 3A, the upper electrode element provided in this embodiment includes a
如第3B圖所示,在本實施例中,上電極元件還包括介電質襯筒22,線圈10上的射頻能量通過該介電質襯筒22饋入反應腔室中。該介電質襯筒22呈環狀結構,且線圈10為多匝柱狀螺旋立體線圈,並環繞在該介電質襯筒22周圍。在本實施例中,功率饋入點103為一個,且位於線圈10的除第一端101與第二端102之外的某一指定位置處,以使該線圈10自該功率饋入點103形成兩個線圈分部,具體為(參照第3A圖):第一線圈分部104和第二線圈分部105。其中,第一線圈分部104位於功率饋入點103的上方;第二線圈分部105位於功率饋入點103的下方。
As shown in FIG. 3B, in this embodiment, the upper electrode element further includes a
通過將線圈10分成相互並聯的兩個線圈分部,使得線圈10的整體阻抗降低,相應地,線圈10的整體電壓也降低,從而可以減小線圈上的電位分佈差異,例如,可以減小每線圈分部中的每匝上的電位分佈差異以及不同匝之間的電位差異,從而可以提高由線圈10產生的電磁場在反應腔室內的分佈均勻性,進而可以提高電漿的分佈均勻性,提高製程均勻性。進一步地,在上電極元件包括介電質襯筒22的情況下,由於線圈10的整體電壓被降低,因而可以減少電漿中的離子對介電質襯筒22的轟擊,從而減少反應腔室內的顆粒污染。By dividing the
在實際應用中,可以通過改變功率饋入點103在線圈10上的位置,來調節由線圈10產生的電磁場在反應腔室內的分佈情況。可以通過設定第二線圈分部105的不同長度,來改變功率饋入點103在線圈10上的位置,較佳的,線圈10的總匝數為5.5,而第二線圈分部105的長度(單位為匝)與線圈10的總長度(單位為匝)的比值的取值範圍在0.9/5.5~1.1/5.5之間。採用上述範圍內的比值,可以獲得較好的電磁場分佈均勻性。In practical applications, the distribution of the electromagnetic field generated by the
下面為採用先前技術中的線圈和本發明實施例中的線圈進行蝕刻製程,以及採用本發明實施例中的不同功率饋入點的位置的線圈進行蝕刻製程的對比試驗。在該對比試驗中,線圈10的總匝數為5.5。The following is a comparison test of the etching process using the coil in the prior art and the coil in the embodiment of the present invention, and the coil using different positions of the power feed point in the embodiment of the present invention. In this comparative test, the total number of turns of the
採用先前技術中的線圈進行蝕刻製程獲得的晶片蝕刻深度分佈如第4A圖所示,在晶片表面上,蝕刻深度等高線呈梯度式偏心分佈,從而蝕刻均勻性較低,一般為3%左右,沒有達到製程要求(2%)。另外,蝕刻深度等高線呈梯度式偏心分佈可能會引起晶片表面損傷的問題。The etching depth distribution of the wafer obtained by the etching process of the coil in the prior art is shown in FIG. 4A. On the wafer surface, the contour of the etching depth is distributed in a gradient eccentricity, so that the etching uniformity is low, generally about 3%, no Meet the process requirements (2%). In addition, the etched depth contours are distributed in a gradient eccentricity, which may cause wafer surface damage.
採用本發明實施例中的線圈10,且使第二線圈分部105的長度與線圈10的總長度的比值為1.15/5.5,採用該功率饋入點103位置的線圈10進行蝕刻製程獲得的晶片蝕刻深度分佈如第4B圖所示,蝕刻深度等高線仍然呈梯度式偏心分佈,蝕刻均勻性較低,而且可能會引起晶片表面損傷的問題。The
採用本發明實施例中的線圈10,且使第二線圈分部105的長度與線圈10的總長度的比值為1.1/5.5或1.05/5.5,採用這兩種該功率饋入點103位置的線圈10進行蝕刻製程獲得的晶片蝕刻深度分佈如第4C圖和第4D圖所示,蝕刻深度等高線趨於同心分佈,蝕刻均勻性有所提高(可達到2%),從而可以滿足製程要求,而且可以避免晶片表面損傷。The
採用本發明實施例中的線圈10,且使第二線圈分部105的長度與線圈10的總長度的比值為1/5.5,採用這該功率饋入點103位置的線圈10進行蝕刻製程獲得的晶片蝕刻深度分佈如第4E圖所示,蝕刻深度等高線的同心分佈情況優於第4C圖和第4D圖所示。The
另外,在本實施例中,如第3A圖所示,線圈10的第一端101通過阻抗配置裝置13接地,而第二端102直接接地。通過設定阻抗配置裝置13的阻抗大小,來使第一線圈分部104和第二線圈分部105的電流方向相同或相反。具體來說,第一線圈分部104的下端接地,上端為功率饋入點103,由此第一線圈分部104中的電流自功率饋入點103向接地的下端流動。若使阻抗配置裝置13的阻抗足夠大,則第二線圈分部105中的電流自第二線圈分部105的連接阻抗配置裝置13的上端(即第一端101)朝向功率饋入點103流動,由此,第一線圈分部104和第二線圈分部105的電流方向相同。反之,若使阻抗配置裝置13的阻抗足夠小,則第二線圈分部105中的電流自功率饋入點103朝向第二線圈分部105的與阻抗配置裝置13連接的上端流動,由此,第一線圈分部104和第二線圈分部105的電流方向相反。因此,通過設定阻抗配置裝置13的阻抗大小,例如,使之足夠大或者足夠小,能夠改變第二線圈分部105中的電流方向。In addition, in this embodiment, as shown in FIG. 3A, the
若第一線圈分部104和第二線圈分部105的電流方向相反,則分別由第一線圈分部104和第二線圈分部105產生的兩個電磁場相互抵消,這會對在二者之間存在的磁場強度差異進行補償,從而進一步提高了由上述兩個電磁場形成的疊加磁場的分佈均勻性。但是,上述兩個電磁場的相互抵消會減小疊加磁場的磁場強度,從而減小了電漿密度,因此,該方式適用於對電漿密度要求不高的製程。而對於對電漿密度要求較高的製程,則可以使第一線圈分部104和第二線圈分部105的電流方向相同,以提高電漿密度。
If the current directions of the
上述阻抗配置裝置13可以包括可調電容。在進行製程之前,可以根據具體需要設置可調電容的大小,以獲得所需的阻抗值,從而提高了阻抗調節的靈活性。上述可調電容的可調範圍在0~2000pF,例如,0pF,20pF,50pF,100pF,200pF,300pF,500pF,800pF,900pF,1000pF,1200pF,1500pF,2000pF等。
The
另外,上述阻抗配置裝置13在起到決定電流方向的基礎上,還可以通過選擇合適的阻抗大小,來使匹配器11更容易實現阻抗匹配。例如,當線圈10的總匝數為5.5,第二線圈分部105的長度與線圈10的總長度的比值為1.1/5.5、1.05/5.5或者1/5.5時,上述可調電容的電容值可以在200~500pF的範圍內設定,200pF,250pF,300pF,350pF,400pF,450pF,500pF等,較佳為350pF。
In addition, the above-mentioned
在實際應用中,上述阻抗配置裝置13和匹配器11可以整合於同一個殼體,也可以分別設置在不同的殼體中。可以理解,二者整合在同一個殼體中,可以減小裝置的佔用空間。
In practical applications, the
需要說明的是,在本實施例中,線圈10的第一端101通過阻抗配置裝置13接地,而第二端102直接接地,但是本發明並不侷限於此,在實際應用中,也可以使線圈10的第一端101直接接地,而第二端102通過阻抗配置裝置13接地;或者,也可以分別為線圈10的第一端101和第二端102配置阻抗配置裝置13,且使阻抗配置裝置13接地;或者,還可以使線圈10的第一端101和第二端102均直接接地。
It should be noted that, in this embodiment, the
還需要說明的是,在本實施例中,線圈10為多匝柱狀螺旋立體線圈,即,該線圈10以螺旋線方式沿軸線方向延伸形成輪廓為柱體的立體結構,但是,本發明並不侷限於此,在實際應用中,線圈10也可以為單匝線圈。無論是單匝線圈還是多匝線圈,構成該線圈的導線沿垂直於該導線的軸向的方向進行剖切所得到的截面的形狀不受限制,例如,為梯形、矩形、正方形、圓形、橢圓形等。
It should also be noted that in this embodiment, the
進一步需要說明的是,在本實施例中,功率饋入點的數量為一個,但是本發明並不侷限於此,在實際應用中,功率饋入點的數量還可以為複數,且不同的功率饋入點位於線圈的除端點之外的不同位置,並且在相鄰的兩個功率饋入點之間設置有接地端點,即,在該線圈上,對應於每一功率饋入點,在其上游端和下游端均設置有接地端點,使得對於每一功率饋入點均設置有並聯在該功率饋入點和地之間的兩個線圈分部,這樣,在該線圈中,線圈分部的數量為功率饋入點數量的兩倍。例如,功率饋入點103為n個,線圈分部的數量為2n個,接地端點的數量為n+1個,其中,n為大於等於1的整數。功率饋入點和接地端點的排布關係遵循以下規律:對於每一功率饋入點而言,沿線圈的纏繞方向在該功率饋入點的上游和下游分別設置有一個接地端 點,該功率饋入點和其上游接地端點之間的線圈構成對應於該功率饋入點的第一線圈分部,該功率饋入點和其下游接地端點之間的線圈構成對應於該功率饋入點的第二線圈分部,該第一線圈分部和第二線圈分部並聯在該功率饋入點和地之間。 It should be further noted that, in this embodiment, the number of power feed points is one, but the present invention is not limited to this. In practical applications, the number of power feed points may also be a complex number, and different power The feeding point is located at a different position except the end point of the coil, and a grounding end point is provided between two adjacent power feeding points, that is, on the coil, corresponding to each power feeding point, The upstream end and the downstream end are provided with grounding end points, so that for each power feeding point, two coil sections connected in parallel between the power feeding point and ground are provided, so that in the coil, The number of coil sections is twice the number of power feed points. For example, there are n power feed points 103, the number of coil sections is 2n, and the number of ground terminals is n+1, where n is an integer greater than or equal to 1. The arrangement relationship between the power feeding point and the grounding terminal follows the following rules: For each power feeding point, a grounding terminal is provided upstream and downstream of the power feeding point along the winding direction of the coil Point, the coil between the power feed point and its upstream ground terminal constitutes the first coil section corresponding to the power feed point, and the coil configuration between the power feed point and its downstream ground terminal corresponds to The second coil part of the power feed point, the first coil part and the second coil part are connected in parallel between the power feed point and ground.
例如第5圖就示出了具有兩個功率饋入點的一種上電極元件的結構圖。如第5圖所示,本實施例提供的上電極元件包括線圈10,在該線圈10上設置有第一功率饋入點1031和第二功率饋入點1032,其位於線圈10的除上端點101和下端點1022之外的位置處,且上端點101定義為第一端點,下端點1022定義為第二端點,線圈10的纏繞方向為自上向下。其中,第一射頻電源121通過第一匹配器111與第一功率饋入點1031電連接,第二射頻電源122通過第二匹配器112與第二功率饋入點1032電連接,用於通過第一功率饋入點1031和第二功率饋入點1032向線圈10載入射頻功率。對應於第一功率饋入點1031,沿該線圈10的纏繞方向在第一功率饋入點1031的上游和下游分別設置有接地端點101和1021,該功率饋入點1031和其上游接地端點101之間的那一段線圈構成第一線圈分部,該功率饋入點1031和其下游接地端點1021之間的那一段線圈構成第二線圈分部,該第一線圈分部和第二線圈分部並聯在該功率饋入點1031和地之間。對應於第二功率饋入點1032,沿該線圈10的纏繞方向在第二功率饋入點1032的上游和下游分別設置有接地端點1021和1022,該功率饋入點1032和其上游接地端點1021之間的那一段線圈構成第一線圈分部,該功率饋入點1032和其下游接地端點1022之間的那一段線圈構成第二線圈分部,該第一線圈分部和第二線圈分部並聯在該功率饋入點1032和地之間。
For example, FIG. 5 shows a structural diagram of an upper electrode element with two power feed points. As shown in FIG. 5, the upper electrode element provided in this embodiment includes a
在第5圖所示的上電極元件中,每一功率饋入點及其所對應的兩個接地端點、第一線圈分部和第二線圈分部以及相應的阻抗配置裝置構成一個上電極單元元件,每一上電極單元元件均類同於前面結合第3A圖和第3B圖所描述的實施例中的上電極元件,各上電極單元元件的結構、配置、參數選擇及由此帶來的相應效果均類似於前述第3A圖至第4E圖所示實施例,例如,每一功率饋入點所對應的第一線圈分部和第二線圈分部的匝數關係所產生的效果類似於前述第3A圖至第4E圖所示實施例,即,對於每一功率饋入點來說,第一線圈分部和第二線圈分部二者其一的長度與二者之和的總長度的比值的取值範圍較佳在0.5/5.5~2.5/5.5之間。進一步較佳地,第一線圈分部和第二線圈分部二者其一的長度與二者之和的總長度的比值的取值範圍可在0.7/5.5~1.5/5.5之間。進一步較佳地,第一線圈分部和第二線圈分部二者其一的長度與二者之和的總長度的比值的取值範圍可在0.9/5.5~1.1/5.5之間。例如,可以將第一線圈分部和第二線圈分部二者其一的長度與二者之和的總長度的比值設定為2.5/5.5、2.0/5.5、1.8/5.5、1.5/5.5、1.4/5.5、1.3/5.5、1.2/5.5、1.1/5.5、1.05/5.5、1.02/5.5、1/5.5、0.97/5.5、0.95/5.5、0.9/5.5、0.8/5.5、0.7/5.5、0.6/5.5或者0.5/5.5,以獲得較好的電磁場分佈均勻性。 In the upper electrode element shown in FIG. 5, each power feed point and its corresponding two grounding terminals, the first coil section and the second coil section, and the corresponding impedance configuration device form an upper electrode Unit element, each upper electrode unit element is similar to the upper electrode element in the embodiment described above in connection with FIGS. 3A and 3B, the structure, configuration, parameter selection of each upper electrode unit element and the resulting The corresponding effects are similar to the embodiments shown in the foregoing FIGS. 3A to 4E, for example, the effect of the turns relationship between the first coil section and the second coil section corresponding to each power feed point is similar In the foregoing embodiments shown in FIGS. 3A to 4E, that is, for each power feed point, the length of one of the first coil section and the second coil section and the total length of the sum of the two The range of the ratio of degrees is preferably between 0.5/5.5 to 2.5/5.5. Further preferably, the ratio of the length of one of the first coil part and the second coil part to the total length of the sum of the two can range from 0.7/5.5 to 1.5/5.5. Further preferably, the ratio of the length of one of the first coil part and the second coil part to the total length of the sum of the two can be in the range of 0.9/5.5 to 1.1/5.5. For example, the ratio of the length of one of the first coil section and the second coil section to the total length of the sum of the two can be set to 2.5/5.5, 2.0/5.5, 1.8/5.5, 1.5/5.5, 1.4 /5.5, 1.3/5.5, 1.2/5.5, 1.1/5.5, 1.05/5.5, 1.02/5.5, 1/5.5, 0.97/5.5, 0.95/5.5, 0.9/5.5, 0.8/5.5, 0.7/5.5, 0.6/5.5 Or 0.5/5.5 to get better uniformity of electromagnetic field distribution.
可以理解的是,當功率饋入點的數量為兩個以上時,相鄰兩個功率饋入點之間設置有一個接地端點,即,這兩個功率饋入點共用一個接地端點。事實上,在兩個功率饋入點之間可以設置複數接地端子,由於這些接地端子等電位,因此將這些接地端子視為一個接地端點。對於線圈端點附近的接地端點,也做上述理解,在此不再贅述。 It can be understood that when the number of power feeding points is more than two, a ground terminal is provided between two adjacent power feeding points, that is, the two power feeding points share a ground terminal. In fact, a plurality of ground terminals can be provided between the two power feed points. Since these ground terminals have the same potential, these ground terminals are regarded as one ground terminal. The above-mentioned understanding is also made for the grounding terminal near the coil terminal, and will not be repeated here.
進一步可以理解的是,線圈被分割為2倍於功率饋入點數量的線圈分部,這樣,線圈的整體電壓降低,從而可以減小線圈上的電位分佈差異,並且更加細化地調節該線圈產生的電磁場在反應腔室內的分佈均勻性,從而可以進一步提高電漿的分佈均勻性。另外,對於複數功率饋入點,每功率饋入點需要配備一套匹配器和射頻電源。 It can be further understood that the coil is divided into coil sections that are twice the number of power feed points. In this way, the overall voltage of the coil is reduced, which can reduce the difference in the potential distribution on the coil and adjust the coil more finely. The distribution uniformity of the generated electromagnetic field in the reaction chamber can further improve the distribution uniformity of the plasma. In addition, for complex power feed points, each power feed point needs to be equipped with a set of matching devices and RF power supply.
此外,還需要說明的是,儘管前述實施例中以包含有介電質襯筒的上電極元件對本發明進行了詳細說明,但是本發明並不侷限於此。在實際應用中,在不影響製程品質的情況下,也可以不設置用來將線圈上的射頻能量饋入反應腔室中的介電質襯筒,而是將線圈直接設置在反應腔室內,例如,在線圈為消耗型線圈(線圈本身即為濺鍍靶材,或者線圈的材質與濺鍍靶材一致)的情況下。 In addition, it should be noted that although the foregoing embodiments have described the present invention in detail with the upper electrode element including the dielectric liner, the present invention is not limited to this. In practical applications, without affecting the quality of the process, the dielectric liner used to feed the RF energy from the coil into the reaction chamber may not be provided, but the coil is directly placed in the reaction chamber. For example, when the coil is a consumable coil (the coil itself is a sputtering target, or the material of the coil is the same as the sputtering target).
作為另一個技術方案,如第6圖所示,本發明還提供一種反應腔室21,其包括本發明上述實施例提供的上電極元件。該上電極元件包括介電質襯筒22和環繞在該介電質襯筒22周圍的線圈10,其中,介電質襯筒22設置在反應腔室21的側壁211中;射頻電源12通過匹配器11與線圈10上的上述功率饋入點103電連接,用於通過該功率饋入點103向線圈10載入射頻功率。射頻能量通過介電質襯筒22饋入反應腔室21中。並且,在反應腔室21中還設置有基座24,該基座24通過基座匹配器25與基座射頻電源26電連接,基座射頻電源26用於向基座24載入負偏壓,以吸引電漿蝕刻晶片表面。
As another technical solution, as shown in FIG. 6, the present invention further provides a
在本實施例中,反應腔室21還包括法拉第遮罩件23,該法拉第遮罩件23環繞設置在介電質襯筒22的內側,用於保護介電質襯筒22不被電漿蝕刻,同時避免自晶片表面濺鍍出來的殘留物附著在介電質襯筒22的內壁
上,從而可以提高介電質襯筒22的能量耦合效率,減少反應腔室21內的顆粒污染。並且,法拉第遮罩件23包括導電環體,在該導電環體上形成有開縫,以避免法拉第遮罩件23產生渦流損耗和發熱。
In this embodiment, the
借助上述法拉第遮罩件23的電磁遮罩效應,可以進一步減小線圈10中存在的電位差異,而且可以對電磁場的分佈產生二次分佈影響,從而可以進一步提高電漿的分佈均勻性,提高製程均勻性。另外,借助法拉第遮罩件23的物理阻擋作用,可以有效防止金屬沉積在介電質襯筒22的內壁上,從而可以避免磁場耦合效率降低。
With the help of the electromagnetic shielding effect of the
在本實施例中,如第7圖所示,上述開縫包括第一子開縫232和第二子開縫231,其中,第一子開縫232沿上述導電環體的圓周方向設置,且與該導電環體的軸線之間形成夾角,用以通過增加電磁場在導電環體的圓周方向上的電場分量的耦合效率,來增加該電磁場的總耦合效率。該第一子開縫232與該導電環體的軸線之間所形成的夾角為90°。上述第一子開縫232為複數,且沿上述導電環體的圓周方向均勻分佈。第二子開縫231沿導電環體的軸向設置,且該第二子開縫231為複數,且沿上述導電環體的圓周方向均勻分佈。
In this embodiment, as shown in FIG. 7, the above-mentioned slit includes a
由線圈10產生的電磁場可以劃分為導電環體的軸向上的磁場分量和導電環體的圓周方向上的電場分量。導電環體的軸向上的磁場分量能夠通過上述第二子開縫231饋入反應腔室21內,同時,導電環體的圓周方向上的電場分量通過上述第一子開縫232饋入反應腔室21內,從而增加了電磁場的總耦合效率。The electromagnetic field generated by the
需要說明的是,在實際應用中,也可以僅設置上述第一子開縫232,且該第一子開縫232相對於導電環體的軸線傾斜,較佳的,第一子開縫232與導電環體的軸線之間形成夾角較佳為45°。這樣,導電環體的軸向上的磁場分量在該第一子開縫232的傾斜方向上的子分量能夠通過第一子開縫232饋入反應腔室21內,同時導電環體的圓周方向上的電場分量在該第一子開縫232的傾斜方向上的子分量能夠通過第一子開縫232饋入反應腔室21內。It should be noted that in practical applications, only the
在實際應用中,上述法拉第遮罩件23可以接地,或者也可以電位懸浮。並且,法拉第遮罩件23可以為單層的筒狀結構;也可以為兩個直徑不同的筒狀結構嵌套在一起而形成的2層或更多層的筒狀結構。In practical applications, the
較佳的,法拉第遮罩件23的上端面高於介電質襯筒22的上端面;法拉第遮罩件23的下端面低於介電質襯筒22的下端面,以保證法拉第遮罩件23完全覆蓋介電質襯筒22的內表面。另外,可以在法拉第遮罩件23的內表面做熔射等的粗化處理,以防止附著在法拉第遮罩件23的內表面上的顆粒脫落,污染晶片表面。Preferably, the upper end surface of the
在實際應用中,反應腔室可以為預清洗腔室。In practical applications, the reaction chamber may be a pre-cleaning chamber.
較佳的,對於含氫的預清洗製程,預清洗腔室中的上射頻電源28可以採用較低的頻率(13.56MHz以下),例如2MHz,這可以使氫原子的激發和離化程度減緩,從而減少氫原子與晶片表面反應釋放出的熱量,從而可以實現低溫預清洗製程。Preferably, for the hydrogen-containing pre-cleaning process, the upper RF power supply 28 in the pre-cleaning chamber may use a lower frequency (below 13.56 MHz), such as 2 MHz, which may slow down the excitation and ionization of hydrogen atoms. Thereby reducing the heat released by the reaction of hydrogen atoms with the surface of the wafer, so that a low temperature pre-cleaning process can be realized.
綜上所述,本發明實施例提供的反應腔室,其通過採用本發明上述實施例提供的上電極元件,可以提高電漿的分佈均勻性,從而可以提高製程均勻性。In summary, the reaction chamber provided by the embodiment of the present invention can improve the uniformity of plasma distribution by using the upper electrode element provided by the above embodiment of the present invention, thereby improving the process uniformity.
作為再一個技術方案,本發明還提供一種半導體加工裝置,其包括前述實施例所述的反應腔室。本發明提供的半導體加工裝置通過採用本發明提供的上述反應腔室,可以提高電漿的分佈均勻性,從而可以提高製程均勻性。As still another technical solution, the present invention also provides a semiconductor processing apparatus, which includes the reaction chamber described in the foregoing embodiments. The semiconductor processing device provided by the present invention can improve the uniformity of plasma distribution by using the above-mentioned reaction chamber provided by the present invention, thereby improving the uniformity of the process.
可以理解的是,以上實施方式僅僅是為了說明本發明的原理而採用的範例性實施方式,然而本發明並不侷限於此。對於本領域內的普通技術人員而言,在不脫離本發明的精神和實質的情況下,可以做出各種變型和改進,這些變型和改進也視為本發明的保護範圍。It can be understood that the above embodiments are merely exemplary embodiments adopted for explaining the principle of the present invention, but the present invention is not limited thereto. For those of ordinary skill in the art, various variations and improvements can be made without departing from the spirit and essence of the present invention, and these variations and improvements are also considered to be within the protection scope of the present invention.
1‧‧‧腔體2、22‧‧‧介電質襯筒3‧‧‧射頻線圈4‧‧‧上匹配器5‧‧‧上射頻電源6‧‧‧基座7‧‧‧晶片8‧‧‧下匹配器9‧‧‧下射頻電源10‧‧‧線圈11‧‧‧匹配器12‧‧‧射頻電源13‧‧‧阻抗配置裝置21‧‧‧反應腔室23‧‧‧法拉第遮罩件24‧‧‧基座25‧‧‧基座匹配器26‧‧‧基座射頻電源101‧‧‧第一端、上端點102‧‧‧第二端103‧‧‧功率饋入點104‧‧‧第一線圈分部105‧‧‧第二線圈分部111‧‧‧第一匹配器112‧‧‧第二匹配器122‧‧‧第二射頻電源121‧‧‧第一射頻電源211‧‧‧側壁231‧‧‧第二子開縫232‧‧‧第一子開縫1021‧‧‧接地端點1022‧‧‧下端點1031‧‧‧第一功率饋入點1032‧‧‧第二功率饋入點1‧‧‧
第1圖為現有的一種預清洗腔室的剖視圖;第2圖為射頻線圈的功率饋入點的位置示意圖;第3A圖為本發明實施例提供的上電極元件的一種結構圖;第3B圖為本發明實施例提供的上電極元件的另一種結構圖;第4A圖為採用先前技術中的線圈進行蝕刻製程獲得的晶片蝕刻深度分佈圖;第4B圖為採用本發明實施例中的一種線圈進行蝕刻製程獲得的晶片蝕刻深度分佈圖;第4C圖為採用本發明實施例中的另一種線圈進行蝕刻製程獲得的晶片蝕刻深度分佈圖;第4D圖為採用本發明實施例中的又一種線圈進行蝕刻製程獲得的晶片蝕刻深度分佈圖;第4E圖為採用本發明實施例中的再一種線圈進行蝕刻製程獲得的晶片蝕刻深度分佈圖;第5圖為本發明實施例提供的具有兩個功率饋入點的上電極元件的結構圖;第6圖為本發明實施例提供的反應腔室的剖視圖;第7圖為本發明實施例採用的法拉第遮罩件的結構圖。Figure 1 is a cross-sectional view of a conventional pre-cleaning chamber; Figure 2 is a schematic diagram of the position of a power feeding point of a radio frequency coil; Figure 3A is a structural diagram of an upper electrode element provided by an embodiment of the present invention; Figure 3B It is another structural diagram of the upper electrode element provided by the embodiment of the present invention; FIG. 4A is a wafer etching depth profile obtained by using the coil in the prior art for the etching process; FIG. 4B is a coil using the embodiment of the present invention The etching depth distribution diagram of the wafer obtained by performing the etching process; FIG. 4C is the etching depth distribution diagram of the wafer obtained by performing the etching process with another coil in the embodiment of the present invention; FIG. 4D is the adoption of yet another coil in the embodiment of the present invention The etching depth profile of the wafer obtained by performing the etching process; FIG. 4E is the etching depth profile of the wafer obtained by using another coil in the embodiment of the present invention for the etching process; FIG. 5 is the embodiment of the present invention with two powers FIG. 6 is a cross-sectional view of a reaction chamber provided by an embodiment of the present invention; FIG. 7 is a structural diagram of a Faraday shield used in an embodiment of the present invention.
10‧‧‧線圈 10‧‧‧coil
11‧‧‧匹配器 11‧‧‧ Matcher
12‧‧‧射頻電源 12‧‧‧RF power supply
13‧‧‧阻抗配置裝置 13‧‧‧Impedance configuration device
101‧‧‧第一端 101‧‧‧First
102‧‧‧第二端 102‧‧‧The second end
103‧‧‧功率饋入點 103‧‧‧Power feeding point
104‧‧‧第一線圈分部 104‧‧‧ First Coil Division
105‧‧‧第二線圈分部 105‧‧‧Second Coil Division
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