TWI680331B - Electronic device - Google Patents

Abstract

An electronic device includes a pixel array substrate, at least one printed circuit board, and at least one pair of connection elements. The pixel array substrate has an external pad group and an internal pad group. The printed circuit board has a first pad group and a second pad group. The pair of connection elements includes a first connection element and a second connection element partially overlapping the first connection element. Both ends of the first connection element are respectively engaged with the first external pad group and the first solder pad group of the first printed circuit board. The two ends of the second connecting element are respectively engaged with the first internal pad group and the second solder pad group of the printed circuit board.

Description

Electronic device

The present invention relates to an electronic device, and more particularly, to an electronic device including at least one pair of connection elements.

Based on the high contrast, high brightness, high color saturation, and wide viewing angle of the existing flat panel displays, Ultra High Definition (UHD) flat panel displays have risen rapidly. Under the premise that the picture quality of a flat display needs to be improved to an ultra-high resolution, the number of pads provided on the periphery of the flat display and the number of output pins of the connecting elements used to connect with the pads of the flat display are bound to increase, so that the bonding Yield drops. In addition, the area of the periphery of the flat display is limited. In order to provide a large number of pads in the limited area, the pads of the flat display need to be arranged in an outer row and an inner row. In order to engage with the outer pads and the inner pads of a flat display, in general, a single connection element has outer pads and inner pads corresponding to the outer pads and the inner pads of the flat display, respectively. A double-layer circuit that is electrically connected to the outer row pins and the inner row pins. However, the high selling price of such connecting elements leads to excessive cost of the flat display.

The invention provides an electronic device with high bonding yield and low cost.

The electronic device of the present invention includes a substrate, a plurality of first signal lines, a plurality of pixel structures, a first external pad group, a first internal pad group, a first printed circuit board, and a first pair of connection elements. The substrate has a first side, a second side opposite to the first side, and a third side connected to the first side and the second side. A plurality of first signal lines are disposed on the substrate. The plurality of pixel structures are electrically connected to the plurality of first signal lines. The first external pad group is disposed on the substrate. The first external pad group includes a plurality of first external pads, which are arranged between the first side edge of the substrate and the second side edge of the substrate and a plurality of first signals. Electrical connection. The first internal pad group is disposed on the substrate, wherein the first external pad group is closer to the third side than the first internal pad group, and the first internal pad group includes a plurality of first internal pads, which are arranged on the first side of the substrate. One side is electrically connected to the second side of the substrate and is partially connected to a plurality of first signal lines. The first printed circuit board has a first pad group and a second pad group. The first pair of connection elements includes a first connection element and a second connection element partially overlapping the first connection element, wherein two ends of the first connection element of the first pair of connection elements are respectively engaged with the first external pad group and the first printed circuit. The first pad group of the board, and the two ends of the second connection element of the first pair of connection elements are respectively engaged with the first internal pad group and the second pad group of the first printed circuit board.

Based on the above, an electronic device according to an embodiment of the present invention has a high bonding yield and low cost.

In order to make the above features and advantages of the present invention more comprehensible, embodiments are hereinafter described in detail with reference to the accompanying drawings.

In the drawings, the thicknesses of layers, films, panels, regions, etc. are exaggerated for clarity. Throughout the description, the same reference numerals denote the same elements. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "connected to" another element, it can be directly on or connected to the other element, or Intermediate elements may also be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element, there are no intervening elements present. As used herein, "connected" may refer to a physical and / or electrical connection. Furthermore, "electrically connected" or "coupled" can mean that there are other components between the two components.

As used herein, "about," "approximately," or "substantially" includes the stated value and an average value within an acceptable deviation range of a particular value determined by one of ordinary skill in the art, taking into account the measurements and A specific number of measurement-related errors (ie, limitations of the measurement system). For example, "about" can mean within one or more standard deviations of the stated value, or within ± 30%, ± 20%, ± 10%, ± 5%. Furthermore, the terms "about", "approximately" or "substantially" used herein may select a more acceptable range of deviations or standard deviations based on optical properties, etching properties, or other properties, and all properties can be applied without one standard deviation. .

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted to have meanings consistent with their meanings in the context of the related art and the present invention, and will not be interpreted as idealized or excessive Formal meaning unless explicitly defined as such in this article.

Exemplary embodiments are described herein with reference to cross-sectional views that are schematic views of idealized embodiments. Accordingly, variations in the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Therefore, the embodiments described herein should not be construed as limited to the specific shape of the area as shown herein, but include shape deviations caused by, for example, manufacturing. For example, a region shown or described as flat may generally have rough and / or non-linear characteristics. Furthermore, the acute angles shown may be round. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the precise shape of a region and are not intended to limit the scope of the claims.

Reference will now be made in detail to the exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.

FIG. 1 is a schematic perspective view of an electronic device according to an embodiment of the present invention. FIG. 2 is an enlarged schematic diagram of a region I in FIG. 1. FIG. 3 is an enlarged schematic view of a region II in FIG. 1. FIG. 4 is an enlarged schematic view of a region III in FIG. 1.

Referring to FIG. 1, the electronic device 10 includes a pixel array substrate AR. In this embodiment, the pixel array substrate AR includes a substrate 11, a plurality of first signal lines SL1, a plurality of second signal lines SL2, and a plurality of pixel structures PX. The substrate 11 includes a first side edge 11a, a second side edge 11b opposite to the first side edge 11a, and a third side edge 11c connected to the first side edge 11a and the second side edge 11b. A plurality of first signal lines SL1 are disposed on the substrate 11 and are arranged between the first side edge 11a and the second side edge 11b along the first direction D1. A plurality of second signal lines SL2 are disposed on the substrate 11 and are arranged between the third side edge 11c and the fourth side edge (not shown) of the substrate 11 along the second direction D2. In this embodiment, the first signal line SL1 extends along the second direction D2, and the second signal line SL2 extends along the first direction D1, wherein the first direction D1 and the second direction D2 are staggered. For example, in this embodiment, the first direction D1 and the second direction D2 may be selectively perpendicular, but the present invention is not limited thereto.

Please refer to FIGS. 1 and 2. In this embodiment, the pixel structure PX may include an active element T and a pixel electrode PE. The active device T is, for example, a thin film transistor, and has a source (not labeled), a drain (not labeled), and a gate (not labeled). The source of the active device T is electrically connected to the corresponding first signal line SL1. The first signal line SL1 is, for example, a data line. The gate of the active device T is electrically connected to the corresponding second signal line SL2. The second signal line SL2 is, for example, a scan line. The drain of the active device T is electrically connected to the corresponding pixel electrode PE.

In this embodiment, based on considerations of electrical conductivity, the materials of the gate, source, drain, first signal line SL1 and second signal line SL2 of the active device T are generally metal materials. However, the present invention is not limited to this. According to other embodiments, the gate, source, drain, first signal line SL1 and second signal line SL2 of the active device T may also use other conductive materials, such as alloys. , Nitrides of metal materials, oxides of metal materials, oxynitrides of metal materials, or other suitable materials, or stacked layers of metal materials and other conductive materials. In this embodiment, the pixel electrode PE may be a penetrating electrode, and the material of the penetrating electrode includes a metal oxide, for example, indium tin oxide, indium zinc oxide, aluminum tin oxide, and aluminum. Zinc oxide, or other suitable oxides, or a stacked layer of at least two of the foregoing. However, the present invention is not limited to this. According to other embodiments, the pixel electrode PE may be a reflective electrode, or a combination of a reflective electrode and a transmissive electrode.

Please refer to FIGS. 1, 2 and 3. In this embodiment, the pixel array substrate AR may optionally further include a first driving circuit GDC1 and a second driving circuit GDC2. The first driving circuit GDC1 is disposed adjacent to the first side edge 11a on the substrate 11 and is electrically connected to at least a part of the plurality of second signal lines SL2. The second driving circuit GDC2 is disposed adjacent to the second side edge 11b on the substrate 11 and is electrically connected to at least a part of the plurality of second signal lines SL2. For example, in this embodiment, the first driving circuit GDC1 and the second driving circuit GDC2 are, for example, an integrated gate driver on array (GOA); that is, an active element of the first driving circuit GDC1 ( (Not shown) and an active element (not shown) of the second driving circuit GDC2 are manufactured together with the active element T of the pixel structure PX, but the invention is not limited thereto.

Referring to FIG. 1, the pixel array substrate AR includes a plurality of external pad groups 110-1, 110-2, and 110-3 and a plurality of internal pad groups 120-1, 120-2, and 120-3, which are disposed on the substrate 11. on. Each external pad group 110-1, 110-2, or 110-3 corresponds to an internal pad group 120-1, 120-2, or 120-3. The corresponding external pad group 110-1, 110-2, or 110-3 and the internal pad group 120-1, 120-2, or 120-3 are adjacent to each other, and are arranged in the second direction D2. The pad group 110-1, 110-2, or 110-3 is closer to the third side 11c of the substrate 11 than the corresponding one of the internal pad groups 120-1, 120-2, or 120-3; that is, the outer pad group 110 -1, 110-2, or 110-3 is disposed between the third side 11c and the inner pad group 120-1, 120-2, or 120-3.

Please refer to FIGS. 1 to 4. Each external pad group 110-1, 110-2, or 110-3 includes a plurality of external pads 112 (labeled in FIGS. 2 to 4), which are arranged along the first direction D1 on the substrate 11. Between the first side edge 11 a and the second side edge 11 b of the substrate 11. In this embodiment, the external pad 112 is electrically connected to a part of the plurality of first signal lines SL1. Each of the interconnection pad groups 120-1, 120-2, or 120-3 includes a plurality of interconnection pads 122, 124, and 126 (labeled in FIGS. 2 to 4), which are arranged along the first direction D1 on the first portion of the substrate 11. Between one side edge 11 a and the second side edge 11 b of the substrate 11. The plurality of interconnection pads 122, 124, 126 of each interconnection pad group 120-1, 120-2, or 120-3 includes a plurality of first interconnection pads 122, and the other portions of the plurality of first signal lines SL1 are electrically connected. Sexual connection.

Please refer to FIGS. 2 to 4. In this embodiment, multiple external pads 112 of one external pad group 110-1, 110-2, or 110-3 may correspond to one internal pad group 120-1, 120 Alignment pads 122, 124, 126 of -2 or part of 120-3 are aligned. For example, in this embodiment, a plurality of external pads 112 of an external pad group 110-1, 110-2, or 110-3 and a corresponding internal pad group 120-1, 120-2, or 120- A plurality of 3 first interconnect pads 122 may be selectively aligned in the second direction D2. However, the present invention is not limited to this. According to other embodiments, a plurality of external pads 112 of one external pad group 110-1, 110-2, or 110-3 and a corresponding internal pad group 120-1, 120-2 Or multiple first inner pads 122 of 120-3 may be misaligned, which will be described in the following paragraphs with other drawings as examples.

Please refer to FIG. 1. In this embodiment, the plurality of external pad groups 110-1, 110-2, and 110-3 may include a first external pad group 110-1, a second external pad group 110-2, and a third external pad. Pad group 110-3. The first external pad group 110-1 is disposed beside the first side 11a of the substrate 11, the second external pad group 110-2 is disposed beside the second side 11b of the substrate 11, and the third external pad group 110-3 is disposed Between the first external pad group 110-1 and the second external pad group 110-2.

Referring to FIG. 1, in this embodiment, a plurality of inline pad groups 120-1, 120-2, and 120-3 may include a first inline pad group 120-1, a second inline pad group 120-2, and Third inner pad group 120-3. The first internal pad group 120-1 is disposed beside the first side edge 11a of the substrate 11, the second internal pad group 120-2 is disposed beside the second side edge 11b of the substrate 11, and the third internal pad group 120 -3 is disposed between the first internal pad group 120-1 and the second external pad group 120-2.

Please refer to FIG. 1 and FIG. 2. In this embodiment, in addition to the first inner pad group 120-1, the first inner pad group 120-1 includes Outside the plurality of first internal pads 122, the first internal pad group 120-1 further includes a plurality of second internal pads 124 (labeled in FIG. 2) and a plurality of third internal pads 126 (labeled in FIG. 2). . The plurality of second interconnection pads 124 of the first interconnection pad group 120-1 are disposed between the plurality of first interconnection pads 122 of the first interconnection pad group 120-1 and the first side edge 11 a of the substrate 11. In this embodiment, the plurality of second internal pads 124 of the first internal pad group 120-1 may be electrically connected to the first driving circuit GDC1. The plurality of third interconnection pads 126 of the first interconnection pad group 120-1 are disposed between the plurality of first interconnection pads 122 of the first interconnection pad group 120-1 and the second side edge 11 b of the substrate 11. In this embodiment, the plurality of third interconnection pads 126 of the first interconnection pad group 120-1 may have a floating potential, a ground potential, or a combination thereof.

Please refer to FIGS. 1 and 3. In this embodiment, in addition to the second inner pad group 120-2, the second inner pad group 120-2 is arranged along the first direction D1 along the second side of the first inner pad group 120-1 and the substrate 11. Outside the plurality of first internal pads 122 between 11b, the second internal pad group 120-2 further includes multiple second internal pads 124 (labeled in FIG. 3) and multiple third internal pads 126 (labeled (Figure 3). The plurality of second interconnection pads 124 of the second interconnection pad group 120-2 are disposed between the plurality of first interconnection pads 122 of the second interconnection pad group 120-1 and the second side 11 b of the substrate 11. In this embodiment, the plurality of second internal pads 124 of the second internal pad group 120-2 may be electrically connected to the second driving circuit GDC2. The plurality of third internal pads 126 of the second internal pad group 120-2 are disposed between the first internal pad group 120-1 and the multiple first internal pads 122 of the second internal pad group 120-1. . In this embodiment, the plurality of third internal pads 126 of the second internal pad group 120-2 may have a floating potential, a ground potential, or a combination thereof.

Please refer to FIGS. 1 and 4. In this embodiment, in addition to the third inner pad group 120-3, the third inner pad group 120-3 includes the first inner pad group 120-1 and the second inner pad group 120. Outside the plurality of first internal pads 122, the third internal pad group 120-3 further includes a plurality of second internal pads 124 (labeled in FIG. 4) and a plurality of third internal pads 126 ( Labeled in FIG. 4), disposed on both sides of the plurality of first internal pads 122 of the third internal pad group 120-3. That is, the plurality of second internal pads 124 and the plurality of third internal pads 126 are respectively arranged in the plurality of first internal pads 122 and the first internal pads of the third internal pad group 120-3 along the first direction D1. Between one side 11a and the second side 11b. The plurality of third internal pads 126 of the third internal pad group 120-3 are arranged along the first direction D1 on the plurality of first of the first internal pad group 120-1 and the third internal pad group 120-3.内 接 垫 122。 Between the inner pads 122. In this embodiment, the plurality of second interconnection pads 124 and the plurality of third interconnection pads 126 of the third interconnection pad group 120-3 may have a floating potential, a ground potential, or a combination thereof.

It should be noted that the present invention is not limited: the number of the external pad groups 110-1, 110-2, and 110-3 of the pixel array substrate AR is three, and the internal pad groups of the pixel array substrate AR The number of 120-1, 120-2, and 120-3 is three; the number of external pad groups and / or the number of internal pad groups of the pixel array substrate AR can be based on actual requirements (for example, the electronic device 10 Size, resolution of the electronic device 10, size of the first connection element 140-1, and size of the second connection element 140-2).

Referring to FIG. 1, the electronic device 10 further includes at least one printed circuit board 130-1, 130-2, and 130-3, and has at least one pair of pad sets 136-1, 136-2, and 136-3. Each pair of pad groups 136-1, 136-2, or 136-3 includes a first pad group 132 and a second pad group 134 disposed beside the first pad group 132. In this embodiment, the first pad group 132 and the second pad group 134 of the same pair of pad groups 136-1, 136-2, or 136-3 may be sequentially arranged along the first direction D1; The plurality of first pad groups 132 and the plurality of second pad groups 134 of the pad groups 136-1, 136-2, and 136-3 may be alternately arranged along the first direction D1; however, the present invention is not limited thereto.

For example, in this embodiment, the electronic device 10 may include a first printed circuit board 130-1, a second printed circuit board 130-2, and a third printed circuit board 130-3, each having a first pair of solder pad groups. 136-1, the second pair of pad groups 136-2, and the third pair of pad groups 136-3. The plurality of first pad groups 132 and the plurality of second pad groups 134 of the first pair of pad groups 136-1, the second pair of pad groups 136-2, and the third pair of pad groups 136-3 may be selectively selected. Alternately arranged along the first direction D1; that is, the first pad group 132 of the first printed circuit board 130-1, the second pad group 132 of the first printed circuit board 130-1, and the second printed circuit board The first pad group 132 of 130-2, the second pad group 134 of the second printed circuit board 130-2, the first pad group 132 of the third printed circuit board 130-3, and the third printed circuit board 13032 The second bonding pad groups 134 are sequentially arranged in the first direction D1; however, the present invention is not limited thereto.

In this embodiment, the first printed circuit board 130-1, the second printed circuit board 130-2, and the third printed circuit board 130-3 can be selectively separated from each other, but the present invention is not limited thereto. According to other embodiments, at least two of the first printed circuit board 130-1, the second printed circuit board 130-2, and the third printed circuit board 130-3 (for example, the first printed circuit board 130-1 and the second printed circuit board 130-1 Circuit board 130-2, second printed circuit board 130-2, and third printed circuit board 130-3, or first printed circuit board 130-1, second printed circuit board 130-2, and third printed circuit board 130- 3) They can also be connected to each other, but the invention is not limited to this. In this embodiment, the printed circuit boards 130-1, 130-2, and 130-3 are, for example, rigid printed circuit boards, but the present invention is not limited thereto.

Referring to FIG. 1, the electronic device 10 further includes at least one pair of connection elements 140-1, 140-2, and 140-3. Each pair of connection elements 140-1, 140-2, 140-3 includes a first connection element 142-1, 142-2, 142-3, and a second connection element 144-1, 144-2, 144-3; The two connecting elements 144-1, 144-2, and 144-3 partially overlap the first connecting elements 142-1, 142-2, and 142-3; for example, in this embodiment, the second connecting element 144-1 , 144-2, and 144-3 are respectively disposed on the first connection elements 142-1, 142-2, and 142-3. Please refer to FIGS. 1 to 4, two ends 142 a and 142 b of the first connection elements 142-1, 142-2, and 142-3 of each pair of connection elements 140-1, 140-2, and 140-3 (labeled in the drawings 2 to FIG. 4) A first bonding pad group 110-1, 110-2, 110-3 and a pair of bonding pad groups 136-1, 136-2, 136-3 of the pixel array substrate AR are respectively bonded to the first bonding pads. Pad group 132, and two ends 144a, 144b of the second connection element 44-1, 144-2, 144-3 of the same pair of connection elements 140-1, 140-2, 140-3 (labeled in FIGS. 2 to 4 ) A second pad group 134 of an inner pad group 120-1, 120-2, 120-3 and a pair of pad groups 136-1, 136-2, 136-3 are respectively joined.

Please refer to FIGS. 2 to 4. In detail, in this embodiment, each of the first connection elements 142-1, 142-2, and 142-3 has a plurality of first output pins (lead) 142d, a plurality of The first input pin 142e, the plurality of first output traces 142f, the plurality of first input traces 142g, and the first driving chip 142h. The plurality of first output pins 142d and the plurality of first input pins 142e are respectively located at two ends 142a and 142b of the first connection element 142. The first driving chip 142h is located between the plurality of first output pins 142d and the plurality of first input pins 142e. The plurality of first output traces 142f are electrically connected between the first driving chip 142h and the plurality of first output pins 142d. The plurality of first output pins 142d are used for bonding an external pad group 110-1, 110-2, or 110-3 of the pixel array substrate AR. The plurality of first input traces 142g are electrically connected between the first driving chip 142h and the plurality of first input pins 142e. The plurality of first input pins 142e are used to engage the first pad group 132 of the printed circuit board 130-1, 130-2, or 130-3.

For example, in this embodiment, the first driving chip 142h may be electrically connected to a plurality of first output traces 142f and a plurality of first input traces 142g by using flip-chip bonding technology, and the first connection element 142-1 , 142-2, and 142-3 can be chip on films. However, the present invention is not limited to this. In other embodiments, the first driving chip 142h may also be electrically connected to a plurality of first output traces 142f and a plurality of first input traces 142g using other technologies. A connection element 142-1, 142-2, and 142-3 may also be other types of packages; for example, in another embodiment, the first driving chip 142h may also be tape-bonded (Tape Automated Bonding, TAB) technology is electrically connected to multiple first output traces 142f and multiple first input traces 142g, and the first connection elements 142-1, 142-2, 142-3 may also be tape and reel packaging (Tape Carrier Package, TCP). It should be noted that the present invention does not limit the first connection element 142-1, 142-2, 142-3 to include the driving chip 142h. According to other embodiments, the first connection element 142-1, 142-2, 142- 3 may also be a flexible circuit board without a driving chip 142h.

Please refer to FIG. 2 to FIG. 4. In detail, in this embodiment, each second connection element 144 has a plurality of second output pins (lead) 144d, a plurality of second input pins 144e, a plurality of first Two output traces 144f, a plurality of second input traces 144g, and a second driving chip 144h. The plurality of second output pins 144d and the plurality of second input pins 144e are respectively located at two ends 144a and 144b of the second connection element 144. The second driving chip 144h is located between the plurality of second output pins 144d and the plurality of second input pins 144e. The plurality of second output traces 144f are electrically connected between the second driving chip 144h and the plurality of second output pins 144d. The plurality of second output pins 144d are used to be connected to an internal pad group 120-1, 120-2, or 120-3 of the pixel array substrate AR. The plurality of second input traces 144g are electrically connected between the second driving chip 144h and the plurality of second input pins 144e. The plurality of second input pins 144e are used to engage the second pad group 134 of the printed circuit board 130-1, 130-2, or 130-3.

For example, in this embodiment, the second driving chip 144h may be electrically connected to a plurality of second output traces 144f and a plurality of second input traces 142g using flip-chip bonding technology, and the second connection element 144-1 , 144-2, 144-3 can be chip on film. However, the present invention is not limited to this. In other embodiments, the second driving chip 144h may also be electrically connected to multiple second output traces 144f and multiple second input traces 144g using other technologies. The two connecting elements 144-1, 144-2, and 144-3 may also be other types of packages; for example, in another embodiment, the second driving chip 144h may also be tape-bonded (Tape Automated Bonding, TAB) technology is electrically connected to multiple second output traces 144f and multiple second input traces 144g, and the second connection elements 144-1, 144-2, 144-3 can also be tape and reel packaging (Tape Carrier Package, TCP). It should be noted that the present invention does not limit the second connection element 144-1, 144-2, 144-3 to include a driving chip. According to other embodiments, the second connection element 144-1, 144-2, 144-3 It can also be a flexible circuit board without a driver chip.

Please refer to FIG. 1. In this embodiment, the electronic device 10 may include a first pair of connection elements 140-1, a second pair of connection elements 140-2, and a third pair of connection elements 140-3. -1 is disposed between the first side 11a of the substrate 11 and the second pair of connection elements 140-2, and the third pair of connection elements 140-3 is disposed between the first pair of connection elements 140-1 and the second pair of connection elements 140 -2. The two ends 142a, 142b (labeled in FIGS. 2 to 4) of the first connection element 142-1 of the first pair of connection elements 140-1 are respectively bonded to the first external pad group 110-1 and the first of the pixel array substrate AR. The first bonding pad group 132 of the printed circuit board 130-1, and the two ends 144a, 144b (labeled in FIGS. 2 to 4) of the first pair of connection elements 140-1 and the second connection elements 144-1 of the first pair of connection elements are respectively bonded to pixels The first inner pad group 120-1 of the array substrate AR and the second pad group 134 of the first printed circuit board 130-1; both ends 142a of the first connection element 142-2 of the second pair of connection elements 140-2 And 142b respectively join the second external pad group 110-2 of the pixel array substrate AR and the first pad group 132 of the second printed circuit board 130-2, and the second connection element 144 of the second pair of connection elements 140-2 The two ends 144a and 144b of -2 are respectively connected to the second pad group 120-2 of the pixel array substrate AR and the second pad group 134 of the second printed circuit board 130-2; the third pair of connection elements 140-3 The two ends 142a and 142b of the first connection element 142-3 are respectively connected to the third external pad group 110-3 of the pixel array substrate AR and the first pad group 132 of the third printed circuit board 130-3, and the third Pair of connecting elements 140 Both ends 144a and 144b of the second connecting element 144-3 of -3 are respectively connected to the third pad group 120-3 of the pixel array substrate AR and the second pad group 134 of the third printed circuit board 130-3.

Please refer to FIG. 1 to FIG. 4. In this embodiment, each pair of first connection elements 142-1, 142-2, or 142-3 of the pair of connection elements 140-1, 140-2, or 140-3 has a plurality of pairs. Bit mark 142c (labeled in Figures 2 to 4). In the process of bonding the first connection element 142-1, 142-2, or 142-3 to the pixel array substrate AR, a plurality of alignment marks 142c of the first connection element 142-1, 142-2, or 142-3 are used. Align with alignment marks (not shown) provided on both sides of an external pad group 110-1, 110-2, or 110-3 of the pixel array substrate AR to help the first connection elements 142-1, 142 -2 or 142-3 is accurately bonded to the plurality of external pads 112 of the pixel array substrate AR. Similarly, the second connection element 144-1, 144-2, or 144-3 of each pair of connection elements 140-1, 140-2, or 140-3 has a plurality of alignment marks 144c. In the process of bonding the second connection element 144-1, 144-2, or 144-3 to the pixel array substrate AR, a plurality of alignment marks 144c of the second connection element 144-1, 144-2, or 144-3 are used. Align with alignment marks (not shown) provided on both sides of an inner pad group 120-1, 120-2, or 120-3 of the pixel array substrate AR to help the second connection element 144-1, 144-2 or 144-3 is accurately bonded to the plurality of internal pads 122, 124, and 126 of the pixel array substrate AR.

Referring to FIG. 1, it is worth mentioning that, in this embodiment, the first connection element 142-1, 142-2, or 142-3 of each pair of connection elements 136-1, 136-2, or 136-3 first Bonded to the pixel array substrate AR; after that, the second connection element 144-1, 144-2, or 144-3 of the pair of connection elements 136-1, 136-2, or 136-3 is bonded to the pixel array substrate AR. That is, when the second connection element 144-1, 144-2, or 144-3 is to be bonded to the pixel array substrate AR, the first connection element 142-1, 142-2, or 142-3 is already bonded to the pixel On the array substrate AR. In order that the arrangement of the first connection elements 142-1, 142-2, and 142-3 does not affect the alignment of the alignment marks 144c of the second connection elements 144-1, 144-2, 144-3 and the pixel array substrate AR The alignment of the marks (not shown), the distance K2 (labeled in FIG. 2) between the plurality of alignment marks 144c of the second connecting element 144-1, 144-2, or 144-3 will be greater than the pixel array The maximum width W1 of the first connection element 142-1, 142-3, or 142-3 of the substrate AR in the first direction D1 (labeled in FIG. 2). That is, the distance K2 between the plurality of alignment marks 144c of the second connection element 144-1, 144-2, or 144-3 is larger than the first connection element 142-1, 142-1, which has been bonded to the pixel array substrate AR. The distance K1 between the plurality of alignment marks 142c of 142-3 or 142-3 (labeled in FIG. 2). Thereby, during the process in which the second connection element 144-1, 144-2, or 144-3 moves from outside the substrate 11 to above the substrate 11 in the third direction D3, the second connection element 144-1, 144-2, or 144 The registration mark 144c of -3 does not overlap the first connection element 142-1, 142-2, or 142-3, so that the camera of the registration machine can clearly capture the registration mark 144c of the second connection element 144 and The alignment mark of the pixel array substrate AR helps the second connection element 144-1, 144-2, or 144-3 to smoothly join the pixel array substrate AR. The first connection elements 142-1, 142-2, 142-3 and the second connection elements 144-1, 144-2, and 144-3 are respectively connected to the external pad groups 110-1 and 110-2 of the pixel array substrate AR. After 110, 110-3 and the inner pad group 120-1, 120-2, 120-3, multiple alignment marks 144c of each second connection element 144-1, 144-2, or 142-3 are on the substrate 11. The plurality of vertical projections are located outside the vertical projections of the corresponding first connection element 142-1, 142-2, or 142-3 on the substrate 11.

Please refer to FIGS. 1 to 4. In this embodiment, based on the consideration of improving the joint yield, each of the inscribed pad groups 120-1, 120-2, or 120-3 may further include a plurality of third inscribed pads 126. . The plurality of third interconnection pads 126 are disposed between the plurality of first interconnection pads 122 and an alignment mark 144c, and electrically isolate the plurality of first signal lines SL1. The plurality of third internal pads 126 are dummy pads, and the plurality of third internal pads 126 have a floating potential, a ground potential, or a combination thereof.

For example, in this embodiment, based on the consideration of simplified types of incoming materials, the plurality of first connection elements 142-1, 142-2, and 142-3 of the electronic device 10 may adopt the same structure. The same structure can also be adopted for the plurality of second connection elements 144-1, 144-2, and 144-3 of the connection elements 140-1, 140-2, and 140-3.

FIG. 5 is a schematic perspective view of an electronic device according to another embodiment of the present invention. FIG. 6 is an enlarged schematic diagram of a region I in FIG. 5. FIG. 7 is an enlarged schematic view of a region II in FIG. 5. FIG. 8 is an enlarged schematic view of a region III in FIG. 5.

Please refer to FIG. 5 to FIG. 7. The electronic device 10A in this embodiment is similar to the aforementioned electronic device 10. The difference between the two is only that in this embodiment, an external pad group 110-1, 110-2, or 110- The plurality of external pads 112 of 3 may not be aligned with the plurality of first internal pads 122 corresponding to one of the internal pad groups 120-1, 120-2, or 120-3; that is, one external pad group 110-1 The plurality of external pads 112, 110-2, or 110-3 and the plurality of first internal pads 122 corresponding to one of the internal pad groups 120-1, 120-2, or 120-3 may be alternately arranged.

In summary, an electronic device according to an embodiment of the present invention includes a pixel array substrate, at least one printed circuit board, and at least one pair of connection elements. The pixel array substrate has an external pad group and an internal pad group. The printed circuit board has a first pad group and a second pad group. The pair of connection elements includes a first connection element and a second connection element disposed on the first connection element, wherein both ends of the first connection element are respectively engaged with the first external pad group and the first solder pad group of the first printed circuit board. , And two ends of the second connection element are respectively connected to the first internal pad group and the second solder pad group of the printed circuit board. Thereby, an electronic device having a high resolution, a high bonding yield, and a low cost can be realized.

Although the present invention has been disclosed as above with the examples, it is not intended to limit the present invention. Any person with ordinary knowledge in the technical field can make some modifications and retouching without departing from the spirit and scope of the present invention. The protection scope of the present invention shall be determined by the scope of the attached patent application.

10, 10A‧‧‧ electronic device

11‧‧‧ substrate

11a‧‧‧first side

11b‧‧‧ second side

11c‧‧‧ Third side

110-1, 110-2, 110-3‧‧‧ External pad set

112‧‧‧External pad

120-1, 120-2, 120-3‧‧‧ Internal pad set

122, 124, 126‧‧‧ Internal pad

130-1, 130-2, 130-3‧‧‧ printed circuit boards

132‧‧‧The first pad set

134‧‧‧Second welding pad set

136-1, 136-2, 136-3 ‧‧‧ a pair of pad sets

140-1, 140-2, 140-3 ‧‧‧ a pair of connecting elements

142-1, 142-2, 142-3‧‧‧ the first connecting element

142a, 142b, 144a, 144b

144-1, 144-2, 144-3‧‧‧Second connection element

142c, 144c‧‧‧Alignment mark

142d, 144d‧‧‧ output pins

142e, 144e‧‧‧ input pins

142f, 144f‧‧‧ output routing

142g, 144g‧‧‧ input wiring

142h, 144h‧‧‧Driver

AR‧‧‧Pixel Array Substrate

D1‧‧‧ first direction

D2‧‧‧ Second direction

D3‧‧‧ Third direction

GDC1‧‧‧first drive circuit

GDC2‧‧‧Second driving circuit

K1, K2‧‧‧ distance

PX‧‧‧Pixel Structure

PE‧‧‧Pixel electrode

SL1‧‧‧First Signal Line

SL2‧‧‧Second Signal Line

T‧‧‧active element

W1‧‧‧Width

Zones I, II, III

FIG. 1 is a schematic perspective view of an electronic device according to an embodiment of the present invention. FIG. 2 is an enlarged schematic diagram of a region I in FIG. 1. FIG. 3 is an enlarged schematic view of a region II in FIG. 1. FIG. 4 is an enlarged schematic view of a region III in FIG. 1. FIG. 5 is a schematic perspective view of an electronic device according to another embodiment of the present invention. FIG. 6 is an enlarged schematic diagram of a region I in FIG. 5. FIG. 7 is an enlarged schematic view of a region II in FIG. 5. FIG. 8 is an enlarged schematic view of a region III in FIG. 5.

Claims (10)

An electronic device includes: a substrate having a first side, a second side opposite to the first side, and a third side connected to the first side and the second side; A plurality of first signal lines are disposed on the substrate; a plurality of pixel structures are electrically connected to the first signal lines; a first external pad group is disposed on the substrate, wherein the first external pad group Comprising a plurality of external pads arranged between the first side edge of the substrate and the second side edge of the substrate and electrically connected to some of the first signal lines; a first internal pad group, provided On the substrate, wherein the first external pad group is closer to the third side than the first internal pad group, the first internal pad group includes a plurality of first internal pads arranged on the first portion of the substrate. One side edge is electrically connected to the second side edge of the substrate and part of the first signal lines; a first printed circuit board having a first pad group and a second pad group; And a first pair of connection elements, including a first connection element and a second portion partially overlapping the first connection element The connection element, wherein both ends of the first connection element of the first pair of connection elements are respectively engaged with the first external pad group and the first solder pad group of the first printed circuit board, and Both ends of the second connection element are respectively engaged with the first internal pad group and the second solder pad group of the first printed circuit board. The electronic device according to item 1 of the patent application scope, wherein the first internal pad group further includes a plurality of second internal pads, and the electronic device further includes: a plurality of second signal lines disposed on the substrate The second signal lines are electrically connected to the pixel structures and are staggered with the first signal lines; and a first driving circuit is disposed adjacent to the first side of the substrate and is connected to the At least a part of the second signal line is electrically connected; wherein the second internal pads of the first internal pad group are electrically connected to the first driving circuit. The electronic device according to item 2 of the scope of patent application, further comprising: a second pair of connection elements, wherein the first pair of connection elements are disposed between the first side of the substrate and the second pair of connection elements, The second pair of connection elements includes a first connection element and a second connection element partially overlapping the first connection element of the second pair of connection elements; a second driving circuit adjacent to the second side of the substrate Arranged and electrically connected to another part of the second signal lines; a second external pad group is arranged between the first external pad group and the second side of the substrate, wherein the second external pad The group includes a plurality of external pads, and is electrically connected to some of the first signal lines; a second internal pad group is disposed on the substrate, and the second external pad group is more than the second internal pad group Close to the third side of the substrate, wherein the second internal pad group includes a plurality of first internal pads and a plurality of second internal pads, and the first internal pads of the second internal pad group Arranged between the first internal pad group and the second side of the substrate and in part and The first signal lines are electrically connected, and the second internal pads of the second internal pad group are electrically connected to the second driving circuit; and a second printed circuit board having a first solder pad group And a second pad set, wherein two ends of the first connection element of the second pair of connection elements are respectively engaged with the second external pad set and the first pad set of the second printed circuit board, the second The two ends of the second connecting element of the connecting element are respectively engaged with the second internal pad group and the second solder pad group of the second printed circuit board. The electronic device according to item 3 of the scope of patent application, wherein the first pad group of the first printed circuit board, the second pad group of the first printed circuit board, and the second pad of the second printed circuit board The first pad group and the second pad group of the second printed circuit board are sequentially arranged along a first direction. According to the third aspect of the patent application, the electronic device further includes: a third external pad group including a plurality of external pads, wherein the external pads of the third external pad group are arranged in the first external pad group and The second external pad group is electrically connected to a portion of the first signal lines; a third internal pad group is disposed on the substrate and the third external pad group is more than the third internal pad group. Close to the third side of the substrate, wherein the third internal pad group includes a plurality of first internal pads, a plurality of second internal pads, and a plurality of third internal pads, and the third internal pad The first internal pads of the group are arranged between the first internal pad group and the second internal pad group and are electrically connected to part of the first signal lines, and the third internal pad group The second internal pads and the third internal pads are disposed on both sides of the first internal pads of the third internal pad group; a third pair of connecting elements, including a first connecting element And a second connection element disposed on the first connection element of the third pair of connection elements; and a third printed circuit board having a first solder And a second pad group, wherein both ends of the first connection element of the third pair of connection elements are respectively engaged with the third external pad group and the first pad group of the third printed circuit board. Two ends of the second connection element of the three pairs of connection elements are respectively engaged with the third internal pad group and the second solder pad group of the third printed circuit board. The electronic device according to item 5 of the patent application scope, wherein the second internal pads and the third internal pads of the third internal pad group have a floating potential, a ground potential, or a combination thereof. The electronic device according to item 2 of the scope of patent application, wherein the first internal pad group further includes a plurality of third internal pads, and the first internal pads disposed in the first internal pad group and the Between the second sides of the substrate. The electronic device according to item 7 of the scope of patent application, wherein the third internal pads of the first internal pad group have a floating potential, a ground potential, or a combination thereof. The electronic device according to item 7 of the scope of patent application, wherein the second connection element has a plurality of alignment marks on opposite sides of the first internal pad set, and the alignment marks of the second connection element The plurality of vertical projections on the substrate are located outside a vertical projection of the first connection element on the substrate, and the third internal pads are disposed at one of the first internal pads and the alignment marks. And electrically isolate the first signal lines. The electronic device according to item 1 of the patent application scope, wherein the second connection element has a plurality of alignment marks on opposite sides of the first internal pad set, and the alignment of the second connection element The plurality of vertical projections marked on the substrate are located outside a vertical projection of the first connection element on the substrate.