TWI847471B - Display device - Google Patents

Abstract

A display device includes a first substrate, a first wiring layer, a first electrode, a second substrate, a display medium layer and a second electrode. The first wiring layer and the first electrode are disposed between the first substrate and the second substrate, the display medium layer is disposed between the first electrode and the second substrate, and the second electrode is disposed between the display medium layer and the second substrate. The first electrode includes plural first lower electrode patterns and plural first upper electrode patterns that are electrically isolated from each other, wherein the plural first lower electrode patterns and the plural first upper electrode patterns are electrically connected to plural first wirings of the first wiring layer respectively, the plural first lower electrode patterns have plural first gaps therebetween, and the plural first upper electrode patterns are overlapped with the plural first gaps respectively.

Description

Display device

The present invention relates to an optoelectronic device, and in particular to a display device.

Reflective liquid crystal displays have the advantages of energy saving and environmental protection. They use the reflection or absorption of ambient light to produce a bright state or a dark state to achieve the purpose of display, so there is no need to set up a backlight source. Generally speaking, the liquid crystal layer of a reflective liquid crystal display can be driven by the electric field formed by the upper and lower electrodes to switch between the transmissive state and the reflective state to achieve the dark state and bright state of each sub-pixel. The effective area of each sub-pixel is determined by the overlapping area of the upper and lower electrodes, and the area where the upper and lower electrodes do not overlap is the ineffective area. However, due to the line width limitation of the process, the ratio of the ineffective area to the effective area becomes higher and higher with the increase of pixel density (pixel per inch, PPI), resulting in a significant decrease in the reflectivity of the reflective liquid crystal display.

The present invention provides a display device with improved reflectivity.

An embodiment of the present invention provides a display device, comprising: a first substrate, a first conductive layer, a first electrode, a second substrate, a display medium layer and a second electrode. The first conductive layer is located on the first substrate and includes a plurality of first conductive wires. The first electrode is located on the first substrate and includes a plurality of first lower electrode patterns and a plurality of first upper electrode patterns that are electrically separated from each other, wherein the plurality of first lower electrode patterns and the plurality of first upper electrode patterns are electrically connected to the plurality of first conductive wires respectively, and there are a plurality of first gaps between the plurality of first lower electrode patterns, and the plurality of first upper electrode patterns overlap a plurality of first gaps respectively. The first conductive layer and the first electrode are located between the first substrate and the second substrate. The display medium layer is located between the first electrode and the second substrate. The second electrode is located between the display medium layer and the second substrate.

In an embodiment of the present invention, the plurality of first conductive lines are electrically independent of each other.

In one embodiment of the present invention, the plurality of first bottom electrode patterns are separated from each other.

In one embodiment of the present invention, the plurality of first upper electrode patterns are separated from each other.

In an embodiment of the present invention, the plurality of first lower electrode patterns and the plurality of first upper electrode patterns extend in the same direction.

In an embodiment of the present invention, the overlapping width of the first lower electrode pattern and the first upper electrode pattern is 1.5 μm to 3 μm.

In one embodiment of the present invention, the potentials of the first upper electrode pattern and the first lower electrode pattern that overlap each other are different.

In one embodiment of the present invention, a distance between adjacent first lower electrode patterns and first upper electrode patterns is greater than 0 and less than 10 μm.

In an embodiment of the present invention, the second electrode includes a plurality of second lower electrode patterns, and the extension direction of the plurality of second lower electrode patterns is perpendicular to the extension direction of the plurality of first lower electrode patterns.

In an embodiment of the present invention, the second electrode further includes a plurality of second upper electrode patterns, and the plurality of second upper electrode patterns and the plurality of second lower electrode patterns extend in the same direction.

In an embodiment of the present invention, a plurality of second gaps are provided between the plurality of second lower electrode patterns, and a plurality of second upper electrode patterns overlap the plurality of second gaps respectively.

In an embodiment of the present invention, the display device further includes a second conductive line layer located between the second substrate and the display medium layer, and includes a plurality of second conductive lines, wherein a plurality of second lower electrode patterns and a plurality of second upper electrode patterns are electrically connected to the plurality of second conductive lines respectively.

In order to make the above features and advantages of the present invention more clearly understood, embodiments are specifically cited below and described in detail with reference to the accompanying drawings.

In the accompanying drawings, for the sake of clarity, the thickness of layers, films, panels, regions, etc. is magnified. Throughout the specification, the same figure markings represent the same elements. It should be understood that when an element such as a layer, film, region or substrate is referred to as being "on" or "connected to" another element, it can be directly on or connected to another element, or an intermediate element can also exist. On the contrary, when an element is referred to as being "directly on" or "directly connected to" another element, there is no intermediate element. As used herein, "connection" can refer to physical and/or electrical connection. Furthermore, "electrical connection" or "coupling" can be the presence of other elements between two elements.

It should be understood that although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers and/or parts, these elements, components, regions, layers and/or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, the first "element", "component", "region", "layer" or "part" discussed below can be referred to as a second element, component, region, layer or part without departing from the teachings of this article.

The terms used herein are for the purpose of describing specific embodiments only and are not restrictive. As used herein, unless the context clearly indicates otherwise, the singular forms "a", "an" and "the" are intended to include plural forms, including "at least one" or to mean "and/or". As used herein, the term "and/or" includes any and all combinations of one or more of the relevant listed items. It should also be understood that when used in this specification, the terms "include" and/or "include" specify the presence of the features, regions, wholes, steps, operations, elements and/or parts, but do not exclude the presence or addition of one or more other features, regions, wholes, steps, operations, elements, parts and/or combinations thereof.

In addition, relative terms such as "lower" or "bottom" and "upper" or "top" may be used herein to describe the relationship of one element to another element, as shown in the figures. It should be understood that relative terms are intended to include different orientations of the device in addition to the orientation shown in the figures. For example, if the device in one figure is flipped, the elements described as being on the "lower" side of the other elements will be oriented on the "upper" side of the other elements. Therefore, the exemplary term "lower" can include both "lower" and "upper" orientations, depending on the specific orientation of the figure. Similarly, if the device in one figure is flipped, the elements described as being "lower" or "below" other elements will be oriented as being "above" other elements. Therefore, the exemplary term "lower" or "below" can include both above and below orientations.

As used herein, "about," "approximately," or "substantially" includes the stated value and the average value within an acceptable deviation range of the particular value determined by a person of ordinary skill in the art, taking into account the measurement in question and the particular amount of error associated with the measurement (i.e., the limitations of the measurement system). For example, "about" can mean within one or more standard deviations of the stated value, or within ±30%, ±20%, ±10%, ±5%. Furthermore, as used herein, "about," "approximately," or "substantially" can select a more acceptable deviation range or standard deviation depending on the optical property, etching property, or other property, and can apply to all properties without a single standard deviation.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by ordinary technicians in the field to which the present invention belongs. It will be further understood that those terms as defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology and the present invention, and will not be interpreted as an idealized or overly formal meaning unless expressly defined as such in this document.

Exemplary embodiments are described herein with reference to cross-sectional views that are schematic illustrations of idealized embodiments. Therefore, variations in the shapes of the illustrations as a result of, for example, manufacturing techniques and/or tolerances are to be expected. Therefore, the embodiments described herein should not be construed as limited to the specific shapes of the regions as shown herein, but rather include shape deviations that result, for example, from manufacturing. For example, a region shown or described as flat may typically have rough and/or nonlinear features. Furthermore, sharp corners shown may be rounded. Therefore, the regions shown in the figures are schematic in nature, and their shapes are not intended to illustrate the exact shape of the regions and are not intended to limit the scope of the claims.

FIG. 1A is a three-dimensional schematic diagram of a display device 10 according to an embodiment of the present invention. FIG. 1B is a cross-sectional schematic diagram taken along the section line A-A' of FIG. 1A. FIG. 1C is a top view schematic diagram of the first substrate 110, the first electrode 130, and the first conductive layer 150 of the display device 10 of FIG. 1A. FIG. 1D is a top view schematic diagram of the second substrate 120, the second electrode 140, and the second conductive layer 160 of the display device 10 of FIG. 1A.

1A to 1D , the display device 10 may include a first substrate 110 and a second substrate 120. In some embodiments, the first substrate 110 overlaps the second substrate 120. In some embodiments, the first substrate 110 is opposite to the second substrate 120, and the surface 111 of the first substrate 110 faces the surface 121 of the second substrate 120. In some embodiments, the first substrate 110 and the second substrate 120 are transparent substrates. For example, the materials of the substrate 110 and the substrate 120 are glass, organic polymers or other appropriate materials.

In some embodiments, the display device 10 further includes a first electrode 130, and the first electrode 130 is disposed on the first substrate 110. In some embodiments, the first electrode 130 is located between the first substrate 110 and the second substrate 120. The first electrode 130 may include a plurality of strip electrodes separated from each other. In some embodiments, the plurality of strip electrodes of the first electrode 130 do not completely belong to the same film layer. In some embodiments, the plurality of strip electrodes of the first electrode 130 are distributed in two film layers.

For example, the first electrode 130 includes a first lower electrode pattern layer 131 and a first upper electrode pattern layer 132. In some embodiments, the display device 10 further includes an insulating layer 112, and the insulating layer 112 separates the first lower electrode pattern layer 131 from the first upper electrode pattern layer 132.

In some embodiments, the first lower electrode pattern layer 131 includes a plurality of first lower electrode patterns E1B, and the plurality of first lower electrode patterns E1B are separated from each other. In some embodiments, the first lower electrode pattern E1B has a stripe pattern, and the plurality of first lower electrode patterns E1B extend parallel to each other along the first direction D1. In some embodiments, a plurality of gaps G1 are provided between the plurality of first lower electrode patterns E1B, and the widths W1 of the plurality of gaps G1 along the second direction D2 are substantially the same. In some embodiments, the first direction D1 is perpendicular to the second direction D2. In some embodiments, the width W1 of the gap G1 is approximately 10 μm.

In some embodiments, the first upper electrode pattern layer 132 is located on the first lower electrode pattern layer 131, and the first upper electrode pattern layer 132 includes a plurality of first upper electrode patterns E1T separated from each other. In some embodiments, the first upper electrode pattern E1T has a stripe pattern, and the extension direction of the first upper electrode pattern E1T is the same as the extension direction of the first lower electrode pattern E1B. In some embodiments, the plurality of first upper electrode patterns E1T extend in parallel with each other along the first direction D1. In some embodiments, there are a plurality of gaps G2 between the plurality of first upper electrode patterns E1T, and the widths W2 of the plurality of gaps G2 along the second direction D2 are substantially the same. In some embodiments, the width W2 of the gap G2 is about 10 μm.

In some embodiments, the plurality of first upper electrode patterns E1T partially overlap the plurality of first lower electrode patterns E1B, respectively. In some embodiments, the overlapping width W3 of the first lower electrode pattern E1B and the first upper electrode pattern E1T is approximately 1.5 μm to 3 μm. In some embodiments, the potentials of the overlapping first upper electrode pattern E1T and the first lower electrode pattern E1B are different. In some embodiments, the voltage of the first upper electrode pattern E1T is approximately 80% to 95% of the voltage of the overlapping first lower electrode pattern E1B.

In some embodiments, the plurality of first upper electrode patterns E1T partially overlap the plurality of gaps G1 between the plurality of first lower electrode patterns E1B. In some embodiments, the side S1 of the first upper electrode pattern E1T in a direction (i.e., the second direction D2) perpendicular to its extension direction (i.e., the first direction D1) partially overlaps the first lower electrode pattern E1B, and the side S2 of the first upper electrode pattern E1T opposite to the side S1 does not overlap the first lower electrode pattern E1B. In some embodiments, the spacing W4 between the side S2 of the first upper electrode pattern E1T that does not overlap the first lower electrode pattern E1B and the adjacent first lower electrode pattern E1B is greater than 0 and less than 10 μm. That is, each first upper electrode pattern E1T only partially overlaps a corresponding first lower electrode pattern E1B, and does not overlap the rest of the first lower electrode pattern E1B, so as to avoid generating parasitic capacitance. In some embodiments, the distance W4 between the side S2 of the first upper electrode pattern E1T that does not overlap the first lower electrode pattern E1B and the adjacent first lower electrode pattern E1B can be further reduced to about 2 μm to 5 μm, so as to reduce the ineffective area of each sub-pixel. In some embodiments, the distance W4 is the minimum distance between the first upper electrode pattern E1T and the non-overlapping first lower electrode pattern E1B.

In some embodiments, the display device 10 further includes a first conductive layer 150, and the first conductive layer 150 is located on the first substrate 110. In some embodiments, the display device 10 further includes an insulating layer 111, and the insulating layer 121 separates the first conductive layer 150 and the first electrode 130. In some embodiments, the first conductive layer 150 is located between the first substrate 110 and the second substrate 120. In some embodiments, the first conductive layer 150 includes a plurality of first conductive lines 152, and each of the plurality of first conductive lines 152 is electrically independent. In some embodiments, the plurality of first conductive lines 152 are physically separated from each other. In some embodiments, the plurality of first bottom electrode patterns E1B and the plurality of first top electrode patterns E1T of the first electrode 130 are electrically connected to the plurality of first conductive lines 152 , respectively.

In some embodiments, the display device 10 further includes a driving element 181, and the plurality of first conductive lines 152 of the first conductive line layer 150 are electrically connected to the driving element 181. In some embodiments, the driving element 181 is disposed on the first substrate 110. In some embodiments, the display device 10 further includes a plurality of pads PD1, and the plurality of pads PD1 are electrically connected to the plurality of first conductive lines 152 and the driving element 181, respectively. In this way, the driving element 181 can provide signals to the plurality of first bottom electrode patterns E1B and the plurality of first top electrode patterns E1T, respectively.

In some embodiments, the display device 10 further includes a display medium layer 170, and the display medium layer 170 is located between the first electrode 130 and the second substrate 120. In some embodiments, the first upper electrode pattern layer 132 of the first electrode 130 is located between the first lower electrode pattern layer 131 and the display medium layer 170. In some embodiments, the display medium layer 170 includes display medium molecules, such as cholesterol liquid crystal (CLC) molecules. In some embodiments, the cholesterol liquid crystal molecules can switch between a focal conic state, a homeotropic state, and a planar state. When the cholesteric liquid crystal molecules are in a focal conical state or a vertical state, the display medium layer 170 can be in a transmissive state. When the cholesteric liquid crystal molecules are in a planar state, the display medium layer 170 can be in a reflective state and reflect incoming light, and the wavelength of the reflected light can be determined by the pitch of the cholesteric liquid crystal molecules.

In some embodiments, the display device 10 further includes a second electrode 140, and the second electrode 140 is located between the display medium layer 170 and the second substrate 120. In some embodiments, the display medium layer 170 is located between the first electrode 130 and the second electrode 140. The second electrode 140 may include a plurality of strip electrodes separated from each other, and the extension direction of the second electrode 140 intersects the extension direction of the first electrode 130. In this way, the overlapping area of the first electrode 130 and the second electrode 140 can drive the display medium molecules in the display medium layer 170 to change direction, thereby serving as the effective area of the individual sub-pixels of the display device 10. In some embodiments, the plurality of strip electrodes of the second electrode 140 do not completely belong to the same film layer. In some embodiments, the plurality of strip electrodes of the second electrode 140 are distributed in two film layers.

For example, the second electrode 140 includes a second lower electrode pattern layer 141 and a second upper electrode pattern layer 142. In some embodiments, the second upper electrode pattern layer 142 of the second electrode 140 is located between the second lower electrode pattern layer 141 and the display medium layer 170. In some embodiments, the display device 10 further includes an insulating layer 122, and the insulating layer 122 separates the second lower electrode pattern layer 141 from the second upper electrode pattern layer 142.

In some embodiments, the second lower electrode pattern layer 141 includes a plurality of second lower electrode patterns E2B, and the plurality of second lower electrode patterns E2B are separated from each other. In some embodiments, the second lower electrode pattern E2B has a stripe pattern, and the plurality of second lower electrode patterns E2B extend in parallel with each other along the second direction D2. In some embodiments, the extension direction of the second lower electrode pattern E2B intersects with the extension direction of the first lower electrode pattern E1B. In some embodiments, there are a plurality of gaps G3 between the plurality of second lower electrode patterns E2B, and the widths W5 of the plurality of gaps G3 along the first direction D1 are substantially the same. In some embodiments, the width W5 of the gap G3 is approximately 10 μm.

In some embodiments, the second upper electrode pattern layer 142 is located on the second lower electrode pattern layer 141, and the second upper electrode pattern layer 142 includes a plurality of second upper electrode patterns E2T separated from each other. In some embodiments, the second upper electrode pattern E2T has a stripe pattern, and the extension direction of the second upper electrode pattern E2T is the same as the extension direction of the second lower electrode pattern E2B. In some embodiments, the plurality of second upper electrode patterns E2T extend in parallel with each other along the second direction D2. In some embodiments, the extension direction of the second upper electrode pattern E2T intersects with the extension direction of the first upper electrode pattern E1T. In some embodiments, a plurality of gaps G4 are disposed between the plurality of second upper electrode patterns E2T, and the widths W6 of the plurality of gaps G4 along the first direction D1 are substantially the same. In some embodiments, the width W6 of the gap G4 is approximately 10 μm.

In some embodiments, the plurality of second upper electrode patterns E2T partially overlap the plurality of second lower electrode patterns E2B. In some embodiments, the overlapping width W7 of the second lower electrode pattern E2B and the second upper electrode pattern E2T is about 1.5 μm to 3 μm. In some embodiments, the potentials of the overlapping second upper electrode pattern E2T and the second lower electrode pattern E2B are different. In some embodiments, the voltage of the second upper electrode pattern E2T is about 80% to 95% of the voltage of the overlapping second lower electrode pattern E2B.

In some embodiments, the maximum electric field strength formed by the overlapping first upper electrode pattern E1T and the first lower electrode pattern E1B in the display dielectric layer 170 is substantially the same. In some embodiments, the maximum electric field strength formed by the overlapping second upper electrode pattern E2T and the second lower electrode pattern E2B in the display dielectric layer 170 is substantially the same.

In some embodiments, the plurality of second upper electrode patterns E2T partially overlap the plurality of gaps G3 between the plurality of second lower electrode patterns E2B. In some embodiments, the side S3 of the second upper electrode pattern E2T in the direction (i.e., the first direction D1) perpendicular to the extension direction (i.e., the second direction D2) partially overlaps the second lower electrode pattern E2B, and the side S4 of the second upper electrode pattern E2T opposite to the side S3 does not overlap the second lower electrode pattern E2B. In some embodiments, the spacing W8 between the side S4 of the second upper electrode pattern E2T that does not overlap the second lower electrode pattern E2B and the adjacent second lower electrode pattern E2B is greater than 0 and less than 10 μm. That is, each second upper electrode pattern E2T only partially overlaps a corresponding second lower electrode pattern E2B, and does not overlap the rest of the second lower electrode pattern E2B, so as to avoid generating parasitic capacitance. In some embodiments, the distance W8 between the side S4 of the second upper electrode pattern E2T that does not overlap the second lower electrode pattern E2B and the adjacent second lower electrode pattern E2B can be further reduced to about 2 μm to 5 μm, so as to reduce the ineffective area of each sub-pixel. In some embodiments, the distance W8 is the minimum distance between the second upper electrode pattern E2T and the non-overlapping second lower electrode pattern E2B.

Since the distance W4 between the first upper electrode pattern E1T and the first lower electrode pattern E1B and the distance W8 between the second upper electrode pattern E2T and the second lower electrode pattern E2B can be further reduced, the ratio of the ineffective area where the first electrode 130 and the second electrode 140 do not overlap with each other to the effective area where the first electrode 130 and the second electrode 140 overlap with each other can be further reduced, thereby improving the reflectivity of the display device 10.

In some embodiments, the display device 10 further includes a second conductive layer 160, which is disposed on the second substrate 120 and is located between the first substrate 110 and the second substrate 120. In some embodiments, the second conductive layer 160 is located between the second electrode 140 and the second substrate 120. In some embodiments, the display device 10 further includes an insulating layer 121, and the insulating layer 121 separates the second conductive layer 160 from the second electrode 140. In some embodiments, the second conductive layer 160 includes a plurality of second conductive lines 162, and each of the plurality of second conductive lines 162 is electrically independent. In some embodiments, the plurality of second conductive lines 162 are physically separated from each other. In some embodiments, the second lower electrode patterns E2B and the second upper electrode patterns E2T of the second electrode 140 are respectively electrically connected to the second conductive lines 162. In some embodiments, the display device 10 further includes a plurality of pads PD22 disposed on the second substrate 120, and the plurality of pads PD22 are respectively electrically connected to the second conductive lines 162.

In some embodiments, the materials of the first lower electrode pattern layer 131, the first upper electrode pattern layer 132, the second lower electrode pattern layer 141 and the second upper electrode pattern layer 142 are transparent conductive materials, such as indium tin oxide, indium zinc oxide, aluminum tin oxide, aluminum zinc oxide, indium gallium zinc oxide or other suitable transparent conductive materials. In some embodiments, the materials of the insulating layers I11, I12, I21, I22 may include transparent insulating materials, such as silicon oxide, silicon nitride, silicon oxynitride, a stack of the above materials or other suitable materials. In some embodiments, the first conductive layer 150 and the second conductive layer 160 are made of metals with good electrical conductivity, such as aluminum, molybdenum, titanium, copper, etc., or alloys or stacks of the above metals, but the present invention is not limited thereto.

In some embodiments, the display device 10 further includes a driving element 182, and the plurality of second wires 162 of the second wire layer 160 are electrically connected to the driving element 182. In some embodiments, the driving element 182 is disposed on the first substrate 110, and the driving elements 181 and 182 are respectively disposed on different sides of the first substrate 110. In some embodiments, the display device 10 further includes a plurality of pads PD21, and the plurality of pads PD21 are respectively electrically connected to the plurality of second wires 162 and the driving element 182. For example, the display device 10 further includes a plurality of connectors AF, and when the first substrate 110 and the second substrate 120 are paired to form a display structure as shown in FIG. 1B , the plurality of connectors AF can electrically connect the plurality of pads PD21 on the first substrate 110 and the plurality of pads PD22 on the second substrate 120, respectively, so that the plurality of second wires 162 can be electrically connected to the driving element 182 through the plurality of pads PD22, the plurality of connectors AF, and the plurality of pads PD21, respectively. In this way, the driving element 182 can provide signals to the plurality of second bottom electrode patterns E2B and the plurality of second top electrode patterns E2T, respectively.

In some embodiments, the material of the pads PD1, PD21, PD22 is a metal with good electrical conductivity, such as aluminum, molybdenum, titanium, copper, etc., or an alloy or a laminate of the above metals, but the present invention is not limited thereto. In some embodiments, the material of the connector AF includes anisotropic conductive film (ACF).

In some embodiments, the display device 10 includes three display structures as shown in FIG. 1B . The three display structures may be stacked in a vertical direction, and the overlapping regions of the first electrode 130 and the second electrode 140 in the three display structures overlap each other. In addition, the display medium molecules of the display medium layer 170 in each display structure may be adjusted so that the reflected light wavelengths of the display medium layer 170 in each display structure are different. In this way, the overlapping area of the first electrode 130 and the second electrode 140 in each display structure can be used as a sub-pixel of the display device 10, and the overlapping sub-pixels in the three display structures can constitute a pixel of the display device 10, so that the display device 10 can achieve full color with a "superimposed" primary color system.

In the following, other embodiments of the present invention are further described using FIGS. 2A to 9 , and the component numbers and related contents of the embodiments of FIGS. 1A to 1D are used, wherein the same numbers are used to represent the same or similar components, and the description of the same technical contents is omitted. For the description of the omitted parts, reference can be made to the embodiments of FIGS. 1A to 1D , and they will not be repeated in the following description.

FIG. 2A to FIG. 6B are cross-sectional schematic diagrams of the steps of the manufacturing method of the first electrode 130 of the display device 10 according to an embodiment of the present invention. In FIG. 2A to FIG. 6B, FIG. 2B is a cross-sectional schematic diagram taken along the section line B-B' of FIG. 2A; FIG. 3B is a cross-sectional schematic diagram taken along the section line C-C' of FIG. 3A; FIG. 4B is a cross-sectional schematic diagram taken along the section line D-D' of FIG. 4A; FIG. 5B is a cross-sectional schematic diagram taken along the section line E-E' of FIG. 5A; and FIG. 6B is a cross-sectional schematic diagram taken along the section line F-F' of FIG. 6A.

First, referring to FIG. 2A and FIG. 2B , a first conductive layer 150 is formed on a first substrate 110. The first conductive layer 150 may include a plurality of first conductive lines 152, and the plurality of first conductive lines 152 are separated from each other. In some embodiments, the plurality of first conductive lines 152 extend in parallel with each other in the same direction. In some embodiments, a plurality of pads PD1 and a plurality of pads PD21 may also be formed on the first substrate 110, and the plurality of first conductive lines 152 are respectively connected to the plurality of pads PD1.

3A and 3B, an insulating layer I11 is formed on the first conductive layer 150 and the first substrate 110. The insulating layer I11 may have a plurality of through holes V1, and the plurality of through holes V1 overlap, for example, an odd number of first conductive lines 152, so that a portion of the odd number of first conductive lines 152 is exposed.

Next, referring to FIG. 4A and FIG. 4B , a first lower electrode pattern layer 131 is formed on the insulating layer I11. The first lower electrode pattern layer 131 may include a plurality of first lower electrode patterns E1B, and the plurality of first lower electrode patterns E1B respectively overlap a plurality of through holes V1 of the insulating layer I11, so that the plurality of first lower electrode patterns E1B can be electrically connected to an odd number of first conductive lines 152 through the through holes V1.

Next, referring to FIG. 5A and FIG. 5B , an insulating layer I12 is formed on the first lower electrode pattern layer 131 and the insulating layer I11. Next, a plurality of through holes V2 are formed penetrating the insulating layer I11 and the insulating layer I12, and the plurality of through holes V2 overlap the even-numbered first conductive wires 152, respectively, so that a portion of the even-numbered first conductive wires 152 is exposed. In some embodiments, when the plurality of through holes V1 of the insulating layer I11 expose the even-numbered first conductive wires 152, respectively, the plurality of through holes V2 expose the odd-numbered first conductive wires 152, respectively.

In some embodiments, multiple through holes V3 may be formed while multiple through holes V2 are formed, and the multiple through holes V3 penetrate the insulating layer I11 and the insulating layer I12, and the multiple through holes V3 overlap the multiple pads PD1 and the multiple pads PD21, respectively. In other words, the multiple through holes V3 expose the multiple pads PD1 and the multiple pads PD21, respectively.

Next, referring to FIG. 6A and FIG. 6B , a first upper electrode pattern layer 132 is formed on the insulating layer I12 . The first upper electrode pattern layer 132 may include a plurality of first upper electrode patterns E1T, and the plurality of first upper electrode patterns E1T respectively overlap a plurality of through holes V2 , so that the plurality of first upper electrode patterns E1T can be electrically connected to an even number of first conductive lines 152 through the through holes V2 .

In some embodiments, one side of the first upper electrode pattern E1T may partially overlap the corresponding first lower electrode pattern E1B as needed, and the distance between the other side of the first upper electrode pattern E1T not overlapping the first lower electrode pattern E1B and the adjacent first lower electrode pattern E1B may be less than 10 μm. For example, by adjusting the relative positions of the mask used to form the first upper electrode pattern E1T and the mask used to form the first lower electrode pattern E1B, it is possible to easily make the minimum distance between the other side of the first upper electrode pattern E1T that does not overlap the first lower electrode pattern E1B and the non-overlapping first lower electrode pattern E1B less than 10μm, for example, this minimum distance is about 2μm to 5μm, thereby reducing the ineffective area of each sub-pixel.

In some embodiments, the manufacturing method of the second electrode 140 is similar to the manufacturing method of the first electrode 130 described above, and will not be repeated here.

In some embodiments, a driving element 181 and a driving element 182 may also be disposed on the first substrate 110, and the plurality of pins PN1 of the driving element 181 may respectively pass through the plurality of through holes V3 to be electrically connected to the plurality of pads PD1, and the plurality of pins PN2 of the driving element 182 (please refer to FIG. 1B ) may also respectively pass through the plurality of through holes V3 to be electrically connected to the plurality of pads PD21.

FIG. 7 is a top view schematic diagram of a first substrate 110, a first electrode 130, a first conductive layer 750, and a driving element 181 according to another embodiment of the present invention. Compared with the first conductive layer 150 shown in FIG. 1C, the first conductive layer 750 shown in FIG. 7 is different mainly in that: the plurality of first conductive lines 752 of the first conductive layer 750 further extend below the plurality of first lower electrode patterns E1B and the plurality of first upper electrode patterns E1T of the first electrode 130, respectively, so as to speed up the signal transmission speed of the first lower electrode pattern E1B and the first upper electrode pattern E1T, thereby reducing the signal delay of each sub-pixel. In some embodiments, the line width W9 of the first conductive line 752 is 5 μm to 10 μm.

FIG8 is a top view schematic diagram of the second substrate 120, the second electrode 140, and the second conductive layer 860 according to another embodiment of the present invention. Compared with the second conductive layer 160 shown in FIG1D, the second conductive layer 860 shown in FIG8 is different mainly in that the plurality of second conductive lines 862 of the second conductive layer 860 also extend below the plurality of second lower electrode patterns E2B and the plurality of second upper electrode patterns E2T of the second electrode 140, respectively, so as to speed up the signal transmission speed of the second lower electrode patterns E2B and the second upper electrode patterns E2T, thereby reducing the signal delay of each sub-pixel. In some embodiments, the line width W10 of the second conductive line 862 is 5 μm to 10 μm.

FIG9 is a cross-sectional schematic diagram of a display device 20 according to an embodiment of the present invention. The display device 20 includes: a first substrate 110, a second substrate 120, a first electrode 130, a second electrode 140, a display medium layer 170, a driving element 182, pads PD21, PD22, connectors AF, and insulating layers I11, I12, I21, and I22, wherein the first electrode 130 includes a first lower electrode pattern layer 131 and a first upper electrode pattern layer 132, and the first lower electrode pattern layer 130 includes a first lower electrode pattern layer 131 and a first upper electrode pattern layer 132. The first electrode pattern layer 131 includes a plurality of first lower electrode patterns E1B, and the first upper electrode pattern layer 132 includes a plurality of first upper electrode patterns E1T; the second electrode 140 includes a second lower electrode pattern layer 141 and a second upper electrode pattern layer 142, the second lower electrode pattern layer 141 includes a plurality of second lower electrode patterns E2B, and the second upper electrode pattern layer 142 includes a plurality of second upper electrode patterns E2T.

Compared with the display device 10 shown in FIG. 1B , the display device 20 shown in FIG. 9 is different mainly in that the insulating layer I12 of the display device 20 only covers the portion of the first lower electrode pattern E1B that overlaps with the first upper electrode pattern E1T to achieve electrical separation of the first lower electrode pattern E1B and the first upper electrode pattern E1T. In some embodiments, the insulating layer I12 includes a plurality of strip-shaped insulating patterns IP separated from each other. In some embodiments, the extension direction of the plurality of strip-shaped insulating patterns IP is parallel to the extension direction of the first lower electrode pattern E1B and the first upper electrode pattern E1T. In some embodiments, each strip-shaped insulating pattern IP partially overlaps the corresponding first lower electrode pattern E1B, and each strip-shaped insulating pattern IP partially overlaps the corresponding first upper electrode pattern E1T.

In summary, the display device of the present invention increases the ratio of the effective area where the first electrode and the second electrode overlap with each other to the ineffective area where the first electrode and the second electrode do not overlap with each other by reducing the minimum distance between the first upper electrode pattern and the non-overlapping first lower electrode pattern, and reducing the minimum distance between the second upper electrode pattern and the non-overlapping second lower electrode pattern, thereby improving the reflectivity of the display device.

Although the present invention has been disclosed as above by the embodiments, they are not intended to limit the present invention. Any person with ordinary knowledge in the relevant technical field can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be defined by the scope of the attached patent application.

10, 20: display device 110: first substrate 111: surface 120: second substrate 121: surface 130: first electrode 131: first lower electrode pattern layer 132: first upper electrode pattern layer 140: second electrode 141: second lower electrode pattern layer 142: second upper electrode pattern layer 150, 750: first conductor layer 152, 752: first conductor 160, 860: second conductor layer 162, 862: second conductor 170: display medium layer 181, 182: driving element A-A’, B-B’, C-C’, D-D’, E-E’, F-F’: section line AF: connector D1: first direction D2: second direction E1B: first lower electrode pattern E1T: first upper electrode pattern E2B: second lower electrode pattern E2T: second upper electrode pattern G1, G2, G3, G4: gap I11, I12, I21, I22: insulation layer IP: strip insulation pattern PD1, PD21, PD22: pad PN1, PN2: pin S1, S2, S3, S4: side V1, V2, V3: through hole W1, W2, W3, W5, W6, W7: width W4, W8: spacing

FIG. 1A is a three-dimensional schematic diagram of a display device 10 according to an embodiment of the present invention. FIG. 1B is a cross-sectional schematic diagram taken along the section line A-A' of FIG. 1A. FIG. 1C is a top view schematic diagram of the first substrate 110, the first electrode 130, and the first conductive layer 150 of the display device 10 of FIG. 1A. FIG. 1D is a top view schematic diagram of the second substrate 120, the second electrode 140, and the second conductive layer 160 of the display device 10 of FIG. 1A. FIG. 2A to FIG. 6B are cross-sectional schematic diagrams of the step flow of the manufacturing method of the first electrode 130 of the display device 10 according to an embodiment of the present invention. FIG. 7 is a top view schematic diagram of the first substrate 110, the first electrode 130, the first conductive layer 750, and the driving element 181 according to another embodiment of the present invention. FIG8 is a top view schematically showing the second substrate 120, the second electrode 140 and the second conductive layer 860 according to another embodiment of the present invention. FIG9 is a cross-sectional schematic diagram of a display device 20 according to an embodiment of the present invention.

10: Display device

110: First substrate

111: Surface

120: Second substrate

121: Surface

130: First electrode

131: First lower electrode pattern layer

132: First upper electrode pattern layer

140: Second electrode

141: Second lower electrode pattern layer

142: Second upper electrode pattern layer

170: Display media layer

182: Driving element

AF: Connectors

D1: First direction

D2: Second direction

E1B: The first lower electrode pattern

E1T: first upper electrode pattern

E2B: Second lower electrode pattern

E2T: Second upper electrode pattern

G1: Gap

I11, I12, I21, I22: Insulation layer

PD21,PD22: pad

PN2: Pin

W1: Width

Claims (12)

A display device comprises: a first substrate; a first conductor layer, located on the first substrate and comprising a plurality of first conductors; a first electrode, located on the first substrate and comprising a plurality of first lower electrode patterns and a plurality of first upper electrode patterns, which are electrically separated from each other, wherein the plurality of first lower electrode patterns and the plurality of first upper electrode patterns are respectively electrically connected to the plurality of first conductors, and there are a plurality of first gaps between the plurality of first lower electrode patterns, and the plurality of first upper electrode patterns respectively overlap the plurality of first gaps; a second substrate, wherein the first conductor layer and the first electrode are located between the first substrate and the second substrate; a display medium layer, located between the first electrode and the second substrate; and a second electrode, located between the display medium layer and the second substrate. A display device as described in claim 1, wherein the plurality of first conductive lines are electrically independent of each other. A display device as described in claim 1, wherein the plurality of first lower electrode patterns are separated from each other. A display device as described in claim 1, wherein the plurality of first upper electrode patterns are separated from each other. The display device as described in claim 1, wherein the plurality of first lower electrode patterns and the plurality of first upper electrode patterns extend in the same direction. The display device as described in claim 1, wherein the overlapping width of the first lower electrode pattern and the first upper electrode pattern is 1.5 μm to 3 μm. The display device as described in claim 1, wherein the potentials of the first upper electrode pattern and the first lower electrode pattern overlapping each other are different. The display device as described in claim 1, wherein a distance between adjacent first lower electrode patterns and first upper electrode patterns is greater than 0 and less than 10 μm. The display device as described in claim 1, wherein the second electrode includes a plurality of second lower electrode patterns, and an extension direction of the plurality of second lower electrode patterns is perpendicular to an extension direction of the plurality of first lower electrode patterns. The display device as described in claim 9, wherein the second electrode further includes a plurality of second upper electrode patterns, and the plurality of second upper electrode patterns extend in the same direction as the plurality of second lower electrode patterns. A display device as described in claim 10, wherein there are multiple second gaps between the multiple second lower electrode patterns, and the multiple second upper electrode patterns overlap the multiple second gaps respectively. The display device as described in claim 10 further includes a second conductive layer located between the second substrate and the display medium layer, and includes a plurality of second conductive lines, wherein the plurality of second lower electrode patterns and the plurality of second upper electrode patterns are electrically connected to the plurality of second conductive lines respectively.

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