TWI822016B - Display device - Google Patents

Abstract

A display device includes a display area and a periphery area surrounding the display area. The display device includes an IC driver substrate, a TFT substrate, a front plane laminate, and multiple conductive wires. The IC driver substrate includes multiple first conductive pads. The TFT substrate includes multiple second conductive pads. The TFT substrate is located on the IC driver substrate. The TFT substrate is located between the IC driver substrate and the front plane laminate. The conductive wires are electrically connected with the first conductive pads and the second conductive pads, respectively. The first conductive pads and the second conductive pads are located in the periphery region.

Description

display device

The present disclosure relates to a display device and a driving circuit structure.

The signal lines (such as data lines and selection lines) in today's display panels will be concentrated on the same side of the panel, that is, to the bonding area in the peripheral area, and then use the chip on film (COF) method. , electrically connecting the signal lines to the driving integrated circuit (IC) located on the flexible substrate. The above-mentioned method of joining the driving integrated circuit and the design of the signal circuit will have a joining area that significantly protrudes from the surrounding area, which will limit the outline of the display device to the design of the protruding joining area.

In view of this, how to provide a display device that can solve the above problems is still a research and development goal in this field.

One technical aspect of the present disclosure is a display device.

In an embodiment of the present disclosure, a display device has a display area and a peripheral area surrounding the display area. The display device includes a driving circuit substrate, a thin film transistor array substrate, a front panel stack, and a plurality of conductive lines. The driving circuit substrate includes a plurality of first conductive pads. The thin film transistor array substrate includes a plurality of second conductive pads. The thin film transistor array substrate is located on the drive circuit substrate. The thin film transistor array substrate is located between the drive circuit substrate and the front panel stack. The plurality of conductive lines are electrically connected to the first conductive pad and the second conductive pad respectively, where the first conductive pad and the second conductive pad are distributed in the peripheral area.

In an embodiment of the present disclosure, the vertical projection of the thin film transistor array substrate on the driving circuit substrate does not overlap the first conductive pad.

In an embodiment of the present disclosure, the area of the driving circuit substrate is larger than the area of the thin film transistor array substrate.

In an embodiment of the present disclosure, the first conductive pad surrounds the thin film transistor array substrate.

In an embodiment of the present disclosure, the first conductive pad is located on a surface of the driving circuit substrate facing the thin film transistor array substrate.

In an embodiment of the present disclosure, the second conductive pad is stacked around the front panel.

In an embodiment of the present disclosure, the driving circuit substrate, the thin film transistor array substrate and the front panel are stacked in an arc shape.

In an embodiment of the present disclosure, the thin film transistor array substrate further includes a plurality of data lines extending in the first direction. The data lines are electrically connected to a portion of the second conductive pad, and this portion of the second conductive pad Located at opposite sides of the display device in the first direction.

In an embodiment of the present disclosure, the thin film transistor array substrate further includes a plurality of scan lines extending in the second direction. The scan lines are electrically connected to a portion of the second conductive pads, and this portion of the second conductive pads Located at opposite sides of the display device in the second direction.

In an embodiment of the present disclosure, the thin film transistor array substrate further includes a plurality of selection lines extending in the second direction. The selection lines are electrically connected to a portion of the second conductive pad, and this portion of the second conductive pad Located at opposite sides of the display device in the second direction.

In an embodiment of the present disclosure, the driving circuit substrate further includes a first pattern, and the thin film transistor array substrate further includes a second pattern paired with the first pattern.

Another technical aspect of the present disclosure is a display device.

In an embodiment of the present disclosure, the display device has a display area and a peripheral area surrounding the display area. The display device includes a driving circuit substrate, a thin film transistor array substrate, a front panel stack, and a plurality of conductive lines. The drive circuit substrate includes a plurality of first conductive pads and a driver connection area, where the driver connection area is located on one side of the drive circuit substrate. The thin film transistor array substrate includes a plurality of second conductive pads, wherein the thin film transistor array substrate is located on the driving circuit substrate. The thin film transistor array substrate is located between the drive circuit substrate and the front panel stack. The conductive lines are electrically connected to the first conductive pad and the second conductive pad respectively. Viewed from a bird's eye view, the side edges of the driving circuit substrate are located within an edge formed by the driving circuit substrate and the thin film transistor array substrate.

In an embodiment of the present disclosure, the driving circuit substrate further includes a plurality of first driving lines, and opposite ends of each first driving line are electrically connected to one of the first conductive pads and the driver connection area respectively.

In an embodiment of the present disclosure, the driving circuit substrate further includes a plurality of second driving lines, and opposite ends of each second driving line are electrically connected to one of the first conductive pads and the driver connection area respectively.

In an embodiment of the present disclosure, the driving circuit substrate further includes a plurality of third driving lines, and opposite ends of each third driving line are electrically connected to one of the first conductive pads and the driver connection area respectively.

In an embodiment of the present disclosure, the driving circuit substrate further includes a plurality of common voltage lines, and opposite ends of each common voltage line are electrically connected to the driver connection area and to at least one of the first conductive pads respectively.

In an embodiment of the present disclosure, one of the first conductive pads is electrically connected to more than one of the common voltage lines.

In an embodiment of the present disclosure, the first conductive pad and the second conductive pad are distributed in the peripheral area.

In an embodiment of the present disclosure, the edges formed by the drive circuit substrate, the thin film transistor array substrate and the front panel stack are arc-shaped.

Another technical aspect of the present disclosure is a driving circuit structure.

In an embodiment of the present disclosure, the driving circuit structure includes a driving circuit substrate and a thin film transistor array substrate. The drive circuit substrate includes a driver connection area, wherein the driver connection area is located on one side of the drive circuit substrate. The thin film transistor array substrate is located on the drive circuit substrate, and when viewing the drive circuit structure from a bird's eye view, the side of the drive circuit substrate is within an edge formed by the drive circuit substrate and the thin film transistor array substrate.

In the above embodiments, the display device of the present disclosure stacks the thin film transistor array substrate and the driving circuit substrate, and distributes the first conductive pads and the second conductive pads evenly in the peripheral area (equivalent to making the first bonding area and the second conductive pad The two joint areas surround the display area), which can avoid setting a joint area that obviously protrudes from the surrounding area. Taking this embodiment as an example, such a design can prevent the outline of the display panel from being affected by the protruding joint area. In addition, selecting to electrically connect the signal lines to different second conductive pads according to the extension direction of the signal lines can reduce the length of the traces and reduce the probability of interlacing traces.

A plurality of embodiments of the present invention will be disclosed in the drawings below. For clarity of explanation, many practical details will be explained in the following description. However, it will be understood that these practical details should not limit the invention. That is to say, in some embodiments of the present invention, these practical details are not necessary. In addition, for the sake of simplifying the drawings, some commonly used structures and components will be illustrated in a simple schematic manner in the drawings. Also, the thicknesses of layers and regions in the drawings may be exaggerated for clarity, and like reference numbers refer to the same elements in the description of the drawings.

Figure 1 is a top view of a display device 100 according to an embodiment of the present disclosure. Figure 2 is a cross-sectional view along line segment 2-2 in Figure 1. Refer to Figure 1 and Figure 2 at the same time. The display device 100 has a display area AA and a peripheral area PA surrounding the display area AA. The display device 100 includes a driving circuit substrate 110, a thin film transistor (TFT) array substrate 120, and a front panel laminate (FPL) 130. The thin film transistor array substrate 120 is located on the driving circuit substrate 110 , and the front panel stack 130 is located on the thin film transistor array substrate 120 . The thin film transistor array substrate 120 is located between the driving circuit substrate 110 and the front panel stack 130 .

For example, the display device 100 is a clock, and the driving circuit substrate 110 integrates an integrated circuit driver (IC Driver) and system components used in the clock, such as motors, batteries, etc. The thin film transistor array substrate 120 includes a glass substrate, and structures such as gates, drains/sources, insulating layers, and pixel electrodes formed on the glass substrate (not shown). The front panel stack 130 includes, for example, a display medium layer, a transparent conductive film or an adhesive layer (not shown), but the disclosure is not limited thereto. For example, the display medium layer may be a liquid crystal display layer or an electronic ink layer.

Refer to Figure 1 and Figure 2 at the same time. The overall outline of the stacked driving circuit substrate 110 and the thin film transistor array substrate 120 is substantially circular. From the top view of FIG. 1 , the driving circuit substrate 110 and the thin film transistor array substrate 120 together form an edge 1002 . The driving circuit substrate 110, the thin film transistor array substrate 120 and the front panel stack 130 are all arc-shaped, but the disclosure is not limited thereto. In other embodiments, display device 100 may be rectangular. The area of the driving circuit substrate 110 is larger than the area of the thin film transistor array substrate 120 , and the area of the thin film transistor array substrate 120 is larger than the area of the front panel stack 130 .

Figure 3 is an enlarged view of the framed area A in Figure 1. Refer to Figures 2 and 3 at the same time. The driving circuit substrate 110 includes a plurality of first conductive pads 112 , and the thin film transistor array substrate 120 includes a plurality of second conductive pads 122 . The first conductive pads 112 and the second conductive pads 122 are evenly distributed in the peripheral area PA. In other words, the first conductive pad 112 and the second conductive pad 122 surround the display area AA. The conductive lines 140 are electrically connected to the first conductive pad 112 and the second conductive pad 122 respectively. The connection method of the conductive lines 140 is not limited to the connection method in Figure 2. In another embodiment of the present invention, a conductive via hole is formed on the thin film transistor array substrate 120 corresponding to the second conductive pad 122, and a conductive via hole is formed in the conductive via hole. The conductive line 140 is connected to the first conductive pad 112, that is, the first conductive pad 112 and the second conductive pad 122 are electrically connected.

Refer to Figure 3. The display device 100 also includes a plurality of conductive lines 140 . For clarity of illustration, the conductive lines 140 are omitted in FIG. 1 . The conductive lines 140 are electrically connected to the first conductive pad 112 and the second conductive pad 122 respectively. The signal lines in the thin film transistor array substrate 120 are connected to the second conductive pads 122, and a part of the second conductive pads 122 may be selectively not connected to the signal lines. In other words, a part of the first conductive pads 112 is a dummy first conductive pad 112', and a part of the second conductive pad 122 is a dummy second conductive pad 122'. The dummy first conductive pad 112' and the dummy second conductive pad 122' are not configured for signal transmission. Through such a design, the spacing between the first conductive pad 112 and the dummy first conductive pad 112' can be made more even, and the spacing between the second conductive pad 122 and the dummy second conductive pad 122' can be made more even.

Refer to Figures 2 and 3 at the same time. The vertical projection of the thin film transistor array substrate 120 on the driving circuit substrate 110 does not overlap with the first conductive pad 112 . In other words, the first conductive pad 112 surrounds the thin film transistor array substrate 120 . The vertical projection of the front panel stack 130 on the thin film transistor array substrate 120 does not overlap with the second conductive pad 122 , that is, the second conductive pad 122 surrounds the front panel stack 130 . The first conductive pad 112 is located on the surface 114 of the driving circuit substrate 110 facing the thin film transistor array substrate, and the second conductive pad 122 is located on the surface 124 of the thin film transistor array substrate 120 facing the front panel stack 130 .

The display device 100 of the present disclosure stacks the thin film transistor array substrate 120 and the driving circuit substrate 110 and distributes the first conductive pads 112 and the second conductive pads 122 evenly in the peripheral area PA, thereby avoiding the need to significantly protrude from the peripheral area PA. joint area. Taking the embodiment in FIG. 1 as an example, such a design can make the shape of the thin film transistor array substrate 120 closer to a circle, that is, the outline of the display device 100 is not affected by the protruding bonding area.

FIG. 4 is a schematic diagram of the bonding area of the display device 100 of FIG. 1 . For clarity of illustration, the conductive line 140 is omitted in FIG. 4 . Refer to Figure 1 and Figure 4 at the same time. The driving circuit substrate 110 includes a first bonding area 116 in which the first conductive pads 112 are evenly distributed. The thin film transistor array substrate 120 includes a second bonding area 126, and the second conductive pads 122 are evenly distributed in the second bonding area 126. In other words, the design in which the first conductive pads 112 and the second conductive pads 122 are evenly distributed in the peripheral area PA can also be regarded as arranging the first bonding area 116 and the second bonding area 126 in the peripheral area PA of the display device 100 , and the first joint area 116 and the second joint area 126 surround the display area AA. The outline of the thin film transistor array substrate 120 in Figure 4 is just another embodiment of the present invention, and the present invention is not limited thereto.

As shown in FIG. 4 , the vertical projection of the second bonding area 126 on the driving circuit substrate 110 is between the first bonding area 116 and the display area AA. The second bonding area 126 surrounds the vertical projection of the front panel stack 130 on the thin film transistor array substrate 120 . In other words, the vertical projection of the front panel stack 130 on the thin film transistor array substrate 120 is within the range surrounded by the second bonding area 126 . In this embodiment, the first joint area 116 and the second joint area 126 are annular. In other embodiments, the shapes of the first bonding area 116 and the second bonding area 126 are determined according to the overall outline of the display device 100 .

Based on the above, it can be seen that the display device 100 of the present disclosure stacks the thin film transistor array substrate 120 and the driving circuit substrate 110 so that the first bonding area 116 and the second bonding area 126 surround the display area AA, thereby avoiding a configuration that obviously protrudes from the surrounding area PA. joint area. Such a design can prevent the outline of the display device 100 from being affected by the protruding bonding area.

FIG. 5 is a schematic diagram of a portion of the signal circuit of the thin film transistor array substrate 120 according to an embodiment of the present disclosure. The signal lines of the thin film transistor array substrate 120 include a plurality of data lines 128A extending in the first direction D1. In this embodiment, the thin film transistor array substrate 120 has 240 data lines 128A, and the plurality of data lines 128A extend to the second conductive pads 122 corresponding to a part of the four regions S1 to S4. FIG. 5 only illustrates a portion of the data line 128A and four corresponding second conductive pads 122 respectively located in the regions S1 to S4. The areas S1 to S4 are located at opposite sides of the second bonding area 126 in the first direction D1. In other words, the distribution positions of the areas S1 to S4 in the second bonding area 126 are determined according to the extending direction of the data line 128A. In this way, the length of the trace electrically connecting the data line 128A to the second conductive pad 122 can be reduced, and it is possible to avoid concentrating all the signal lines in the same place to create a bonding area that significantly protrudes from the peripheral area PA.

FIG. 6 is a schematic diagram of another part of the signal circuit of the thin film transistor array substrate 120 of FIG. 5 . In this embodiment, the thin film transistor array substrate 120 is divided into 24 blocks. Blocks B1, B9, B12, B13, and B24 are marked in Figure 6 only as examples. Each block includes 20 scan lines 128B extending in the second direction D2. FIG. 6 shows only a part of the scan lines 128B of the block B9 as an example, and the scan lines 128B in other blocks are omitted. The scan lines 128B in each block are electrically connected to each other and then jointly electrically connected to the second conductive pads 122 in a part of the four regions S5 to S8. As shown in FIG. 6 , the regions S5 and S6 each include 10 second conductive pads 122 , and the regions S7 and S8 each include 2 second conductive pads 122 . Regions S5 to S8 are located at opposite sides of the second bonding area 126 in the second direction D2. In this way, the length of the traces electrically connecting the scan line 128B to the second conductive pad 122 can be reduced, and it is possible to avoid concentrating all the signal lines at the same place to create a bonding area that significantly protrudes from the peripheral area PA.

FIG. 7 is a schematic diagram of another part of the signal circuit of the thin film transistor array substrate 120 of FIG. 5 . The thin film transistor array substrate 120 includes a plurality of selection lines 128C extending in the second direction D2. In this embodiment, each selection line 128C is electrically connected to the aforementioned 24 blocks. The plurality of selection lines 128C extend to a portion of the second conductive pads 122 in two different regions S9-S10. FIG. 7 shows two selection lines 128C and two second conductive pads 122 located in areas S9 to S10 by way of example only. Regions S9 to S10 are located at opposite sides of the second bonding area 126 in the second direction D2. In this way, the trace length of the selection line 128C that is electrically connected to the second conductive pad 122 can be reduced, and it is possible to avoid concentrating all the signal lines in the same place to create a bonding area that significantly protrudes from the peripheral area PA.

Referring to FIGS. 5 to 7 at the same time, it can be seen that the aforementioned multiple areas S1 to S10 are scattered in the peripheral area PA of the display device 100 , and the areas S1 to S10 are staggered from each other. In this way, the signal lines of the display device 100 can be dispersedly connected to the second conductive pads 122 evenly distributed in the peripheral area PA. In addition, by choosing to electrically connect the signal lines to different second conductive pads 122 according to the extension direction of the signal lines, the length of the traces can be reduced and the probability of interlacing traces can be reduced. In the above embodiment, the relative positions of the areas S1 to S10 can be changed as long as it can have the technical effect of reducing the trace length and reducing trace interleaving.

FIG. 8 is a schematic diagram of a part of the signal circuit of the driving circuit substrate 110 according to an embodiment of the present disclosure. The drive circuit substrate 110 has a driver connection area 1102, and the driver connection area 1102 is located on the side 1104 of the drive circuit substrate 110. In this embodiment, the sides 1104 are flush. In other words, from the top view in FIG. 8 , the side 1104 of the driving circuit substrate 110 is located within the edge 1002 formed by the driving circuit substrate 110 and the thin film transistor array substrate 120 , that is, the side 1104 is between the thin film transistor array substrate 110 and the thin film transistor array substrate 120 . The projection of the crystal array substrate 120 will be located inside the edge 1002 of the projection of the thin film transistor array substrate 120 . Such a design can make the shape of the thin film transistor array substrate 120 closer to a circle, that is, the outline of the display device 100 will not be affected by the protruding bonding area. The driving integrated circuit of the driving circuit substrate 110 can be disposed in the driver connection area 1102, or can be electrically connected to the driving integrated circuit disposed on the flexible substrate through flip-chip film bonding.

The signal lines of the driving circuit substrate 110 include a plurality of first driving lines 118A. FIG. 8 only shows four first driving lines 118A by way of example. Opposite ends of the first driving line 118A are electrically connected to the driver connection area 1102 and a portion of the first conductive pad 112 respectively. In this embodiment, the first driving line 118A of the driving circuit substrate 110 corresponds to the data line 128A of the thin film transistor array substrate 120 shown in FIG. 5 . In other words, the four first driving lines 118A in FIG. 8 are electrically connected to the second conductive pads 122 and the data lines 128A located in the regions S1 to S4 through the first conductive pads 112 .

Please refer to Figure 8 and Figure 1 for the drive circuit structure of another embodiment of the present invention. The drive circuit structure is composed of a drive circuit substrate 110 and a thin film transistor array substrate 120. The drive circuit substrate 110 includes a driver connection area. 1102, and the driver connection area 1102 is located on the side 1104 of the drive circuit substrate 110, the thin film transistor array substrate 120 is located on the drive circuit substrate 110, and when viewing the above drive circuit structure from a top view, the drive circuit substrate 110 The side 1104 is located within an edge 1002 formed by the driving circuit substrate 110 and the thin film transistor array substrate 120 .

Figure 9 is a schematic diagram of another part of the signal circuit of the drive circuit substrate in Figure 8. The signal lines of the driving circuit substrate 110 include a plurality of second driving lines 118B. FIG. 9 shows two second driving lines 118B by way of example only. Opposite ends of the second driving line 118B are electrically connected to the driver connection area 1102 and a portion of the first conductive pad 112 respectively. In this embodiment, the second driving line 118B of the driving circuit substrate 110 corresponds to the scanning line 128B of the thin film transistor array substrate 120 shown in FIG. 6 . The two second driving lines 118B in Figure 9 are electrically connected to the second conductive pads 122 and the scan lines 128B located in the regions S5 to S6 through the first conductive pads 112.

Figure 10 is a schematic diagram of another part of the signal circuit of the drive circuit substrate in Figure 8. The signal lines of the driving circuit substrate 110 include a plurality of third driving lines 118C. FIG. 10 shows two third driving lines 118C by way of example only. Opposite ends of the third driving line 118C are electrically connected to the driver connection area 1102 and a portion of the first conductive pad 112 respectively. In this embodiment, the third driving line 118C of the driving circuit substrate 110 corresponds to the selection line 128C of the thin film transistor array substrate 120 shown in FIG. 7 . The two third driving lines 118C in Figure 10 are electrically connected to the second conductive pads 122 and the selection lines 128C located in the regions S9-S10 through the first conductive pads 112.

Figure 11 is a schematic diagram of another part of the signal circuit of the drive circuit substrate in Figure 8. The signal lines of the driving circuit substrate 110 include a plurality of common voltage lines 118D. Opposite ends of the common voltage line 118D are electrically connected to the driver connection area 1102 and a portion of the first conductive pad 112 respectively. In this embodiment, each common voltage line 118D is electrically connected to at least one first conductive pad 112 . The first conductive pad 112 may be electrically connected to more than one of the common voltage lines 118D. In other words, the electrical connection between the first conductive pad 112 and the common voltage line 118D is not limited to a one-to-one electrical connection. For example, as shown in FIG. 11 , loop lines with different voltage values can be extended and connected to the same first conductive pad 112 .

Referring to Figures 8 to 11 at the same time, it can be seen that the first driving line 118A, the second driving line 118B, and the third driving line 118C correspond to the multiple areas S1 to S10 of the aforementioned Figures 5 to 7, so that are scattered in the peripheral area PA of the display device 100, and the areas S1 to S10 are staggered from each other. In this way, the signal lines of the display device 100 can be connected to the first conductive pads 112 and the second conductive pads 122 evenly distributed in the peripheral area PA. FIG. 12A is a schematic diagram of an alignment mark 150 according to an embodiment of the present disclosure. Refer also to Figure 1 and Figure 12A. The display device 100 includes a central area C, and the alignment mark 150 is disposed in the central area C. The alignment mark 150 is composed of a first pattern 152 and a second pattern 154 , and the second pattern 154 is configured to match the first pattern 152 . The first pattern 152 and the second pattern 154 may be formed on the driving circuit substrate 110 and the thin film transistor array substrate 120 at positions corresponding to the central region C, respectively. When the driving circuit substrate 110 and the thin film transistor array substrate 120 are stacked, the alignment marks 150 can be used for alignment. The above-mentioned first pattern 152 is a rectangular frame, and the second pattern 154 is a cross shape, but the disclosure is not limited thereto.

FIG. 12B is a schematic diagram of an alignment mark 150 according to another embodiment of the present disclosure. In this embodiment, the alignment mark 150 can also be disposed close to the first conductive pad 112 and the second conductive pad 122, such as the framed area A in Figure 1. In other embodiments, the display device 100 includes a plurality of alignment marks 150 to achieve alignment in the first direction D1 and the second direction D2. In other embodiments, the alignment marks may be composed of two sets of ruler and compass marks, and the ruler and compass marks may be arranged along the first direction D1 or the second direction D2 to achieve alignment in the first direction D1 and the second direction D2 .

Figures 13A to 13C are schematic diagrams of alignment marks 150a according to another embodiment of the present disclosure. The alignment mark 150a includes a first pattern 152a and a second pattern 154a. The first pattern 152a and the second pattern 154a are formed on the driving circuit substrate 110 and the thin film transistor array substrate 120 respectively. In this embodiment, the first patterns 152a and the first conductive pads 112 are arranged in a ring shape, and the second patterns 154a and the second conductive pads 122 are arranged in a ring shape. In other words, the first pattern 152a may be disposed in the first bonding area 116, and the second pattern 154a may be disposed in the second bonding area 126.

The alignment marks 150a in FIGS. 13A to 13C respectively correspond to the upper right, right and lower right of the display device 100 (see FIG. 1 ). Similarly, the alignment mark 150a can also be disposed at the upper left, left and lower left of the display device 100 . In other words, the display device 100 may include a plurality of first patterns 152a evenly distributed in the first bonding area 116 and a plurality of second patterns 154a evenly distributed in the second bonding area 126, so as to achieve the desired direction in the first direction D1. and alignment in the second direction D2.

In summary, the display device of the present disclosure stacks the thin film transistor array substrate and the driving circuit substrate, and evenly distributes the first conductive pads and the second conductive pads in the peripheral area (equivalent to making the first bonding area and the second The joint area surrounds the display area), which can avoid setting a joint area that obviously protrudes from the surrounding area. This design prevents the outline of the display panel from being affected by the protruding joint area. In addition, selecting to electrically connect the signal lines to different second conductive pads according to the extension direction of the signal lines can reduce the length of the traces and reduce the probability of interlacing traces.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Anyone skilled in the art can make various modifications and modifications without departing from the spirit and scope of the present invention. Therefore, the protection of the present invention is The scope shall be determined by the appended patent application scope.

100:Display device 1002: Edge 110:Drive circuit substrate 1102:Drive connection area 1104:Side 112: First conductive pad 112’: Dummy first conductive pad 114:Surface 116:First joint area 118A: First drive line 118B: Second drive line 118C: Third drive line 118D: Common voltage line 120:Thin film transistor array substrate 122: Second conductive pad 122’: Dummy second conductive pad 124:Surface 126:Second joint area 128A: Data line 128B: Scan line 128C: Select line 130: Front panel stacking 140: Conductive thread 150,150a: Alignment mark 152,152a: first pattern 154,154a: Second pattern AA: display area PA: Surrounding area 2-2: Line segment A: Frame selection area C: Central area D1: first direction D2: second direction B1, B9, B12, B13, B24: blocks S1~S10: area

Figure 1 is a top view of a display device according to an embodiment of the present disclosure. Figure 2 is a cross-sectional view along line segment 2-2 in Figure 1. Figure 3 is an enlarged view of the framed area A in Figure 1. FIG. 4 is a schematic diagram of the bonding area of the display device in FIG. 1 . FIG. 5 is a schematic diagram of a portion of signal circuits of a thin film transistor array substrate according to an embodiment of the present disclosure. Figure 6 is a schematic diagram of another part of the signal circuit of the thin film transistor array substrate in Figure 5. Figure 7 is a schematic diagram of another part of the signal circuit of the thin film transistor array substrate of Figure 5. FIG. 8 is a schematic diagram of a part of the signal circuit of the driving circuit substrate according to an embodiment of the present disclosure. Figure 9 is a schematic diagram of another part of the signal circuit of the drive circuit substrate in Figure 8. Figure 10 is a schematic diagram of another part of the signal circuit of the drive circuit substrate in Figure 8. Figure 11 is a schematic diagram of another part of the signal circuit of the drive circuit substrate in Figure 8. Figure 12A is a schematic diagram of an alignment mark according to an embodiment of the present disclosure. Figure 12B is a schematic diagram of an alignment mark according to another embodiment of the present disclosure. Figures 13A to 13C are schematic diagrams of alignment marks according to another embodiment of the present disclosure.

100:Display panel 1002: Edge 110:Driver substrate 112: First conductive pad 120:Thin film transistor array substrate 122: Second conductive pad 130: Front panel stacking AA: display area PA: Surrounding area 2-2: Line segment A: Frame selection area C: Central area D1: first direction D2: second direction

Claims (16)

A display device having a display area and a peripheral area surrounding the display area, wherein the display device includes: a drive circuit substrate including a plurality of first conductive pads; a thin film transistor array substrate including a plurality of second conductive pads , wherein the thin film transistor array substrate is located on the driving circuit substrate; a front panel stack, wherein the thin film transistor array substrate is located between the driving circuit substrate and the front panel stack; and a plurality of conductive lines, The first conductive pads and the second conductive pads are electrically connected respectively, wherein the first conductive pads and the second conductive pads are distributed in the peripheral area. The display device of claim 1, wherein the vertical projection of the thin film transistor array substrate on the drive circuit substrate does not overlap the first conductive pads. The display device according to claim 1, wherein the area of the driving circuit substrate is larger than the area of the thin film transistor array substrate. The display device of claim 1, wherein the first conductive pads evenly surround the thin film transistor array substrate. The display device of claim 1, wherein the first conductive pads are located between the driving circuit substrate and the thin film transistor array substrate. surface. The display device of claim 1, wherein the second conductive pads are evenly stacked around the front panel. The display device of claim 1, wherein the driving circuit substrate, the thin film transistor array substrate and the front panel are stacked in an arc shape. The display device of claim 1, wherein the thin film transistor array substrate further includes a plurality of data lines extending in a first direction, and the data lines are electrically connected to a portion of the second conductive pads, And the second conductive pads of the portion are located on opposite sides of the display device in the first direction. The display device of claim 1, wherein the thin film transistor array substrate further includes a plurality of scan lines extending in a second direction, and the scan lines are electrically connected to a portion of the second conductive pads, And the second conductive pads of the portion are located on opposite sides of the display device in the second direction. The display device of claim 1, wherein the thin film transistor array substrate further includes a plurality of selection lines extending in a second direction, and the selection lines are electrically connected to a portion of the second conductive pads, And the ministry The second conductive pads are located on opposite sides of the display device in the second direction. The display device of claim 1, wherein the driving circuit substrate further includes a first pattern, and the thin film transistor array substrate further includes a second pattern paired with the first pattern. A display device has a display area and a peripheral area surrounding the display area, wherein the display device includes: a drive circuit substrate including a plurality of first conductive pads and a driver connection area, wherein the driver connection area is located in the drive circuit One side of the substrate; a thin film transistor array substrate including a plurality of second conductive pads, wherein the thin film transistor array substrate is located on the drive circuit substrate; a front panel stack, wherein the thin film transistor array substrate is located on between the drive circuit substrate and the front panel stack; and a plurality of conductive lines electrically connecting the first conductive pads and the second conductive pads respectively; where viewed from a bird's eye view, the drive circuit substrate The side is located within an edge formed by the driving circuit substrate and the thin film transistor array substrate. The display device of claim 12, wherein the driving circuit substrate further includes a plurality of first driving lines, each of the first driving lines Opposite ends of the line are electrically connected to one of the first conductive pads and the driver connection area respectively. The display device of claim 12, wherein the driving circuit substrate further includes a plurality of common voltage lines, and opposite ends of each of the common voltage lines are electrically connected to the driver connection area and to the first ones respectively. At least one of the conductive pads. The display device of claim 14, wherein one of the first conductive pads is electrically connected to a plurality of the common voltage lines. The display device according to claim 12, wherein the edge formed by the driving circuit substrate, the thin film transistor array substrate and the front panel stack is an arc shape.