TWI679779B - Led package structure, chip carrier, and method for manufacturing thereof - Google Patents

Abstract

The invention discloses a light-emitting diode packaging structure, a chip carrier and a manufacturing method thereof. The wafer carrier includes a substrate and an electrode layer disposed on the substrate. The electrode layer includes at least one solid crystal portion. Wherein, a plurality of concave microstructures that are elongated and substantially parallel to each other are formed on one surface of the solid crystal portion.

Description

Light-emitting diode packaging structure, wafer carrier and manufacturing method thereof

The invention relates to a carrier, in particular to a light emitting diode packaging structure, a wafer carrier and a manufacturing method thereof.

The existing wafer carrier includes a substrate and an electrode layer disposed on the substrate, and a solid-crystal portion of the electrode layer can be used to fix at least one light-emitting wafer. However, when the light-emitting wafer is fixed to the solid crystal portion with a solder material, the solder material easily flows out of the solid crystal portion laterally and flows to other parts of the electrode layer, so that there is a problem such as short circuit.

Therefore, the present inventor believes that the above-mentioned defects can be improved, and with special research and cooperation with the application of scientific principles, he finally proposes an invention with a reasonable design and effective improvement of the above-mentioned defects.

The embodiments of the present invention provide a light emitting diode package structure, a wafer carrier and a manufacturing method thereof, which can effectively improve defects that may occur in the existing wafer carrier.

An embodiment of the present invention discloses a wafer carrier including: a substrate; an electrode layer disposed on a plate surface of the substrate, the electrode layer including at least one solid crystal portion; wherein a surface of the solid crystal portion There are formed a plurality of concave microstructures that are elongated and substantially parallel to each other. An embodiment of the present invention also discloses a light emitting diode packaging structure using the above wafer carrier.

Another embodiment of the present invention discloses a method for manufacturing a wafer carrier, which includes: implementing a preparation step: providing a substrate; implementing a patterning step: forming a patterned electrode layer on a surface of the substrate; wherein The electrode layer includes at least one solid crystal portion; and a forming step is performed: a plurality of recessed microstructures that are elongated and substantially parallel to each other are formed on a surface of the solid crystal portion. The embodiment of the present invention also discloses a manufacturing method of a light emitting diode packaging structure using the above wafer carrier.

In summary, the light emitting diode packaging structure disclosed in the embodiments of the present invention, and the wafer carrier and the manufacturing method thereof, can receive a part of the welding material through the recessed microstructure of the electrode layer, so as to prevent the welding material from flowing to The other parts of the electrode layer other than the solid crystal part can effectively reduce the short-circuit problem caused by the welding material.

In order to further understand the features and technical contents of the present invention, please refer to the following detailed description and drawings of the present invention, but these descriptions and drawings are only used to illustrate the present invention, and not to make any limitation to the protection scope of the present invention. limit.

100‧‧‧light emitting diode package structure

1‧‧‧ substrate

11‧‧‧ the first plate

12‧‧‧Second board surface

13‧‧‧ conductive post

2‧‧‧ electrode layer

2a‧‧‧copper

2b‧‧‧metal plating

21‧‧‧The first metal pad

211‧‧‧Wire line department (function department)

211-1‧‧‧First Wire Division

212‧‧‧First extension

2121‧‧‧L-shaped slot

213‧‧‧The first welding department

22‧‧‧Second metal pad

221‧‧‧Solid Crystal Department (Functional Department)

221-2‧‧‧Second Solid Crystal Division

221-5‧‧‧The fifth solid crystal department

222‧‧‧second extension

2221‧‧‧L-shaped slot

223‧‧‧Second welding section

23‧‧‧Third metal pad

231‧‧‧Solid Crystal Department (Functional Department)

231-1‧‧‧The first solid crystal department

231-2‧‧‧Second Solid Crystal Division

231-3‧‧‧The third solid crystal department

231-4‧‧‧The fourth solid crystal department

2311‧‧‧T-shaped slot

232‧‧‧Wire Line Department (Functional Department)

232-2‧‧‧Second Wire Division

232-3‧‧‧Third line department

232-4‧‧‧The Fourth Wire Division

232-5‧‧‧The fifth line department

24‧‧‧ Clearance

25‧‧‧ Depression Microstructure

26‧‧‧ Receiving slot

261‧‧‧long side wall

262‧‧‧ end wall

3‧‧‧ pad

31‧‧‧pad

311‧‧‧Negative electrode pad

312‧‧‧Positive electrode pad

4‧‧‧light-emitting diode chip

5‧‧‧Zina diode chip

6‧‧‧ fluorescent powder

61‧‧‧light surface

7‧‧‧welding material

8‧‧‧ Insulation

9‧‧‧Reflective shell

91‧‧‧top plane

92‧‧‧ opening

93‧‧‧ spacer

U‧‧‧Light-emitting unit

G‧‧‧ transparent adhesive layer

D1, D2, D3, D4‧‧‧ distance

W1, W2, W3‧‧‧Width

L1‧‧‧First direction

L2‧‧‧ Second direction

T1, T2 ‧‧‧ pitch

FIG. 1 is a schematic perspective view of a light emitting diode packaging structure according to the present invention.

FIG. 2 is an exploded view of FIG. 1.

FIG. 3 is an exploded view of FIG. 1 from another perspective.

FIG. 4 is a schematic diagram of an electrode layer of a light emitting diode packaging structure according to the present invention.

FIG. 5 is a schematic diagram of another aspect of FIG. 4.

FIG. 6 is a schematic diagram of another aspect of FIG. 4.

FIG. 7 is a schematic cross-sectional view of FIG. 1 along a line XII-XII.

FIG. 8 is a partially enlarged view of a part XIII in FIG. 7.

FIG. 9 is a partially enlarged view of a portion IX in FIG. 7.

FIG. 10 is a schematic perspective view of another aspect of the electrode layer of the light emitting diode package structure of the present invention.

FIG. 11 is a cross-sectional view of the electrode layer of the light emitting diode package structure of the present invention corresponding to FIG. 10. schematic diagram.

FIG. 12 is a schematic perspective view of another aspect of an electrode layer of a light emitting diode package structure of the present invention.

FIG. 13 is a schematic cross-sectional view of an electrode layer of a light emitting diode package structure corresponding to FIG. 12 according to the present invention.

FIG. 14 is an exploded view of another embodiment of the light emitting diode package structure of the present invention.

FIG. 15 is a schematic diagram of an electrode layer in FIG. 14.

FIG. 16 is a schematic flowchart of a method for manufacturing a wafer carrier according to the present invention.

Please refer to FIG. 1 to FIG. 16, which are embodiments of the present invention. It should be noted that this embodiment corresponds to the related quantities and appearances mentioned in the drawings, and is only used to specifically describe the implementation of the present invention. Mode to facilitate understanding of the content of the present invention, but not to limit the protection scope of the present invention.

As shown in FIG. 1 to FIG. 9, this embodiment discloses a light emitting diode package structure 100 including a substrate 1, an electrode layer 2 and an insulating layer 8 provided on one side of the substrate 1, and a substrate 1 provided. A pad layer 3 on the other side, a plurality of light-emitting diode wafers 4 (or light-emitting wafers) and a plurality of Zener diode wafers 5 mounted on the electrode layer 2 are respectively attached to the plurality of light-emitting diodes. A plurality of phosphor chips 6 of the diode wafer 4 and a reflective casing 9 disposed on the electrode layer 2 and the insulating layer 8. It should be noted that, as shown in FIG. 8, in this embodiment, the electrode layer 2 is described by using a copper layer 2 a and a metal plating layer 2 b (such as a nickel-gold layer) formed on the copper layer 2 a, but the present invention does not Limited to this.

In order to facilitate the description of this embodiment, each light-emitting diode wafer 4 and the phosphor chip 6 attached thereto may also be collectively referred to as a light-emitting unit U, and the substrate 1, the electrode layer 2, and the insulation The layer 8 may be collectively referred to as a wafer carrier. In the following, each element structure of the light emitting diode package structure 100 will be introduced separately, and then the connection relationship between the elements will be described in due course.

As shown in FIGS. 2 and 3, the substrate 1 has a first plate surface 11 and a second plate surface 12 on opposite sides, and a plurality of conductive pillars 13 are embedded in the substrate 1. The opposite ends are exposed from the first plate surface 11 and the second plate surface 12 of the substrate 1, respectively.

As shown in FIGS. 2 and 4, the electrode layer 2 is disposed on the first plate surface 11 of the substrate 1, and the electrode layer 2 includes a first metal pad 21, a second metal pad 22, and the first metal. Four third metal pads 23 are arranged between the pads 21 and the second metal pads 22 at intervals.

The first metal pad 21 includes a first wire-bonding portion 211-1 (also referred to as a wire-bonding portion 211), an elongated first extension portion 212, and a rectangular first weld. The first extension portion 212 connects the first wire-bonding portion 211-1 and the first soldering portion 213. The second metal pad 22 includes a fifth solid crystal portion 221-5 (also referred to as a solid crystal portion 221) having an L shape, a second extending portion 222 having a long shape, and a first Two welding portions 223, and the second extension portion 222 connects the fifth solid crystal portion 221-5 and the second welding portion 223. Each of the third metal pads 23 includes an L-shaped solid crystal portion 231 (such as the first, second, third, and fourth solid crystal portions 231-1 to 231-4) and is integrally connected to the solid crystal portion. The crystal portion 231 is an L-shaped wire portion 232 (such as the second, third, fourth, and fifth wire portions 232-2 to 232-5). Among them, each of the above-mentioned solid crystal portions 221-5, 231-1 to 231-4 (that is, the first, second, third, fourth, and fifth solid crystal portions) is used for a light-emitting diode wafer 4 Installation and setting with a Zener diode wafer 5, each of the above-mentioned wire bonding sections 211-1, 232-2 ~ 232-5 (that is, the first, second, third, fourth, and fifth wire bonding sections) is It is used to wire a light emitting diode wafer 4 and a zener diode wafer 5.

In addition, the first wire bonding portion 211-1 of the first metal pad 21 and the second to fifth wire bonding portions 232-2 to 232-5 of the plurality of third metal pads 23 are along a first direction L1. The fifth solid crystal portions 221-5 of the second metal pad 22 and the first to fourth solid crystal portions 231-1 to 231-4 of the plurality of third metal pads 23 are arranged in a row at intervals. The first direction L1 is arranged in another row at intervals.

To put it another way, the wire bonding portions 211 of the first metal pad 21 in this embodiment may be defined as the first wire bonding portions 211-1, and the remaining wire bonding portions 232 are sequentially defined from the first wire bonding portions 211-1 along the first direction L1. These are the second wiring section 232-2, the third wiring section 232-3, the fourth wiring section 232-4, and the fifth wiring section 232-5. In addition, the third metal pad 23 solid crystal portion 231 farthest from the second metal pad 22 solid crystal portion 221 is defined as the first solid crystal portion 231-1, and the remaining solid crystal portions 231 and 221 are from the first solid crystal portion. The portion 231 is sequentially defined along the first direction L1 as the second solid crystal portion 231-2, the third solid crystal portion 231-3, the fourth solid crystal portion 231-4, and the fifth solid crystal portion 221-5.

The first threaded portion 211-1 is spaced apart from the first solid crystal portion 231-1 along a second direction L2 perpendicular to the first direction L1 and forms a gap 24 having at least one turn; the second threaded portion 232-2 is spaced apart from the second solid crystal portion 231-2 along the second direction L2 and forms a gap 24 having at least one turn; the third wire-bonding portion 232-3 is spaced from the third direction along the second direction L2 The die-bonding portions 231-3 are spaced apart and formed with a gap 24 having at least one turn; the fourth wire-bonding portion 232-2 is spaced apart from the fourth die-bonding portion 231-4 along the second direction L2 and formed with at least one The gap 24 for turning; the fifth wire-bonding portion 232-5 is spaced apart from the fifth solid crystal portion 221-5 along the second direction L2 and forms a gap 24 having at least one turning. Wherein, each of the gaps 24 is substantially W-shaped in this embodiment, but the present invention is not limited thereto.

The five light-emitting diode wafers 4 are respectively fixed to the first solid crystal portion 231-1, the second solid crystal portion 231-2, the third solid crystal portion 231-3, the fourth solid crystal portion 231-4, and The fifth solid crystal portion 221-5 is wired to the first wiring portion 211-1, the second wiring portion 232-2, the third wiring portion 232-3, the fourth wiring portion 232-4, and the fifth wiring portion, respectively. 232-5. The five Zener diode wafers 5 are also fixed to the first solid crystal portion 231-1, the second solid crystal portion 231-2, the third solid crystal portion 231-3, and the fourth solid crystal portion 231-4, respectively. , And the fifth solid crystal portion 221-5, and are wired to the first wiring portion 211-1, the second wiring portion 232-2, the third wiring portion 232-3, the fourth wiring portion 232-4, and the fifth Wire section 232-5.

It should be added that each of the solid crystal portions 221 and 231 or the wire bonding portions 211 and 232 in the L-shape described above may also be referred to as functional portions 221, 231, 211, and 232 in this embodiment. That is, the multiple functional sections 221, 231, 211, and 232 of this embodiment are respectively a plurality of die-fixing sections 221, 231 carrying a plurality of the light-emitting units U and a plurality of the light-emitting units U are connected by wires. A plurality of wire bonding portions 211 and 232.

In addition, the third metal pad 23 of the electrode layer 2 can be adjusted correspondingly according to the number of the light emitting diode wafers 4. For example, as shown in FIG. 5, the number of the light-emitting diode wafers 4 of the light-emitting diode packaging structure 100 may be only two, and the electrode layer 2 includes the first metal pad 21 and the first metal pad 21. The two metal pads 22 and one of the third metal pads 23 are located between the first metal pad 21 and the second metal pad 22 and are arranged at intervals. Wherein, the structure and connection relationship of each element of the electrode layer 2 shown in FIG. 5 are substantially similar to the corresponding elements of FIG. 4, and the same parts are not described repeatedly.

Further, the wire bonding portion 211 of the first metal pad 21 in this embodiment may be defined as the first wire bonding portion 211-1, and the wire bonding portion 232 of the third metal pad 23 is defined as the second wire bonding portion 232-2. The solid crystal portion 231 of the third metal pad 23 is defined as the first solid crystal portion 231-1, and the solid crystal portion 221 of the second metal pad 22 is defined as the second solid crystal portion 221-2.

The first wire-bonding portion 211 is spaced apart from the first die-bonding portion 231 along the second direction L2 and forms a gap 24 having at least one turn; the second wire-bonding portion 232-2 is aligned with the second direction L2. The second solid crystal portions 221-2 are spaced apart and form a gap 24 having at least one turning.

The two light-emitting diode wafers 4 are respectively fixed to the first die-bonding portion 231-1 and the second die-bonding portion 221-2, and are wired to the first wire-bonding portion 211-1 and the second wire-bonding portion 232-2, respectively. . The two Zener diode wafers 5 are also fixed to the first die-bonding portion 231-1 and the second die-bonding portion 221-2, respectively, and are wired to the first wire-bonding portion 211-1 and the second wire-bonding portion 232, respectively. -2. The light-emitting diode wafer 4 is fixed to the corresponding die-fixing portions 231 and 221 with the following welding material 7 in this embodiment, and the specific implementation thereof will be described later.

In addition, as shown in FIG. 6, when the number of the light-emitting diode wafers 4 of the light-emitting diode packaging structure 100 is only one, the electrode layer 2 may omit the third metal. 垫 23。 Mat 23. Specifically, the electrode layer 2 includes the first metal pad 21 and the second metal pad 22. The light-emitting diode wafer 4 is fixed to the die-fixing portion 221 of the second metal pad 22 and is wired to the wire-bonding portion 211 of the first metal pad 21 respectively. The Zener diode wafer 5 is also fixed to the die-fixing portion 221 of the second metal pad 22 and is wired to the wire-bonding portion 211 of the first metal pad 21 respectively. Wherein, the structure and connection relationship of each element of the electrode layer 2 shown in FIG. 6 are substantially similar to the corresponding elements in FIG. 4, and the same parts are not described repeatedly.

As shown in FIGS. 2 and 3, the insulating layer 8 is disposed on the first plate surface 11 of the substrate 1, and the insulating layer 8 and the electrode layer 2 are complementary in shape and coplanar. That is, the insulating layer 8 is disposed on the first plate surface 11 portion of the substrate 1 on which the electrode layer 2 is not provided, and the side edges of the insulating layer 8 are aligned with the side edges of the substrate 1.

The pad layer 3 is disposed on the second plate surface 12 of the substrate 1 and is electrically connected to the electrode layer 2 and the light-emitting diode wafer 4. Wherein, the bonding pad layer 3 includes a plurality of sets of bonding pads 31, and the plurality of sets of bonding pads 31 are respectively electrically connected to the fixing of the electrode layer 2 through a plurality of conductive pillars 13 embedded in the substrate 1. The crystal portions 231 and 221 and the wire bonding portions 211 and 232.

In more detail, each set of pads 31 includes a negative pad 311 and a positive pad 312; and the negative pads 311 of the plurality of sets of pads 31 are respectively located below the solid-crystal parts 231 and 221, and the negative pads 311 is electrically connected to the corresponding die-bonding portions 231 and 221 through the conductive pillars 13. The positive electrode pads 312 of the plurality of sets of pads 31 are respectively located below the wire bonding portions 211 and 232, and the positive electrode pads 312 and the corresponding The wire bonding portions 211 and 232 are electrically connected through the conductive pillar 13.

In this way, the design of the electrode layer 2 and the wire bonding method can make all the light-emitting diode wafers 4 be connected in electrical series. The multiple sets of pads 31 of the pad layer 3 are electrically independent, so that each set of pads 31 can independently energize the corresponding light-emitting diode wafer 4. That is, any light-emitting diode wafer 4 can be independently controlled by the corresponding set of bonding pads 31, and thus can be applied to an adaptive front lighting system (AFS).

In this embodiment, the light-emitting diode wafer 4 is a vertical chip, and the plurality of light-emitting diode wafers 4 are respectively mounted on a plurality of solid crystal portions 221 and 231 of the electrode layer 2. The plurality of light emitting diode wafers 4 are connected to the plurality of wire bonding portions 211 and 232 of the electrode layer 2 through wire bonding, respectively. Wherein, at least three edges of each of the light-emitting diode wafers 4 described above are aligned with the outer edges of the corresponding die-fixing portions 221 and 231.

As shown in FIG. 2, FIG. 7, and FIG. 8, the phosphor sheet 6 in this embodiment refers to PIG (phosphor in glass) or PIC (phosphor in ceramic). Wherein, the top surface of the light-emitting diode wafer 4 is substantially completely covered by the phosphor chip 6, and at least one side edge of the phosphor chip 6 protrudes from the light-emitting diode wafer 4. The distance D1 is approximately 5 microns to 10 microns. Further, at least three side edges of the phosphor chip 6 in this embodiment are at least three edges of the light-emitting diode wafer 4 protruding from the outer edges of the solid crystal portions 221 and 231. Furthermore, each light-emitting unit U preferably has a transparent adhesive layer G, and in this embodiment, the fluorescent powder sheet 6 is fixed to the corresponding light-emitting diode wafer 4 through the transparent adhesive layer G described above. .

As shown in FIG. 2 and FIG. 3, the plurality of zener diode wafers 5 are respectively mounted on a plurality of die-bonding portions 221 and 231 of the electrode layer 2 and are respectively wire-connected to the plurality of wire-bonding portions 211 and 232 of the electrode layer 2. Wherein, the zener diode wafer 5 and the light emitting diode wafer 4 on each of the die-fixing sections 221 and 231 are respectively disposed in different regions, so as to avoid process interference caused by the die-bonding glue overflow.

As shown in FIG. 2, FIG. 7, and FIG. 8, the reflective case 9 is disposed on the electrode layer 2 and the insulating layer 8, and the reflective case 9 and the insulating layer 8 are preferably formed integrally, but are not limited thereto. this. The reflective casing 9 is coated on the side edges of the plurality of light-emitting units U (that is, the reflective casing 9 is coated on the side edges of the light-emitting diode wafer 4 and the side edges of the phosphor powder sheet 6) A plurality of Zener diode wafers 5 are buried in the reflective casing 9 to avoid the problem of light shielding. A plurality of openings 92 are formed in a top plane 91 of the reflective casing 9 to expose the light emitting surfaces 61 of the plurality of fluorescent powder sheets 6 respectively. It is best to be aligned with the phase of the reflection housing 9 Corresponding to the side wall of the opening 92.

In more detail, the distance D2 of the top plane 91 of the reflective casing 9 with respect to the substrate 1 is greater than the distance D3 of the light-emitting surface 61 of any fluorescent powder sheet 6 with respect to the substrate 1, and the top of the reflective casing 9 is The distance D4 between the plane 91 and the light emitting surface 61 of the phosphor sheet 6 is approximately 10 μm to 30 μm. In addition, in other embodiments not shown in the present invention, the top plane 91 of the reflective casing 9 may also be coplanar with the light emitting surface 61 of the phosphor sheet 6.

Furthermore, a portion of the reflective housing 9 between any two adjacent light-emitting units U is defined as a space portion 93, and the space portion 93 has an inverted T-shaped cross section. The width W1 of the spacer portion 93 adjacent to the insulation layer 8 is larger than the width W2 of the spacer portion 93 far from the insulation layer 8. To put it another way, the cross section of the light emitting unit U corresponding to the spacer 93 is T-shaped.

Thereby, the light emitting diode packaging structure 100 is provided with a reflection case 9 between the adjacent light emitting diode wafers 4 and between the adjacent phosphor powder sheets 6, and the top plane 91 of the reflection housing 9 is higher than the phosphor powder. The light emitting surface 61 of the sheet 6 is about 10 micrometers to 30 micrometers, so as to avoid the mutual interference between the adjacent light emitting diode wafer 4 and the adjacent phosphor powder sheet 6, and the light emitting efficiency can be effectively improved. In addition, the spacer portion 93 of the reflection case 9 has an inverted T-shaped structure with a narrow upper and a lower width, and the size of the opening 92 of the reflection case 9 is substantially the same as that of the fluorescent powder sheet 6 so as to avoid the light-emitting diode wafer. 4 blue light is exposed.

In addition, although the light-emitting diode package structure 100 of this embodiment is described by using the structure of FIGS. 1 to 3, the designer can also adjust and change according to requirements. For example, the type of the light emitting diode chip 4 used in the light emitting diode packaging structure 100 may also be a flip chip as shown in FIG. 14, and the light emitting diode packaging structure The number of light-emitting diode wafers 4 used in 100 can also be a single wafer as shown in FIG. 6 or two wafers as shown in FIG. 5, while other corresponding components and structures are based on the number of light-emitting diode wafers 4. Make adaptive adjustments.

As shown in FIG. 15, the electrode layer 2 includes a first metal pad 21, a second metal pad 22, and four third metal pads located between the first metal pad 21 and the second metal pad 22. 属 垫 23。 The mat 23. The first metal pad 21 and the second metal pad 22 each include an L-shaped functional portion 211, 221 (such as for wire bonding and solid crystal use), rectangular first and second extension portions 212, 222, and a rectangular first portion. First and second welding portions 213 and 223. The first and second extension portions 212 and 222 further include two L-shaped slot holes 2121 and 2221 provided thereon. The third metal pads 23 are substantially S-shaped, and each third metal pad 23 is arranged at intervals. The upper half of the third metal pad 23 is used as the wire bonding portion 232 for the Zener diode wafer 5 to be wired, and the lower half of the third metal pad 23 is used as the solid crystal portion 231 for the Zener diode wafer 5 and The light emitting diode wafer 4 is disposed, and the lower half of the third metal pad 23 further includes a T-shaped slot 2311. It is worth noting that this embodiment uses a flip-chip type light emitting diode wafer 4, and the light emitting diode wafer 4 is bridged on two adjacent metal pads 21, 22, and 23, respectively. Among them, as shown in FIG. 15, the first light-emitting diode wafer 4 counted from left to right is connected across the first metal pad 21 and a third metal pad 23 adjacent to the first metal pad 21. The second, third and fourth light emitting diode wafers 4 bridge two adjacent third metal pads 23. The fifth light-emitting diode wafer 4 is connected across the second metal pad 22 and a third metal pad 23 adjacent to the second metal pad 22. The L-shaped slot 2121, 2221 and the T-shaped slot 2311 are provided for alignment of the light emitting diode wafer 4.

The above is the description of the relationship between the components of the light emitting diode package structure 100 according to the embodiment of the present invention, but it should be added that the light emitting diode chip 4 of the light emitting diode package structure 100 is fixed with a soldering material 7 At the corresponding solid crystal portions 231, 221. However, in order to avoid the short-circuit problem caused by the welding material 7 flowing to other parts of the electrode layer 2, the light-emitting diode packaging structure 100 of this embodiment further forms a plurality of recessed microstructures on a surface of the electrode layer 2 away from the substrate 1. Structure 25. It should be noted that in the embodiment, the plurality of depressed microstructures 25 are covered on the surface of the electrode layer 2, but the present invention is not limited thereto. For example, in other embodiments not shown in the present invention, the electrode layer 2 may be formed with a plurality of recessed microstructures 25 only on a surface of each of the solid crystal portions 231 and 221 away from the substrate 1.

As shown in FIG. 4, the plurality of solid-crystal portions 231 and 221 of the electrode layer 2 are along the first The direction L1 is arranged in a row, and the plurality of concave microstructures 25 of each of the solid crystal portions 231 and 221 are elongated and substantially parallel to each other. The surface of each of the solid crystal portions 231 and 221 is formed by a plurality of concave microstructures. The structure 25 has a centerline average roughness (Ra) between 0.2 and 3.5 microns and a ten-point average roughness (Rz) between 1.0 and 2.0 microns. It should be noted that, in this embodiment, each of the recessed microstructures 25 is linear and is substantially perpendicular to the first direction L1. However, in other embodiments not shown in the present invention, the recessed microstructures 25 are also It may be wavy and its length direction is substantially perpendicular to the first direction L1.

It should be noted that, compared with the electrode layer 2 shown in FIG. 4, the difference between the electrode layer 2 shown in FIGS. 5 and 6 mainly lies in the number of the third metal pads 23; that is, as shown in FIGS. 4 to 6. The recessed microstructures 25 of the electrode layer 2 shown are substantially the same (see the above description), but the invention is not limited thereto. Among them, since the electrode layer 2 in FIG. 6 includes only one solid crystal portion 221, the first direction L1 may be defined by the arrangement direction of the first metal pad 21 and the second metal pad 22; A direction substantially perpendicular to the microstructures 25 is defined as a first direction L1, and a direction substantially parallel to the recessed microstructures 25 is defined as a second direction L2.

Furthermore, as shown in FIG. 9, any one of the light-emitting diode wafers 4 and the corresponding die-bonding portions 231 and 221 are connected with the soldering material 7, and the soldering material 7 is filled in the die-bonding portions 231, At least a portion of the plurality of recessed microstructures 25 in 221. According to this, the wafer carrier can receive a portion of the solder material 7 through the recessed microstructure 25 of the electrode layer 2 to effectively prevent the solder material 7 from flowing to other parts of the electrode layer 2 other than the solid crystal portions 231 and 221.

In addition, as shown in FIG. 10 to FIG. 13, the wafer carrier can further be recessed on the surface of each of the solid crystal portions 231 and 221 (eg, the surface on which the recessed microstructure 25 is formed) with a long shape.个 容 槽 槽 26。 26 receiving slots 26. Each receiving slot 26 is substantially parallel to any one of the recessed microstructures 25, and the depth of each receiving slot 26 is greater than the depth of any one of the recessed microstructures 25. Each receiving slot 26 has a width W3 perpendicular to its length direction, and the width W3 of each receiving slot 26 is greater than any one of the recesses. The width of the recessed microstructure 25 is preferably between 80 μm and 150 μm.

In more detail, in any one of the solid crystal portions 231 and 221, the inner wall of each accommodation slot 26 has two long side walls 261 and two end walls 262, and the edges of the solid crystal portions 231 and 221 A first pitch T1 of not more than 200 micrometers is formed between one of the adjacent long side walls 261 of the plurality of accommodating slot holes 26, and the edges of the solid crystal portions 231, 221 and the plurality of accommodating slot holes 26 are formed. A second interval T2 of not more than 100 microns is formed between one of the adjacent end walls 262.

Furthermore, in any one of the solid crystal portions 231 and 221, the welding material 7 is filled in at least a part of the plurality of accommodation slots 26, and the accommodation slot formed by any of the solid crystal portions 231 and 221 The depth can be adjusted and changed according to design requirements, which is not limited in the present invention. For example, as shown in FIGS. 12 and 13, each of the accommodation slots 26 is penetrating, and in any of the accommodation slots 26 filled with the welding material 7, the welding material 7 is located in the accommodation. A filling depth of the receiving slot 26 is less than 50% of the depth of the receiving slot 26. Alternatively, as shown in FIG. 10 and FIG. 11, each of the accommodation slots 26 is in the shape of a blind hole and has a depth between 50 micrometers and 100 micrometers (μm). Slot holes 26, but the invention is not limited thereto.

In addition, please refer to FIG. 16 and refer to other diagrams of this embodiment in a timely manner. The invention also discloses a method for manufacturing a wafer carrier, which includes a preparation step (that is, providing the substrate 1), a patterning step, a forming step, and a plating step. Among them, since the specific structure of the wafer carrier has been described above, the same technical features will not be described in detail below.

It should be additionally noted that the wafer carrier can be manufactured by performing the above steps of this embodiment, but the present invention is not limited thereto. That is, in other embodiments not shown in the present invention, the wafer carrier can also be manufactured and formed in other ways. In addition, the light-emitting diode package structure 100 of this embodiment may also be manufactured by using the manufacturing method of the wafer carrier; that is, this embodiment is also equivalent to the A method for manufacturing a light emitting diode package structure is provided, which includes the method for manufacturing the wafer carrier.

Specifically, the patterning step is performed: a patterned electrode layer 2 is formed on a plate surface of the substrate 1, and the electrode layer 2 includes adjacently arranged in a row along the first direction L1. The plurality of solid crystal portions 231, 221. The electrode layer 2 in this step corresponds to the copper layer 2 a in FIG. 8. In the above-mentioned patterning step, a plurality of elongated accommodating slots 26 can be further formed on the surface of each of the solid crystal portions 231 and 221. In addition, corresponding to the type of FIG. 6, when the patterning step is performed, the electrode layer 2 only forms a single solid-crystal portion 221, and the definition of the first direction L is the same as that described above, and will not be repeated here.

The forming step is performed: a plurality of elongated microstructures 25 are formed on the surface of each solid crystal portion 231, 221 away from the substrate 1, so that the surface of each solid crystal portion 231, 221 has a value between 0.2 and 0.2. Centerline average roughness (Ra) of ~ 3.5 microns and ten-point average roughness (Rz) of 1.0 to 2.0 microns. Wherein, the recessed microstructures 25 of the plurality of solid crystal portions 231 and 221 are substantially parallel to each other, and preferably perpendicular to the first direction L1. Furthermore, each receiving slot 26 is substantially parallel to any one of the recessed microstructures 25, and the depth of each receiving slot 26 is greater than the depth of any one of the recessed microstructures 25.

It should be noted that, in the forming step of this embodiment, the recessed microstructures of the plurality of solid crystal portions are processed by a brush manner, a pumice manner, or a chemical etching method (micro- etch manner), but the present invention is not limited thereto.

Carrying out the electroplating step: electroplating at least one metal plating layer 2b, such as a nickel layer, for isolation and migration, and a gold layer on the surface of the patterned electrode layer 2 (that is, the surface of the electrode layer 2 provided with the recessed microstructure 25) , Used to improve the quality of signal transmission or nickel-gold multilayer stack or alloy layer. To put it another way, as shown in FIG. 8, in this embodiment, the electrode layer 2 may include a copper layer 2 a and a metal plating layer 2 b formed on the copper layer 2 a.

In addition, the method for manufacturing the wafer carrier may further include or be applicable to a die-bonding step, that is, as shown in FIG. 11, the light-emitting diode wafer 4 is welded and fixed to the corresponding die-bonding portion with a soldering material 7. 231, 221, and the recessed microstructure 25 on the electrode layer 2 and the accommodating slot 26 receive a part of the welding material 7, so as to prevent the welding material 7 on the solid crystal portion 231, 221 from overflowing to the adjacent electrode layer 2Other parts can avoid short circuit.

[Technical effect of the embodiment of the present invention]

According to the above, the light emitting diode package structure disclosed in the embodiments of the present invention, the wafer carrier and the manufacturing method thereof have the following technical effects:

1. The electrode layer is formed with a plurality of recessed microstructures capable of accommodating a part of the welding material, so as to prevent the above-mentioned welding material from flowing to other parts of the electrode layer other than the solid crystal part, thereby effectively reducing Caused by a short circuit problem.

2. The electrode layer has a centerline average roughness (Ra) between 0.2 and 3.5 microns and a ten-point average roughness (Rz) between 1.0 and 2.0 microns on the surface of the solid crystal part, thereby controlling the process capability. Achieve roughness consistency.

3. The electrode layer is provided with a plurality of recessed microstructures in the solid crystal part, so that the light-emitting diode wafer and the solidified part of the electrode layer are effectively promoted through the close bonding of the plurality of recessed microstructures and the welding material. Of adhesion.

4. The electrode layer can be further formed with a receiving slot capable of accommodating a part of the welding material in the solid crystal part, so as to prevent the welding material from flowing to other parts of the electrode layer other than the solid crystal part, thereby effectively Reduce short-circuit problems caused by soldering materials.

The above description is only the preferred and feasible embodiments of the present invention, and is not intended to limit the protection scope of the present invention. Any equivalent changes and modifications made according to the patent scope of the present invention shall fall within the protection scope of the claims of the present invention.

Claims (12)

A wafer carrier includes: a substrate; and an electrode layer disposed on a surface of the substrate. The electrode layer includes a plurality of metal pads, and at least one of the plurality of metal pads. There is a solid crystal part for fixing at least one light-emitting wafer; wherein the solid crystal part has a plurality of recessed microstructures formed on a surface thereof away from the substrate, and a plurality of the solid crystal part The depression microstructures are all elongated and substantially parallel to each other, and the surface of the solid crystal portion has a centerline average roughness (Ra) between 0.2 to 3.5 microns and a ten-point average roughness between 1.0 to 2.0 microns Degrees (Rz). The wafer carrier according to claim 1, wherein at least two of the plurality of metal pads each have one of the solid crystal portions, and the two solid crystal portions are along a first direction. Arranged in a row; and in each of the solid crystal portions, each of the recessed microstructures is linear and substantially perpendicular to the first direction. The wafer carrier according to claim 1, wherein the solid crystal part is recessed from the surface to form a plurality of elongated accommodation slots, and each of the accommodation slots is substantially parallel to any one of the accommodation slots. The recessed microstructures, and the depth of each of the accommodating slots is greater than the depth of any one of the recessed microstructures. The wafer carrier according to claim 3, wherein each of the accommodating slots has a width perpendicular to its length direction, and the width of each of the accommodating slots is between 80 μm and 150 Microns. The wafer carrier according to claim 3, wherein an inner wall of each of the accommodating slots has two long side walls and two end walls, and an edge of the solid crystal portion and a plurality of the accommodating slots. A first pitch of not more than 200 micrometers is formed between one of the slot holes adjacent to the long side wall, and an edge of the solid crystal portion and one of the plurality of receiving slot holes are adjacent to the end. A second pitch is formed between the walls that is not greater than 100 microns. A light emitting diode packaging structure, comprising: the wafer carrier according to any one of claims 1 to 5; at least one light emitting diode wafer mounted on the crystal-immobilized portion of the electrode layer; and A soldering material connects at least one of the light-emitting diode wafer and the solid-crystal portion of the electrode layer, and the soldering material fills at least a part of the plurality of recessed microstructures. The light emitting diode package structure according to claim 6, wherein the solid crystal portion is recessed from the surface to form a plurality of elongated receiving slots, and each of the receiving slots is substantially parallel In any one of the recessed microstructures, and the depth of each of the accommodating slots is greater than the depth of any one of the recessed microstructures; the welding material fills at least a portion of the plurality of accommodating slots. The light emitting diode packaging structure according to claim 7, wherein in any one of the accommodation slots filled with the solder material, the solder material is located at a filling depth of the accommodation slot. , Which is less than 50% of the depth of the receiving slot. A method for manufacturing a wafer carrier includes: implementing a preparation step: providing a substrate; implementing a patterning step: forming a patterned electrode layer on a plate surface of the substrate; wherein the electrode layer includes There are a plurality of solid crystal portions arranged adjacently in a row along a first direction; and a forming step is performed: a plurality of elongated recessed microstructures are formed on a surface of each of the solid crystal portions away from the substrate. The structure is such that the surface of each solid crystal portion has a centerline average roughness (Ra) between 0.2 and 3.5 microns and a ten-point average roughness (Rz) between 1.0 and 2.0 microns; wherein, The recessed microstructures of a plurality of the solid crystal portions are substantially parallel to each other. The method for manufacturing a wafer carrier according to claim 9, wherein in the forming step, the recessed microstructures of the plurality of solid crystal portions are processed by a brush manner or a sandblasting method. (pumice manner), or a chemical etching method (micro-etch manner). The method for manufacturing a wafer carrier according to claim 9, wherein in the forming step, the recessed microstructures of the plurality of solid crystal portions are substantially perpendicular to the first direction. The method for manufacturing a wafer carrier according to claim 9, wherein in the patterning step, a plurality of elongated receiving slots are further formed on the surface of each of the solid crystal portions; wherein, Each of the receiving slots is substantially parallel to any one of the recessed microstructures, and the depth of each of the receiving slots is greater than the depth of any one of the recessed microstructures.