TWI678108B - Image processing system and method for an image sensor - Google Patents

Abstract

An image processing system of an image sensor includes an analog-to-digital conversion unit that performs analog-to-digital conversion on pixel signals to generate digital pixel signals; a correlated double sampling unit that performs correlated double sampling on digital pixel signals; black level estimation A unit that generates a negative offset voltage according to the estimated dark voltage obtained by performing digital correlation double sampling of the optical black pixel, and feeds the pixel signal to the analog to digital conversion unit after subtracting the negative offset voltage; The active pixel sensing element and the compensation optical black pixel perform black level compensation.

Description

Image processing system and method of image sensor

The invention relates to an image sensor, in particular to a column-parallel image sensor with an improved signal-chain dynamic range.

An image sensor (such as a complementary metal oxide semiconductor image sensor) is a device that converts an optical image into an electronic signal. Image sensors are commonly used in various applications, such as mobile phones or cameras. Complementary metal oxide semiconductor (CMOS) image sensors can be used in demanding applications such as automotive and security.

Even if there is no light, dark current will still pass through the photodiode of the complementary metal oxide semiconductor (CMOS) image sensor. Since the dark current increases exponentially with temperature, at high temperatures (for example, above 60 degrees Celsius), the dark current can become an important source of noise, making the output image saturated. Even if the traditional black level compensation mechanism is used, the output image cannot be recognized.

In view of the fact that traditional image sensors cannot operate effectively at high temperatures, it is urgent to propose a novel image sensor that is suitable for high temperatures and has an improved signal chain dynamic range.

In view of the foregoing, one object of the embodiments of the present invention is to provide an image sensor based on black level estimation, which can effectively improve the dynamic range of the signal chain at high temperatures.

According to an embodiment of the present invention, the image processing system of the image sensor includes a pixel array, an analog-to-digital conversion unit, a correlated double sampling unit, a black level estimation unit, and a black level compensation unit. The pixel array provides pixel signals. The pixel array includes an active pixel sensing element (APS), a compensated optical black pixel (OBP), and an estimated optical black pixel. The analog-to-digital conversion unit performs analog-to-digital conversion on the pixel signal to generate a digital pixel signal. The correlated double sampling unit performs correlated double sampling on the digital pixel signal. The black level estimation unit generates a negative offset voltage according to the estimated dark voltage obtained by performing digital correlated double sampling of the optical black pixel, and the pixel signal is fed to the analog-to-digital conversion unit after subtracting the negative offset voltage. The black level compensation unit performs black level compensation on the active pixel sensing element and the compensated optical black pixel.

100‧‧‧Image Sensor

11‧‧‧ pixel array

110‧‧‧ pixels

111‧‧‧active pixel sensing element

112‧‧‧Compensated optical black pixels

113‧‧‧Estimated optical black pixels

12‧‧‧ column decoder

13‧‧‧Current draw column

131‧‧‧ current draw circuit

14‧‧‧ Comparator

141A‧‧‧amplifier

141B‧‧‧Amplifier

141C‧‧‧amplifier

15‧‧‧Slope generator

16‧‧‧ Counter

17‧‧‧Memory device

18‧‧‧ black level estimation unit

181‧‧‧Estimator

182‧‧‧Offset generator

400‧‧‧Image Processing System

41‧‧‧ Analog to Digital Conversion Unit

42‧‧‧ Related Double Sampling Unit

43‧‧‧black level compensation unit

431‧‧‧ Optical Black Pixel Subunit

432‧‧‧ active pixel sensing element subunit

433‧‧‧Subtractor

600‧‧‧Image Sensor

700‧‧‧Image Processing System

72‧‧‧ Subtractor

91‧‧‧ Multiplexer

92‧‧‧Buffer

APS‧‧‧Active Pixel Sensor

OBP‧‧‧ Optical Black Pixel

VDD‧‧‧ supply voltage

RX‧‧‧Reset transistor

TX‧‧‧Transistor

PD‧‧‧Photodiode

FD‧‧‧Floating Diffusion Node

SF‧‧‧Source Followed Coupling Transistor

SX‧‧‧Select transistor

BL‧‧‧bit line

Vramp‧‧‧ Ramp signal

t1 ~ t4‧‧‧Time

V _BL ‧‧‧Bit Line Voltage

Vrst‧‧‧ reset voltage

Vsig‧‧‧Optical Signal

BLC‧‧‧Black level compensation

ADC‧‧‧ Analog to Digital Conversion

CDS‧‧‧ Related Double Sampling

BLE‧‧‧Black Level Estimate

Neg_offset‧‧‧Negative offset voltage

BLE <M: 0> ‧‧‧Offset control signal

VB ₁ ‧‧‧ input voltage

VB ₂ ‧‧‧ input voltage

R ₀ ~ R _N ‧‧‧Resistance column

ref ₁ ~ ref _N ‧‧‧ reference voltage

SW ₁ ‧‧‧First switch

SW ₂ ‧‧‧Second switch

C1‧‧‧First capacitor

C2‧‧‧Second capacitor

C3‧‧‧Third capacitor

The first figure shows a block diagram of a line-parallel image sensor.

The second figure illustrates a circuit diagram of the pixels of the first figure.

The third diagram illustrates a timing diagram of the image sensor in the first diagram performing correlated double sampling.

The fourth figure shows a block diagram of the image processing system of the image sensor.

The fifth diagram illustrates another timing diagram of the image sensor in the first diagram performing correlated double sampling.

FIG. 6 is a block diagram of a parallel image sensor according to an embodiment of the present invention.

The seventh figure shows a block diagram of an image processing system of an image sensor according to an embodiment of the present invention.

The eighth figure illustrates a timing diagram of the image sensor in the sixth figure performing correlated double sampling.

The ninth figure illustrates a circuit diagram of the offset generator of the seventh figure.

The tenth diagram A illustrates the circuit diagram of the comparator of the sixth diagram.

The tenth diagram B illustrates another circuit diagram of the comparator of the sixth diagram.

The tenth diagram C illustrates another circuit diagram of the comparator of the sixth diagram.

The first figure shows a block diagram of a column-parallel image sensor 100, such as a complementary metal oxide semiconductor (CMOS) image sensor. The image sensor 100 may include a pixel array 11 including a plurality of pixels 110 arranged in a matrix form. The pixel array may include a complex active pixel sensing element (APS) 111 and a complex optical black pixel (OBP) 112. The active pixel sensing element (APS) 111 receives incident light, whereas the optical black pixel (OBP) 112 is blocked from receiving incident light. The optical black pixel (OBP) 112 is used as black level compensation (BLC). The details will be described later.

The second figure illustrates a circuit diagram of the pixel 110 of the first figure. The pixel 110 may include a photodiode PD, a reset transistor RX, a transmission transistor TX, a source follower transistor SF, and a selection transistor SX, which are connected as a four-transistor structure as shown in the figure. When the reset transistor RX is turned on, the reset voltage is defined at the floating diffusion node FD, and its magnitude is the power supply voltage VDD minus the voltage drop of the reset transistor RX. When the transmitting transistor TX is turned on, the optical signal accumulated by the photodiode PD can be transmitted through the floating diffusion node FD. The source follower transistor SF is turned on to buffer or amplify the optical signal of the photodiode PD. When the selection transistor SX is turned on, a pixel signal can be read out from the pixel array 11 via the bit line BL.

Referring to the first figure, the pixel array 11 of the image sensor 100 may include a current sinking column 13 including a plurality of current sink circuits 131 respectively coupled to the output nodes of the selection transistor SX, as shown in the second figure. Instantiation. The current drawing circuit 131 (for example, a current source) is coupled between the output node of the selection transistor SX and the ground, and serves as a bias circuit for drawing current from the output node of the selection transistor SX.

The image sensor 100 may include a column decoder 12 which selects one column of the pixel array 11 at a time for reading out pixel signals of the selected column.

The image sensor 100 of the first figure may use a single-slope column-parallel analog-to-digital conversion mechanism to convert a pixel signal from an analog form to a digital form. The analog-to-digital conversion mechanism may include a set of comparators 14. Each comparator 14 is coupled to receive a corresponding pixel signal of the pixel array 11 and to receive a signal generated by a ramp generator 15 Ramp signal Vramp. The analog-to-digital conversion mechanism may include a set of counters 16 which are coupled to receive the comparison results of the comparator 14 and receive the counting clock, respectively. The analog-to-digital conversion mechanism may further include a set of memory devices 17 coupled to receive the count values of the counters 16 respectively. The data stored in the memory device 17 can be processed by a digital image processor (not shown) to generate a digital image output. The comparator 14, the counter 16 and the memory device 17 mainly construct a pixel readout circuit of a signal chain of the image sensor 100.

The third diagram illustrates a timing diagram of the image sensor 100 in the first diagram performing a correlated double sampling (CDS). During the reset period, the reset voltage Vrst of the floating diffusion node FD (second figure) is sampled and fed to the corresponding comparator 14. When the ramp signal Vramp starts to be generated at time t1, the counter 16 starts counting. When the comparator 14 (at time t2) detects a cross point where both the ramp signal Vramp and the pixel signal are equal, the counter 16 stops counting. It is worth noting that the count value during the reset period includes the (comparator-related) offset voltage and reset voltage Vrst. The reset voltage Vrst in the figure is negative.

During the signal period, the optical signal Vsig of the photodiode PD plus the reset voltage Vrst of the floating diffusion node FD is sampled and fed to the corresponding comparator 14. The optical signal Vsig in the figure is negative. When the ramp signal Vramp starts to be generated at time t3, the counter 16 starts counting. When the comparator 14 (at time t4) detects a cross point where both the ramp signal Vramp and the pixel signal are equal, the counter 16 stops counting. It is worth noting that the count value during the signal period includes the offset voltage and the reset voltage Vrst (same as the reset period), and further includes the optical signal Vsig and the dark voltage, where the dark voltage is a dark electron of the photodiode PD ( Or dark current).

The fourth figure shows a block diagram of an image processing system 400 of an image sensor, such as a complementary metal oxide semiconductor image sensor. The image processing system (hereinafter referred to as the system 400) may include an analog-to-digital conversion (ADC) unit 41 for performing analog-to-digital conversion on a pixel signal received from the pixel array 11. The system 400 may include a correlated double sampling (CDS) unit 42 for performing correlated double sampling (such as digital correlated double sampling or DDS) on the digital pixel signals generated by the ADC unit to remove the offset voltage and reset voltage, thereby generating Related pixel signals. system The 400 may further include a black level compensation (BLC) unit 43 for removing a dark voltage, thereby generating a compensated pixel signal. In another example, the CDS unit 42 is located before the ADC unit 41. Therefore, before performing the analog-to-digital conversion, the pixel signal is subjected to (analog) correlated double sampling.

In detail, during the reset period, the ADC unit 41 first processes the optical black pixels (OBP) 112 (first image) of the pixel array 11, and thus generates a first digital pixel signal including an offset voltage and a reset voltage. Then, during the signal period, the ADC unit 41 processes the optical black pixel (OBP) 112, thereby generating a second digital pixel signal including an offset voltage, a reset voltage, and a dark voltage. The CDS unit 42 subtracts the first digital pixel signal from the second digital pixel signal, thereby generating a dark voltage (but excluding the offset voltage and the reset voltage). The generated dark voltage is temporarily stored in the optical black pixel (OBP) sub-unit 431 among the BLC units 43.

In a similar situation, during the reset period, the ADC unit 41 first processes the active pixel sensing element (APS) 111 (first picture) of the pixel array 11 and thus generates a third digital pixel signal including an offset voltage and a reset voltage. . Then, during the signal period, the ADC unit 41 processes the active pixel sensing element (APS) 111, thereby generating a fourth digital pixel signal including an offset voltage, a reset voltage, a dark voltage, and an optical signal. The CDS unit 42 subtracts the third digital pixel signal from the fourth digital pixel signal, thereby generating a dark voltage and a light signal (but not including an offset voltage and a reset voltage). The generated dark voltage and light signal are temporarily stored in the active pixel sensing element (APS) sub-unit 432 of the BLC unit 43.

Finally, the subtractor 433 of the BLC unit 43 subtracts the dark voltage and the light signal stored in the APS sub-unit 432 from the dark voltage stored in the OBP sub-unit 431, thereby generating a compensated pixel signal that does not contain the dark voltage. Black level compensation can be expressed as: ('dark voltage + light signal') _APS -('dark voltage') _OBP = light signal

Thereby, the value of the black compensation pixel signal can be very close to the digital zero value. Conversely, if black level compensation is not performed, the black related pixel signal looks gray. Furthermore, the dark current of the photodiode PD increases exponentially with temperature.

The fifth diagram illustrates another timing diagram of the image sensor 100 in the first diagram performing a correlated double sampling (CDS). In a high temperature situation, the comparator 14 cannot detect the intersection of the ramp signal Vramp and the pixel signal, and the counter 16 causes an overflow. In addition, as the temperature rises, the OBP subunit 431 and the APS subunit 432 need to use more storage space or more bits. To overcome the shortcomings of the system 400, a novel system is proposed below.

The sixth figure shows a block diagram of a column-parallel image sensor 600 (such as a complementary metal oxide semiconductor image sensor) according to an embodiment of the present invention. The image sensor 600 may include a pixel array 11 including a plurality of pixels 110 arranged in a matrix form. In this embodiment, the pixel array may include a complex active pixel sensing element (APS) 111, a complex compensated optical black pixel (OBP) 112, and a complex estimated optical black pixel (OBP) 113. The active pixel sensing element (APS) 111 receives the incident light, but the compensated optical black pixel (OBP) 112 and the estimated optical black pixel (OBP) 113 are blocked without receiving the incident light. The compensated optical black pixel (OBP) 112 is used as the black level compensation, as described above, and the estimated optical black pixel (OBP) 113 is used as the black level estimation. The details will be described later.

Similar to the first figure, the image sensor 600 may include a column decoder 12 which selects one column of the pixel array 11 at a time for reading out pixel signals of the selected column. The image sensor 600 may include a current drawing column 13 including a plurality of current drawing circuits 131 respectively coupled to the output nodes of the selection transistor SX, as illustrated in the second figure. The current drawing circuit 131 (for example, a current source) is coupled between the output node of the selection transistor SX and the ground, and serves as a bias circuit for drawing current from the output node of the selection transistor SX.

The image sensor 600 of this embodiment may use a single-slope column-parallel analog-to-digital conversion mechanism to convert a pixel signal from an analog form to a digital form. The analog-to-digital conversion mechanism may include a set of comparators 14. Each comparator 14 is coupled to receive a corresponding pixel signal of the pixel array 11 and to receive a ramp signal Vramp generated by a ramp generator 15. The analog-to-digital conversion mechanism may include a set of counters 16 which are coupled to receive the comparison results of the comparator 14 and receive the counting clock, respectively. Analog to digital conversion mechanism It further includes a set of memory devices 17 coupled to receive the count values of the counter 16 respectively. The data stored in the memory device 17 can be processed by a digital image processor (not shown) to generate a digital image output.

According to one of the features of this embodiment, the image sensor 600 may include a black level estimation (BLE) unit 18, which is based on correlated double sampling (e.g., digitally performed on estimated optical black pixel (OBP) 113) Correlation Double Sampling) to generate a negative offset voltage Neg_offset. The negative offset voltage Neg_offset is fed to the comparator 14 to cancel the dark voltage of the pixel signal.

The seventh figure shows a block diagram of an image processing system 700 of an image sensor (such as a complementary metal oxide semiconductor image sensor) according to an embodiment of the present invention. The blocks of the seventh figure may be implemented using hardware (such as a circuit) or software (such as being executed on a digital signal processor). Blocks 11, 41, 42, 43 have been discussed in the fourth figure, and the details will not be repeated. In this embodiment, the image processing system 700 (hereinafter referred to as the system 700) may include a black level estimation (BLE) unit 18 that is coupled to receive the output of the CDS unit 42 to generate a negative offset voltage Neg_offset. The subtracter 72 subtracts the negative offset voltage Neg_offset from the pixel signal (output from the pixel array 11), and the output of the subtractor 72 is fed to the ADC unit 41.

In detail, the black level estimation (BLE) unit 18 in this embodiment may include an estimator 181 and an offset generator 182. In this embodiment, the estimator 181 is a digital circuit or program, and the offset generator 182 is an analog circuit. The estimator 181 is coupled to receive the dark voltage obtained by performing correlated double sampling on the estimated optical black pixel (OBP) 113, which can be expressed as: BLE: (offset signal + reset voltage + dark voltage)-(offset (Signal + reset voltage) = dark voltage

If the estimator 181 determines that the dark voltage is greater than a preset threshold, the estimator 181 drives the offset generator 182 with an offset control signal BLE <M: 0> to generate (analogically) a negative offset voltage Neg_offset for Black level compensation is performed on the compensated optical black pixels (OBP) 112 and the active pixel sensing element (APS) 111. Thereby, the dark voltages of the compensated optical black pixel (OBP) 112 and the active pixel sensing element (APS) 111 can be cancelled by the negative offset voltage Neg_offset. The resulting negative offset The voltage Neg_offset can be used as the active pixel sensing element (APS) 111 of the current column and subsequent columns to perform black level compensation. The BLC unit 43 performs the following black level compensation: OBP: (offset voltage + reset voltage + dark voltage-negative offset voltage)-(offset voltage + reset voltage) = dark voltage-negative offset voltage

APS: (offset voltage + reset voltage + dark voltage + optical signal-negative offset voltage)-(offset voltage + reset voltage) = dark voltage + optical signal-negative offset voltage

BLC: (dark voltage + light signal-negative offset voltage) _APS- (dark voltage-negative offset voltage) _OBP = light signal

The eighth figure illustrates a timing diagram of the image sensor 600 of the sixth figure performing a correlated double sampling (CDS). Under high temperature conditions, the dark voltage can be offset by the negative offset voltage Neg_offset. The negative offset voltage Neg_offset in the figure is a positive value, which is opposite to the optical signal Vsig of a negative value. As a result, the comparator 14 can detect the intersection of the ramp signal Vramp and the pixel signal without causing the counter 16 to overflow. Therefore, the storage space or number of bits of the OBP sub-unit 431 and the APS sub-unit 432 can be effectively reduced, and the dynamic range of the signal chain can be greatly improved under high temperature conditions.

The ninth figure illustrates a circuit diagram of the offset generator 182 of the seventh figure. In this embodiment, the offset generator 182 may include a voltage divider composed of the resistor columns R ₀ to R _N. The voltage divider distributes the input voltages VB ₁ -VB ₂ to the resistor columns R ₀ ~ R _N , and thus generates reference voltages ref ₁ ~ ref _N. The offset generator 182 may include a multiplexer 91 coupled to receive the reference voltages ref ₁ to ref _N. The multiplexer 91 selects one of the reference voltages ref ₁ to ref _N as an output according to a selection bit in the offset control signal BLE <M: 0>.

The offset generator 182 may include a first switch SW ₁ and a second switch SW ₂ . Between the first input is connected to the out switch SW ₁ of the multiplexer 91 and output buffer 92. A first terminal of the second switch SW ₂ is connected to the input of the buffer 92 and a second terminal is connected to the ground. When the estimated optical black pixel (OBP) 113 performs black level compensation, the first switch SW _{1 is} closed and the second switch SW _{2 is} open, so the multiplexer 91 outputs the selected reference voltage, which is passed through the buffer 92 as a negative bias. Shift voltage Neg_offset. When the estimated optical black pixel (OBP) 113 does not perform black level compensation, the first switch SW1 is opened and the second switch SW2 is closed, so the multiplexer 91 does not generate any negative offset voltage Neg_offset.

The tenth diagram A illustrates a circuit diagram of the comparator 14 of the sixth diagram. The comparator 14 may include a differential to single-ended amplifier 141A (eg, an operational amplifier). The pixel signal and the negative offset voltage Neg_offset are connected to the inverting input of the amplifier 141A via the first capacitor C1 and the second capacitor C2, respectively. The ramp signal Vramp is connected to a non-inverting input of the amplifier 141A. The tenth diagram B illustrates another circuit diagram of the comparator 14 of the sixth diagram. The comparator 14 may include a differential-to-differential amplifier 141B (eg, an operational amplifier). The pixel signal and the negative offset voltage Neg_offset are connected to the inverting input of the amplifier 141B via the first capacitor C1 and the second capacitor C2, respectively. The ramp signal Vramp is connected to the non-inverting input of the amplifier 141B via a third capacitor C3. The tenth diagram C illustrates another circuit diagram of the comparator 14 of the sixth diagram. The comparator 14 may include a single-ended input single-ended output amplifier 141C (eg, an operational amplifier). The pixel signal, the negative offset voltage Neg_offset and the ramp signal Vramp are connected to the input of the amplifier 141C via the first capacitor C1, the second capacitor C2, and the third capacitor C3, respectively.

The above is only a preferred embodiment of the present invention, and is not intended to limit the scope of patent application of the present invention; all other equivalent changes or modifications made without departing from the spirit disclosed by the invention should be included in the following Within the scope of patent application.

Claims (20)

An image processing system of an image sensor includes: a pixel array for providing pixel signals, the pixel array including an active pixel sensing element (APS), a compensated optical black pixel (OBP), and an estimated optical black pixel; an analogy to A digital conversion unit that performs analog-to-digital conversion on the pixel signal to generate a digital pixel signal; a correlated double sampling unit that performs correlated double sampling on the digital pixel signal; a black level estimation unit that performs The dark voltage obtained by digitally correlated double sampling is used to generate a negative offset voltage. The pixel signal is subtracted from the negative offset voltage and fed to the analog-to-digital conversion unit; and a black level compensation unit for the active pixel sensing element. And the compensation optical black pixel performs black level compensation. According to the image processing system of the image sensor according to item 1 of the scope of the patent application, the pixel array includes a current drawing row, which includes a plurality of current drawing circuits, which are respectively coupled to the output nodes of the pixel signal. According to the image processing system of the image sensor described in the first item of the patent application scope, the image processing system further includes a column of decoders, which selects one column of the pixel array each time to read out the pixel signals of the selected column. According to the image processing system of the image sensor according to item 1 of the patent application scope, the analog-to-digital conversion unit includes: a ramp generator that generates a ramp signal; a set of comparators, each of which is coupled to receive the Corresponding pixel signals, ramp signals and negative offset voltages of the pixel array; and a set of counters, each of which is coupled to receive a counting clock and a comparison result of a corresponding comparator. According to the image processing system of the image sensor according to item 4 of the patent application scope, the analog-to-digital conversion unit further includes a set of memory devices coupled to receive the count values of the counters, respectively. According to the image processing system of the image sensor according to item 4 of the patent application scope, wherein the comparator includes: a differential to single-ended amplifier; a first capacitor for connecting the pixel signal to the inverting input of the amplifier; And a second capacitor, whereby a negative offset voltage is connected to the inverting input of the amplifier; wherein the ramp signal is connected to the non-inverting input of the amplifier. According to the image processing system of the image sensor according to item 4 of the scope of patent application, the comparator includes: a differential-to-differential amplifier; a first capacitor for connecting a pixel signal to an inverting input of the amplifier; A second capacitor is used to connect the negative offset voltage to the inverting input of the amplifier; a third capacitor is used to connect the ramp signal to the non-inverting input of the amplifier. According to the image processing system of the image sensor according to item 4 of the patent application scope, wherein the comparator includes: a single-ended input single-ended output amplifier; a first capacitor for connecting a pixel signal to the input of the amplifier; A second capacitor is used to connect a negative offset voltage to the input of the amplifier; and a third capacitor is used to connect a ramp signal to the input of the amplifier. According to the image processing system of the image sensor according to item 1 of the scope of patent application, the black level compensation unit includes an optical black pixel sub-unit and an active pixel sensing element sub-unit. During the reset period, the analog to digital The conversion unit processes the compensated optical black pixel, thereby generating a first digital pixel signal including an offset voltage and a reset voltage; during the signal period, the analog-to-digital conversion unit processes the compensated optical black pixel, thereby generating a second digital pixel The signal includes an offset voltage, a reset voltage, and a dark voltage; the correlated double sampling unit subtracts the first digital pixel signal from the second digital pixel signal, so that a dark voltage is temporarily stored in the optical black pixel subunit; During the reset period, the analog-to-digital conversion unit processes the active pixel sensing element, thereby generating a third digital pixel signal including an offset voltage and a reset voltage; during the signal period, the analog-to-digital conversion unit processes the active pixel sensor. Measuring element, thereby generating a fourth digital pixel signal including an offset voltage, a reset voltage, a dark voltage, and a light signal ; The relevant double sampling unit subtracts the third digital pixel signal from the fourth digital pixel signal, thereby generating dark voltage and light signals temporarily stored in the active pixel sensing element sub-unit; and stored in the active pixel sensing element sub-unit The dark voltage and the light signal are subtracted from the dark voltage stored in the optical black pixel sub-unit, thereby generating a compensated pixel signal. According to the image processing system of the image sensor according to item 1 of the patent application scope, the correlation double sampling unit includes a digital correlation double sampling unit. According to the image processing system of the image sensor according to item 1 of the scope of the patent application, the black level estimation unit includes: an estimator coupled to receive the estimated optical black pixels obtained by performing correlated double sampling Dark voltage; and an offset generator. When the dark voltage received by the estimator is greater than a preset threshold, the estimator drives the offset generator with an offset control signal. According to the image processing system of the image sensor according to item 11 of the scope of patent application, the offset generator includes: a voltage divider to generate a plurality of reference voltages; and a multiplexer to select among them according to the offset control signal. A reference voltage is used as the output. According to the image processing system of the image sensor according to item 12 of the scope of patent application, the offset generator further includes: a buffer; a first switch connected to the output of the multiplexer and the input of the buffer Between; and a second switch connected between the input of the buffer and ground; wherein when the estimated optical black pixel performs black level compensation, the first switch is closed and the second switch is open; when the When it is estimated that the optical black pixel does not perform black level compensation, the first switch is opened and the second switch is closed. An image processing system of an image sensor includes: a pixel array for providing pixel signals, the pixel array including an active pixel sensing element (APS), a compensated optical black pixel (OBP), and an estimated optical black pixel; a related dual A sampling unit that performs correlated double sampling on the pixel signal; a black level estimation unit that generates a negative offset voltage based on the estimated dark voltage obtained by performing the correlated double sampling on the optical black pixel, and subtracts the negative offset from the pixel signal A correlated double sampling is performed after the voltage is shifted; and a black level compensation unit performs black level compensation on the active pixel sensing element and the compensated optical black pixel. According to the image processing system of the image sensor according to item 14 of the scope of patent application, the black level estimation unit includes: an estimator coupled to receive the estimated optical black pixel obtained by performing a correlated double sampling Dark voltage; and an offset generator. When the dark voltage received by the estimator is greater than a preset threshold, the estimator drives the offset generator with an offset control signal. According to the image processing system of the image sensor according to item 15 of the patent application scope, the offset generator includes: a voltage divider to generate a plurality of reference voltages; and a multiplexer to select among them according to the offset control signal. A reference voltage is used as the output. According to the image processing system of the image sensor according to item 16 of the patent application scope, wherein the offset generator further includes: a buffer; a first switch connected to the output of the multiplexer and the input of the buffer Between; and a second switch connected between the input of the buffer and ground; wherein when the estimated optical black pixel performs black level compensation, the first switch is closed and the second switch is open; when the When it is estimated that the optical black pixel does not perform black level compensation, the first switch is opened and the second switch is closed. An image processing method of an image sensor includes: a pixel array provides pixel signals, the pixel array includes an active pixel sensing element (APS), a compensated optical black pixel (OBP), and an estimated optical black pixel; Analog-to-digital conversion to generate digital pixel signals; correlation double sampling of digital pixel signals; dark voltages obtained by performing digital correlation double sampling of digital black pixels based on the estimated optical black pixels to generate negative offset voltages, and subtracting the pixel signals An analog-to-digital conversion is performed after the negative offset voltage; and a black level compensation is performed on the active pixel sensing element and the compensation optical black pixel. According to the image processing method of the image sensor according to item 18 of the patent application scope, the black level compensation step includes: performing an analog-to-digital conversion on the compensated optical black pixel during the reset period, thereby generating a first digital pixel signal , Which includes an offset voltage and a reset voltage; during the signal period, an analog-to-digital conversion is performed on the compensated optical black pixel, thereby generating a second digital pixel signal, which includes the offset voltage, the reset voltage, and the dark voltage; Double sampling, subtracting the first digital pixel signal from the second digital pixel signal, thereby generating and temporarily storing a dark voltage; during the reset period, performing an analog-to-digital conversion on the active pixel sensing element, thereby generating a third digital pixel signal , Which includes an offset voltage and a reset voltage; during the signal period, an analog-to-digital conversion is performed on the active pixel sensing element, thereby generating a fourth digital pixel signal, which includes an offset voltage, a reset voltage, a dark voltage, and light Signal; performs correlated double sampling, subtracts the fourth digital pixel signal from the third digital pixel signal, thereby generating and temporarily storing dark Pressing the optical signal; and the dark voltage by subtracting the dark voltage of the light signal will be stored in the storage, thereby generating a pixel compensation signal. According to the image processing method of the image sensor according to item 18 of the scope of application for patent, the black level estimation step includes: receiving a dark voltage obtained by performing the correlated double sampling of the estimated optical black pixel; and when the dark voltage When it is greater than a preset threshold, an offset control signal is generated to generate the negative offset voltage.