TWI674037B - LED driver circuit supporting low voltage input and its control chip - Google Patents
LED driver circuit supporting low voltage input and its control chip Download PDFInfo
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Abstract
一種支援低電壓輸入的LED驅動電路,具有:一電源轉換單元,用以依一開關通道之控制將一輸入電壓轉成一輸出電流;以及一控制單元,具有:一邏輯控制單元,用以產生一開關信號;一驅動電路,具有該開關通道以與該電源轉換單元耦接,且該開關通道係受該開關信號控制;一過壓保護模組,用以依一關斷期間和一預設時間之一比較結果產生一過壓信號;以及一遮罩邏輯電路,用以判斷一導通期間是否超過一最大導通期間並依一判斷結果決定一遮罩信號之電位,及利用該遮罩信號遮罩該過壓信號以避免一LED模組發生閃爍現象。An LED driving circuit supporting low voltage input has: a power conversion unit for converting an input voltage into an output current under the control of a switching channel; and a control unit having: a logic control unit for generating A switching signal; a driving circuit having the switching channel to be coupled with the power conversion unit, and the switching channel is controlled by the switching signal; an overvoltage protection module for a shutdown period and a preset A comparison result of time generates an overvoltage signal; and a mask logic circuit for determining whether a conduction period exceeds a maximum conduction period and determining a potential of a mask signal according to a judgment result, and using the mask signal to mask Cover the overvoltage signal to avoid flickering of an LED module.
Description
本案係有關一種LED驅動電路,特別是關於一種支援低電壓輸入的LED驅動電路。 This case relates to an LED driving circuit, and more particularly to an LED driving circuit supporting low voltage input.
請參照圖1,其繪示一習知開關型LED驅動電路的電路圖。如圖1所示,該習知開關型LED驅動電路具有一橋式整流單元11、一電容12、一電阻13、一電容14、一電容15、一LED模組16、一二極體17、一電感18、一控制晶片19、一電阻20及一電阻21。 Please refer to FIG. 1, which is a circuit diagram of a conventional switch-type LED driving circuit. As shown in FIG. 1, the conventional switch-type LED driving circuit has a bridge rectifier unit 11, a capacitor 12, a resistor 13, a capacitor 14, a capacitor 15, an LED module 16, a diode 17, a The inductor 18, a control chip 19, a resistor 20 and a resistor 21.
於操作時,一AC交流電經過橋式整流單元11和電容12的整流及濾波作用後產生一母線電壓VIN;母線電壓VIN通過電阻13和電容14的低通濾波作用後產生一供電電壓給控制晶片19;控制晶片19通過內部在DRAIN接腳和CS接腳之間所設之一500V開關電晶體(未示於圖中)控制一電源轉換操作;電阻20決定了一過電壓保護單元所需的一參考電壓值;電阻21提供一電流採樣信號VCS;電容15提供使LED模組16的電流漣波降低的作用;二極體17提供一電感電流釋放路徑;電感18提供一累積電流iL;以及控制晶片19依所述電流採樣信號VCS決定所述電源轉換操作的占空比,及依所述參考電壓值決定是否進入一過電壓保護模式。 During operation, an AC alternating current is rectified and filtered by the bridge rectifier unit 11 and the capacitor 12 to generate a bus voltage V IN . The bus voltage V IN generates a power supply voltage after low-pass filtering of the resistor 13 and the capacitor 14. Control chip 19; control chip 19 controls a power conversion operation through a 500V switching transistor (not shown in the figure) provided between the DRAIN pin and the CS pin internally; the resistor 20 determines an overvoltage protection unit. The required reference voltage value; resistor 21 provides a current sampling signal V CS ; capacitor 15 provides the effect of reducing the current ripple of LED module 16; diode 17 provides an inductor current release path; inductor 18 provides a cumulative current iL; and the control chip 19 determines the duty cycle of the power conversion operation according to the current sampling signal V CS and determines whether to enter an over-voltage protection mode according to the reference voltage value.
請參照圖2,其繪示圖1之習知開關型LED驅動電路的電感電流波形圖。如圖2所示,其係一臨界導通模式之電感電流iL的波形,主要分為導通階段和截止階段。 Please refer to FIG. 2, which illustrates an inductor current waveform diagram of the conventional switching LED driving circuit of FIG. 1. As shown in FIG. 2, it is a waveform of the inductor current iL in a critical conduction mode, which is mainly divided into an on-phase and an off-phase.
在導通階段中,控制晶片19使內部之所述開關電晶體導通,以對電感18進行儲能,此時電感電流iL會一直上升,電阻21所提供的所述電流採樣信號VCS的電壓也隨之上升。當所述電流採樣信號VCS的電壓大於一內部基準電壓VREF(未示於圖中)時,控制晶片19會關斷所述開關電晶體,此時電感電流iL上升到最大值IPK。導通階段的時間TON可表示如下:
在截止階段中,控制晶片19使內部之所述開關電晶體關斷,電感18經由二極體17釋放能量,電感電流iL乃從峰值IPK下降。當電感電流iL降至零時,控制晶片19內部之一電流過零檢測模組(未示於圖中)會將所述開關電晶體重新導通,截止階段的時間TOFF可表示如下:
由於沒有輔助繞組的存在,無法直接檢測LED模組16兩端的電壓,因此,目前通用的做法是通過檢測截止階段的時間TOFF,和一內部的基準時間TOVP進行比較,TOVP的時間大小可由電阻20的電阻值決定。如果TOFF>TOVF,表示LED模組16兩端電壓較小,電路可正常工作;如果TOFF<TOVP,表示LED模組16兩端電壓較大,電路需要進入過壓保護模式以防止LED模組16被燒壞。 Since there is no auxiliary winding, can not directly detect the voltage across the LED module 16, therefore, the current common practice is detected by comparing the phase of the off time T OFF, and an internal reference time T OVP, the size of the time of T OVP It can be determined by the resistance value of the resistor 20. If T OFF > T OVF , the voltage across the LED module 16 is low, and the circuit can work normally; If T OFF <T OVP , it indicates that the voltage across the LED module 16 is high, the circuit needs to enter the overvoltage protection mode to prevent The LED module 16 is burned out.
然而,由於輸入的交流電壓AC經過橋式整流單元11和電容12後,一般仍會在母線電壓VIN產生漣波。尤其是當VIN較小且LED模組16的電壓較大,且VIN的最小值接近LED模組16的電壓時,此時Ton會很大,很可能會使電路的開關切換頻率落入人耳能聽到的聲音頻率範圍(20~20KHz)內,此現象一般稱為電感嘯叫。電感嘯叫的一般解決辦法是在控制晶片19內部增加一最大導通時間模組,其係在當所需的TON超過一最大導通時間時,即使電感電流正峰值仍未達到IPK,也會關斷所述開關電晶體。然而,由於此時電感電流iL的峰值較低,TOFF的時間也會相應減小,因此很可能會出現TOFF<TOVP的情形而使電路進入過壓保護模式,從而導致LED模組16產生閃爍現象。 However, after the input AC voltage AC passes through the bridge rectifier unit 11 and the capacitor 12, ripples are still generally generated in the bus voltage V IN . Especially when V IN is small and the voltage of LED module 16 is large, and the minimum value of V IN is close to the voltage of LED module 16, Ton will be very large at this time, which may cause the switching frequency of the circuit to fall into In the frequency range of the sound (20 ~ 20KHz) that human ears can hear, this phenomenon is generally called inductance howling. The general solution to the inductor howling is to add a maximum on-time module inside the control chip 19, which is when the required T ON exceeds a maximum on-time, even if the positive peak value of the inductor current does not reach I PK Turn off the switching transistor. However, since the peak value of the inductor current iL is low at this time, the T OFF time will be correspondingly reduced, so it is likely that T OFF <T OVP will cause the circuit to enter the overvoltage protection mode, which will cause the LED module 16 Flicker occurs.
為解決上述問題,本領域亟需一新穎的LED驅動電路。 To solve the above problems, a new LED driving circuit is urgently needed in the art.
本案之一目的在於提供一種支援低電壓輸入的LED驅動電路,其可在一輸入電壓和一LED模組的跨壓之間具有低壓差的情況下,藉由一遮罩機制防止一LED驅動電路進入過壓保護模式,以避免該LED模組發生閃爍現象。 It is an object of the present invention to provide an LED driving circuit supporting low voltage input, which can prevent an LED driving circuit by a mask mechanism in the case of a low voltage difference between an input voltage and the cross-voltage of an LED module. Enter the over-voltage protection mode to avoid flickering of the LED module.
本案之另一目的在於提供一種支援低電壓輸入的LED驅動電路,其可在一LED驅動電路之一導通期間超過一預設的最大導通時間時,藉由一遮罩機制防止該LED驅動電路進入過壓保護模式,以避免一LED模組發生閃爍現象。 Another object of the present invention is to provide an LED driving circuit supporting low voltage input, which can prevent the LED driving circuit from entering through a mask mechanism when one of the LED driving circuits exceeds a preset maximum on time. Over-voltage protection mode to avoid flickering of an LED module.
為達上述目的,一種支援低電壓輸入的LED驅動電路乃被提出,其具有:一含一電感、一電容及一二極體之一電源轉換單元,係用以依一開關通道之控制將一輸入電壓轉成一輸出電流以驅動一LED模組;以及一控制單元,其具有:一邏輯控制單元,用以產生一開關信號,該開關信號具有一導通期間及一關斷期間;一驅動電路,具有該開關通道,該開關通道之一端係與該電源轉換單元耦接,該開關通道之另一端係經由一電阻耦接至一地電位以在該電阻產生一電流感測信號,且該開關通道係受該開關信號控制;一過壓保護模組,用以依所述關斷期間和一預設時間之一比較結果產生一過壓信號,當所述關斷期間小於該預設時間時,該過壓信號呈現一第一作用電位,當所述關斷期間不小於該預設時間時,該過壓信號呈現一第一不作用電位,該第一作用電位和該第一不作用電位係二互補的邏輯電位;以及一遮罩邏輯電路,用以判斷所述導通期間是否超過一最大導通期間並依一判斷結果決定一遮罩信號之電位,以及利用該遮罩信號遮罩該過壓信號以產生一過壓保護信號,其中,當所述導通期間超過該最大導通期間時,該遮罩信號呈現一第二作用電位,當所述導通期間未超過該最大導通期間時,該遮罩信號呈現一第二不作用電位,該第二作用電位和該第二不作用電位係二互補的邏輯電位;以及當該遮罩信號呈現所述第二作用電位時,該過壓保護信號 係呈現一不作用狀態以避免該邏輯控制單元進入一過壓保護模式,當該遮罩信號呈現所述第二不作用電位,且該過壓信號呈現所述第一作用電位時,該過壓保護信號係呈現一作用狀態以驅使該邏輯控制單元進入所述的過壓保護模式。 In order to achieve the above purpose, an LED driving circuit supporting low voltage input is proposed, which has: a power conversion unit including an inductor, a capacitor, and a diode, which is used to control a The input voltage is converted into an output current to drive an LED module; and a control unit having: a logic control unit for generating a switching signal, the switching signal has an on period and an off period; a driving circuit With the switch channel, one end of the switch channel is coupled to the power conversion unit, and the other end of the switch channel is coupled to a ground potential via a resistor to generate a current sensing signal at the resistor, and the switch The channel is controlled by the switching signal; an overvoltage protection module is used to generate an overvoltage signal according to a comparison result between the off period and a preset time, when the off period is less than the preset time , The overvoltage signal presents a first applied potential, and when the off period is not less than the preset time, the overvoltage signal presents a first inactive potential, the first applied potential and the An inactive potential is two complementary logic potentials; and a mask logic circuit for determining whether the conduction period exceeds a maximum conduction period and determining a potential of a mask signal according to a determination result, and using the mask signal The over-voltage signal is masked to generate an over-voltage protection signal, wherein when the conduction period exceeds the maximum conduction period, the mask signal presents a second action potential, and when the conduction period does not exceed the maximum conduction period When the mask signal presents a second inactive potential, the second applied potential and the second inactive potential are two complementary logic potentials; and when the mask signal exhibits the second applied potential, the transition Voltage protection signal It is in an inactive state to prevent the logic control unit from entering an overvoltage protection mode. When the mask signal represents the second inactive potential and the overvoltage signal represents the first active potential, the overvoltage The protection signal is in an active state to drive the logic control unit into the over-voltage protection mode.
在一實施例中,所述控制單元具有一電流過零檢測模組以在所述電感的電流降至零時使該開關信號開始一所述的導通期間。 In one embodiment, the control unit has a current zero-crossing detection module to enable the switching signal to start a conducting period when the current of the inductor drops to zero.
在一實施例中,該遮罩邏輯電路具有:一閂鎖單元,具有一第一輸入端、一第二輸入端及一輸出端,該第一輸入端係用以與一最大導通時間狀態信號耦接,且該第二輸入端係與一電流峰值信號耦接;一反相器,具有一輸入端以與該閂鎖單元的所述輸出端耦接,及一輸出端以提供所述的遮罩信號;以及一反及閘,具有二輸入端以分別與所述的遮罩信號及所述的過壓信號耦接,及一輸出端以提供所述的過壓保護信號。 In one embodiment, the mask logic circuit includes a latch unit having a first input terminal, a second input terminal, and an output terminal. The first input terminal is used to communicate with a maximum on-time state signal. Coupled, and the second input terminal is coupled to a current peak signal; an inverter having an input terminal to be coupled to the output terminal of the latch unit, and an output terminal to provide the A mask signal; and an inverse gate, having two input terminals to be coupled to the mask signal and the overvoltage signal, respectively, and an output terminal to provide the overvoltage protection signal.
在一實施例中,該遮罩邏輯電路具有:一最大導通時間模組,用以產生所述最大導通時間狀態信號,且其係在所述導通期間超過所述最大導通期間時使所述最大導通時間狀態信號呈現一作用狀態;以及一峰值電流檢測模組,用以產生所述的電流峰值信號,且其係在所述電感的電流到達一峰值時使所述的電流峰值信號呈現一作用狀態。 In one embodiment, the mask logic circuit has a maximum on-time module for generating the maximum on-time status signal, and the maximum-on-time state signal is used to make the maximum on-time when the on-time exceeds the maximum on-time. The on-time state signal exhibits an active state; and a peak current detection module for generating the current peak signal, and the peak current signal exhibits an effect when the current of the inductor reaches a peak status.
在一實施例中,該閂鎖單元包含一反或閘閂鎖器。 In one embodiment, the latch unit includes a reverse or gate latch.
在一實施例中,該閂鎖單元包含一反及閘閂鎖器。 In one embodiment, the latch unit includes a reverse latch latch.
在一實施例中,該遮罩邏輯電路具有:一閂鎖單元,具有一第一輸入端、一第二輸入端及一輸出端,該第一輸入端係用以與一前沿消隱信號耦接,且該第二輸入端係與一電流比較信號耦接;一反相器,具有一輸入端以與該閂鎖單元的所述輸出端耦接,及一輸出端以提供所述的遮罩信號;一反及閘,具有二輸入端以分別與所述的遮罩信號及所述的過壓信號耦接,及一輸出端以提供所述的過壓保護信號; 一前沿消隱信號產生模組,用以產生所述的前沿消隱信號,且其係在所述導通期間的一初始期間呈現一作用狀態;以及一比較器,用以依該電流感測信號及一參考電壓進行一比較運算以產生所述的電流比較信號。 In one embodiment, the mask logic circuit has a latch unit having a first input terminal, a second input terminal, and an output terminal. The first input terminal is used for coupling with a leading edge blanking signal. Connected, and the second input terminal is coupled with a current comparison signal; an inverter having an input terminal to be coupled to the output terminal of the latch unit, and an output terminal to provide the shielding Shroud signal; a reverse sum brake having two input terminals to be coupled to the mask signal and the overvoltage signal, and an output terminal to provide the overvoltage protection signal; A leading-edge blanking signal generating module for generating the leading-edge blanking signal, which is in an active state during an initial period of the conducting period; and a comparator for sensing the signal according to the current Perform a comparison operation with a reference voltage to generate the current comparison signal.
在一實施例中,該閂鎖單元包含一反或閘閂鎖器。 In one embodiment, the latch unit includes a reverse or gate latch.
在一實施例中,該閂鎖單元包含一反及閘閂鎖器。 In one embodiment, the latch unit includes a reverse latch latch.
另外,本發明亦提出一種控制晶片,其包含如前述之支援低電壓輸入的LED驅動電路的所述控制單元。 In addition, the present invention also provides a control chip including the control unit of the LED driving circuit supporting the low voltage input as described above.
為使 貴審查委員能進一步瞭解本創作之結構、特徵及其目的,茲附以圖式及較佳具體實施例之詳細說明如後。 In order to allow your reviewers to further understand the structure, characteristics and purpose of this creation, drawings and detailed descriptions of the preferred embodiments are attached below.
11‧‧‧橋式整流單元 11‧‧‧Bridge rectifier unit
12、14、15‧‧‧電容 12, 14, 15‧‧‧ capacitors
13、20、21‧‧‧電阻 13, 20, 21‧‧‧ resistance
16、300‧‧‧LED模組 16, 300‧‧‧LED module
17‧‧‧二極體 17‧‧‧diode
18‧‧‧電感 18‧‧‧Inductance
19‧‧‧控制晶片 19‧‧‧control chip
100‧‧‧電源轉換單元 100‧‧‧ Power Conversion Unit
200‧‧‧控制單元 200‧‧‧Control unit
201‧‧‧邏輯控制單元 201‧‧‧Logic Control Unit
202‧‧‧驅動電路 202‧‧‧Drive circuit
203‧‧‧電流過零檢測模組 203‧‧‧Current zero-crossing detection module
204‧‧‧過壓保護模組 204‧‧‧Overvoltage protection module
205‧‧‧遮罩邏輯電路 205‧‧‧Mask logic circuit
2051‧‧‧閂鎖單元 2051‧‧‧Latch unit
2051a、2051b‧‧‧反或閘 2051a, 2051b ‧‧‧ reverse OR gate
2052‧‧‧反相器 2052‧‧‧Inverter
2053‧‧‧反及閘 2053‧‧‧Reverse Gate
2054‧‧‧最大導通時間模組 2054‧‧‧Maximum On-Time Module
2055‧‧‧峰值電流檢測模組 2055‧‧‧Peak current detection module
2056‧‧‧前沿消隱信號產生模組 2056‧‧‧ Leading-Edge Blanking Signal Generation Module
2057‧‧‧比較器 2057‧‧‧ Comparator
圖1繪示一習知開關型LED驅動電路的電路圖。 FIG. 1 is a circuit diagram of a conventional switch-type LED driving circuit.
圖2繪示圖1之習知開關型LED驅動電路的電感電流波形圖。 FIG. 2 is a waveform diagram of an inductor current of the conventional switching LED driving circuit of FIG. 1.
圖3繪示本發明支援低電壓輸入的LED驅動電路之一實施例方塊圖。 FIG. 3 is a block diagram of an LED driving circuit supporting low voltage input according to an embodiment of the present invention.
圖4為圖3所示之一控制單元中之一遮罩邏輯電路之一實施例方塊圖。 FIG. 4 is a block diagram of an embodiment of a mask logic circuit in a control unit shown in FIG. 3.
圖5為圖3所示之一控制單元中之一遮罩邏輯電路之另一實施例方塊圖。 FIG. 5 is a block diagram of another embodiment of a mask logic circuit in a control unit shown in FIG. 3.
請參照圖3,其繪示本發明支援低電壓輸入的LED驅動電路之一實施例方塊圖。如圖3所示,該LED驅動電路具有一電源轉換單元100及一控制單元200以驅動一LED模組300。 Please refer to FIG. 3, which is a block diagram illustrating an embodiment of an LED driving circuit supporting low voltage input according to the present invention. As shown in FIG. 3, the LED driving circuit has a power conversion unit 100 and a control unit 200 to drive an LED module 300.
電源轉換單元100含有一電感、一電容及一二極體,且係用以依一開關通道(該開關通道係由控制單元200內部之一開關電晶體(未示於圖中)提供)之控制將一輸入電壓VIN轉成一輸出電流IOUT以驅動LED模組300,其中LED模組300具有一跨壓VLED。 The power conversion unit 100 includes an inductor, a capacitor, and a diode, and is used to control a switching channel (the switching channel is provided by a switching transistor (not shown) inside the control unit 200). An input voltage V IN is converted into an output current I OUT to drive the LED module 300, wherein the LED module 300 has a cross-voltage V LED .
控制單元200,可由一控制晶片實現,具有一邏輯控制單元201、一驅動電路202、一電流過零檢測模組203、一過壓保護模組204及一遮罩邏輯電路205。 The control unit 200 may be implemented by a control chip, and has a logic control unit 201, a driving circuit 202, a current zero crossing detection module 203, an overvoltage protection module 204, and a mask logic circuit 205.
邏輯控制單元201係用以產生一開關信號VPWM,該開關信號VPWM具有一導通期間及一關斷期間,且係一電流過零信號ZCD之觸發開始一所述的導通期間。 The logic control unit 201 is used to generate a switching signal V PWM . The switching signal V PWM has a turn-on period and a turn-off period, and is triggered by a current zero-crossing signal ZCD to start a turn-on period.
驅動電路202具有該開關通道,該開關通道之一端D係與該電源轉換單元100耦接,另一端CS係經由一電阻210耦接至一地電壓以產生該電感的一電流感測信號VCS,且該開關通道係受該開關信號VPWM控制。 The driving circuit 202 has the switching channel. One end D of the switching channel is coupled to the power conversion unit 100, and the other end CS is coupled to a ground voltage via a resistor 210 to generate a current sensing signal V CS of the inductor. , And the switching channel is controlled by the switching signal V PWM .
電流過零檢測模組203係用以在所述電感的電流降至零時使該開關信號開始一所述的導通期間。 The current zero-crossing detection module 203 is used to make the switching signal start a conducting period when the current of the inductor drops to zero.
過壓保護模組204係用以依所述關斷期間之一代表信號TOFF和一預設時間之一比較結果產生一過壓信號OVP,當所述關斷期間小於該預設時間時,該過壓信號OVP呈現一第一作用電位,以及當所述關斷期間不小於該預設時間時,該過壓信號OVP呈現一第一不作用電位,且該第一作用電位和該第一不作用電位係二互補的邏輯電位(例如分別為一高邏輯電位和一低邏輯電位,或分別為一低邏輯電位和一高邏輯電位)。 The over-voltage protection module 204 is configured to generate an over-voltage signal OVP according to a comparison result between a representative signal T OFF and a preset time during the shutdown period. When the shutdown period is shorter than the preset time, The overvoltage signal OVP presents a first applied potential, and when the off period is not less than the preset time, the overvoltage signal OVP presents a first inactive potential, and the first applied potential and the first applied potential The inactive potential is two complementary logic potentials (eg, a high logic potential and a low logic potential, or a low logic potential and a high logic potential, respectively).
遮罩邏輯電路205係用以判斷所述導通期間是否超過一最大導通期間並依一判斷結果決定一遮罩信號之電位,以及利用該遮罩信號遮罩該過壓信號OVP以產生一過壓保護信號OVPOUT,其中,當所述導通期間超過該最大導通期間時,該遮罩信號呈現一第二作用電位,及當所述導通期間未超過該最大導通期間時,該遮罩信號呈現一第二不作用電位,該第二作用電位和該第二不作用電位係二互補的邏輯電位(例如分別為一高邏輯電位和一低邏輯電位,或分別為一低邏輯電位和一高邏輯電位);以及當該遮罩信號呈現所述第二作用電位時,該過壓保護信號OVPOUT係呈現一不作用狀態以避免該邏輯控制單元201進入一過壓保護模式,及當該遮罩信號呈現所述第二不作用電位,且該過壓信號OVP呈現所述第一作用電位時,該過壓保護信號OVPOUT係呈現一作用狀態以驅使該邏輯控制單元201進入所述的過壓保護模式。 The mask logic circuit 205 is used to determine whether the conduction period exceeds a maximum conduction period and determine the potential of a mask signal according to a judgment result, and use the mask signal to mask the overvoltage signal OVP to generate an overvoltage. The protection signal OVPOUT, wherein when the conducting period exceeds the maximum conducting period, the mask signal presents a second applied potential, and when the conducting period does not exceed the maximum conducting period, the mask signal presents a first Two inactive potentials, the second inactive potential and the second inactive potential are two complementary logic potentials (eg, a high logic potential and a low logic potential, or a low logic potential and a high logic potential, respectively) ; And when the mask signal presents the second applied potential, the overvoltage protection signal OVPOUT assumes an inactive state to prevent the logic control unit 201 from entering an overvoltage protection mode, and when the mask signal presents When the second inactive potential is described and the overvoltage signal OVP presents the first applied potential, the overvoltage protection signal OVPOUT presents an active state to drive the logic control Overvoltage protection means 201 enters the mode.
請參照圖4,其為圖3之控制單元200之遮罩邏輯電路205之一實施例之方塊圖。如圖4所示,該遮罩邏輯電路205具有一閂鎖單元2051、一反相器2052、一反及閘2053、一最大導通時間模組2054及一峰值電流檢測模組2055。 Please refer to FIG. 4, which is a block diagram of an embodiment of a mask logic circuit 205 of the control unit 200 of FIG. 3. As shown in FIG. 4, the mask logic circuit 205 has a latch unit 2051, an inverter 2052, a reverse AND gate 2053, a maximum on-time module 2054, and a peak current detection module 2055.
閂鎖單元2051具有一第一輸入端、一第二輸入端及一輸出端,該第一輸入端係用以與一最大導通時間狀態信號TON_MAX耦接,且該第二輸入端係與一電流峰值信號CS_OUT耦接。在此實施例中,雖然閂鎖單元2051係由一反或閘閂鎖器(由反或閘2051a及反或閘2051b構成)實現,其亦可由一反及閘閂鎖器實現。 The latch unit 2051 has a first input terminal, a second input terminal, and an output terminal. The first input terminal is used for coupling with a maximum on-time state signal TON_MAX, and the second input terminal is connected with a current. The peak signal CS_OUT is coupled. In this embodiment, although the latch unit 2051 is implemented by a reverse OR gate latch (consisting of reverse OR gate 2051a and reverse OR gate 2051b), it can also be implemented by a reverse OR gate latch.
反相器2052具有一輸入端以與該閂鎖單元2051的所述輸出端耦接,及一輸出端以提供一遮罩信號MSK。 The inverter 2052 has an input terminal to be coupled to the output terminal of the latch unit 2051, and an output terminal to provide a mask signal MSK.
反及閘2053具有二輸入端以分別與所述的遮罩信號MSK及所述的過壓信號OVP耦接,及一輸出端以提供所述的過壓保護信號OVPOUT。 The inverting gate 2053 has two input terminals to be respectively coupled to the mask signal MSK and the overvoltage signal OVP, and an output terminal to provide the overvoltage protection signal OVPOUT.
最大導通時間模組2054係用以產生一最大導通時間狀態信號TON_MAX,且其係在所述導通期間超過所述最大導通期間時使所述最大導通時間狀態信號TON_MAX呈現一作用狀態(在此實施例中,所述作用狀態係一高邏輯電位)。 The maximum on-time module 2054 is used to generate a maximum on-time status signal TON_MAX, and it causes the maximum on-time status signal TON_MAX to assume an active state when the on-period exceeds the maximum on-period (implemented here) In the example, the action state is a high logic potential).
峰值電流檢測模組2055係用以產生一電流峰值信號CS_OUT,且其係在所述電感的電流到達一峰值時使所述的電流峰值信號CS_OUT呈現一作用狀態,以在每個開關週期中給遮罩邏輯電路205重置。 The peak current detection module 2055 is used to generate a current peak signal CS_OUT, and it makes the current peak signal CS_OUT present an active state when the current of the inductor reaches a peak value, so as to provide The mask logic circuit 205 is reset.
請參照圖5,其為圖3之控制單元200之遮罩邏輯電路205之另一實施例之方塊圖。如圖5所示,該遮罩邏輯電路205具有一閂鎖單元2051、一反相器2052、一反及閘2053、一前沿消隱信號產生模組2056及一比較器2057。 Please refer to FIG. 5, which is a block diagram of another embodiment of the mask logic circuit 205 of the control unit 200 of FIG. 3. As shown in FIG. 5, the mask logic circuit 205 has a latch unit 2051, an inverter 2052, an inverse AND gate 2053, a leading-edge blanking signal generation module 2056, and a comparator 2057.
閂鎖單元2051具有一第一輸入端、一第二輸入端及一輸出端,該第一輸入端係用以與一前沿消隱信號CS_LEB耦接,且該第二輸入端係與一電流比較信號CMP耦接。在此實施例中,雖然閂鎖單元2051係由一反或閘閂鎖器(由反或閘2051a及反或閘2051b構成)實現,其亦可由一反及閘閂鎖器實現。 The latch unit 2051 has a first input terminal, a second input terminal and an output terminal. The first input terminal is used for coupling with a leading edge blanking signal CS_LEB, and the second input terminal is compared with a current. The signal CMP is coupled. In this embodiment, although the latch unit 2051 is implemented by a reverse OR gate latch (consisting of reverse OR gate 2051a and reverse OR gate 2051b), it can also be implemented by a reverse OR gate latch.
反相器2052具有一輸入端以與該閂鎖單元2051的所述輸出端耦接,及一輸出端以提供一遮罩信號MSK。 The inverter 2052 has an input terminal to be coupled to the output terminal of the latch unit 2051, and an output terminal to provide a mask signal MSK.
反及閘2053具有二輸入端以分別與所述的遮罩信號MSK及所述的過壓信號OVP耦接,及一輸出端以提供所述的過壓保護信號OVPOUT。 Reverse gate 2053 has two input terminals to be coupled to the mask signal MSK and the overvoltage signal OVP, respectively, and an output terminal to provide the overvoltage protection signal OVPOUT.
前沿消隱信號產生模組2056係用以產生所述的前沿消隱信號CS_LEB,且其係在所述導通期間的一初始期間呈現一作用狀態(在此實施例中,所述作用狀態係一高邏輯電位脈衝)以在每個開關週期中給遮罩邏輯電路205重置。 The leading-edge blanking signal generation module 2056 is used to generate the leading-edge blanking signal CS_LEB, and it shows an active state during an initial period of the on period (in this embodiment, the active state is a High logic potential pulse) to reset the mask logic circuit 205 in each switching cycle.
比較器2057係用以依該電感的電流感測信號VCS及一參考電壓VREF進行一比較運算以產生所述的電流比較信號CMP。電流感測信號VCS的波形如圖2的電感電流iL的波形,在導通階段中,控制單元200使內部之所述開關電晶體導通,以對該電感進行儲能,此時該電感的電流iL會一直上升,電阻210所提供的電流感測信號VCS的電壓也隨之上升;在截止階段中,控制單元200使內部之所述開關電晶體關斷,該電感經由該二極體釋放能量,該電感的電流iL乃從峰值IPK下降,電流感測信號VCS的電壓也隨之下降。當電流感測信號VCS的峰值電壓大於參考電壓VREF時,代表所述導通期間超過該最大導通期間。 The comparator 2057 is configured to perform a comparison operation according to the current sensing signal V CS of the inductor and a reference voltage V REF to generate the current comparison signal CMP. The waveform of the current sensing signal V CS is shown in the waveform of the inductor current iL in FIG. 2. During the conducting phase, the control unit 200 turns on the internal switching transistor to store energy in the inductor. At this time, the current of the inductor iL will keep rising, and the voltage of the current sensing signal V CS provided by the resistor 210 will also rise accordingly; in the cut-off phase, the control unit 200 turns off the internal switching transistor, and the inductance is released through the diode Energy, the current iL of the inductor decreases from the peak value I PK , and the voltage of the current sensing signal V CS also decreases accordingly. When the peak voltage of the current sensing signal V CS is greater than the reference voltage V REF , it means that the on-period exceeds the maximum on-period.
依上述之技術方案,本發明即可在VIN的電壓與LED模組300的跨壓VLED之間具有低壓差的情況下,藉由一遮罩機制防止LED驅動電路進入過壓保護模式,從而避免LED模組300發生閃爍現象。另外,由於本發明係於每個開關週期的所述導通期間將遮罩邏輯電路205重置,以及在所述截止期間檢測VIN和VLED的電壓差,以決定是否需要產生遮罩信號MSK,因此,當VIN電壓由低上升到很高時,遮罩信號MSK就不會因一直呈現所述作用狀態而一直遮罩過壓信號OVP,而使LED模組300有燒燈的風險。也就是說,本發明既可避免LED模組300發生閃爍現象,亦可使LED模組300免除燒燈的風險。 According to the above technical solution, the present invention can prevent the LED driving circuit from entering the over-voltage protection mode by a mask mechanism in the case where there is a low voltage difference between the voltage of V IN and the across-voltage V LED of the LED module 300. As a result, flickering of the LED module 300 is prevented. In addition, the present invention resets the mask logic circuit 205 during the on period of each switching cycle, and detects the voltage difference between V IN and V LED during the off period to determine whether the mask signal MSK needs to be generated. Therefore, when the V IN voltage rises from low to high, the mask signal MSK will not always mask the over-voltage signal OVP because it always presents the operating state, so that the LED module 300 has a risk of burning. In other words, the present invention can prevent the LED module 300 from flickering, and can also avoid the risk of burning the LED module 300.
另外,由於全球民用交流電標準主要有220V區域和110V區域兩種交流電標準,本發明特針對所述兩種交流電標準提供不同的對應實施例: In addition, since the global civil alternating current standard mainly has two alternating current standards of 220V area and 110V area, the present invention provides different corresponding embodiments for the two alternating current standards:
(1)220V區域(220V~240V),主要有中國,歐洲,印度等140個國家採用。 (1) The 220V area (220V ~ 240V) is mainly used in 140 countries including China, Europe, and India.
當驅動一18W的系統時,LED輸出典型值為150V/110mA,電容C1一般採用4.7uF。如果交流電的輸入電壓低至176VAC(低於典型值220VAC的20%),母線電壓VIN會接近LED模組的輸出電壓而使所述導通期間超過所述的最大導通時間,從而可能會過早關閉開關通道。此時,採用本發明的技術方案即可避免過早關閉開關通道而使LED模組不致發生閃爍現象。 When driving an 18W system, the typical LED output is 150V / 110mA, and the capacitor C1 generally uses 4.7uF. If the input voltage of the AC power is as low as 176VAC (less than 20% of the typical value of 220VAC), the bus voltage V IN will be close to the output voltage of the LED module and the on-time will exceed the maximum on-time, which may be premature. Switch off the channel. At this time, using the technical solution of the present invention can avoid prematurely closing the switch channel and preventing the LED module from flickering.
(2)110V區域(100V~130V),主要有美國,日本,加拿大等國家採用。 (2) 110V area (100V ~ 130V), mainly used in the United States, Japan, Canada and other countries.
當驅動一18W的系統,LED輸出典型值為72V/240mA時,電容C1一般採用6.8uF。如果交流電的輸入電壓低至88VAC(低於典型值220VAC的20%),母線電壓VIN會接近LED模組的輸出電壓而使所述導通期間超過所述的最大導通時間,從而可能會過早關閉開關通道。此時,採用本發明的技術方案即可避免過早關閉開關通道而使LED模組不致發生閃爍現象。 When driving an 18W system with a typical LED output of 72V / 240mA, the capacitor C1 generally uses 6.8uF. If the input voltage of the AC power is as low as 88VAC (less than 20% of the typical value of 220VAC), the bus voltage V IN will be close to the output voltage of the LED module and the on-time will exceed the maximum on-time, which may be premature. Switch off the channel. At this time, using the technical solution of the present invention can avoid prematurely closing the switch channel and preventing the LED module from flickering.
藉由前述所揭露的設計,本發明乃具有以下的優點: With the design disclosed above, the present invention has the following advantages:
1、本發明的支援低電壓輸入的LED驅動電路可在一輸入電壓和一LED模組的跨壓之間具有低壓差的情況下,藉由一遮罩機制防止一LED驅動電路進入過壓保護模式,以避免該LED模組發生閃爍現象。 1. The LED driving circuit supporting low voltage input of the present invention can prevent an LED driving circuit from entering overvoltage protection by a mask mechanism in the case of a low voltage difference between an input voltage and the cross-voltage of an LED module. Mode to avoid flickering of the LED module.
2、本發明的支援低電壓輸入的LED驅動電路可在一LED驅動電路之一導通期間超過一預設的最大導通時間時,藉由一遮罩機制防止該LED驅動電路進入過壓保護模式,以避免一LED模組發生閃爍現象。 2. The LED driving circuit supporting low voltage input of the present invention can prevent the LED driving circuit from entering the overvoltage protection mode by a mask mechanism when one of the LED driving circuits is turned on during a preset maximum on time. To avoid flickering of an LED module.
本案所揭示者,乃較佳實施例之一種,舉凡局部之變更或修飾而源於本案之技術思想而為熟習該項技藝之人所易於推知者,俱不脫本案之專利權範疇。 The one disclosed in this case is one of the preferred embodiments, and any change or modification that originates from the technical ideas of this case and is easily inferred by those who are familiar with the technology, does not depart from the scope of patent rights in this case.
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