TWI419450B - A system and method for reducing the standby power consumption of a switch mode power converter - Google Patents

Description

System and method for reducing standby power consumption of a switch mode power converter

The present invention relates to an integrated circuit. More specifically, the present invention provides systems and methods for reducing power consumption under light or no load conditions. By way of example only, the invention has been applied to a switch mode power converter under standby conditions. However, it will be appreciated that the invention has a broader range of applications.

Power converters have been widely used in consumer electronics such as portable devices. A power converter converts electrical energy from one form to another. As an example, electrical energy is converted from alternating current (AC) to direct current (DC), from DC to AC, from AC to AC, or from DC to DC. In addition, the power converter can convert electrical energy from one voltage level to another. Specifically, the power converter includes a linear converter and a switch mode converter. Switch mode converters typically use pulse width modulation (PWM) or pulse frequency modulation (PFM) mechanisms. Switch mode converters are generally more efficient than linear converters.

Power converters often have to meet various international standards related to energy efficiency, such as Energy Star requirements and Blue Angel requirements. Therefore, power converters typically require low power consumption and high power efficiency under light load or no load conditions such as standby, suspend, or some other idle state.

1 is a simplified conventional schematic diagram illustrating a switched mode power converter system having an X resistor and an X capacitor. Switch mode power converter system 100 includes X resistor 110, X capacitor 120, input terminals 122 and 124, switch mode controller 130, diodes 152, 154, 156 and 158, capacitor 160, primary winding 172, secondary winding 174. Auxiliary winding 176 and switch 180. For example, switch mode controller 130 includes terminals 132, 134, 136, 138, and 139. In another example, terminals 132, 134, 136, 138, and 139 are a GND pin, a FB pin, a VCC pin, a GATE pin, and a CS pin, respectively.

In order to reduce the power consumption of the conversion system 100 under standby conditions, it is generally important to reduce the power consumption of the switch mode controller 130. In addition, the conversion system 100 also includes other components that may become more significant in standby conditions when the power consumption of the switch mode controller 130 is reduced. Therefore, there is also a need to reduce the power consumption of these other components to further reduce the power consumption of the switched mode power converter system 100.

As shown in FIG. 1, switch mode power converter system 100 includes an X capacitor 120 coupled to input terminals 122 and 124. The X capacitor 120 is typically used to solve the problem of electromagnetic interference (EMI). However, in order to maintain the safety of the power converter system 100 to the human body, the X capacitor 120 needs to be quickly discharged so that the voltage across the X capacitor 120 can drop in 1 second after the input terminals 122 and 124 are disconnected from the AC power source. Below the predetermined threshold. To assist in discharging the X capacitor 120, the power converter system 100 also includes an X resistor 110 coupled in parallel with the X capacitor 120. However, the X resistor 110 will increase the power consumption of the power converter system 100 under standby conditions.

Therefore, it is highly desirable to improve the technique of reducing power consumption in standby conditions.

The present invention relates to an integrated circuit. More specifically, the present invention provides systems and methods for reducing power consumption under light or no load conditions. Merely by way of example, the invention has been applied to switch mode power converters in standby conditions. However, it will be appreciated that the invention has a broader range of applications.

According to one embodiment, a power conversion system includes: a first capacitor including a first capacitor terminal and a second capacitor terminal; a second capacitor including a third capacitor terminal and a fourth capacitor terminal; and a plurality of diodes including the first a diode, a second diode, a third diode, and a fourth diode. The first diode is coupled to the second diode at the first node, the second diode is coupled to the fourth diode at the second node, and the fourth diode is coupled to the third node at the third node The diode, the third diode, couples the first diode at the fourth node. Additionally, the system includes a fifth diode including a first anode and a first cathode, and a sixth diode including a second anode and a second cathode. The first anode is connected to the first input terminal, the second anode is connected to the second input terminal, and the first cathode and the second cathode are connected to the fifth node. Additionally, the system includes a system controller including a first controller terminal, a second controller terminal, a third controller terminal, a fourth controller terminal, and a fifth controller terminal. Additionally, the system includes a primary winding including a first winding terminal and a second winding terminal, a secondary winding coupled to the primary winding, and an auxiliary winding coupled to the secondary winding. Additionally, the system includes a switch including a first switch terminal and a second switch terminal. The first node is connected to the first input terminal, the second node is connected to the first winding terminal, the third node is connected to the second input terminal, the fourth node is biased to a predetermined voltage, and the fifth node is connected to the first controller terminal . The second controller terminal is connected to the second input terminal, the third controller terminal is biased to a predetermined voltage, and the fourth controller terminal is connected to the third capacitor terminal. The fourth capacitor terminal is biased to a predetermined voltage, the first capacitor terminal is connected to the first input terminal, and the second capacitor terminal is connected to the second input terminal. The first switch terminal is connected to the fifth controller terminal, and the second switch terminal is connected to the second winding terminal. The first input terminal and the second input terminal are configured to receive an input voltage, and the secondary winding is configured to generate an output voltage based at least on information associated with the input voltage.

In accordance with another embodiment, a system for discharging a capacitor of a power conversion system includes a first capacitor including a first capacitor terminal and a second capacitor terminal. The first capacitor terminal is connected to the first input terminal and the second capacitor terminal is connected to the second input terminal. Additionally, the system includes a second capacitor including a third capacitor terminal and a fourth capacitor terminal, the fourth capacitor terminal being biased to a predetermined voltage. Additionally, the system includes a first diode including a first anode and a first cathode, and a second diode including a second anode and a second cathode. The first anode is connected to the first input terminal and the second anode is connected to the second input terminal. Additionally, the system includes a system controller including a first controller terminal, a second controller terminal, a third controller terminal, and a fourth controller terminal. The first controller terminal is connected to the first cathode and the second cathode, the second controller terminal is connected to the second input terminal, the third controller terminal is biased to a predetermined voltage, and the fourth controller terminal is connected to the third capacitor Terminal. The system controller also includes a sensing element, a transistor, and an undervoltage lockout element. The detecting component is configured to receive a first input voltage from the second input terminal via the second controller terminal, receive a first signal from the undervoltage lockout component, based at least on information associated with the first input voltage and the first signal A second signal is generated and the second signal is sent to the first transistor. If the first input voltage is lower in magnitude than the first threshold voltage and the first signal is at a logic high level, then the second signal is at a logic high level. The transistor includes a first transistor terminal, a second transistor terminal, and a third transistor terminal. The first transistor terminal is configured to receive a second signal from the sensing element and the second transistor terminal is coupled to the third controller terminal. The undervoltage lockout element is configured to receive a second input voltage from the third capacitor terminal via the fourth controller terminal and to generate the first signal based on at least information associated with the second input voltage. If the second input voltage is greater in magnitude than the second threshold voltage, the second signal is at a logic high level.

In accordance with yet another embodiment, a system for discharging a capacitor of a power conversion system includes a first controller terminal. The first controller terminal is configured to receive a discharge current from the first diode or the second diode. The first diode and the second diode are coupled to the first capacitor, and the first capacitor is configured to be charged by the first input terminal and the second input terminal. Additionally, the system includes a second controller terminal configured to receive a first input voltage from the second input terminal, a third controller terminal biased to a predetermined voltage, and a fourth controller terminal configured to receive A second input voltage from the second capacitor. Furthermore, the system comprises a detection element. The detecting component is configured to receive a first input voltage from the second input terminal via the second controller terminal, receive a first signal from the undervoltage lockout component, based at least on information associated with the first input voltage and the first signal The second signal is generated and the second signal is sent to the transistor. If the first input voltage is lower in magnitude than the first threshold voltage and the first signal is at a logic high level, then the second signal is at a logic high level. Additionally, the system includes a transistor including a first transistor terminal, a second transistor terminal, and a third transistor terminal. The first transistor terminal is configured to receive a second signal from the sensing element and the second transistor terminal is coupled to the third controller terminal. Additionally, the system includes an under-pressure locking element. The undervoltage lockout element is configured to receive a second input voltage from the second capacitor via the fourth controller terminal and to generate the first signal based on at least information associated with the second input voltage. If the second input voltage is greater in magnitude than the second threshold voltage, the second signal is at a logic high level.

Many benefits are obtained by the present invention compared to conventional techniques. Certain embodiments of the present invention reduce standby power consumption of PWM controlled switched mode power converters, such as off-line flyback converters and/or forward converters.

One or more of these benefits may be obtained depending on the embodiment. These and other additional objects, features and advantages of the present invention will be fully understood from the description and appended claims.

The present invention relates to an integrated circuit. More specifically, the present invention provides systems and methods for reducing power consumption under light or no load conditions. Merely by way of example, the invention has been applied to switch mode power converters in standby conditions. However, it will be appreciated that the invention has a much broader range of applications.

Referring to FIG. 1, after the input terminals 122 and 124 are removed from the AC power source, the electric charge accumulated on the X capacitor 120 is discharged via the X resistor 110. Therefore, the voltage across the X capacitor 120 will decrease over time as follows.

Where V _xc is the voltage across the X capacitor 120 and V _O is the voltage value of V _xc when the input terminals 122 and 124 are disconnected from the AC power source. R _x and C _x are resistance values and capacitance values of the X resistor 110 and the X capacitor 120, respectively.

In order for V _{xc to} drop by a factor of e in 1 second,

In general, the size of _Cx depends on the power of the switched mode power converter system 100 and the resolution of electromagnetic interference. If the capacitance of the X capacitor 120 is increased, the resistance of the X resistor 110 will become smaller according to Equation 2. Therefore, the power consumption of the X resistor 110 also increases under standby conditions, although the X resistor 110 is typically useful for discharging the X capacitor 120 after the terminals 122 and 124 are disconnected from the AC power source.

Therefore, in order to reduce the power consumption of the switch mode power converter system 100, it is desirable to disconnect the X resistor 110 under standby conditions or simply avoid using the X resistor 110 for discharging the X capacitor 120.

2 is a simplified schematic diagram illustrating a switched mode power converter system in accordance with an embodiment of the present invention. This schematic is merely an example and should not unduly limit the scope of the claimed patent. Those skilled in the art will recognize many variations, substitutions and modifications.

As shown in FIG. 2, the switched mode power converter system 200 includes diodes 210 and 212, an X capacitor 220, input terminals 222 and 224, a switch mode controller 230, diodes 252, 254, 256, and 258, and a capacitor 260. Primary winding 272, secondary winding 274, auxiliary winding 276, and switch 280. For example, switch mode controller 230 includes terminals 232, 234, 236, 238, 239, 240, and 242. In another example, terminals 232, 234, 236, 238, 239, 240, and 242 are a GND pin, a FB pin, a VCC pin, a GATE pin, a CS pin, a Z pin, and a VAC pin, respectively. In yet another example, terminal 232 is biased to ground.

3(A) and (B) are simplified diagrams illustrating the discharge of X capacitor 220 in a switched mode power converter system 200 in accordance with some embodiments of the present invention. These diagrams are merely examples and should not unduly limit the scope of the patent application. Those skilled in the art will recognize many variations, substitutions and modifications.

As shown in FIG. 3(A), according to an embodiment, input terminals 222 and 224 are disconnected from the AC power source during the positive half cycle of the AC input. After the disconnection, the positive charge accumulated on the X capacitor 220 is released by flowing from one terminal to the other terminal. For example, a positive charge flows through the diode 210, the terminal 240, the terminal 232, and the diode 256.

As shown in FIG. 3(B), according to another embodiment, input terminals 222 and 224 are disconnected from the AC power source during the negative half cycle of the AC input. After the disconnection, the positive charge accumulated on the X capacitor 220 is released by flowing from one terminal to the other terminal. For example, a positive charge flows through the diode 212, the pin 240, the pin 232, and the diode 252.

4 is a simplified schematic diagram illustrating a switch mode controller 230 in a switched mode power converter system 200 in accordance with an embodiment of the present invention. This schematic is merely an example and should not unduly limit the scope of the claimed patent. Those skilled in the art will recognize many variations, substitutions and modifications.

As shown in FIG. 4, the switch mode controller 230 includes a detecting component 410, transistors 420, 422, and 424, an under-voltage-lockout (UVLO) component 430, a resistor 440, a PWM signal generator 450, and logic. Control element 452 and gate driver 454.

For example, detection element 410 is configured to receive an input voltage from terminal 242 and an output signal 432 of UVLO element 430 and generate an output signal 412. In another example, if the input voltage at terminal 242 is equal to or higher than a first predetermined threshold, then output signal 412 of detection element 410 is at a logic low level. In yet another example, if the input voltage at terminal 242 falls below a first predetermined threshold, then if output signal 432 of UVLO element 430 is also at a logic high level, output signal 412 of detection element 410 is a logic high. Bit.

According to an embodiment, if terminals 222 and 224 are connected to the AC input during startup of switch mode power converter system 200, the input voltage at terminal 242 is equal to or higher than a first predetermined threshold. For example, if the input voltage received by terminal 236 is below a second predetermined threshold, then output signal 432 of UVLO element 430 is at a logic low level and controller 230 is in a UVLO protection mode. In another example, the output signal 412 of the sensing element 410 is at a logic low level and the transistor 424 is off. In yet another example, the transistor 422 is off and the transistor 420 is on. In yet another example, current flows through diode 210 or 212 and through terminal 240 and transistor 420 and charges capacitor 260, thereby raising the input voltage at terminal 236.

According to another embodiment, if the input voltage at terminal 242 remains equal to or above a first predetermined threshold and the input voltage at terminal 236 reaches or rises above a second predetermined threshold, then signal 432 becomes a logic high. Bits, and controller 230 is in an operational mode. For example, the output signal 412 of the sensing element 410 remains at a logic low level and the transistor 424 remains off. In another example, transistor 422 is open and transistor 420 is off. In yet another example, current can no longer flow through diode 210 or 212 and through terminal 240 and transistor 420 to charge capacitor 260. In yet another example, a small current flows through the diode 210 or 212 and through the terminal 240 and the resistor 440, wherein the resistor 440 has a large resistance. In yet another example, the input voltage to terminal 236 is provided by auxiliary winding 276 during each switching cycle.

According to yet another embodiment, if terminals 222 and 224 are disconnected from the AC input, the input voltage at terminal 242 drops below a first predetermined threshold. For example, when the output signal 432 of the UVLO element 430 is at a logic high level, in response, the output signal 412 of the sense element 410 becomes a logic high level and the controller 230 is in a mode that discharges the capacitor 220. In one embodiment, in the mode in which capacitor 220 is discharged, drive signal 456 generated by gate driver 454 remains at a logic low level. In another embodiment, transistor 424 is opened to discharge capacitor 220 via diode 210 or 212 and terminal 240, transistor 424, and terminal 232.

According to yet another embodiment, if terminals 222 and 224 remain disconnected from the AC input and the input voltage at terminal 242 remains below a first predetermined threshold, then output signal 432 of UVLO element 430 becomes a logic low level. In response, for example, the output signal 412 of the sensing element 410 becomes a logic low level and the transistor 424 is turned off.

As discussed above and further emphasized herein, FIG. 4 is merely an example and should not unduly limit the scope of the claimed scope. Those skilled in the art will recognize many variations, substitutions and modifications. For example, resistor 440 is replaced by a JFET. In one embodiment, the base of the JFET is biased to ground, the drain of the JFET is directly connected to terminal 240, and the source of the JFET is directly connected to the gate of transistor 420.

FIG. 5 is a simplified schematic diagram illustrating a switch mode controller 230 in a switched mode power converter system 200 in accordance with another embodiment of the present invention. This schematic is merely an example and should not unduly limit the scope of the claimed patent. Those skilled in the art will recognize many variations, substitutions and modifications.

As shown in FIG. 5, the switch mode controller 230 includes a detection element 510, transistors 520, 522, and 524, an undervoltage lockout (UVLO) element 530, a resistor 540, a PWM signal generator 550, a logic control element 552, and a gate driver. 554.

For example, detection element 510 is configured to receive an input voltage from terminal 242 and an output signal 532 of UVLO element 530 and generate an output signal 512. In another example, if the input voltage at terminal 242 is equal to or higher than a first predetermined threshold, then output signal 512 of detection element 510 is at a logic low level. In yet another example, if the input voltage at terminal 242 falls below a first predetermined threshold, then if output signal 532 of UVLO element 530 is also at a logic high level, output signal 512 of detection element 510 is a logic high. Bit.

According to an embodiment, if terminals 222 and 224 are connected to the AC input during startup of switch mode power converter system 200, the input voltage at terminal 242 is equal to or higher than a first predetermined threshold. For example, if the input voltage received by terminal 236 is below a second predetermined threshold, then output signal 532 of UVLO element 530 is at a logic low level and controller 230 is in a UVLO protection mode. In another example, the output signal 512 of the sensing element 510 is at a logic low level and the transistor 524 is off. In yet another example, the transistor 522 is turned off and the transistor 520 is turned on. In yet another example, current flows through diode 210 or 212 and through terminal 240 and transistor 520 and charges capacitor 260, thereby raising the input voltage at terminal 236.

According to another embodiment, if the input voltage at terminal 242 remains equal to or above a first predetermined threshold and the input voltage at terminal 236 reaches or rises above a second predetermined threshold, signal 532 becomes a logic high. Bits, and controller 230 is in an operational mode. For example, the output signal 512 of the sensing element 510 remains at a logic low level and the transistor 524 remains off. In another example, transistor 522 is open and transistor 520 is off. In yet another example, current can no longer flow through diode 210 or 212 and through terminal 240 and transistor 520 to charge capacitor 260. In yet another example, a small current flows through the diode 210 or 212 and through the terminal 240 and the resistor 540, wherein the resistor 540 has a large resistance. In yet another example, the input voltage to terminal 236 is provided by auxiliary winding 276 during each switching cycle.

According to yet another embodiment, if terminals 222 and 224 are disconnected from the AC input, the input voltage at terminal 242 drops below a first predetermined threshold. For example, when the output signal 532 of the UVLO element 530 is at a logic high level, in response, the output signal 512 of the detection element 510 becomes a logic high level and the controller 230 is in a mode that discharges the capacitor 220. In one embodiment, in the mode in which capacitor 220 is discharged, drive signal 556 generated by gate driver 554 remains at a logic low level. In another embodiment, transistor 524 is turned on to discharge capacitor 260 and the input voltage at terminal 236 drops below a second predetermined threshold. For example, in response, the output signal 532 of the UVLO element 530 becomes a logic low level and the controller 230 changes to the UVLO protection mode. In another example, transistor 522 is off and transistors 520 and 524 are open. In yet another example, current flows through diode 210 or 212 and through terminal 240, transistor 520, and transistor 524 to discharge capacitor 220.

According to yet another embodiment, if terminals 222 and 224 remain disconnected from the AC input and the input voltage at terminal 242 remains below a first predetermined threshold, output signal 532 of UVLO element 530 becomes a logic low level. In response, for example, the output signal 512 of the sensing element 510 becomes a logic low level and the transistor 524 is turned off. Current flows through diode 210 or 212 and through terminal 240, transistor 520, terminal 236, and capacitor 260 to discharge capacitor 220.

As discussed above and further emphasized herein, FIG. 5 is merely an example and should not unduly limit the scope of the claimed scope. Those skilled in the art will recognize many variations, substitutions and modifications. For example, resistor 540 is replaced by a JFET. In one embodiment, the base of the JFET is biased to ground, the drain of the JFET is directly connected to terminal 240, and the source of the JFET is directly connected to the gate of transistor 520.

FIG. 6 is a simplified schematic diagram illustrating a switched mode power converter system 200 in accordance with another embodiment of the present invention. This schematic is merely an example and should not unduly limit the scope of the claimed patent. Those skilled in the art will recognize many variations, substitutions and modifications.

In contrast to FIG. 2, power converter system 200 as shown in FIG. 6 includes three additional components 610, 612, and 630. For example, component 610 is coupled between terminal 222 and diode 210. In another example, element 612 is coupled between terminal 224 and diode 212. In yet another example, element 630 is coupled between node 632 and terminal 240. According to some embodiments, each of elements 610, 612, and 630 includes a resistor and/or an inductor. According to some embodiments, elements 610, 612, and 630 are used to protect diode 210, diode 212, and terminal 240, respectively.

According to another embodiment, for example, as shown in Figures 2, 4, 5, and/or 6, a power conversion system (e.g., 200) is depicted. The system (eg, 200) includes a first capacitor (eg, 220) including a first capacitor terminal and a second capacitor terminal, a second capacitor (eg, 260) including a third capacitor terminal and a fourth capacitor terminal, and including the first A plurality of diodes of a diode (e.g., 252), a second diode (e.g., 254), a third diode (e.g., 256), and a fourth diode (e.g., 258). A first diode (e.g., 252) is coupled to a second diode (e.g., 254) at a first node, and a second diode (e.g., 254) is coupled to a fourth diode (e.g., 258) at a second node. a fourth diode (eg, 258) coupled to the third diode (eg, 256) at the third node, and the third diode coupled to the first diode (eg, 252) at the fourth node . Additionally, the system (eg, 200) includes a fifth diode (eg, 210) including a first anode and a first cathode, and a sixth diode (eg, 212) including a second anode and a second cathode. The first anode is connected to a first input terminal (eg 222), the second anode is connected to a second input terminal (eg 224), and the first cathode and the second cathode are connected to a fifth node. Additionally, the system (eg, 200) includes a system controller (eg, 230) including a first controller terminal (eg, 240), a second controller terminal (eg, 242), a third controller terminal (eg, 232) ) a fourth controller terminal (eg, 236) and a fifth controller terminal (eg, 238). Additionally, the system (eg, 200) includes a primary winding (eg, 272) including a first winding terminal and a second winding terminal, a secondary winding (eg, 274) coupled to the primary winding (eg, 272), and a secondary winding coupled to the secondary winding Auxiliary winding (eg 276) (eg 274). Additionally, the system (eg, 200) includes a switch (eg, 280) including a first switch terminal and a second switch terminal. The first node is connected to the first input terminal, the second node is connected to the first winding terminal, the third node is connected to the second input terminal, the fourth node is biased to a predetermined voltage, and the fifth node is connected to the first controller Terminal (eg 240). A second controller terminal (eg, 242) is coupled to the second input terminal, a third controller terminal (eg, 232) is biased to a predetermined voltage, and a fourth controller terminal (eg, 236) is coupled to the third capacitor terminal. The fourth capacitor terminal is biased to a predetermined voltage, the first capacitor terminal is connected to the first input terminal, and the second capacitor terminal is connected to the second input terminal. The first switch terminal is connected to a fifth controller terminal (eg 238) and the second switch terminal is connected to a second winding terminal. The first input terminal and the second input terminal are configured to receive an input voltage, and the secondary winding is configured to generate an output voltage based at least on information associated with the input voltage.

For example, the first anode is indirectly connected to the first input terminal (eg, 222) via a first component (eg, 610) and the second anode is indirectly coupled to a second input terminal (eg, 224) via a second component (eg, 612) . In another example, the first component (eg, 610) includes at least one selected from the group consisting of a resistor and an inductor. In yet another example, the second component (eg, 612) includes at least one selected from the group consisting of a resistor and an inductor. In yet another example, the fifth node (eg, 632) is indirectly connected to the first controller terminal (eg, 240) via an element (eg, 630), the element (630) being included from a group of resistors and inductors At least one of the selected ones.

In yet another example, the system controller (eg, 230) includes a sensing element (eg, 410 or 510), a transistor (eg, 424 or 524), and an undervoltage lockout element (eg, 430 or 530), the detection element (eg, 410 or 510) ) coupled to a second controller terminal (eg, 242), an undervoltage lockout component (eg, 430 or 530), and a transistor (eg, 424 or 524). In yet another example, the detecting element (eg, 410 or 510) is configured to receive a first input voltage from the second input terminal (eg, 224) via the second controller terminal (eg, 242), receiving from the undervoltage lockout element ( A first signal, such as 430 or 530), generates a second signal based on at least information associated with the first input voltage and the first signal, and transmits the second signal to the first transistor (eg, 424 or 524). In yet another example, if the first input voltage is smaller in magnitude than the first threshold voltage and the first signal is at a logic high level, the second signal is at a logic high level. In yet another example, a transistor (eg, 424 or 524) includes a first transistor terminal, a second transistor terminal, and a third transistor terminal. The first transistor terminal is configured to receive a second signal from a sensing element (eg, 410 or 510) and the second transistor terminal is coupled to a third controller terminal (eg, 232). In yet another example, the third transistor terminal is coupled to the first controller terminal (eg, 240). In yet another example, the third terminal is coupled to a fourth controller terminal (eg, 236). In yet another example, the first transistor terminal is a gate terminal, the second transistor terminal is a source terminal, and the third transistor terminal is a gate terminal. In yet another example, the undervoltage lockout element (eg, 430 or 530) is configured to receive a second input voltage from the third capacitor terminal via the fourth controller terminal (eg, 236) and based at least on the second input voltage Linked information to generate the first signal. In yet another example, if the second input voltage is greater in magnitude than the second threshold voltage, the second signal is at a logic high level.

According to yet another embodiment, for example, as shown in Figures 2, 4, 5, and/or 6, a system for discharging a capacitor of a power conversion system (e.g., 200) is described. The system includes a first capacitor (eg, 220) including a first capacitor terminal and a second capacitor terminal. The first capacitor terminal is connected to the first input terminal (eg 222) and the second capacitor terminal is connected to the second input terminal (eg 224). Additionally, the system includes a second capacitor (eg, 260) including a third capacitor terminal and a fourth capacitor terminal, the fourth capacitor terminal being biased to a predetermined voltage. Additionally, the system includes a first diode (e.g., 210) including a first anode and a first cathode, and a second diode (e.g., 212) including a second anode and a second cathode. The first anode is connected to the first input terminal (eg 222) and the second anode is connected to the second input terminal (eg 224). Additionally, the system includes a system controller (e.g., 230) including a first controller terminal (e.g., 240), a second controller terminal (e.g., 242), a third controller terminal (e.g., 232), and a fourth Controller terminal (for example, 236). A first controller terminal (eg, 240) is coupled to the first cathode and a second cathode, a second controller terminal (eg, 242) is coupled to the second input terminal, and a third controller terminal (eg, 232) is biased to a predetermined voltage A fourth controller terminal (eg, 236) is coupled to the third capacitor terminal. The system controller (e.g., 230) also includes a sensing element (e.g., 410 or 510), a transistor (e.g., 424 or 524), and an undervoltage locking element (e.g., 430 or 530). A sensing element (eg, 410 or 510) is configured to receive a first input voltage from a second input terminal (eg, 224) via a second controller terminal (eg, 242), receiving an undervoltage lockout component (eg, 430 or 530) The first signal, based on at least information associated with the first input voltage and the first signal, generates a second signal and transmits the second signal to the first transistor (eg, 424 or 524). If the first input voltage is lower in magnitude than the first threshold voltage and the first signal is at a logic high level, then the second signal is at a logic high level. The transistor (e.g., 424 or 524) includes a first transistor terminal, a second transistor terminal, and a third transistor terminal. The first transistor terminal is configured to receive a second signal from a sensing element (eg, 410 or 510) and the second transistor terminal is coupled to a third controller terminal (eg, 232). An undervoltage lockout element (eg, 430 or 530) is configured to receive a second input voltage from a third capacitor terminal via a fourth controller terminal (eg, 236) and to generate a first based on at least information associated with the second input voltage signal. If the second input voltage is greater in magnitude than the second threshold voltage, the second signal is at a logic high level.

For example, the third transistor terminal is connected to a first controller terminal (eg, 240). In another example, the third transistor terminal is coupled to a fourth controller terminal (eg, 236). In yet another example, the first transistor terminal is a gate terminal, the second transistor terminal is a source terminal, and the third transistor terminal is a gate terminal. In yet another example, the first anode is indirectly coupled to the first input terminal (eg, 222) via a first component (eg, 610), and the second anode is indirectly coupled to the second input terminal via a second component (eg, 612) (eg 224). In yet another example, the first component (eg, 610) includes at least one selected from the group consisting of a resistor and an inductor. In yet another example, the second component (eg, 612) includes at least one selected from the group consisting of a resistor and an inductor. In yet another example, the first controller terminal (eg, 240) is indirectly coupled to the first cathode and the second cathode via an element (eg, 630), and the element (eg, 630) includes from the group consisting of a resistor and an inductor At least one of the selected ones in the group. In yet another example, the predetermined voltage is a ground voltage.

According to yet another embodiment, for example, as shown in Figures 2, 4, 5, and/or 6, a system (e.g., 230) for discharging a capacitor of a power conversion system (e.g., 200) is depicted. The system (e.g., 230) includes a first controller terminal (e.g., 240). The first controller terminal (eg, 240) is configured to receive a discharge current from the first diode or the second diode. The first diode and the second diode are coupled to the first capacitor, and the first capacitor is configured to be charged by the first input terminal and the second input terminal. Additionally, the system (eg, 230) includes a second controller terminal (eg, 242) configured to receive a first input voltage from a second input terminal (eg, 224); a third controller terminal (eg, 232), Biased to a predetermined voltage; and a fourth controller terminal (eg, 236) configured to receive a second input voltage from a second capacitor (eg, 260). Additionally, the system (e.g., 230) includes a sensing element (e.g., 410 or 510). The detecting element (eg, 410 or 510) is configured to receive a first input voltage from a second input terminal (eg, 224) via a second controller terminal (eg, 242), receiving from an undervoltage lockout component (eg, 430 or 530) The first signal, based on at least information associated with the first input voltage and the first signal, generates a second signal and transmits the second signal to a transistor (eg, 424 or 524). If the first input voltage is lower in magnitude than the first threshold voltage and the first signal is at a logic high level, then the second signal is at a logic high level. Additionally, the system (eg, 230) includes a transistor (eg, 424) including a first transistor terminal, a second transistor terminal, and a third transistor terminal. The first transistor terminal is configured to receive a second signal from a sensing element (eg, 410 or 510) and the second transistor terminal is coupled to a third controller terminal (eg, 232). Additionally, the system (e.g., 230) includes an under-pressure locking element (e.g., 430 or 530). The undervoltage lockout element (eg, 430 or 530) is configured to receive a second input voltage from a second capacitor (eg, 260) via a fourth controller terminal (eg, 236) and based at least on a second input voltage The information produces the first signal. If the second input voltage is greater in magnitude than the second threshold voltage, the second signal is at a logic high level.

For example, the third transistor terminal is connected to a first controller terminal (eg, 240). In another example, the third transistor terminal is coupled to a fourth controller terminal (eg, 236). In yet another example, the first transistor terminal is a gate terminal, the second transistor terminal is a source terminal, and the third transistor terminal is a gate terminal. In yet another example, the first diode (eg, 210) is coupled to the first input terminal (eg, 222) and the second diode (eg, 212) is coupled to the second input terminal (eg, 224). In yet another example, the first diode is indirectly coupled to the first input terminal (eg, 222) via a first component (eg, 610), and the second diode is indirectly coupled to the second component (eg, 612) via a second component (eg, 612) A second input terminal (eg, 224). In yet another example, the first controller terminal (eg, 240) is configured to receive a discharge current from the first diode or the second diode via an element (eg, 630), the element (eg, 630) including the resistor At least one selected from the group consisting of: an inductor and an inductor. In yet another example, the predetermined voltage is a ground voltage.

Although specific embodiments of the invention have been described, it will be understood by those skilled in the art Therefore, it is understood that the invention is not limited to the specific embodiments described, but only by the scope of the claims.

100. . . Power converter system

110. . . X resistor

120. . . X capacitor

122, 124. . . Input terminal

130. . . Switch mode controller

132. . . Terminal (GND pin)

134. . . Terminal (FB pin)

136. . . Terminal (VCC pin)

138. . . Terminal (GATE pin)

139. . . Terminal (CS pin)

152, 154, 156, 158. . . Dipole

160. . . Capacitor

172. . . Primary winding

174. . . Secondary winding

176. . . Auxiliary winding

180. . . switch

200. . . Switch mode power converter system

210, 212. . . Dipole

220. . . X capacitor

222, 224. . . Input terminal

230. . . Switch mode controller

232, 234, 236, 238, 239, 240, 242. . . Terminal

252, 254, 256, 258. . . Dipole

260. . . Capacitor

272. . . Primary winding

274. . . Secondary winding

276. . . Auxiliary winding

280. . . switch

410. . . Detection element

412. . . output signal

420, 422, 424. . . Transistor

430. . . Under-voltage-lockout (UVLO) component

432. . . output signal

440. . . Resistor

450. . . PWM signal generator

452. . . Logic control element

454. . . Gate driver

456. . . Drive signal

510. . . Detection element

512. . . output signal

520, 522, 524. . . Transistor

530. . . Undervoltage lockout (UVLO) component

532. . . output signal

540. . . Resistor

550. . . PWM signal generator

552. . . Logic control element

554. . . Gate driver

556. . . Drive signal

610, 612, 630. . . element

632. . . node

1 is a simplified conventional schematic diagram illustrating a switched mode power converter system having an X resistor and an X capacitor.

2 is a simplified schematic diagram illustrating a switched mode power converter system in accordance with an embodiment of the present invention.

3(A) and (B) are simplified schematic diagrams illustrating discharge of an X capacitor in a switched mode power converter system in accordance with some embodiments of the present invention.

4 is a simplified schematic diagram illustrating a switch mode controller in a switched mode power converter system in accordance with an embodiment of the present invention.

5 is a simplified schematic diagram illustrating a switch mode controller in a switched mode power converter system in accordance with another embodiment of the present invention.

6 is a simplified schematic diagram illustrating a switched mode power converter system in accordance with another embodiment of the present invention.

200. . . Switch mode power converter system

210, 212. . . Dipole

220. . . X capacitor

222, 224. . . Input terminal

230. . . Switch mode controller

232, 234, 236, 238, 239, 240, 242. . . Terminal

252, 254, 256, 258. . . Dipole

260. . . Capacitor

272. . . Primary winding

274. . . Secondary winding

276. . . Auxiliary winding

280. . . switch

Claims (24)

A power conversion system includes: a first capacitor including a first capacitor terminal and a second capacitor terminal; a second capacitor including a third capacitor terminal and a fourth capacitor terminal; and a plurality of diodes including the first diode a second diode, a third diode, and a fourth diode, the first diode being coupled to the second diode at a first node, the second diode being at a second node Coupled to the fourth diode, the fourth diode is coupled to the third diode at a third node, the third diode being coupled to the first diode at a fourth node; a fifth diode comprising a first anode and a first cathode, the first anode being indirectly connected to the first input terminal via the first element; the sixth diode comprising a second anode and a second cathode, the second The anode is indirectly connected to the second input terminal via a second component, the first cathode and the second cathode being connected to the fifth node; a system controller comprising a first controller terminal, a second controller terminal, a third control Terminal, fourth controller terminal, and fifth control a primary winding comprising a first winding terminal and a second winding terminal; a primary winding coupled to the primary winding; an auxiliary winding coupled to the secondary winding; and a switch including a first switching terminal and a second a switch terminal; wherein: the first node is connected to the first input terminal; the second node is connected to the first winding terminal; the third node is connected to the second input terminal; the fourth node is biased to a a predetermined voltage; the fifth node is indirectly connected to the first controller terminal via an inductor; the second controller terminal is coupled to the second input terminal; the third controller terminal is biased to the predetermined voltage; The fourth controller terminal is connected to the third capacitor terminal; the fourth capacitor terminal is biased to the predetermined voltage; the first capacitor terminal is connected to the first input terminal; the second capacitor terminal is connected to the second An input terminal; the first switch terminal is connected to the fifth controller terminal; and the second switch terminal is connected to the second winding terminal; wherein: the first input terminal and the second input terminal are configured to receive an input a voltage; the secondary winding is configured to generate an output voltage based on at least information associated with the input voltage; and the first component and the second component are each an inductor. The system of claim 1, wherein the system controller includes a detecting component, a transistor, and an undervoltage lockout component coupled to the second controller terminal, the undervoltage A locking element, and the transistor. The system of claim 2, wherein the detecting component is configured to receive a first input voltage from the second input terminal via the second controller terminal, to receive a first from the undervoltage lockout component The signal, based on at least information associated with the first input voltage and the first signal, generates a second signal and transmits the second signal to the transistor. The system of claim 3, wherein the second signal is a logic high level if the first input voltage is lower in magnitude than the first threshold voltage and the first signal is at a logic high level . The system of claim 2, wherein the transistor comprises a first transistor terminal, a second transistor terminal, and a third transistor terminal, the first transistor terminal being configured to receive from the detection The second signal of the component, the second transistor terminal is coupled to the third controller terminal. The system of claim 5, wherein the third transistor terminal is connected to the first controller terminal. The system of claim 5, wherein the third transistor terminal is coupled to the fourth controller terminal. The system of claim 5, wherein the first transistor terminal is a gate terminal, the second transistor terminal is a source terminal, and the third transistor terminal is a terminal terminal . The system of claim 6, wherein the undervoltage lockout element is configured to receive a second input voltage from the third capacitor terminal via the fourth controller terminal, and based at least on the second input The voltage associated information produces the first signal. The system of claim 9, wherein the second signal is at a logic high level if the second input voltage is greater in magnitude than the second threshold voltage. A system for discharging a capacitor of a power conversion system, the system comprising: a first capacitor comprising a first capacitor terminal and a second capacitor terminal, the first capacitor terminal being connected to a first input terminal, the second capacitor terminal being connected a second input terminal; the second capacitor includes a third capacitor terminal and a fourth capacitor terminal, the fourth capacitor terminal being biased to a predetermined voltage; the first diode comprising a first anode and a first cathode, a first anode is indirectly connected to the first input terminal via a first component; a second diode comprising a second anode and a second cathode, the second anode being indirectly connected to the second input via a second component a first component and the second component are respectively an inductor; and a system controller including a first controller terminal, a second controller terminal, a third controller terminal, and a fourth controller terminal, a first controller terminal is connected to the first cathode and the second cathode, the second controller terminal is connected to the second input terminal, and the third controller terminal is biased To the predetermined voltage, the fourth control terminal is connected to the third capacitor terminal; wherein: the system further comprises a controller detecting element, a transistor, and an undervoltage lockout An element configured to receive a first input voltage from the second input terminal via the second controller terminal, receive a first signal from the undervoltage lockout element, based at least on the first input voltage and the Information associated with the first signal to generate a second signal, and transmitting the second signal to the transistor if the first input voltage is lower in magnitude than the first threshold voltage and the first signal is at a logic high level And the second signal is a logic high level; the transistor includes a first transistor terminal, a second transistor terminal, and a third transistor terminal, the first transistor terminal configured to receive from the detecting component a second signal, the second transistor terminal is coupled to the third controller terminal; and the undervoltage lockout component is configured to receive a second input voltage from the third capacitor terminal via the fourth controller terminal, and Generating the first signal based on at least information associated with the second input voltage, and if the second input voltage is greater in magnitude than the second threshold voltage, the second signal is Edit a high level. The system of claim 11, wherein the third transistor terminal is coupled to the first controller terminal. The system of claim 11, wherein the third transistor terminal is connected to the fourth controller terminal. The system of claim 11, wherein the first transistor terminal is a gate terminal, the second transistor terminal is a source terminal, and the third transistor terminal is a terminal terminal . The system of claim 11, wherein the first controller terminal is indirectly connected to the first cathode and the second cathode via an element, the element comprising: consisting of a resistor and an inductor At least one of the selected groups. The system of claim 11, wherein the predetermined voltage is a ground voltage. A system for discharging a capacitor of a power conversion system, comprising: a first controller terminal configured to receive a discharge current from a first diode or a second diode, the first a diode and the second diode are coupled to a first capacitor configured to be charged by the first input terminal and the second input terminal; a second controller terminal configured to receive a first input voltage from the second input terminal; a third controller terminal And being biased to a predetermined voltage; a fourth controller terminal configured to receive a second input voltage from the second capacitor; a detecting component configured to receive from the second controller terminal The first input voltage of the two input terminals receives a first signal from an undervoltage lockout component, generates a second signal based on at least information associated with the first input voltage and the first signal, and the second signal Transmitting a signal to a transistor, if the first input voltage is lower in magnitude than the first threshold voltage and the first signal is at a logic high level, the second signal is a logic high level; the transistor includes a transistor terminal, a second transistor terminal, and a third transistor terminal, the first transistor terminal being configured to receive the second signal from the detecting component, the second transistor a body terminal connected to the third controller terminal; and the undervoltage lockout element configured to receive the second input voltage from the second capacitor via the fourth controller terminal, and based at least on the second input voltage The associated information generates the first signal, and if the second input voltage is greater in magnitude than the second threshold voltage, the second signal is at a logic high level. The system of claim 17, wherein the third transistor terminal is coupled to the first controller terminal. The system of claim 17 wherein the third transistor terminal is coupled to the fourth controller terminal. The system of claim 17, wherein the first transistor terminal is a gate terminal, the second transistor terminal is a source terminal, and the third transistor terminal is a terminal terminal . The system of claim 17, wherein: the first diode is connected to the first input terminal; The second diode is connected to the second input terminal. The system of claim 21, wherein: the first diode is indirectly connected to the first input terminal via a first component; and the second diode is indirectly connected to the second diode via the second component Second input terminal. The system of claim 17, wherein the first controller terminal is configured to receive the discharge current from the first diode or the second diode via a component, the component comprising At least one selected from the group consisting of a resistor and an inductor. The system of claim 17, wherein the predetermined voltage is a ground voltage.