TWI671760B - Memory circuit and method for operating three-dimentional cross point memory array - Google Patents

Abstract

An integrated circuit includes a three-dimensional cross-point memory array, and the three-dimensional cross-point memory array has M layers of memory cells arranged at the intersections of N first access line layers and P second access line layers . The integrated circuit also includes first and second sets of first access line drivers. A first set of first access line drivers are operatively coupled to apply a total first operating voltage to a selected first access line in an odd number of first access line layers. A second set of first access line drivers are operatively coupled to apply a common first operating voltage to a selected first access line in an even number of first access line layers. Multiple sets of second access line drivers are operatively configured to apply a second operating voltage to a selected second access line in a selected second access line layer.

Description

Memory circuit and method for operating three-dimensional intersection memory array

The present invention relates generally to integrated circuits. More specifically, the present invention relates to a decoding operation in a cross-point memory device and a cross-point memory device.

In a three-dimensional (3D) cross-point memory array, multiple memory cells are stacked vertically on top of each other to increase the amount of storage in an area available for storing data. The memory cells are disposed at intersections of the first access lines (for example, bit lines or word lines) and the second access lines (for example, word lines or bit lines) that are staggered. Examples of memory cells included in a 3D cross-point memory array include magnetoresistive random access memory (MRAM), resistive random access memory (RRAM), ferroelectric random access memory (FRAM), Nitride-oxide semiconductor memory, polymer memory, and phase change memory.

Various circuits (sometimes called peripheral circuits) can be used to read data from and write data to memory cells in a 3D cross-point memory array. Examples include sense amplifiers, decoders, pass gates, drivers, buffers, Registers, etc. The decoder is connected to a driver for the access line, and an operating voltage is applied to the selected memory cell by the driver for reading and writing operations. The area occupied by the decoder depends on the number of first access lines and second access lines in the 3D crosspoint memory array. Stacking more memory arrays or adding more layers of memory cells to a 3D crosspoint memory array will result in a larger decoder. Larger decoders can be complex and require more areas.

It is expected to provide a smaller and less complex decoder for a 3D crosspoint memory array.

This disclosure describes an integrated circuit including a 3D cross-point memory array having memory cells of M or more layers, the memory cells being disposed at the intersections of the first and second access lines, wherein Decoding circuits may be shared between the layers.

The features of the 3D crosspoint memory array include M layers, N first access line layers, and P second access line layers interlaced with the N first access line layers, and have memory cells disposed therebetween. . Each of the first access line layers (n) from n to 1 includes a plurality of first access lines for a memory cell of a corresponding row. Each second access line layer (p) from p to 1 includes a plurality of second access lines for the memory cells of the corresponding column.

In the embodiment described herein, the decoder and driver circuits are configured to apply an operating voltage to the first access lines in the memory cells of the selected and unselected rows and to apply the operating voltage to the selected and unselected The second access line in the memory cell of the column.

As described above, for any read operation of the memory cells in the array, by applying a common operating voltage to the selected first access line and applying a set of first access line layers with more than one component Applying a common operating voltage to the unselected first access line can reduce the decoding load for accessing the memory cells in the array. Therefore, the decoding load is reduced.

Here, applying a common operating voltage to multiple access lines (i.e., a group of components with more than one component) means that multiple access lines are received in a read operation on any memory cell in the array The same operating voltage, so no independent decoding is required for this read.

Therefore, in order to select a specific memory cell arranged in the M layer in the intersection of the specific first access line and the specific second access line, when the specific first access line layer is a component of the first access line group The decoder and driver circuits are configured to select a row of memory cells to identify the selected and unselected first access lines, a row of memory cells to identify the selected and unselected second access lines, select The set of first access line layers is used to identify a selected first access line layer and a non-selected first access line layer including a specific first access line layer, and one or A plurality of selected second access line layers, and an unselected second access line layer. In the described embodiment, the set of first access line layers includes an odd number of first access line layers (n), where n is an odd number. Furthermore, the decoder and driver circuits may be configured to apply a common operating voltage to a second set of first access line layers, which includes an even number of first access line layers (n), where n is an even number.

In some embodiments, the decoder and driver circuits are configured to convert the common An operating voltage is applied to a selected second access line in a set of second access line layers having more than one member. Therefore, the decoding load for selecting the second access line layer and for selecting the first access line layer is reduced. In one example, this set of second access line layers includes a top second access line layer and a bottom second access line layer, which includes a layer (p), where p is 1 and is M for an M-layer array / 2 + 1.

In some embodiments, the memory cell may include a unidirectional element. In these embodiments, even greater sharing of decoding load between access line layers can be obtained. For example, the decoder in the decoder and driver circuits may be configured to apply a combined operating voltage to a second access line in a plurality of sets of second access line layers, where for the M-layer array this plurality of sets Includes M / 4 groups of every two second access line layers.

The disclosure also discloses a method for operating a 3D crosspoint memory array in the above manner.

Other aspects and advantages of the technology can be seen by reviewing the drawings, detailed description, and scope of patent applications.

In order to make the above features and advantages of the present invention more comprehensible, embodiments are hereinafter described in detail with reference to the accompanying drawings.

100‧‧‧3D Crosspoint Memory Array

101, 102, 103, 104, 105, 106, 107, 108, 109‧‧‧ Second access line

111, 112, 113, 114, 115, 116‧‧‧ First access line

121, 122, 123, 124‧‧‧ Two-way memory cells

161‧‧‧stack

171, 172‧‧‧‧ Shared decoder / driver

151‧‧‧The first element

152‧‧‧Second Element

153‧‧‧Memory element

202, 203, 204, 204a, 204b, 204c, 206‧‧‧ drives

208‧‧‧Drive Selector

301, 302, 303, 304, 305‧‧‧ Second access line

311, 312, 313, 314‧‧‧ first access line

321, 322, 323, 324, 325, 326, 327, 328‧‧‧ two-way memory cells

351‧‧‧shared decoder

352, 353, 361, 362, 363, 364, 365‧‧‧ drives

371‧‧‧stack

401, 402, 403, 404, 405, 406‧‧‧ steps

501, 502, 503, 504, 505, 506, 507, 508, 509‧‧‧ first access line

511, 512, 513, 514, 515, 516‧‧‧ second access line

521, 522, 523, 524‧‧‧ one-way memory cells

561‧‧‧stack

571, 572‧‧‧ shared decoder

551‧‧‧First component

552‧‧‧Second Element

553‧‧‧Memory element

554‧‧‧Intermediate element

555‧‧‧Direction element

602, 603, 605‧‧‧ drives

701, 702, 703, 704, 705‧‧‧ first access line

711,712,713,714‧‧‧Second Access Line

721, 722, 723, 724, 725, 726, 727, 728‧‧‧ one-way memory cells

751‧‧‧shared decoder

752, 753‧‧‧Drive

761‧‧‧shared decoder

762, 763‧‧‧Drive

771‧‧‧ stacked

800‧‧‧3D Crosspoint Memory Array

801‧‧‧shared layer decoder

802‧‧‧Shared decoder for the second access line layer

803‧‧‧shared decoder for the first access line layer

805‧‧‧Bus

806‧‧‧block

807‧‧‧Bus

808‧‧‧Control circuit

821‧‧‧Data input line

822‧‧‧Data output line

850‧‧‧Integrated Circuit

L1‧‧‧First floor

L2‧‧‧The second floor

L3‧‧‧ Third floor

L4‧‧‧Fourth floor

L5‧‧‧Fifth floor

L6‧‧‧ Sixth floor

L7‧‧‧Seventh floor

L8‧‧‧eighth floor

FIG. 1A and FIG. 1B respectively show a 3D cross-point memory array and a bidirectional memory cell with a bidirectional memory cell.

FIG. 2A is a 3D cross-point memory array in a bidirectional memory cell with four layers The first and second access line decoders in the column are shared to show the arrangement of the first and second access lines in a single stacked memory cell.

FIG. 2B illustrates exemplary voltages applied to read operations on the first and second access lines in a 3D cross-point memory array with four layers of bidirectional memory cells.

FIG. 2C illustrates a first embodiment of a shared decoder and driver circuit.

FIG. 2D illustrates a second embodiment of a shared decoder and driver circuit.

FIG. 3A illustrates an arrangement of first and second access lines and a shared first and second access line decoder in a 3D crosspoint memory array having eight layers of bidirectional memory cells.

FIG. 3B illustrates exemplary voltages applied to read operations on first and second access lines in a single stacked memory cell in a 3D cross-point memory array with eight layers of bidirectional memory cells.

FIG. 4 is a flowchart illustrating a method for reading data in a memory cell of a 3D cross-point memory array having a bidirectional memory cell.

5A and 5B illustrate a 3D crosspoint memory array and a unidirectional memory cell with unidirectional memory cells, respectively.

FIG. 6A illustrates an arrangement of first and second access lines and a shared first and second access line decoder in a 3D crosspoint memory array having four layers of unidirectional memory cells.

FIG. 6B illustrates exemplary voltages applied to read operations on the first and second access lines in a 3D crosspoint memory array having four layers of unidirectional memory cells.

FIG. 7A illustrates a 3D cross-point memory array with eight layers of unidirectional memory cells Arrangement of first and second access lines and a shared first and second access line decoder.

FIG. 7B illustrates exemplary voltages applied to read operations on the first and second access lines in a 3D crosspoint memory array having eight layers of bidirectional memory cells.

FIG. 8 is a schematic block diagram of an integrated circuit according to an embodiment of the present invention.

A detailed description of embodiments of the present technology is provided below with reference to FIGS. 1 to 8.

FIG. 1A illustrates a 3D crosspoint memory array 100 having a bidirectional memory cell. The 3D crosspoint memory array 100 includes a plurality of bidirectional memory cells, including bidirectional memory cells 121, 122, 123, 124. The bidirectional memory cells are provided in a plurality of first access lines 111, 112, 113, 114, 115, and 116 arranged in a column direction and a plurality of second access lines 101, 102, 103, 104, 105 arranged in a row direction. , 106, 107, 108, and 109. The column and row directions are orthogonal or non-parallel, so that an intersection array can be formed. Each bidirectional memory cell is connected to a specific first access line and a specific second access line. For example, the bidirectional memory cell 121 is connected to the first access line 111 and the second access line 101. A "bidirectional" memory cell allows current to flow in both directions between a first access line and a second access line connected to the memory cell. For example, in the bidirectional memory cell 121, current may flow from the first access line 111 (at a more positive voltage) to the second access line 101 (at a more negative voltage), or from the second access line 101 (at a more positive voltage) ) To the first access line 111 (at a relatively negative voltage).

As described in this disclosure, a "stack" of memory cells in a 3D intersection memory array (eg, stack 161) of M layers includes M memory cells directly stacked on top of each other, where M is a positive integer, for example. Stack 161 includes bi-directional memory cells 121, 122, 123, and 124 stacked on top of each other. A specific stack is selected by accessing specific columns and specific rows in multiple memory cell layers.

The 3D cross-point memory array implemented in the configuration of FIG. 1A may have multiple layers, and each layer may have multiple first and second access lines for use in a very high density memory device. form. In a preferred embodiment, the number M of layers of the bidirectional memory cell may be a multiple of 2, for example, M = 2, 4, 8, 16, 32, or 64. Other 3D configurations can also be implemented. A 3D cross-point memory array with M layers of bidirectional memory cells may have N first access line layers, where N is a positive integer, for example, where N = M / 2. Each first access line layer (n) includes a plurality of first access lines, where n is, for example, a positive integer, where n is 1 to M / 2. The 3D crosspoint memory array with M layers further includes P second access line layers interlaced with N first access line layers, where P is a positive integer, for example, where P = M / 2 + 1. Each second access line layer (p) includes a plurality of second access lines, where p is, for example, a positive integer, where 1 to M / 2 + 1 for p.

The 3D crosspoint memory array in FIG. 1A includes M = 4 layers of directional memory cells, N = 2 first access line layers, and P = 3 second access line layers. The first bidirectional memory cell in the 3D cross-point memory array is inserted in the second access line layer (SAL1) including the second access lines 101, 102, and 103 and includes the first access lines 111, 112, and 113 Between the first access line layer (FAL1). The second layer of bidirectional memory cells in the 3D crosspoint memory array is inserted in the first access Between the first access line layer (FAL1) of the lines 111, 112, and 113 and the second access line layer (SAL2) including the second access lines 104, 105, and 106. The third layer in the 3D crosspoint memory array is inserted in the second access line layer (SAL2) including the second access lines 104, 105, and 106 and the first storage line including the first access lines 114, 115, and 116 Take the line layer (FAL2). The fourth layer in the 3D crosspoint memory array is inserted in the first access line layer (FAL2) including the first access lines 114, 115, and 116 and the second storage line including the second access lines 107, 108, and 109. Take the line layer (SAL3).

Referring to FIG. 1A, the 3D cross-point memory array implemented in the M layer in the configuration of FIG. 1A is coupled to a decoder and driver circuit, and the decoder and driver circuit includes shared decoding for the first access line layer Driver / driver and shared decoder / driver line for the second access line layer. The decoder includes a driver selection circuit that responds to an address (not shown in FIG. 1A for clarity), which is operatively coupled to the driver, which applies an operating voltage to an access line identified by the driver selection circuit, where The operation voltage has a value according to an operation being performed. As described in this disclosure, driver groups for access lines in more than one layer of access lines are operatively coupled to the decoder in a shared manner such that they apply a common operating voltage to their corresponding accesses line. This reduces the decoding load of the device, allowing smaller or less complex decoding circuits. A driver set for access lines in more than one layer may include one driver for each access line of each of the multiple layers, which is operatively coupled to the decoder to apply a common operating voltage . In the alternative, a driver set of access lines used in more than one layer may include multiple shared drivers, where each shared driver drives a common operating voltage on access lines in multiple layers, and in multiple layers Each layer in Take the line.

In an example, the shared decoder for the first access line layer is operatively coupled to the first set of first access line drivers and the second set of first access line drivers. A given driver in the first access line driver set may be coupled to one first access line from a particular column of a particular layer of the 3D crosspoint memory array. Further, a given driver in the first access line driver group may be coupled to one first access line of a particular column from each of a plurality of layers of the 3D crosspoint memory array.

The first set of first access line drivers are operatively coupled to a decoder to apply a common operating voltage to a first access line selected in an odd number of first access line layers (n). The second set of first access line drivers are operatively coupled to the decoder to apply a common operating voltage to the first access lines selected in the even number of first access line layers (n). The shared decoder for the second access line layer is operatively coupled to the M / 2 group of second access line drivers, and the second access line driver is configured to apply a common operating voltage to the selected first access line driver. The second access line selected in the two access line layer (p). Each driver in the second access line driver group may be coupled to a second access line of a particular row of the M-layer 3D crosspoint memory array. The first set of second access line drivers from the M / 2 set of second access line drivers are operatively coupled to apply a common operating voltage to the selected first and second access line layers (p). Two access lines, where p is 1 and M / 2 + 1. Each set of second access line drivers (except the first set of second access line drivers) from the M / 2 set of second access line drivers may be operatively coupled to the decoder to apply an operating voltage To the second access line selected in one of the second access line layers (p), where p is not 1 or M / 2 + 1.

Referring to FIG. 1A, a 3D crosspoint array is coupled and electrically connected to a shared decoder / driver 171 for a first access line layer and a shared decoder / driver 172 for a second access line layer. The shared decoder / driver 171 for the first access line layer includes a first set of first access line drivers and a second set of first access line drivers. The shared decoder / driver 172 for the second access line layer may include multiple sets of second access line drivers. The control circuit (not shown in FIG. 1A) is coupled to the shared decoder / driver for the first access line layer 171, the shared decoder / driver for the second access line layer 172, and the integrated circuit Other resources to perform write operations, read operations, and other memory device operations that require operating voltage pulse sequences to be applied to bidirectional memory cells in a 3D crosspoint memory array, where the drive is selected for a particular access line and Specific operating voltages (eg, read voltage, write voltage, reference voltage, etc.) are set by the driver in response to the decoded memory cell address and the specific operation being performed.

The shared decoder / driver for the first access line layer 171 includes first and second sets of first access line drivers. The first set of first access line drivers are operatively coupled to a decoder to apply a common operating voltage to a first access line selected in an odd number of first access line layers (FAL1), including a first An access line 111, 112, and 113. The second set of first access line drivers are operatively coupled to apply a common operating voltage to a first access line selected in an even number of first access line layers (FAL2), which includes a first access line 114 , 115 and 116. Further coupling details between the first access line driver group and the first access line will be described below with reference to FIGS. 2A and 2B.

Shared decoder / driver 172 for the second access line layer includes M / 2 = 2 Set of second access line drivers. The first set of second access line drivers are operatively coupled to the decoder to apply a common operating voltage to the second access line (including the second access line) selected in the second access line layer (SAL1). Lines 101, 102, and 103), and the second access line (including the second access line) selected in the second access line layer (p = M / 2 + 1 = 3) (SAL3) by applying a common operating voltage Lines 107, 108, and 109). The second set of second access line drivers are operatively coupled to apply an operating voltage to a selected second access line (including the second access lines 104, 105) in the second access line layer (SAL2). And 106). Further coupling details between the second access line driver group and the second access line are described below with reference to FIGS. 2A and 2B.

The sense amplifier (not shown in FIG. 1A) may be configured to be connected to the first access line or the second access line. In an embodiment of the technology described in this disclosure, the sense amplifier is coupled to one of the first and second access lines, and a current source circuit (such as a current mirror-based load circuit) is connected to the first and second access lines. Two access lines to limit current during read and write operations.

FIG. 1B is a close-up view of the exemplary bidirectional memory cell 121 in FIG. 1A. The memory cell 121 has a first element 151 in contact with the first access line 111 and a second element 152 in contact with the second access line 101. The memory element 153 is disposed between the first element 151 and the second element 152. The first element 151 connects the memory element 153 to the first access line 111. The second element 152 connects the memory element 153 to the second access line 101.

The first element 151 and the second element 152 may include a conductive material having a thickness of about 5 to 50 nm. Example materials for the first element 151 and the second element 152 may be metal nitrides, such as titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), molybdenum nitride (MoN), niobium nitride (NbN), titanium silicon nitride (TiSiN), titanium aluminum nitride (TiAlN), titanium boron nitride (TiBN), zirconium silicon nitride (ZrSiN), Tungsten silicon nitride (WSiN), tungsten boron nitride (WBN), zirconium aluminum nitride (ZrAlN), molybdenum silicon nitride (MoSiN), molybdenum aluminum nitride (MoAlN), tantalum silicon nitride (TaSiN), nitride Tantalum aluminum (TaAlN). In addition to metal nitride, the first element 151 and the second element 152 may include doped polycrystalline silicon, tungsten (W), copper (Cu), titanium (Ti), molybdenum (Mo), tantalum (Ta), and titanium silicide. (TiSi), tantalum silicide (TaSi), titanium tungsten (TiW), titanium oxynitride (TiON), aluminum oxynitride (TiAlON), tungsten oxynitride (WON), and tantalum oxynitride (TaON). In some embodiments, the first element 151 may have a different material from the second element 152.

The memory element 153 may include a layer of a programmable resistive material. The programmable resistance material may have a first resistance value representing a bit “0” and a second resistance value representing a bit “1”. In some embodiments, more than two resistance values may be used to store multiple bits for each cell.

In one embodiment, the memory element 153 includes a layer of a phase change memory material as a programmable resistive material in series with the switching element. For example, the switching element may be a two-terminal, bidirectional ovonic threshold switch (OTS), which includes a chalcogenide material.

In other embodiments, the switching element may include other types of devices, including directional devices such as diodes and other bidirectional devices.

In embodiments that include OTS, the read operation involves applying a voltage that exceeds the OTS threshold on the first access line and the second access line. Embodiments described in this disclosure Among them, the operation voltage applied to the access line in the read operation includes a first voltage (for example, + 3V), a second voltage (for example, -3V), and an intermediate voltage (for example, 0V). To read memory cells at the intersection of the selected first and second access lines, first and second voltages are applied to the selected first and second access lines to establish a read potential that exceeds the OTS threshold (For example, 6V). The intermediate voltage is applied to an unselected access line. The read potential in the memory cell at the intersection of the unselected access lines is 0V (or the difference between intermediate voltages applied to different access lines). The voltage on the memory cell at the intersection of the unselected access line and the selected access line is the difference between the intermediate voltage and the first voltage (e.g., + 3V) and the intermediate voltage and the second voltage (e.g., , -3V).

Phase change materials are capable of switching between a relatively high resistance state, an amorphous phase, and a relatively low resistance state crystalline phase by applying energy such as heat or current. Phase change materials for the memory element 153 may include chalcogenide-based materials and other materials. A chalcogenide alloy includes a combination of a chalcogenide and other materials such as transition metals. Chalcogenide alloys usually contain one or more elements of Group IVA of the periodic table, such as germanium (Ge) and tin (Sn). Generally, the chalcogenide alloy includes a combination including one or more of antimony (Sb), gallium (Ga), indium (In), and silver (Ag). Many phase change-based memory materials have been described in technical literature, including alloys: Ga / Sb, In / Sb, In / Se, Sb / Te, Ge / Te, Ge / Sb / Te, In / Sb / Te , Ga / Se / Te, Sn / Sb / Te, In / Sb / Ge, Ag / In / Sb / Te, Ge / Sn / Sb / Te, Ge / Sb / Se / Te, and Te / Ge / Sb / S . In the Ge / Sb / Te alloy family, various alloy compositions are possible. This composition may be, for example, Ge ₂ Sb ₂ Te ₅ , GeSb ₂ Te ₄ and GeSb ₄ Te ₇ . More generally, transition metals such as chromium (Cr), iron (Fe), nickel (Ni), niobium (Nb), palladium (Pd), platinum (Pt), and mixtures or alloys thereof can interact with Ge / Sb / Te or Ga / Sb / Te combination forms a phase change alloy with programmable resistance characteristics. Specific examples of memory materials are disclosed in columns 11-13 of U.S. Patent No. 5,687,112 to Ovshinsky, and these embodiments can be incorporated by reference in this disclosure. Various phase change memory devices described in US Pat. No. 6,579,760 entitled “SELF-ALIGNED, PROGRAMMABLE PHASE CHANGE MEMORY” are incorporated herein by reference.

In one example, the OTS switching element may include a chalcogen compound layer, such as As ₂ Se ₃ , ZnTe, and GeSe, selected for use as a bidirectional threshold switch, and has a thickness of, for example, about 5 nm to about 25 nm, preferably about 15 nm. In some embodiments, the switching element may include a component selected from the group consisting of tellurium (Te), selenium (Se), germanium (Ge), silicon (Si), arsenic (As), titanium (Ti), sulfur (S), and antimony ( Sb) A chalcogen compound in which one or more elements of the group are combined.

In one embodiment, the memory element 153 may be a resistive random access memory or a ferroelectric random access memory. The programmable resistance material in the memory element 153 may be a metal oxide, such as hafnium oxide, magnesium oxide, nickel oxide, niobium oxide, titanium oxide, aluminum oxide, vanadium oxide, tungsten oxide, zinc oxide, or cobalt oxide.

In some embodiments, other resistive memory structures may be implemented, such as metal oxide resistive memory, magnetoresistive memory, conductive bridge resistive memory, and the like.

The first access line and the second access line may include various metals, metal-based materials, doped semiconductors, or a combination thereof. Embodiments of the first and second access lines can be used One or more layers to implement, such as tungsten (W), aluminum (Al), copper (Cu), titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), doped polycrystalline silicon, silicidation Cobalt (CoSi), tungsten silicide (WSi), TiN / W / TiN, and other materials. The thickness of the first access line and the second access line may be in a range of 10 to 100 nm. In other embodiments, the first access line and the second access line may be very thin or thicker.

FIG. 2A illustrates an arrangement of a first access line (FAL) and a second access line (SAL) and a shared first and second access line decoder for the stack 161 of the bidirectional memory cell of FIG. 1A. A stack of two-way cells 161 is selected by a column and row decoder (not shown). The layers in the stack are selected by the layer decoders 171, 172.

In an embodiment, the stack includes bi-directional memory cells 121, 122, 123, and 124 in four layers of the array, which have the same column address and the same row address. The two-way memory cells 121, 122, 123, and 124 are located at the intersections of different levels between the N = 2 first access line layers and the P = 3 second access line layers. The bidirectional memory cell 121 of the first layer L1 is inserted between the second access line 101 of the second access line layer (SAL1) and the first access line 111 of the first access line layer (FAL1). The bidirectional memory cell 122 of the second layer L2 is inserted between the first access line 111 of the first access line layer (FAL1) and the second access line 104 of the second access line layer (SAL2). The bidirectional memory cell 123 of the third layer L3 is inserted between the second access line 104 of the second access line layer (SAL2) and the first access line 114 of the first access line layer (FAL2). The bidirectional memory cell 124 of the fourth layer L4 is inserted between the first access line 114 of the first access line layer (FAL2) and the second access line 107 of the second access line layer (SAL3).

The shared decoder 171 for the first access line layer is operatively coupled to The first and second sets of first access line drivers are configured to select the first and second sets of first access line drivers in response to the location of the target memory cell and the operation being performed. In the illustrated example, there are two first access line layers and two sets of first access line drivers. As the number of layers increases, these groups can include multiple components. By selecting groups instead of individual first access lines, the decoding load can be reduced when the number of groups is less than the number of first access line layers.

The first group includes a driver 203 for the first access line 111, which corresponds to a column of memory cells selected in the first access line layer FAL1. The second group includes a driver 202 for the first access line 114, which corresponds to a column of memory cells selected in the first access line layer FAL2. A driver 203 from the first set of first access line drivers is coupled to apply an operating voltage to the first access lines 111 in the odd-numbered first access line layer (FAL1). The driver 202 from the second set of first access line drivers is coupled to apply an operating voltage to the first access lines 114 in the even first access line layer (FAL2). Therefore, in this example, the first set of first access line layers may include all odd-numbered layers, and the second set may include all even-numbered layers.

The shared decoder and driver circuit 172 for the second access line layer is operatively coupled to the first and second sets of second access line drivers and is configured to respond to the position and the positive of the target memory cell. Perform the operation to select the first and second set of second access line drivers. In the selection for the second access line layer shared decoder and driver circuit 172, a group of second access line drivers will apply an operating voltage to its corresponding second access line group. In the example shown, there are three second access line layers and two sets of second access line drivers. By selecting a group instead of a separate second access When the number of groups is smaller than the number of second access line layers, the decoding load can be reduced.

The first set of second access line drivers includes one or more drivers 204 corresponding to the selected row of memory cells in the second access line layers SAL1 and SAL3. One or more drivers 204 apply a common operating voltage to a set of second access lines, which includes the second access line 101 in the second access line layer SAL1 and the second storage line in the second access line layer SAL3. Take the line 107. In a first embodiment of a shared decoder and driver circuit (for example, the driver circuit shown in FIG. 2C), the driver selector 208 is operatively connected to a second access line driver 204a (in this drawing ), Which are connected to a second access line in a common row (or column) in more than one second access line layer, and drive a common operating voltage to the connected access lines. The driver 204a may be connected to an access line in a common row among all the layers of the second set of access line layers, or to a subset of the layers in the second set of access line layers. The driver selector is configured to enable the second access line driver 204a in this example to apply the same (i.e., common) operating voltage to the second access line 101 and the second storage line in the second access line layer SAL1. The second access line in the second access line 107 in the fetch layer SAL3. In a second embodiment of a shared decoder (such as the shared decoder shown in FIG. 2D), the driver selector 208 is operatively connected to two second access line drivers 204b and 204c. Each driver is connected to a second access line in a common column (or row) in a second access line layer. The driver 204b is connected to the second access line 107 in the second access line layer SAL3. The driver 204c is connected to the second access line 101 in the second access line layer SAL1. The driver selector 208 is configured to enable both drivers 204b and 204c to apply a common operating voltage to the second access line 101 in a given column in the second access line layer SAL1. And the second access line 107 in a given column in the second access line layer SAL3. Because there are fewer drivers, the area occupied by the first embodiment of the shared decoder and driver circuit is smaller than that of the second embodiment. Because the driver is only responsible for applying an operating voltage to one of the second access lines in the second access line layer group, the peripheral circuit required by the second embodiment is less. The configurations of the first and second embodiments of the shared decoder and driver circuit as shown in FIG. 2C and FIG. 2D are applicable to any of the shared decoders in FIG. 3, FIG. 5, FIG. 6 and FIG. One access line and any shared decoder for the second access line.

The second set of second access line drivers includes a driver 206 corresponding to the row of the selected memory cell, and in the example including the second access line 104 in the second access line layer SAL2 is coupled to transfer A common operating voltage is applied to a second set of second access lines having only one member.

FIG. 2B illustrates an exemplary operating voltage applied to the first and second access lines for a read operation for each of the four memory cells 121-124 of the layers L1 to L4 of the stack 161 shown in FIG. 2A. In this example, the driver 202, 203, 204, 206 is configured to apply + 3V, 0V, or -3V as the operating voltage, which depends on the memory cell address decoded for a read operation. Voltages of other sizes and polarities can be used as voltages suitable for a particular embodiment. As can be seen from the table of FIG. 2B, in all read operations of the array, a common operating voltage is applied to the second access lines 101 and 107 at the layers SAL1 and SAL3. This reduces the decoding load on the memory.

In order to read the data in the bidirectional memory cell 121 at the first layer L1, a voltage of six volts is applied to the memory cell through the first access line 111 and the second access line 101, and the other memory cells on the stack are applied. No more than 3 volts. To apply six volts A voltage of -3 V is applied to the second access line 101 of the second access line layer (SAL1) and a second access line 107 of the second access line layer (SAL3). The driver 203 applies an operating voltage of 3V from the first set of first access line drivers to the first access line 111 of the first access line layer (FAL1). An operating voltage of 0 V is applied to the first access line 114 of the first access line layer (FAL2) by the driver 202. An operating voltage of 0V is applied to the second access line 104 of the second access line layer (SAL2) by the driver 206.

In order to read the data in the two-way memory cell 122 at the second layer L2, a six-volt voltage is applied to the memory cell through the first access line 111 (FAL1) and the second access line 104 (SAL2), not exceeding 3 Volts are applied to other memory cells in the stack. A common operating voltage of 0V is applied to the second access line 101 (SAL1) and the second access line 107 (SAL3). The driver 203 applies an operating voltage of 3V from the first set of first access line drivers to the first access line 111 of the first access line layer (FAL1). An operating voltage of 0 V is applied to the first access line 114 of the first access line layer (FAL2) by the driver 202. An operating voltage of -3V is applied to the second access line 104 of the second access line layer (SAL2) by the driver 206.

In order to read the data in the bi-directional memory cell 123 at the third layer L3, a six volt voltage is applied to the memory cell through the first access line 114 (FAL2) and the second access line 104 (SAL2), not exceeding 3 Volts are applied to other memory cells in the stack. A common operating voltage of 0V is applied to the second access line 101 (SAL1) and the second access line 107 (SAL3). The driver 203 applies an operating voltage of 0 V from the first set of first access line drivers to the first access line 111 of the first access line layer (FAL1). Pressure. An operating voltage of 3V is applied to the first access line 114 of the first access line layer (FAL2) by the driver 202. An operating voltage of -3V is applied to the second access line 104 of the second access line layer (SAL2) by the driver 206.

In order to read the data in the bidirectional memory cell 124 at the fourth layer L4, a six volt voltage is applied to the memory cell through the first access line 114 (FAL2) and the second access line 107 (SAL3), not exceeding 3 Volt voltage is applied to other memory cells in the stack. A common operating voltage of -3V is applied to the second access line 101 (SAL1) and the second access line 107 (SAL3). The driver 203 applies an operating voltage of 0V from the first group of first access line drivers to the first access line 111 of the first access line layer (FAL1). An operating voltage of 3V is applied to the first access line 114 of the first access line layer (FAL2) by the driver 202. An operating voltage of 0V is applied to the second access line 104 of the second access line layer (SAL2) by the driver 206.

FIG. 3A illustrates an arrangement of first (column) and second (row) access lines and a shared first and second access line decoder for a stack 371 of a bidirectional memory cell in a 3D crosspoint memory array. It has eight layers from L1 to L8. The two-way memory cell stack 371 includes two-way memory cells 321, 322, 323, 324, 325, 326, 327, and 328. The bidirectional memory cells 321, 322, 323, 324, 325, 326, 327, and 328 are located in the first access line layer of N = M / 2 = 4 first access line layers (FAL1 to FAL4) and P = M / 2 + 1 = at the intersection between the second access lines in the 5 second access line layers (SAL1 to SAL5).

The bidirectional memory cell 321 of the first layer L1 is inserted in the second access line 301 of the second access line layer (SAL1) and the first access of the first access line layer (FAL1). Between lines 311. The bidirectional memory cell 322 of the second layer L2 is inserted between the first access line 311 of the first access line layer (FAL1) and the second access line 302 of the second access line layer (SAL2). The bidirectional memory cell 323 of the third layer L3 is inserted between the second access line 302 of the second access line layer (SAL2) and the first access line 312 of the first access line layer (FAL2). The bidirectional memory cell 324 of the fourth layer L4 is inserted between the first access line 312 of the first access line layer (FAL2) and the second access line 303 of the second access line layer (SAL3). The bidirectional memory cell 325 of the fifth layer L5 is inserted between the second access line 303 of the second access line layer (SAL3) and the first access line 313 of the first access line layer (FAL3). The bidirectional memory cell 326 of the sixth layer L6 is inserted between the first access line 313 of the first access line layer (FAL3) and the second access line 304 of the second access line layer (SAL4). The bidirectional memory cell 327 of the seventh layer L7 is inserted between the second access line 304 of the second access line layer (SAL4) and the first access line 314 of the first access line layer (FAL4). The bidirectional memory cell 328 of the eighth layer L8 is inserted between the first access line 314 of the first access line layer (FAL4) and the second access line 305 of the second access line layer (SAL5).

The shared decoder 351 for the first access line layer is operatively coupled to select between the first and second sets of first access line drivers. The first set of first access line drivers includes drivers 352 for the first access lines in the odd-numbered first access line layers (FAL1 and FAL3). The second set of first access line drivers includes drivers 353 for the first access lines in the even-numbered first access line layers (FAL2 and FAL4). The driver 352 is a first access line 311 coupled to the decoder to apply a total first operating voltage to the odd-numbered first access line layer (FAL1), and is applied to the odd-numbered The first access line 313 (FAL3) in the first access line layer of. The driver 353 is operatively coupled to the decoder to apply a total first operating voltage to the first access lines 312 in the even-numbered first access line layer (FAL2) and the even-numbered first access line layers ( FAL4). In a first embodiment of a shared decoder for a first access line layer 351, the driver selector is operatively connected to two first access line drivers for a common line in two different layers (Or row) of the first access line. The driver selector may be configured to cause one of the first access line drivers to apply the same (i.e., common) operating voltage to the first in a common row of the odd first access line layers (FAL1 and FAL3). Access line group, and cause another first access line driver to apply the same operating voltage to the first access line group in a common row of the even first access line layers (FAL2 and FAL4). In a second embodiment of the shared decoder for the first access line layer, the driver selector 208 is operatively connected to four first access line drivers, each of which is connected to one first access The first access line in a common row in the line layer. The driver selector in the second embodiment is configured to enable a driver connected to a first access line in a common row in an odd-numbered first access line layer to apply a common operating voltage to the first access line The first access line 311 in the layer FAL1 and the first access line 313 in the first access line layer FAL3, and the drivers connected to the first access lines in the even-numbered first access line layer will share An operation voltage is applied to the first access line 312 in a common row in the first access line layer FAL2 and the first access line 314 in a common row in the first access line layer FAL4.

The shared decoder 361 for the second access line layer is operatively coupled to select among the M / 2 = 4 sets of second access line drivers. First set of second access line drives The actuator includes a driver 362 for the second access line in the second access line layers (SAL1 and SAL5). The second set of second access line drivers includes a driver 363 for the second access line in the second access line layer (SAL2). The third set of second access line drivers includes a driver 364 for the second access line in the second access line layer (SAL3). The fourth set of second access line drivers includes a driver 365 for the second access line in the second access line layer (SAL4). The driver 362 is coupled to the decoder to apply a common operating voltage to the second access line 301 in the second access line layer (SAL1), and to the second access in the second access line layer (SAL5) Line 305. The driver 363 is a second access line 302 operatively coupled to the decoder to apply an operating voltage to the second access line layer (SAL2). The driver 364 is a second access line 303 operatively coupled to the decoder to apply an operating voltage to the second access line layer (SAL3). The driver 365 is a second access line 304 operatively coupled to the decoder to apply an operating voltage to the second access line layer (SAL4).

FIG. 3B illustrates an exemplary operating voltage applied to the first and second access lines in the stack 371 of the bi-directional memory cell with M = 8 eight layers as shown in FIG. 3A. It can be seen that for the read operation of the memory cells of any layer, the common operating voltage will be applied to the first access line layer group, which includes the first group including the odd layers FAL1 and FAL3 and the first group including the even layers FAL2 and FAL4. Second Group. Moreover, for the read operation of the memory cells of any layer, the common operation voltage is applied to the second access line layer group, which includes the first group including the top and bottom layers SAL1 and SAL5, and the second group including the layer SAL2 Group, a third group containing layer SAL3, and a fourth group containing layer SAL4. Therefore, the decoding load will be reduced from the selection of four layers to the selection of two sets of first access line layers, and from the five layers. The choice is reduced to four sets of second access line layer choices.

FIG. 4 is a flowchart illustrating a method for reading data from a memory cell in a 3D cross-point memory array with a shared layer decoding. In a read operation, in some embodiments, a read command and an address of a memory cell to be read are received. The controller executes a read procedure, which involves setting the bias voltage, driver, and sense amplifier to perform the read. In addition, the decoder is used to decide which access lines to drive to complete the read operation of the memory cell at a specific address. In a 3D array, memory cells can be represented by columns, rows, and layers. The method shown in Figure 4 begins by decoding the memory cell address to determine the columns and rows of the memory cell (step 401). In addition, the method includes selecting a set of column access line layers (ie, the first access line layer) according to the layer of the memory cell (step 402). Furthermore, the method includes selecting a set of row access line layers (ie, second access line layers) according to the layers of the memory cells (step 403). When the number of row access line layer groups selected by the decoder is less than the number of row access line layers, the decoding load is reduced.

The read operation includes applying a first operating voltage to a column access line in a determined column in each component of the selected set of column access line layers (step 404). When the number of column access line layer groups selected by the decoder is less than the number of column access line layers, the decoding load is reduced.

At the same time, the method includes applying a second operating voltage to the row access lines in the determined row in each component of the selected set of row access line layers (step 405). In addition, this method includes applying an intermediate voltage for the above-mentioned type of memory cells to the column access lines and row access lines in the unselected columns and rows, and each of the unselected column and row access line layers Components (step 406).

In an embodiment of the technology described in this disclosure, at least one set of column access line layers or at least one set of row access line layers includes more than one component. Therefore, the decoding load is reduced.

In the embodiments discussed above, the column access line layer or the row access line layer are grouped into a group including each odd layer of the first group and each even layer of the second group. The other of the column access line layer or the row access line layer is grouped into a group including a first group and other groups, wherein the bottom layer and the top layer in this first group are components, and the other groups One of the individual layers between the top and bottom is included in each group.

FIG. 5A illustrates a 3D cross-point memory array with unidirectional memory cells. The 3D crosspoint array includes a plurality of unidirectional memory cells, which include unidirectional memory cells 521, 522, 523, 524. Unidirectional memory cells are arranged in a plurality of first access lines 501, 502, 503, 504, 505, 506, 507, 508, and 509 (i.e., column access lines) arranged in a column direction and arranged in a row direction. At the intersection of a plurality of second access lines 511, 512, 513, 514, 515, and 516 (ie, row access lines). Each unidirectional memory cell is connected to a specific first access line and a specific second access line. For example, the unidirectional memory cell 521 is connected to the first access line 501 and the second access line 511. In addition to memory elements, "unidirectional" memory cells also include directional elements. The directional element allows a current to flow into the memory cell in a specific direction between a specific first access line and a specific second access line of the memory cell. Examples of such directional elements include diodes. For example, in the unidirectional memory cell 521, a current can flow from the second access line 511 to the first access line 501, but not vice versa. Stack 561 includes unidirectional memory cells 521, 522, 523, and 524 stacked on top of another.

A 3D cross-point memory array with unidirectional memory cells implemented in the configuration of FIG. 5A may have many layers and many first and second access lines in each layer for forming very High-density memory device. In a preferred embodiment, the number of layers M of the unidirectional memory cell is, for example, a positive integer, and M may be a multiple of 2, for example, M = 2, 4, 8, 16, 32, or 64. Other 3D configurations can also be implemented. A 3D crosspoint memory array with M layers of unidirectional memory cells may have N first access line layers, where N is a positive integer, for example, where N = M / 2 + 1. Each first access line layer (n) may include a plurality of first access lines, where n is, for example, a positive integer, where n is from 1 to M / 2 + 1. The 3D crosspoint memory array with M layers may further include P second access line layers interleaved with N first access line layers, where P is a positive integer, for example, where P = M / 2. Each second access line layer (p) may include a plurality of second access lines, where p is, for example, a positive integer, where p is from 1 to M / 2.

The 3D crosspoint memory array in FIG. 5A includes M = 4 layers of directional memory cells, N = 3 first access line layers, and P = 2 second access line layers. The unidirectional memory cell of the first layer in the 3D cross-point memory array is inserted in the first access line layer (FAL1) including the first access lines 501, 502, and 503 and includes the second access line 511, 512, and 513 Between the second access line layer (SAL1). The unidirectional memory cell of the second layer in the 3D cross-point memory array is inserted in the second access line layer (SAL1) including the second access lines 511, 512, and 513 and includes the first access lines 504, 505, and 506. Between the first access line layer (FAL2). The third layer in the 3D crosspoint memory array is inserted in the first access line layer (FAL2) including the first access lines 504, 505, and 506, and the second storage line including the second access lines 514, 515, and 516. Take the line layer (SAL2). 3D Intersection The fourth layer in the memory array is inserted between the second access line layer (SAL2) including the second access lines 514, 515, and 516 and the first access line layer including the first access lines 507, 508, and 509 (FAL3).

FIG. 5A illustrates a 3D crosspoint memory array of M layers, which includes a shared decoder 571 for a first access line layer and a shared decoder 572 for a second access line layer. The control circuit (not shown in FIG. 5A) is a shared decoder 571 for the first access line layer, a shared decoder for the second access line layer 572, and other resources in the integrated circuit. To perform write operations, read operations, and other memory device operations that require a sequence of voltage pulses to be applied to unidirectional memory cells in the 3D cross-point memory array.

More details regarding the arrangement of the first access line decoder 571, the second access line decoder 572, and the first and second access lines are described below with reference to FIG. 6A.

FIG. 5B is a close-up view of the example unidirectional memory cell 521 in FIG. 5A. The memory cell 521 has a first element 551 in contact with the first access line 501 and a second element 552 in contact with the second access line 511. The memory element 553 is disposed between the first element 551 and the intermediate element 554. The directional element 555 is disposed between the intermediate element 554 and the second element 552. The first element 551 connects the memory element 553 to the first access line 501. The second element 552 connects the directional element 555 to the second access line 511. In some embodiments, the directional element may be between the intermediate element and the first element, and the memory element may be between the intermediate element and the second element.

In the embodiment of FIG. 5B, the directional element allows current to flow from the second element to the first element, but not vice versa. In some embodiments, the directional element may allow Current flows from the first element to the second element, but not vice versa.

The first element 551, the second element 552, and the intermediate element 554 may include a conductive material having a thickness of about 5 to 50 nm. Example materials have been described above with reference to FIG. 1B.

The memory element 553 may include a layer of programmable resistive material. The programmable resistance material may have a first resistance value representing a bit “0” and a second resistance value representing a bit “1”. In some embodiments, each memory cell can store multiple bits.

In one embodiment, the memory element 553 may be a phase change memory, which includes a phase change material layer as a programmable resistive material, as described in the above example.

In other embodiments, the memory element 553 may be a resistive random access memory or a ferroelectric random access memory. The programmable resistive material in the memory element 553 may be a metal oxide, such as hafnium oxide, magnesium oxide, nickel oxide, niobium oxide, titanium oxide, aluminum oxide, vanadium oxide, tungsten oxide, zinc oxide, or cobalt oxide.

In some embodiments, other resistive memory structures may be implemented, such as metal oxide resistive memory, magnetoresistive memory, conductive bridge resistive memory, and the like.

The directional element 555 may be, for example, a diode.

The first access line and the second access line may include various metals, metal-based materials, doped semiconductors, or a combination thereof as described above.

FIG. 6A illustrates first and second access lines and a shared first and second access line for a stack 561 of selected columns and unidirectional memory cells in a selected row in the array as in FIG. 5A The arrangement of the decoder. The stack of unidirectional memory cells 561 includes unidirectional memory cells 521, 522, 523, and 524 stacked on each other. Unidirectional memory cells 521, 522, 523, and 524 are located at the intersection between N = 3 first access line layers and P = 2 second access line layers. At the fork. The unidirectional memory cell 521 of the first layer L1 is inserted between the first access line 501 of the first access line layer (FAL1) and the second access line 511 of the second access line layer (SAL1). The unidirectional memory cell 522 of the second layer L2 is inserted between the second access line 511 of the second access line layer (SAL1) and the first access line 504 of the first access line layer (FAL2). The unidirectional memory cell 523 of the third layer L3 is inserted between the first access line 504 of the first access line layer (FAL2) and the second access line 514 of the second access line layer (SAL2). The unidirectional memory cell 524 of the fourth layer L4 is inserted between the second access line 514 of the second access line layer (SAL2) and the first access line 507 of the first access line layer (FAL3).

The shared decoder 571 for the first access line layer is operatively coupled to the first and second sets of first access line drivers and is configured to select the first or second set of first access line drivers to Respond to the location of the target memory cell and the operation being performed. In the example shown, there are three first access line layers and two sets of first access line drivers. By selecting groups instead of individual first access lines, the decoding load can be reduced when the number of groups is less than the number of first access line layers.

The first group of first access line drivers includes a driver 602 for the first access line 501 and the first access line 507. The first access line 501 is a memory cell corresponding to the first access line layer FAL1. The first access line 507 is a column corresponding to the memory cell selected in the first access line layer FAL3. The second group includes a driver 603 for a first access line 504, which is a column corresponding to the selected memory cell in the first access line layer FAL2. The driver 602 from the first set of first access line drivers is operatively coupled to the decoder 571 to apply a common operating voltage to the odd-numbered layers, including This includes applying a common operating voltage to the first access line 501 in the first access line layer FAL1 and the first access line 507 in the first access line layer FAL3. The driver 603 from the second set of first access line drivers is coupled to the decoder 571 to apply a common operating voltage to the even-numbered layers, which includes applying a common operating voltage to the first An access line 504. Therefore, in this example, the first set of first access line layers may include all odd-numbered layers, and the second set may include all even-numbered layers.

The shared decoder 572 for the second access line layer is operatively coupled to the first set of second access line drivers and is configured to select a set of second access line drivers in response to using the decoder 572. The location of the target memory cell within the block of the array and the operation being performed. In the example shown, there are two second access line layers and a set of second access line drivers. By selecting a group instead of a separate second access line, when the number of groups is smaller than the number of second access line layers, the decoding load can be reduced.

The first set of second access line drivers includes a driver 605, which corresponds to a selected row of memory cells in the second access line layers SAL1 and SAL2.

FIG. 6B illustrates an example operating voltage applied to the first and second access lines in the stack 561 of the unidirectional memory cell in FIG. 6A for a read operation. As long as the first operating voltage and the second operating voltage generate a voltage drop on the memory cell, any voltage of any size and polarity can be used as the first operating voltage and the second operating voltage to allow current to flow through the directional element to determine the memory cell. (That is, the bits stored in the resistance unit are determined), and thus the data in the unidirectional memory cell is read.

In this example, the drivers 602, 603, and 605 are configured to apply one of + 3V, 0V, and -3V based on the decoded memory cell address used for the read operation. As the operating voltage. Voltages of other sizes and polarities can be used as voltages suitable for a particular embodiment. It can be seen from the table of FIG. 6B that in all read operations of the array, a common operating voltage is applied to the second access lines 511 and 514 at the layers SAL1 and SAL2. At the same time, in some read operations of the array, a common operating voltage is applied to the first access lines 501 and 507 at the layers FAL1 and FAL3. This reduces the decoding load on the memory.

In order to read data in the unidirectional memory cell 521 at the first layer L1, a forward bias of 6 volts is applied by -3V on the first access line 501 and + on the second access line 511. 3V is applied across the memory cells, and a forward or reverse bias not exceeding +3 volts is applied across the other memory cells in the stack. In order to apply a forward bias of 6 volts, a common operating voltage of + 3V is applied to the second access line 511 of the second access line layer SAL1 and the second storage line of the second access line layer SAL2 by the driver 605. Take line 514. An operation voltage of -3V is applied to the first access line 501 of the first access line layer FAL1 and the first access line 507 of the first access line layer FAL3 by the driver 602. An operating voltage of 0V is applied to the first access line 504 of the first access line layer FAL2 by the driver 603.

In order to read data in the unidirectional memory cell 522 at the second layer L2, the 6 volt forward bias will pass through the memory cell through the first access line 504 (FAL2) and the second access line 511 (SAL1). Is applied without exceeding 3 volts or reverse bias is applied across the other memory cells in the stack. In order to apply a forward bias of 6 volts, a common operating voltage of -3 V is applied to the second access line 511 and the second access line 514 (SAL2). With the driver 603 from the second set of first access line drivers, An operating voltage of + 3V is applied to the first access line 504 of the first access line layer (FAL2). By applying an operating voltage of 0 V through the driver 602 to the first access line 501 of the first access line layer (FAL1) and the first access line 507 of the first access line layer FAL3.

In order to read the data in the unidirectional memory cell 523 at the third layer L3, a forward bias of 6 volts is applied through the first access line 504 (FAL2) and the second access line 514 (SAL2). Memory cells, not exceeding 3 volts or reverse bias, will be applied to other memory cells in the stack. To apply a forward bias of 6 volts, a common operating voltage of +3 V is applied to the second access line 514 (SAL2) and the second access line 511 (SAL1). An operating voltage of -3V is applied to the first access line 504 of the first access line layer (FAL2) by a driver 603 from the second set of first access line drivers. An operating voltage of 0V is applied by the driver 602 is applied to the first access line 501 of the first access line layer (FAL1) and the first access line 507 of the first access line layer FAL3.

In order to read the data in the unidirectional memory cell 524 at the fourth layer L4, a forward bias of 6 volts is applied through the memory through the first access line 507 (FAL3) and the second access line 514 (SAL2). Cells, no more than 3 volts or reverse bias will be applied to other memory cells in the stack. In order to apply a forward bias of 6 volts, a common operating voltage of -3 V is applied to the second access line 514 (SAL2) and the second access line 511 (SAL1). An operating voltage of 0V is applied to the first access line 504 of the first access line layer (FAL2) by a driver 603 from the second set of first access line drivers. An operating voltage of 3V is applied by the driver 602 To the first access line 501 of the first access line layer (FAL1) and the first access line 507 of the first access line layer FAL3.

FIG. 7A illustrates first and second access lines of a stack 771 of unidirectional memory cells at specific columns and rows in a 3D cross-point memory array of M = 8 layers and shared first and second accesses Arrangement of line decoder. The one-way memory cell stack 771 includes one-way memory cells 721, 722, 723, 724, 725, 726, 727, and 728 stacked on top of each other. Unidirectional memory cells 721, 722, 723, 724, 725, 726, 727, and 728 are located at the first access line in the N = M / 2 + 1 = 5 first access line layer and P = M / 2 = 4 At the intersection between the second access lines in the two second access line layers. The unidirectional memory cell 721 of the first layer L1 is inserted between the first access line 701 of the first access line layer (FAL1) and the second access line 711 of the second access line layer (SAL1). The unidirectional memory cell 722 of the second layer L2 is inserted between the second access line 711 of the second access line layer (SAL1) and the first access line 702 of the first access line layer (FAL2). The unidirectional memory cell 723 of the third layer L3 is inserted between the first access line 702 of the first access line layer (FAL2) and the second access line 712 of the second access line layer (SAL2). The unidirectional memory cell 724 of the fourth layer L4 is inserted between the second access line 712 of the second access line layer (SAL2) and the first access line 703 of the first access line layer (FAL3). The unidirectional memory cell 725 of the fifth layer L5 is inserted between the first access line 703 of the first access line layer (FAL3) and the second access line 713 of the second access line layer (SAL3). The unidirectional memory cell 726 of the sixth layer L6 is inserted between the second access line 713 of the second access line layer (SAL3) and the first access line 704 of the first access line layer (FAL4). The unidirectional memory cell 727 of the seventh layer L7 is inserted between the first access line 704 of the first access line layer (FAL4) and the second access line 714 of the second access line layer (SAL4). The unidirectional memory cell 728 of the eighth layer L8 is inserted in the second access line 714 and the first access line in the second access line layer (SAL4). Between the first access lines 705 of an access line layer (FAL5).

The shared decoder 751 for the first access line layer includes first and second sets of first access line drivers. The first set of first access line drivers includes a driver 752, which is coupled to apply a common operating voltage to the first access lines 701 in the odd first access line layer (FAL1), the odd first accesses The first access line 703 in the line layer (FAL3) and the first access line 705 in the odd-numbered first access line layer (FAL5). The second set of first access line drivers includes a driver 753, which is coupled to apply a common operating voltage to the first access line 702 in the even first access line layer (FAL2) and the even first access The first access line 704 in the line layer (FAL4).

The shared decoder 761 for the second access line layer includes M / 4 = 2 sets of second access line drivers. The first set of second access line drivers includes a driver 762 that is coupled to apply a common operating voltage to the second access line 711 and the second access line layer (SAL2) in the second access line layer (SAL1).中 的 第二 access 线 712. The second set of second access line drivers includes a driver 763 coupled to apply a common operating voltage to the second access line 713 and the second access line layer (SAL4) in the second access line layer (SAL3).中 的 second access line 714.

FIG. 7B illustrates an exemplary operating voltage applied to the first and second access lines in the stack 771 of the unidirectional memory cells of M = 8 eight layers as shown in FIG. 7A. It can be seen that for the read operation of the memory cells of any layer, the common operation voltage is applied to the first access line layer group, which includes the first group including the odd layers FAL1, FAL3, and FAL5, and the even layer FAL2 And the second set of FAL4. In addition, for a read operation of a memory cell in any layer, a common operating voltage is applied to multiple sets of second access line layers, including The first group containing layers SAL1 and SAL2 and the second group containing layers SAL3 and SAL4. Therefore, the decoding load is reduced from the selection of five first access line layers to the selection of two sets of first access line layers, and from the selection of four second access line layers to two sets of second access lines. Selection of layers.

FIG. 8 is a schematic block diagram of an integrated circuit 850 including a 3D cross-point memory array 800. The 3D crosspoint memory array 800 includes unidirectional memory cells in some embodiments and bidirectional memory cells in other embodiments.

The shared layer decoder 801 is coupled to and electrically communicated with the shared decoder 802 for the second access line layer and the shared decoder 803 for the first access line layer. It is implemented as described above to Reduce the decoding load of 3D array. The shared decoder 802 for the second access line layer is coupled and electrically connected to a plurality of second access lines arranged in a column in the 3D intersection array 800. The second access line decoder 802 may include a plurality of sets of second access line drivers. The first access line decoder 803 is coupled to and electrically communicates with a plurality of first access lines arranged in a row in the 3D crosspoint array 800. The first access line decoder 803 may include a first set of first access line drivers and a second set of first access line drivers. The address on the bus 805 is provided to the layer decoder 801, the shared decoder 802 for the second access line layer, and the shared decoder 803 for the first access line layer. In this embodiment, the sense amplifier and other supporting circuits such as a precharge circuit and the data-in-structure in the block 806 are coupled to the first access line via the bus 807 Layer shared decoder 803. In some embodiments, the sense amplifier may be independent of the data input structure in block 806.

Data from the integrated circuit 850 or other data sources via the data input line 821 The input / output terminal on the data input structure is provided to the data input structure in block 806. The data is provided to the input / output terminal on the integrated circuit 850 from the sense amplifier in the block 806 through the data output line 822, or to other data destinations inside or outside the integrated circuit 850.

The bias configuration state machine is in a control circuit 808 that controls the bias configuration supply voltage 808 as described in this disclosure. In addition, the control circuit coordinates the operation of the sensing circuit and the data input structure for read and write operations in block 806, which includes performing the method of FIG. 4. This circuit can be implemented using dedicated logic, a general-purpose processor, or a combination thereof to perform read, write, and erase operations.

Although the present disclosure has been disclosed as above by way of example, it is not intended to limit the present disclosure. Any person with ordinary knowledge in the technical field should make some changes and modifications without departing from the spirit and scope of the present disclosure. The scope of protection of this disclosure shall be determined by the scope of the attached patent application.

Claims (20)

A memory circuit includes: a three-dimensional cross-point memory array having at least M layers of memory cells, which are arranged at the intersection of a first access line and a second access line; and the Nth An access line layer, where n is a first access line layer (n) from 1 to N (n) includes a plurality of first access lines coupled to memory cells of a corresponding column; P for the M layers A second access line layer, the P second access line layers are interleaved with the N first access line layers, where p is a second access line layer from 1 to P (p) includes a coupling A plurality of second access lines to the corresponding rows of memory cells; a decoder and a driver circuit for applying a common operating voltage to a selected first access line in a set of first access line layers, said one The group of first access line layers has more than one and less than N components; and the decoder and driver circuit for applying an operating voltage to a selected second memory of the second access line layer. Take a line, where M, N, P, n, and p are positive integers. The memory circuit according to item 1 of the scope of patent application, wherein the M layer is selected in an intersection of a specific first access line and a specific second access line provided in a specific first access line layer in the M layer. When the specific first access line layer is a component of the group of first access line layers, the decoder and the driving circuit are further used to select a column memory cell, a row memory cell, The set of first access line layers and one or more second access line layers including the specific second access line. The memory circuit according to item 2 of the scope of patent application, wherein the decoder and driver circuit includes a first access line driver, and the first access line driver is operatively connected to the group of first memory lines. The first access line in a common column in more than one first access line layer in the fetch layer is used to cause the first access line driver to apply the common operating voltage to the set of first First access lines in a common column in more than one first access line layer. The memory circuit according to item 2 of the patent application scope, wherein the decoder and driver circuit includes a plurality of first access line drivers, and wherein the first access lines of the plurality of first access line drivers A driver is operatively connected to a first access line in a given column in only one of the first access line layers in the set and serves to cause the plurality of first access lines to An access line driver applies the common operating voltage to all first access lines in the set of first access line layers. The memory circuit according to item 1 of the scope of patent application, wherein the set of first access line layers includes an odd number of first access line layers (n), where n is an odd number, and wherein the decoder and The driver circuit is further configured to apply a common operating voltage to a selected first access line layer in the second set of first access line layers, the second set of first access line layers including an even number of first access lines. Layer (n), where n is an even number. The memory circuit according to item 1 of the patent application scope, wherein the memory cell in the three-dimensional memory array includes a memory element, and the memory element includes a programmable resistive material. The memory circuit according to item 1 of the scope of patent application, wherein the decoder and the driver circuit are configured to apply a common operating voltage to a selected second access line in a set of second access line layers, the A set of second access line layers has more than one and less than P components. The memory circuit according to item 7 of the scope of patent application, wherein the set of second access line layers includes a second access line layer (p), where p is 1 and M / 2 + 1, respectively. The memory circuit according to item 1 of the patent application scope, wherein the memory cells in the array are unidirectional, and wherein the decoder and the driver circuit are configured to apply a common operating voltage to a plurality of sets of second A second access line in an access line layer, the plurality of sets of second access line layers including M / 4 sets of second access line layers; and wherein each of the M / 4 sets of second access line layers The set of second access line layers includes a pair of second access line layers including a second access line layer (p) and a second access line layer (p + 1). A method for operating a three-dimensional cross-point memory array, the three-dimensional cross-point memory array having at least M layers of memory cells arranged at the intersection of a first access line and a second access line, the array Including N first access line layers for the M layers, where n is a first access line layer from 1 to N (n) including a plurality of first accesses coupled to memory cells of a corresponding column And P second access line layers interleaved with the N first access line layers for the M layer, where p is a second access line layer from 1 to P (p) includes a coupling A plurality of second access lines connected to a corresponding row of memory cells; the method includes: applying a common operating voltage to a selected first access line in a set of first access line layers, the set of first access lines An access line layer has more than one and less than N components; and an operating voltage is applied to a selected second access line in the second access line layer, where M, N, P, n, and p is a positive integer. The method for operating a three-dimensional crosspoint memory array according to item 10 of the scope of patent application, comprising: selecting a specific first access line and a specific first access line set in a specific first access line layer in the M layer A specific memory cell at the intersection of the second access lines. When the specific first access line layer is a component of the group of first access line layers, by selecting a column memory cell, a row memory cell, The set of first access line layers and one or more second access line layers including the specific second access line. The method for operating a three-dimensional cross-point memory array according to item 10 of the application, wherein the set of first access line layers includes an odd number of first access line layers (n), where n is an odd number And the method further includes applying a common operating voltage to a selected first access line in the second set of first access line layers, the second set of first access line layers including an even number of first access lines Layer (n), where n is an even number. The method for operating a three-dimensional cross-point memory array according to item 10 of the application, wherein the memory cells in the three-dimensional memory array include a memory element, and the memory element includes a programmable resistance material. The method for operating a three-dimensional crosspoint memory array according to item 10 of the patent application scope, comprising applying a common operating voltage to a selected second access line in a set of second access line layers, the first The group second access line layer has more than one and less than P components. The method for operating a three-dimensional crosspoint memory array according to item 14 of the scope of patent application, wherein the set of second access line layers includes a second access line layer (p), where p is 1 respectively With M / 2 + 1. The method for operating a three-dimensional cross-point memory array as described in claim 10, wherein the memory cells in the array are unidirectional, and the method includes applying a common operating voltage to multiple groups A second access line in a second access line layer, the plurality of sets of second access line layers including M / 4 sets of second access line layers; and wherein the M / 4 sets of second access line layers Each set of second access line layers includes a pair of second access line layers, the pair of second access line layers including a second access line layer (p) and a second access line layer (p + 1) ). A memory circuit includes: a three-dimensional cross-point memory array having at least M layers of memory cells, which are arranged at the intersection of a first access line and a second access line; and the Nth An access line layer, where n is a first access line layer (n) from 1 to N (n) includes a plurality of first access lines coupled to memory cells of a corresponding column; P for the M layers A second access line layer, the P second access line layers are interleaved with the N first access line layers, where p is a second access line layer from 1 to P (p) includes a coupling A plurality of second access lines to the corresponding rows of memory cells; a decoder and a driver circuit for applying a common operating voltage to a selected first access line in a set of first access line layers, said one A set of first access line layers having more than one and less than N components, wherein the set of first access line layers includes an odd number of first access line layers (n), where n is an odd number; and The decoder and driver circuit are used to apply a common operating voltage to a second access line in a given row of a plurality of sets of second access line layers, the plurality of sets of second access line layers including M / 4 groups Second access Layer, wherein each of the M / 4 sets of second access line layers includes a pair of second access line layers, and the pair of second access line layers includes a second access line Layer (p) and second access line layer (p + 1), where M, N, P, n, and p are positive integers. The memory circuit according to item 17 of the scope of patent application, wherein the M layer is selected in an intersection of a specific first access line and a specific second access line provided in a specific first access line layer in the M layer. When the specific first access line layer is a component of the group of first access line layers, the decoder and the driving circuit are configured to select a column memory cell, a row memory cell, the A set of first access line layers and one or more second access line layers including the specific second access line. The memory circuit according to item 17 of the scope of patent application, wherein the memory cell in the three-dimensional memory array includes a memory element, and the memory element includes a programmable resistive material. The memory circuit of claim 17 in which the decoder and the driver circuit are further configured to apply a common operating voltage to a selected one of the given columns in the second set of first access line layers. A first access line, the second set of first access line layers including an even number of first access line layers (n), where n is an even number.