TWI670472B - Zero-crossing detection circuit and sensing device - Google Patents
Zero-crossing detection circuit and sensing device Download PDFInfo
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- TWI670472B TWI670472B TW106116060A TW106116060A TWI670472B TW I670472 B TWI670472 B TW I670472B TW 106116060 A TW106116060 A TW 106116060A TW 106116060 A TW106116060 A TW 106116060A TW I670472 B TWI670472 B TW I670472B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/153—Arrangements in which a pulse is delivered at the instant when a predetermined characteristic of an input signal is present or at a fixed time interval after this instant
- H03K5/1536—Zero-crossing detectors
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02P—CONTROL OR REGULATION OF ELECTRIC MOTORS, ELECTRIC GENERATORS OR DYNAMO-ELECTRIC CONVERTERS; CONTROLLING TRANSFORMERS, REACTORS OR CHOKE COILS
- H02P6/00—Arrangements for controlling synchronous motors or other dynamo-electric motors using electronic commutation dependent on the rotor position; Electronic commutators therefor
- H02P6/14—Electronic commutators
- H02P6/16—Circuit arrangements for detecting position
- H02P6/18—Circuit arrangements for detecting position without separate position detecting elements
- H02P6/182—Circuit arrangements for detecting position without separate position detecting elements using back-emf in windings
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Abstract
本發明提供一種可不受雜訊的影響地以高精度檢測零交越的零交越檢測電路。本發明具備第一比較電路、具有磁滯功能的第二比較電路以及邏輯電路,且為具備如下單元的構成:所述單元中,第一比較電路輸出第一輸入訊號與第二輸入訊號的零交越檢測結果,第二比較電路輸出第一輸入訊號與第二輸入訊號的比較結果,邏輯電路基於零交越檢測結果與比較結果而決定是否將零交越檢測結果反映至輸出中。The present invention provides a zero-crossing detection circuit that can detect zero-crossing with high precision without being affected by noise. The present invention includes a first comparison circuit, a second comparison circuit having a hysteresis function, and a logic circuit, and is configured to include a unit in which the first comparison circuit outputs zeros of the first input signal and the second input signal. The second comparison circuit outputs a comparison result between the first input signal and the second input signal, and the logic circuit determines whether to reflect the zero-crossing detection result to the output based on the zero-crossing detection result and the comparison result.
Description
本發明是有關於一種零交越(zero-cross)檢測電路及感測裝置,尤其是有關於一種可基於來自感測元件的訊號而準確地檢測零交越點的零交越檢測電路。 The present invention relates to a zero-cross detection circuit and a sensing device, and more particularly to a zero-crossing detection circuit that can accurately detect a zero-crossing point based on a signal from a sensing element.
在習知上,各種感測裝置被裝載於電子設備而受到有效利用。作為一例,可列舉為了檢測無刷馬達(brushless motor)的活動件的位置而使用磁力感測裝置的例子。無刷馬達包括圓筒狀的定子(stator)、以及在該定子的內周或外周相向地設置的圓筒狀的轉子(rotor)。轉子以旋轉軸為中心相對於定子自如地旋轉。在轉子中沿圓周方向配置有勵磁用的磁鐵,在定子的定子鐵心上捲繞有線圈,利用藉由使電流流至線圈而產生的磁場與勵磁用的磁鐵所形成的磁場的相互作用,轉子進行旋轉。 Conventionally, various sensing devices are loaded on an electronic device and are effectively utilized. As an example, an example in which a magnetic force sensing device is used to detect the position of a movable member of a brushless motor can be cited. The brushless motor includes a cylindrical stator and a cylindrical rotor that is disposed to face each other on the inner circumference or the outer circumference of the stator. The rotor freely rotates relative to the stator about the rotation axis. A magnet for excitation is disposed in the rotor in the circumferential direction, and a coil is wound around the stator core of the stator, and an interaction between a magnetic field generated by a current flowing to the coil and a magnetic field formed by the magnet for excitation is used. The rotor rotates.
為了對轉子的旋轉進行控制,需要進行轉子的旋轉位置的檢測,作為位置檢測的手段,通常使用磁力感測元件。利用磁力感測元件對磁鐵的S極與N極的切換、即零交越的位置進行檢測,藉此檢測轉子的旋轉位置。於零交越檢測中,為了防止零交越附近的顫動(chattering)而對使具有磁滯(hysteresis)特性的方法進行了各種研究。但是,受該磁滯的影響,原本的零交越位置與藉由感測訊號檢測而得的零交越檢測位置之間產生偏差,產 生馬達的效率降低、旋轉不均或發生振動等問題。因此,需要一種在零交越附近不產生顫動且輸出不具有磁滯特性的零交越檢測電路。 In order to control the rotation of the rotor, it is necessary to detect the rotational position of the rotor. As a means of position detection, a magnetic sensing element is generally used. The position at which the S pole and the N pole of the magnet are switched, that is, the position where the zero crosses, is detected by the magnetic sensing element, thereby detecting the rotational position of the rotor. In the zero-crossing detection, various methods for making hysteresis characteristics have been studied in order to prevent chattering in the vicinity of zero-crossing. However, due to the hysteresis, the original zero-crossing position and the zero-crossing detection position detected by the sensing signal are deviated. Problems such as reduced efficiency, uneven rotation, or vibration of the motor. Therefore, there is a need for a zero-crossing detection circuit that does not produce chattering near zero crossings and that does not have hysteresis characteristics.
將習知的零交越檢測電路的一例的電路圖示於圖12。習知的零交越檢測電路包括:運算放大器50,將被檢測訊號S輸入至反相輸入端子,並作為零交越檢測訊號fa而加以輸出;以及比較訊號形成電路51,形成比較訊號h並賦予至運算放大器50的非反相輸入端子,其中藉由零交越檢測訊號fa,所述比較訊號h相對於被檢測訊號S而在零交越檢測後立即成為正負相反的位準,並且依序發生位準變化,在規定時間後成為零位準。比較訊號形成電路51包括電阻R10、電阻R11及電容Ca,且設定為時間常數T=(R10+R11).Ca。 A circuit diagram of an example of a conventional zero-crossing detection circuit is shown in FIG. The conventional zero-crossing detection circuit includes an operational amplifier 50 that inputs the detected signal S to the inverting input terminal and outputs it as a zero-crossing detection signal fa; and compares the signal forming circuit 51 to form a comparison signal h and Provided to the non-inverting input terminal of the operational amplifier 50, wherein the comparison signal h is positively and negatively opposite to the detected signal S after the zero-crossing detection by the zero-crossing detection signal fa, and The order changes in the order and becomes zero after the specified time. The comparison signal forming circuit 51 includes a resistor R10, a resistor R11 and a capacitor Ca, and is set to a time constant T=(R10+R11). Ca.
將如此般構成的習知的零交越檢測電路的動作示於圖13。若將被檢測訊號S賦予至運算放大器50的反相輸入端子,則運算放大器50對被檢測訊號S與比較訊號h的各位準進行比較,並輸出作為其比較結果的零交越檢測訊號fa。於時刻t1,被檢測訊號S為正側位準,比較訊號h為負側位準,運算放大器50輸出低位準的零交越檢測訊號fa。自該狀態起經過一定時刻,比較訊號h跟隨時間常數T發生位準變化而成為零位準,若於時刻t2被檢測訊號S進行零交越,則運算放大器50的反相輸入端子的電壓自正側的位準成為零位準,進而變化為負側位準。藉此,自演算放大器50輸出的零交越檢測訊號fa於時刻t2反相為高位準。此 時,對電容器Ca賦予高位準的零交越檢測訊號fa、即+Vdd,因此於該電容器Ca的另一端出現為+2Vdd的電壓c。該電壓c經電阻R10與電阻R11分壓,作為比較訊號h而供給至運算放大器50的非反相輸入端子。因此,緊接於時刻t2後,利用運算放大器50對變化為負側位準的被檢測訊號S與成為正側位準的比較訊號h進行比較。藉此,即便在零交越附近雜訊ns附加於被檢測訊號S而強制地進行了零交越,藉由比較訊號形成電路51的作用,亦以比較訊號h的位準相對於被檢測訊號S而成為正負相反的位準的方式動作,因此自運算放大器50輸出的零交越檢測訊號fa不會因雜訊ns而反相,不會發生零交越的誤檢測。此後,比較訊號h跟隨時間常數T而其位準緩慢降低,在來到下一零交越時刻t3以前到達零位準。若來到時刻t3而被檢測訊號S再次進行零交越,則自運算放大器50輸出的零交越檢測訊號fa反相而成為低位準。此時,對電容器Ca賦予低位準的零交越檢測訊號fa、即電壓-Vdd,因此於電容器Ca的另一端出現為-2Vdd的電壓c。該電壓c經電阻R10與電阻R11分壓,作為比較訊號h而供給至運算放大器50的非反相輸入端子。每當發生被檢測訊號的正負位準的變化時便進行以上動作,以輸出零交越檢測訊號fa。因此,實現了即便發生由雜訊引起的零交越亦不會發生誤檢測即顫動的零交越檢測訊號。 The operation of the conventional zero-crossing detection circuit configured as described above is shown in FIG. When the detected signal S is supplied to the inverting input terminal of the operational amplifier 50, the operational amplifier 50 compares the detected signal S with the comparison signal h, and outputs a zero-crossing detection signal fa as a result of the comparison. At time t1, the detected signal S is the positive side level, the comparison signal h is the negative side level, and the operational amplifier 50 outputs the low level zero crossing detection signal fa. After a certain time from the state, the comparison signal h follows the time constant T and changes to a zero level. If the detected signal S is zero-crossed at time t2, the voltage of the inverting input terminal of the operational amplifier 50 is self-regulated. The level on the positive side becomes the zero level, which in turn changes to the negative side level. Thereby, the zero-crossing detection signal fa output from the amplifier 50 is inverted to a high level at time t2. this At this time, the capacitor Ca is given a high level zero crossing detection signal fa, that is, +Vdd, so that a voltage c of +2 Vdd appears at the other end of the capacitor Ca. This voltage c is divided by the resistor R10 and the resistor R11, and supplied as a comparison signal h to the non-inverting input terminal of the operational amplifier 50. Therefore, immediately after the time t2, the detected signal S which changes to the negative side level is compared with the comparison signal h which becomes the positive side level by the operational amplifier 50. Thereby, even if the noise ns is added to the detected signal S near the zero crossing and the zero crossing is forcibly performed, by comparing the signal forming circuit 51, the level of the comparison signal h is relative to the detected signal. Since S is operated in a positive or negative opposite manner, the zero-crossing detection signal fa outputted from the operational amplifier 50 is not inverted by the noise ns, and erroneous detection of zero-crossing does not occur. Thereafter, the comparison signal h follows the time constant T and its level slowly decreases, reaching the zero level before the next zero crossing time t3. When the detected signal S is zero-crossed again at time t3, the zero-crossing detection signal fa output from the operational amplifier 50 is inverted to become a low level. At this time, the low-level zero-crossing detection signal fa, that is, the voltage -Vdd is given to the capacitor Ca, so that a voltage c of -2 Vdd appears at the other end of the capacitor Ca. This voltage c is divided by the resistor R10 and the resistor R11, and supplied as a comparison signal h to the non-inverting input terminal of the operational amplifier 50. The above action is performed whenever a change in the positive and negative levels of the detected signal occurs to output a zero-crossing detection signal fa. Therefore, a zero-crossing detection signal in which erroneous detection, that is, chattering, does not occur even if zero crossing due to noise occurs occurs.
[專利文獻1]日本專利特開昭63-75670號公報 [Patent Document 1] Japanese Patent Laid-Open Publication No. SHO 63-75670
然而,於習知的零交越檢測電路中,如上所述般構成為僅在由電阻與電容所定義的時間常數T所決定的時間期間消除雜訊所引起的零交越的影響,從而存在以下課題:於在較時間常數T所決定的時間短的時間內被檢測訊號S重複進行零交越的情況下,無法檢測被檢測訊號S的零交越點。因此,例如於無刷馬達中的使用中,無法應對對高速旋轉的要求,存在因零交越檢測電路而無刷馬達的旋轉速度被限速的課題。另外,若以時間常數T變短的方式選擇電阻與電容的值,則存在無法消除雜訊的課題。因此,例如於無刷馬達中,存在因雜訊而零交越檢測電路進行誤輸出,無法達成準確的旋轉控制的課題。 However, in the conventional zero-crossing detection circuit, as described above, the effect of zero-crossing caused by noise is eliminated only during the time period determined by the time constant T defined by the resistance and the capacitance, so that there is The following problem is that, when the detection signal S is repeatedly zero-crossed in a time shorter than the time determined by the time constant T, the zero-crossing point of the detected signal S cannot be detected. Therefore, for example, in the use of the brushless motor, the requirement for high-speed rotation cannot be coped with, and there is a problem that the rotational speed of the brushless motor is limited by the zero-crossing detection circuit. Further, if the values of the resistor and the capacitor are selected such that the time constant T becomes shorter, there is a problem that noise cannot be eliminated. Therefore, for example, in the brushless motor, there is a problem that the zero-crossing detection circuit performs erroneous output due to noise, and accurate rotation control cannot be achieved.
為了解決習知的此種問題點,本發明的零交越檢測電路設為以下構成。 In order to solve such a problem, the zero crossover detecting circuit of the present invention has the following configuration.
本發明的零交越檢測電路具備輸入有第一輸入訊號與第二輸入訊號的第一比較電路、輸入有第一輸入訊號與第二輸入訊號且具有磁滯功能的第二比較電路以及邏輯電路,且為具備以下單元的構成:所述單元中,第一比較電路輸出第一輸入訊號與第二輸入訊號的零交越檢測結果,第二比較電路輸出第一輸入訊號與第二輸入訊號的比較結果,邏輯電路基於零交越檢測結果與 比較結果而決定輸出。 The zero-crossing detection circuit of the present invention includes a first comparison circuit having a first input signal and a second input signal, a second comparison circuit having a first input signal and a second input signal and having a hysteresis function, and a logic circuit And the configuration is as follows: in the unit, the first comparison circuit outputs a zero-crossing detection result of the first input signal and the second input signal, and the second comparison circuit outputs the first input signal and the second input signal. Comparing the results, the logic circuit is based on the zero crossing detection result and The output is determined by comparing the results.
根據本發明的零交越檢測電路,可高精度地檢測所輸入的訊號由正切換為負、以及由負切換為正的零交越點,且可消除由雜訊引起的零交越的影響,並且能夠以相對較小的電路規模以及簡便的構成來實現零交越檢測電路。不僅可應用於所列舉的無刷馬達,亦可廣泛地應用於感測輸出等通常的訊號的零交越點檢測。 According to the zero-crossing detecting circuit of the present invention, it is possible to accurately detect that the input signal is switched from positive to negative, and from negative to positive zero-crossing point, and the effect of zero-crossing caused by noise can be eliminated. And the zero-crossing detection circuit can be realized with a relatively small circuit scale and a simple configuration. It can be applied not only to the brushless motors listed, but also widely used for zero crossing point detection of normal signals such as sensing outputs.
1a、1b、1c‧‧‧霍耳元件 1a, 1b, 1c‧‧‧Horse components
2a、2b、2c‧‧‧差動放大電路/差動放大器 2a, 2b, 2c‧‧‧Differential Amplifying Circuit / Differential Amplifier
10、11、12、13、14、15‧‧‧比較電路 10, 11, 12, 13, 14, 15‧‧‧ comparison circuits
20‧‧‧邏輯電路 20‧‧‧Logical circuits
30‧‧‧鎖存電路 30‧‧‧Latch circuit
40‧‧‧磁滯產生電路 40‧‧‧hysteresis generating circuit
50‧‧‧運算放大器 50‧‧‧Operational Amplifier
51‧‧‧比較訊號形成電路 51‧‧‧Comparative signal forming circuit
Aa、Ab、Ac、Cb、Cc、Ba、Da、Bb、Db、Bc、Dc‧‧‧端子 Aa, Ab, Ac, Cb, Cc, Ba, Da, Bb, Db, Bc, Dc‧‧‧ terminals
c、Vdd‧‧‧電壓 c, Vdd‧‧‧ voltage
C‧‧‧時脈端子 C‧‧‧clock terminal
Ca‧‧‧電容/電容器 Ca‧‧‧Capacitor/Capacitor
CK1、CK2、CK3‧‧‧時脈訊號 CK1, CK2, CK3‧‧‧ clock signal
D‧‧‧資料輸入端子 D‧‧‧ data input terminal
fa‧‧‧零交越檢測訊號 Fa‧‧‧ zero crossing detection signal
h‧‧‧比較訊號 h‧‧‧Comparative signal
HC‧‧‧控制端子/磁滯控制端子 HC‧‧‧Control terminal/hysteresis control terminal
Hi‧‧‧高位準 Hi‧‧‧ high standard
Lo‧‧‧低位準 Lo‧‧‧low standard
LT1、LT2、LT3‧‧‧鎖存器 LT1, LT2, LT3‧‧‧ latches
ns‧‧‧雜訊 Ns‧‧‧ noise
N1、N2‧‧‧輸入端子 N1, N2‧‧‧ input terminals
N2’‧‧‧連接點 N2’‧‧‧ connection point
out、out0、out1、out2、out3、out4、out5‧‧‧輸出端子 Out, out0, out1, out2, out3, out4, out5‧‧‧ output terminals
Q‧‧‧資料輸出端子 Q‧‧‧ data output terminal
R10、R11‧‧‧電阻 R10, R11‧‧‧ resistance
S‧‧‧被檢測訊號 S‧‧‧Detected signal
t‧‧‧時間經過 t‧‧‧Time passes
t1、t2、t3‧‧‧時刻 T1, t2, t3‧‧‧ moments
Vn1、Vn2‧‧‧輸入電壓 Vn1, Vn2‧‧‧ input voltage
Vn2-Vn1‧‧‧輸入電壓差 Vn2-Vn1‧‧‧ input voltage difference
Vout‧‧‧輸出電壓/電壓 Vout‧‧‧ output voltage / voltage
Vout0、Vout1、Vout4、Vout5‧‧‧輸出電壓 Vout0, Vout1, Vout4, Vout5‧‧‧ output voltage
Vout2‧‧‧比較電路12的輸出電壓 Vout2‧‧‧Compare circuit 12 output voltage
Vout3‧‧‧比較電路13的輸出電壓 Vout3‧‧‧Compare circuit 13 output voltage
Vth1、Vth2、Vn2’‧‧‧電壓 Vth1, Vth2, Vn2'‧‧‧ voltage
圖1為第1實施形態的零交越檢測電路的電路圖。 Fig. 1 is a circuit diagram of a zero-crossing detecting circuit of the first embodiment.
圖2為表示第1實施形態的零交越檢測電路的各要素的動作的圖。 Fig. 2 is a view showing the operation of each element of the zero-crossing detecting circuit of the first embodiment;
圖3為表示第1實施形態的零交越檢測電路的動作的圖。 Fig. 3 is a view showing the operation of the zero-crossing detecting circuit of the first embodiment;
圖4為第1實施形態的零交越檢測電路的另一例的圖。 Fig. 4 is a view showing another example of the zero-crossing detecting circuit of the first embodiment.
圖5為表示第1實施形態的零交越檢測電路的另一例的各要素的動作的圖。 Fig. 5 is a view showing the operation of each element of another example of the zero-crossing detecting circuit of the first embodiment.
圖6為第2實施形態的零交越檢測電路的電路圖。 Fig. 6 is a circuit diagram of a zero-crossing detecting circuit of the second embodiment.
圖7為第3實施形態的零交越檢測電路的電路圖。 Fig. 7 is a circuit diagram of a zero-crossing detecting circuit of the third embodiment.
圖8為將第1實施形態的零交越檢測電路應用於磁力感測裝置的第1應用例的電路圖。 Fig. 8 is a circuit diagram showing a first application example in which the zero-crossing detection circuit of the first embodiment is applied to a magnetic force sensing device.
圖9為將第1實施形態的零交越檢測電路應用於磁力感測裝 置的第2應用例的電路圖。 Fig. 9 is a view showing the zero crossover detecting circuit of the first embodiment applied to a magnetic sensing device A circuit diagram of a second application example.
圖10為將第2實施形態的零交越檢測電路應用於磁力感測裝置的第3應用例的電路圖。 Fig. 10 is a circuit diagram showing a third application example in which the zero-crossing detecting circuit of the second embodiment is applied to a magnetic force sensing device.
圖11為將第3實施形態的零交越檢測電路應用於磁力感測裝置的第4應用例的電路圖。 Fig. 11 is a circuit diagram showing a fourth application example in which the zero-crossing detecting circuit of the third embodiment is applied to a magnetic force sensing device.
圖12為習知的零交越檢測電路的電路圖。 Figure 12 is a circuit diagram of a conventional zero crossover detection circuit.
圖13為表示習知的零交越檢測電路的動作的圖。 Fig. 13 is a view showing the operation of a conventional zero-crossing detecting circuit.
本發明的零交越檢測電路可作為半導體電路中的零交越檢測電路而被廣泛利用。以下,參照圖式對本發明的零交越檢測電路進行說明。 The zero-crossing detection circuit of the present invention can be widely utilized as a zero-crossing detection circuit in a semiconductor circuit. Hereinafter, the zero-crossing detecting circuit of the present invention will be described with reference to the drawings.
<第1實施形態> <First embodiment>
圖1為第1實施形態的零交越檢測電路的電路圖。第1實施形態的零交越檢測電路包括比較電路10、比較電路11以及邏輯電路20。 Fig. 1 is a circuit diagram of a zero-crossing detecting circuit of the first embodiment. The zero-crossing detection circuit of the first embodiment includes a comparison circuit 10, a comparison circuit 11, and a logic circuit 20.
比較電路10具有兩個輸入端子與一個輸出端子,詳細而言,具有反相輸入端子、非反相輸入端子以及輸出端子out0。另外,比較電路11具有兩個輸入端子與一個輸出端子,詳細而言,具有反相輸入端子、非反相輸入端子以及輸出端子out1。比較電路10的反相輸入端子與比較電路11的反相輸入端子由輸入端子N1共同連接。比較電路10的非反相輸入端子與比較電路11的非反相輸入端子由輸入端子N2共同連接。對輸入端子N1與輸入端 子N2分別供給第一輸入訊號與第二輸入訊號。比較電路10的輸出端子out0與比較電路11的輸出端子out1連接於邏輯電路20。邏輯電路20將輸出端子out0的訊號與輸出端子out1的訊號作為輸入,並自輸出端子out輸出邏輯演算結果。在以下的說明中,將輸入端子N1、輸入端子N2、輸出端子out0、輸出端子out1、輸出端子out的各電壓分別設為輸入電壓Vn1、輸入電壓Vn2、輸出電壓Vout0、輸出電壓Vout1、輸出電壓Vout。 The comparison circuit 10 has two input terminals and one output terminal, and specifically has an inverting input terminal, a non-inverting input terminal, and an output terminal out0. Further, the comparison circuit 11 has two input terminals and one output terminal, and specifically has an inverting input terminal, a non-inverting input terminal, and an output terminal out1. The inverting input terminal of the comparison circuit 10 and the inverting input terminal of the comparison circuit 11 are commonly connected by the input terminal N1. The non-inverting input terminal of the comparison circuit 10 and the non-inverting input terminal of the comparison circuit 11 are commonly connected by the input terminal N2. For input terminal N1 and input Sub-N2 supplies the first input signal and the second input signal, respectively. The output terminal out0 of the comparison circuit 10 and the output terminal out1 of the comparison circuit 11 are connected to the logic circuit 20. The logic circuit 20 takes the signal of the output terminal out0 and the signal of the output terminal out1 as inputs, and outputs a logical calculation result from the output terminal out. In the following description, the respective voltages of the input terminal N1, the input terminal N2, the output terminal out0, the output terminal out1, and the output terminal out are set as the input voltage Vn1, the input voltage Vn2, the output voltage Vout0, the output voltage Vout1, and the output voltage. Vout.
繼而,使用圖2及圖3對第1實施形態的零交越檢測電路的動作進行說明。 Next, the operation of the zero-crossing detecting circuit of the first embodiment will be described with reference to Figs. 2 and 3 .
首先,對比較電路10的動作進行說明。比較電路10以如下方式動作:當供給至非反相輸入端子的電壓高於供給至反相輸入端子的電壓時,自輸出端子out0輸出高位準,與此相反地,當供給至非反相輸入端子的電壓低於供給至反相輸入端子的電壓時,自輸出端子out0輸出低位準。將該動作的詳情示於圖2的(a)。此處,橫軸表示輸入電壓Vn1與輸入電壓Vn2的輸入電壓差,縱軸表示各輸出電壓。如圖2的(a)所示,輸出電壓Vout0在輸入電壓Vn2高於輸入電壓Vn1時、即Vn2-Vn1>0時輸出高位準。與此相反地,在輸入電壓Vn2低於輸入電壓Vn1時、即Vn2-Vn1<0時,輸出低位準。輸出電壓Vout0自高位準向低位準的遷移於Vn2-Vn1=0處進行。另外,輸出電壓Vout0自低位準向高位準的遷移同樣地於Vn2-Vn1=0處進行。 First, the operation of the comparison circuit 10 will be described. The comparison circuit 10 operates in such a manner that when the voltage supplied to the non-inverting input terminal is higher than the voltage supplied to the inverting input terminal, the high level is output from the output terminal out0, and conversely, when supplied to the non-inverting input When the voltage of the terminal is lower than the voltage supplied to the inverting input terminal, the low level is output from the output terminal out0. The details of this operation are shown in (a) of Fig. 2 . Here, the horizontal axis represents the input voltage difference between the input voltage Vn1 and the input voltage Vn2, and the vertical axis represents the respective output voltages. As shown in (a) of FIG. 2, the output voltage Vout0 outputs a high level when the input voltage Vn2 is higher than the input voltage Vn1, that is, when Vn2-Vn1>0. Conversely, when the input voltage Vn2 is lower than the input voltage Vn1, that is, when Vn2-Vn1 < 0, the low level is output. The transition of the output voltage Vout0 from the high level to the low level is performed at Vn2-Vn1=0. Further, the transition of the output voltage Vout0 from the low level to the high level is performed similarly at Vn2-Vn1=0.
另外,將輸入電壓差Vn2-Vn1發生時間變化的情況下的 比較電路10的動作示於圖3的(a)及圖3的(b)。此處,橫軸表示時間經過,縱軸表示輸入電壓差或輸出電壓。圖3的(a)表示輸入電壓差Vn2-Vn1根據時間而變化的情況。輸入電壓差Vn2-Vn1隨時間變化而可取各種值。尤其將成為Vn2-Vn1=0時表現為零交越。圖3的(b)表示輸出電壓Vout0隨輸入電壓差Vn2-Vn1的時間變化而變化的情況。如圖3的(b)所示,輸出電壓Vout0在Vn2-Vn1>0時輸出高位準,在Vn2-Vn1<0時輸出低位準。在Vn2-Vn1=0時、即Vn1=Vn2時,輸出電壓Vout0進行零交越檢測。 In addition, when the input voltage difference Vn2-Vn1 changes in time, The operation of the comparison circuit 10 is shown in (a) of FIG. 3 and (b) of FIG. Here, the horizontal axis represents time passage, and the vertical axis represents input voltage difference or output voltage. (a) of FIG. 3 shows a case where the input voltage difference Vn2-Vn1 changes according to time. The input voltage difference Vn2-Vn1 can take various values as a function of time. In particular, it will become zero crossover when Vn2-Vn1=0. (b) of FIG. 3 shows a case where the output voltage Vout0 changes with time variation of the input voltage difference Vn2-Vn1. As shown in (b) of FIG. 3, the output voltage Vout0 outputs a high level when Vn2-Vn1>0, and outputs a low level when Vn2-Vn1<0. When Vn2-Vn1=0, that is, Vn1=Vn2, the output voltage Vout0 performs zero-crossing detection.
繼而,對比較電路11的動作進行說明。比較電路11以如下方式動作:當供給至非反相輸入端子的電壓高於供給至反相輸入端子的電壓與電壓Vth1的和時,自輸出端子out1輸出高位準,與此相反地,當供給至非反相輸入端子的電壓低於供給至反相輸入端子的電壓與電壓Vth2的和時,自輸出端子out1輸出低位準。將該動作的詳情示於圖2的(b)。如圖2的(b)所示,輸出電壓Vout1在輸入電壓Vn2高於輸入電壓Vn1與電壓Vth1的和時、即Vn2-Vn1>Vth1時輸出高位準,在輸入電壓Vn2低於輸入電壓Vn1與電壓Vth2的和時、即Vn2-Vn1<Vth2時輸出低位準。此處,電壓Vth1為正值且表示正數側的磁滯值,電壓Vth2為負值且表示負數側的磁滯值。輸出電壓Vout1自高位準向低位準的遷移於Vn2-Vn1=Vth2處進行。另外,輸出電壓Vout1自低位準向高位準的遷移於Vn2-Vn1=Vth1處進行。當Vn2-Vn1為Vth1與Vth2之間時,根據緊跟在前的狀態而輸出高位準或低位準。即, 比較電路11作為具有磁滯寬度|Vth1|+|Vth2|的比較電路而動作。 Next, the operation of the comparison circuit 11 will be described. The comparison circuit 11 operates in such a manner that when the voltage supplied to the non-inverting input terminal is higher than the sum of the voltage supplied to the inverting input terminal and the voltage Vth1, the high level is output from the output terminal out1, and conversely, when supplied When the voltage to the non-inverting input terminal is lower than the sum of the voltage supplied to the inverting input terminal and the voltage Vth2, the low level is output from the output terminal out1. The details of this operation are shown in (b) of FIG. 2 . As shown in (b) of FIG. 2, the output voltage Vout1 outputs a high level when the input voltage Vn2 is higher than the sum of the input voltage Vn1 and the voltage Vth1, that is, Vn2-Vn1>Vth1, and the input voltage Vn2 is lower than the input voltage Vn1 and The sum of the voltage Vth2, that is, Vn2-Vn1 < Vth2, outputs a low level. Here, the voltage Vth1 is a positive value and represents a hysteresis value on the positive side, and the voltage Vth2 is a negative value and represents a hysteresis value on the negative side. The transition of the output voltage Vout1 from the high level to the low level is performed at Vn2-Vn1=Vth2. In addition, the transition of the output voltage Vout1 from the low level to the high level is performed at Vn2-Vn1=Vth1. When Vn2-Vn1 is between Vth1 and Vth2, a high level or a low level is output according to the immediately preceding state. which is, The comparison circuit 11 operates as a comparison circuit having a hysteresis width |Vth1|+|Vth2|.
另外,將輸入電壓差Vn2-Vn1發生時間變化的情況下的比較電路11的動作示於圖3的(a)及圖3的(c)。圖3的(c)表示輸出電壓Vout1隨圖3的(a)所示的輸入電壓差Vn2-Vn1的時間變化而變化的情況。當為時刻t1時、即Vn2-Vn1>Vth1時,輸出電壓Vout1輸出高位準,於其後的時間經過後亦維持高位準,隨著Vn2-Vn1的減小,當成為Vn2-Vn1<Vth2時,自高位準遷移為低位準的輸出,於其後的時間經過後亦維持低位準,隨著Vn2-Vn1的增大,當成為Vn2-Vn1>Vth1時,自低位準遷移為高位準。 In addition, the operation of the comparison circuit 11 when the input voltage difference Vn2-Vn1 changes temporally is shown in (a) of FIG. 3 and (c) of FIG. (c) of FIG. 3 shows a case where the output voltage Vout1 changes with time variation of the input voltage difference Vn2-Vn1 shown in (a) of FIG. When it is time t1, that is, Vn2-Vn1>Vth1, the output voltage Vout1 outputs a high level, and maintains a high level after the lapse of the subsequent time, and becomes Vn2-Vn1<Vth2 as Vn2-Vn1 decreases. The output from the high level to the low level is maintained at a low level after the elapse of time. As Vn2-Vn1 increases, when Vn2-Vn1>Vth1, the low level shifts to a high level.
繼而,對邏輯電路20的動作進行說明。邏輯電路20以如下方式動作:根據輸出電壓Vout0與輸出電壓Vout1的邏輯狀態來決定輸出電壓Vout的邏輯。更詳細而言,邏輯電路20在Vout1為高位準時,藉由Vout0自高位準向低位準的遷移而使Vout自高位準遷移為低位準。若Vout原本為低位準,則Vout不發生變化。Vout不會因Vout0自低位準向高位準的遷移而發生變化。另外,在Vout1為低位準時,藉由Vout0自低位準向高位準的遷移而使Vout自低位準遷移為高位準。若Vout原本為高位準,則Vout不發生變化。Vout不會因Vout0自高位準向低位準的遷移而發生變化。使用圖3對以上動作進行說明。 Next, the operation of the logic circuit 20 will be described. The logic circuit 20 operates in such a manner as to determine the logic of the output voltage Vout based on the logic state of the output voltage Vout0 and the output voltage Vout1. In more detail, when Vout1 is at a high level, logic circuit 20 shifts Vout from a high level to a low level by shifting Vout0 from a high level to a low level. If Vout is originally low, Vout does not change. Vout does not change due to the transition of Vout0 from a low level to a high level. In addition, when Vout1 is low, Vout transitions from a low level to a high level by Vout0 moving from a low level to a high level. If Vout is originally at a high level, Vout does not change. Vout does not change due to the transition of Vout0 from a high level to a low level. The above operation will be described using FIG. 3.
如上文所述,圖3的(a)、圖3的(b)、圖3的(c)分別表示輸入電壓差Vn2-Vn1、輸出電壓Vout0、輸出電壓Vout1 的時間變化。圖3的(d)表示輸出電壓Vout的時間變化。 As described above, (a) of FIG. 3, (b) of FIG. 3, and (c) of FIG. 3 indicate input voltage difference Vn2-Vn1, output voltage Vout0, and output voltage Vout1, respectively. Time changes. (d) of FIG. 3 shows a temporal change of the output voltage Vout.
於圖3的(a)~圖3的(d)中,當為時刻t1時,輸出電壓Vout0與輸出電壓Vout1為高位準。其後,時間經過而Vn2-Vn1減小,且在進行了零交越時Vout0自高位準遷移為低位準。此時,Vout1為高位準,因此邏輯電路20將Vout0的自高位準向低位準的零交越的檢測輸出至Vout。其後,若時間經過而成為Vn2-Vn1<Vth2,則Vout1自高位準遷移為低位準。其後,時間經過而Vn2-Vn1增大,且在進行了零交越時Vout0自低位準遷移為高位準。此時,Vout1為低位準,因此邏輯電路20將Vout0的自低位準向高位準的零交越的檢測輸出至Vout。其後,若時間經過而成為Vn2-Vn1>Vth1,則Vout1自低位準遷移為高位準。進而,其後,當時間經過而為時刻t2時,成為與時刻t1相同的狀態。 In (a) to (d) of FIG. 3, when the time is t1, the output voltage Vout0 and the output voltage Vout1 are at a high level. Thereafter, the time passes and Vn2-Vn1 decreases, and Vout0 shifts from a high level to a low level when zero crossing is performed. At this time, Vout1 is at a high level, and therefore the logic circuit 20 outputs a detection of Vout0 from a high level to a low level zero crossing to Vout. Thereafter, if Vn2-Vn1 < Vth2 is passed after the passage of time, Vout1 shifts from a high level to a low level. Thereafter, the time passes and Vn2-Vn1 increases, and Vout0 migrates from a low level to a high level when zero crossing is performed. At this time, Vout1 is at a low level, so the logic circuit 20 outputs a detection of Vout0 from a low level to a high level zero crossing to Vout. Thereafter, if Vn2-Vn1>Vth1 is reached after the elapse of time, Vout1 shifts from a low level to a high level. Further, thereafter, when the time elapses and the time t2 is reached, the same state as the time t1 is obtained.
當為時刻t2時,輸出電壓Vout0與輸出電壓Vout1為高位準。其後,時間經過而Vn2-Vn1減小,且在進行了零交越時Vout0自高位準遷移為低位準。此時,Vout1為高位準,因此邏輯電路20將Vout0的自高位準向低位準的零交越的檢測輸出至Vout。其後,時間經過,Vn2-Vn1因雜訊ns而進行兩次零交越,輸出電壓Vout0在自低位準遷移為高位準後進而遷移為低位準。此時,Vout1為高位準,因此邏輯電路20以不將Vout0的自低位準向高位準的遷移輸出至Vout的方式動作。因此,由雜訊引起的零交越檢測不會出現於輸出端子out。進而,若時間經過而成為Vn2-Vn1<Vth2,則Vout1自高位準遷移為低位準。其後,時間經過而Vn2-Vn1增 大,且在進行了零交越時Vout0自低位準遷移為高位準。此時,Vout1為低位準,因此邏輯電路20將Vout0的自低位準向高位準的零交越的檢測輸出至Vout。其後,時間經過,Vn2-Vn1因雜訊ns而進行兩次零交越,輸出電壓Vout0在自高位準遷移為低位準後進而遷移為高位準。此時,Vout1為低位準,因此以不將Vout0的自高位準向低位準的遷移輸出至Vout的方式動作。因此,由雜訊引起的零交越檢測不會出現於輸出端子out。其後,若時間經過而成為Vn2-Vn1>Vth1,則Vout1自低位準遷移為高位準。進而,其後,當時間經過而為時刻t3時,成為與時刻t1及時刻t2相同的狀態。 When it is time t2, the output voltage Vout0 and the output voltage Vout1 are at a high level. Thereafter, the time passes and Vn2-Vn1 decreases, and Vout0 shifts from a high level to a low level when zero crossing is performed. At this time, Vout1 is at a high level, and therefore the logic circuit 20 outputs a detection of Vout0 from a high level to a low level zero crossing to Vout. Thereafter, after the time elapses, Vn2-Vn1 performs two zero crossings due to the noise ns, and the output voltage Vout0 migrates from the low level to the high level and then migrates to the low level. At this time, since Vout1 is at the high level, the logic circuit 20 operates so as not to output the transition from the low level to the high level of Vout0. Therefore, zero-crossing detection caused by noise does not occur at the output terminal out. Further, when Vn2-Vn1 < Vth2 is passed as time elapses, Vout1 shifts from a high level to a low level. Thereafter, the time passes and Vn2-Vn1 increases. Large, and Vout0 migrates from a low level to a high level when zero crossing occurs. At this time, Vout1 is at a low level, so the logic circuit 20 outputs a detection of Vout0 from a low level to a high level zero crossing to Vout. Thereafter, after the time elapses, Vn2-Vn1 performs two zero crossings due to the noise ns, and the output voltage Vout0 migrates to a high level after moving from the high level to the low level. At this time, since Vout1 is at a low level, the operation is performed such that the transition from the high level to the low level of Vout0 is not outputted to Vout. Therefore, zero-crossing detection caused by noise does not occur at the output terminal out. Thereafter, if Vn2-Vn1>Vth1 is reached after the elapse of time, Vout1 shifts from a low level to a high level. Further, thereafter, when the time elapses and the time t3 is reached, the same state as the time t1 and the time t2 is obtained.
藉由以上內容對第1實施形態的零交越檢測電路的動作進行了說明,且示出了以下情況:可進行零交越檢測並且可消除由雜訊引起的零交越的影響,能夠以簡便的電路構成獲得高精度的零交越檢測結果。若在無刷馬達中使用本實施形態的零交越檢測電路,則可應對對高速旋轉的要求。亦不會發生習知的於應對高速化時成為課題的由雜訊引起的誤輸出,而可實現準確的旋轉控制。 The operation of the zero-crossing detection circuit of the first embodiment has been described above, and the following cases are shown: zero-crossing detection can be performed and the influence of zero-crossing caused by noise can be eliminated, and The simple circuit configuration achieves high-precision zero-crossing detection results. When the zero-crossing detection circuit of this embodiment is used in a brushless motor, it is possible to cope with the demand for high-speed rotation. There is no known erroneous output caused by noise in order to cope with the problem of high speed, and accurate rotation control can be realized.
於本說明中,將電壓Vth1與電壓Vth2作為比較電路11的磁滯電壓進行了說明,但亦可如圖4的電路圖及圖5的動作圖所示,將比較電路11分為比較電路12與比較電路13,藉由比較電路12來判別Vn2-Vn1是大於抑或小於電壓Vth1,藉由比較電路13來判別Vn2-Vn1是大於抑或小於電壓Vth2。此處,圖5的 (a)表示比較電路10的動作,圖5的(b)表示比較電路12的動作,圖5的(c)表示比較電路13的動作,圖5的(d)表示邏輯電路20的動作。 In the present description, the voltage Vth1 and the voltage Vth2 are used as the hysteresis voltage of the comparison circuit 11. However, as shown in the circuit diagram of FIG. 4 and the operation diagram of FIG. 5, the comparison circuit 11 may be divided into the comparison circuit 12 and The comparison circuit 13 determines whether Vn2-Vn1 is greater than or less than the voltage Vth1 by the comparison circuit 12, and the comparison circuit 13 determines whether Vn2-Vn1 is greater than or less than the voltage Vth2. Here, Figure 5 (a) shows the operation of the comparison circuit 10, (b) of FIG. 5 shows the operation of the comparison circuit 12, (c) of FIG. 5 shows the operation of the comparison circuit 13, and (d) of FIG. 5 shows the operation of the logic circuit 20.
<第2實施形態> <Second embodiment>
圖6為第2實施形態的零交越檢測電路的電路圖。與圖1所示的第1實施形態的不同在於:去除了比較電路10與比較電路11,追加了比較電路14,且在比較電路14與邏輯電路20之間追加了鎖存電路30。所追加的要素如下所述般構成、連接。另外,由於所去除的要素,以下連接與第1實施形態不同。 Fig. 6 is a circuit diagram of a zero-crossing detecting circuit of the second embodiment. The difference from the first embodiment shown in FIG. 1 is that the comparison circuit 10 and the comparison circuit 11 are removed, the comparison circuit 14 is added, and the latch circuit 30 is added between the comparison circuit 14 and the logic circuit 20. The added elements are configured and connected as described below. Further, the following connections are different from the first embodiment due to the removed elements.
比較電路14具有兩個輸入端子、一個輸出端子以及一個控制端子HC。詳細而言,具有反相輸入端子、非反相輸入端子、輸出端子out4以及磁滯控制端子HC。比較電路14的反相輸入端子連接於輸入端子N1,比較電路14的非反相輸入端子連接於輸入端子N2。比較電路14的磁滯控制端子HC根據輸入至磁滯控制端子的控制訊號來調整比較電路14的磁滯電壓。磁滯控制端子HC的控制電路未圖示。比較電路14的輸出端子out4連接於鎖存電路30。鎖存電路30包括鎖存器LT1、鎖存器LT2、鎖存器LT3,輸出端子out4連接於鎖存器LT1、鎖存器LT2、鎖存器LT3的資料輸入端子D。鎖存器LT1、鎖存器LT2、鎖存器LT3的資料輸出端子Q分別為輸出端子out0、輸出端子out2、輸出端子out3,且與圖4所示的第1實施形態相同地連接於邏輯電路20。鎖存器LT1、鎖存器LT2、鎖存器LT3具備時脈端子C,分別根據時脈訊 號CK1、時脈訊號CK2、時脈訊號CK3將輸入至資料輸入端子D的資料鎖存並輸出至資料輸出端子Q。時脈訊號CK1、時脈訊號CK2、時脈訊號CK3的控制電路未圖示。關於其他的連接及構成與第1實施形態相同。在以下的說明中,將輸出端子out4的電壓設為輸出電壓Vout4。 The comparison circuit 14 has two input terminals, one output terminal, and one control terminal HC. Specifically, it has an inverting input terminal, a non-inverting input terminal, an output terminal out4, and a hysteresis control terminal HC. The inverting input terminal of the comparison circuit 14 is connected to the input terminal N1, and the non-inverting input terminal of the comparison circuit 14 is connected to the input terminal N2. The hysteresis control terminal HC of the comparison circuit 14 adjusts the hysteresis voltage of the comparison circuit 14 in accordance with the control signal input to the hysteresis control terminal. The control circuit of the hysteresis control terminal HC is not shown. The output terminal out4 of the comparison circuit 14 is connected to the latch circuit 30. The latch circuit 30 includes a latch LT1, a latch LT2, and a latch LT3. The output terminal out4 is connected to the data input terminal D of the latch LT1, the latch LT2, and the latch LT3. The data output terminals Q of the latch LT1, the latch LT2, and the latch LT3 are the output terminal out0, the output terminal out2, and the output terminal out3, respectively, and are connected to the logic circuit in the same manner as the first embodiment shown in FIG. 20. The latch LT1, the latch LT2, and the latch LT3 are provided with the clock terminal C, respectively according to the time pulse signal. The signal CK1, the clock signal CK2, and the clock signal CK3 latch the data input to the data input terminal D and output it to the data output terminal Q. The control circuit of the clock signal CK1, the clock signal CK2, and the clock signal CK3 is not shown. Other connections and configurations are the same as in the first embodiment. In the following description, the voltage of the output terminal out4 is set to the output voltage Vout4.
繼而,對第2實施形態的零交越檢測電路的動作進行說明。 Next, the operation of the zero-crossing detection circuit of the second embodiment will be described.
比較電路14以如下方式動作:根據輸入至磁滯控制端子HC的控制訊號,分時地進行第1實施形態的比較電路10與比較電路11的動作。即,若以電壓Vth1與電壓Vth2成為零的方式控制比較電路14,則比較電路14以與比較電路10相同的方式動作,若以電壓Vth1與電壓Vth2不成為零的方式進行控制,則比較電路14以與比較電路12或比較電路13相同的方式動作。關於進行此種動作的比較電路,因是公知技術,故省略說明。若在比較電路14以與比較電路10相同的方式受到控制的狀態下,根據時脈訊號CK1藉由鎖存器LT1來鎖存比較電路14的輸出電壓Vout4,則輸出電壓Vout0成為與圖5的(a)及圖3的(b)所示的Vout0相同的輸出電壓。若在比較電路14以與比較電路12、比較電路13相同的方式受到控制的狀態下,根據時脈訊號CK2、時脈訊號CK3藉由鎖存器LT2、鎖存器LT3來鎖存比較電路14的輸出電壓Vout4,則輸出電壓Vout1成為與圖5的(b)、圖5的(c)及圖3的(c)所示的Vout1相同的輸出電壓。邏輯電路20的動作與第1 實施形態相同,輸出電壓Vout可進行零交越檢測,並且可消除由雜訊引起的零交越的影響。 The comparison circuit 14 operates to perform the operations of the comparison circuit 10 and the comparison circuit 11 of the first embodiment in a time-division manner based on the control signal input to the hysteresis control terminal HC. In other words, when the comparison circuit 14 is controlled such that the voltage Vth1 and the voltage Vth2 become zero, the comparison circuit 14 operates in the same manner as the comparison circuit 10, and if the voltage Vth1 and the voltage Vth2 are not zero, the comparison circuit is controlled. 14 operates in the same manner as the comparison circuit 12 or the comparison circuit 13. Since the comparison circuit for performing such an operation is a well-known technique, description is abbreviate|omitted. If the comparison circuit 14 is controlled in the same manner as the comparison circuit 10, the output voltage Vout4 of the comparison circuit 14 is latched by the latch LT1 according to the clock signal CK1, and the output voltage Vout0 becomes the same as that of FIG. (a) The same output voltage as Vout0 shown in (b) of Fig. 3 . If the comparison circuit 14 is controlled in the same manner as the comparison circuit 12 and the comparison circuit 13, the comparison circuit 14 is latched by the clock signal CK2 and the clock signal CK3 by the latch LT2 and the latch LT3. When the output voltage Vout4 is reached, the output voltage Vout1 becomes the same output voltage as Vout1 shown in (b) of FIG. 5, (c) of FIG. 5, and (c) of FIG. The action of the logic circuit 20 and the first In the same embodiment, the output voltage Vout can perform zero-crossing detection and eliminate the effects of zero-crossing caused by noise.
第2實施形態中,使比較電路14分時動作,因此相對於第1實施形態而動作速度變慢,但具有藉由減少比較電路的數量而電路規模變小的優點。 In the second embodiment, since the comparison circuit 14 operates in a time-division manner, the operation speed is slower than that of the first embodiment, but there is an advantage that the circuit scale is reduced by reducing the number of comparison circuits.
藉由以上內容對第2實施形態的零交越檢測電路的動作進行了說明,且與第1實施形態同樣地示出了以下情況:可進行零交越檢測並且可消除由雜訊引起的零交越的影響,能夠以簡便的電路構成獲得高精度的零交越檢測結果。 The operation of the zero-crossing detection circuit of the second embodiment has been described above, and similarly to the first embodiment, it is possible to perform zero-crossing detection and eliminate zero caused by noise. With the influence of crossover, high-precision zero-crossing detection results can be obtained with a simple circuit configuration.
<第3實施形態> <Third embodiment>
圖7為第3實施形態的零交越檢測電路的電路圖。與圖6所示的第2實施形態的不同在於:去除了比較電路14而追加了比較電路15,且在輸入端子N2與比較電路15的非反相輸入端子之間追加了磁滯產生電路40。所追加的要素以如下方式構成、連接。另外,由於所去除的要素,以下連接與第2實施形態不同。 Fig. 7 is a circuit diagram of a zero-crossing detecting circuit of the third embodiment. The difference from the second embodiment shown in FIG. 6 is that the comparison circuit 15 is added to the comparison circuit 14, and the hysteresis generation circuit 40 is added between the input terminal N2 and the non-inverting input terminal of the comparison circuit 15. . The added elements are configured and connected as follows. Further, the following connections are different from the second embodiment due to the removed elements.
比較電路15具有兩個輸入端子與一個輸出端子,詳細而言,具有反相輸入端子、非反相輸入端子以及輸出端子out5。比較電路15的反相輸入端子連接於輸入端子N1,比較電路15的非反相輸入端子連接於磁滯產生電路40的輸出端子。在磁滯產生電路40的輸入端子連接有輸入端子N2。比較電路15的輸出端子out5連接於鎖存電路30。磁滯產生電路40具備磁滯控制端子HC,根據控制訊號來調整磁滯電壓。磁滯控制端子HC的控制電路未圖 示。關於其他的連接及構成與第2實施形態相同。在以下的說明中,將比較電路15的非反相輸入端子與磁滯產生電路40的輸出端子的連接點設為N2’,將連接點N2’的電壓設為Vn2’,將輸出端子out5的電壓設為輸出電壓Vout5。 The comparison circuit 15 has two input terminals and one output terminal, and specifically has an inverting input terminal, a non-inverting input terminal, and an output terminal out5. The inverting input terminal of the comparison circuit 15 is connected to the input terminal N1, and the non-inverting input terminal of the comparison circuit 15 is connected to the output terminal of the hysteresis generating circuit 40. An input terminal N2 is connected to an input terminal of the hysteresis generating circuit 40. The output terminal out5 of the comparison circuit 15 is connected to the latch circuit 30. The hysteresis generating circuit 40 includes a hysteresis control terminal HC, and adjusts the hysteresis voltage in accordance with the control signal. The hysteresis control terminal HC control circuit is not shown Show. Other connections and configurations are the same as in the second embodiment. In the following description, the connection point between the non-inverting input terminal of the comparison circuit 15 and the output terminal of the hysteresis generating circuit 40 is N2', the voltage of the connection point N2' is Vn2', and the output terminal out5 is The voltage is set to the output voltage Vout5.
繼而,對第3實施形態的零交越檢測電路的動作進行說明。 Next, the operation of the zero-crossing detection circuit of the third embodiment will be described.
比較電路15以與第1實施形態的比較電路10相同的方式動作。即,比較電路15以如下方式動作:當供給至非反相輸入端子的電壓高於供給至反相輸入端子的電壓時,自輸出端子out5輸出高位準,與此相反地,當供給至非反相輸入端子的電壓低於供給至反相輸入端子的電壓時,自輸出端子out5輸出低位準。磁滯產生電路40以如下方式動作:根據磁滯控制端子HC的控制狀態,在直接輸出輸入電壓、或者與為正值的電壓Vth1相加後輸出、或者與為負值的電壓Vth2相加後輸出之間進行切換。即,以磁滯產生電路40的輸出電壓成為Vn2’=Vn2、或Vn2’=Vn2+Vth1、或Vn2’=Vn2+Vth2中的任一者的方式受到控制。關於進行此種動作的磁滯產生電路,為公知技術,例如可藉由電阻及定電流源以及開關元件來實現。 The comparison circuit 15 operates in the same manner as the comparison circuit 10 of the first embodiment. That is, the comparison circuit 15 operates in such a manner that when the voltage supplied to the non-inverting input terminal is higher than the voltage supplied to the inverting input terminal, the high level is output from the output terminal out5, and conversely, when supplied to the non-reverse When the voltage of the phase input terminal is lower than the voltage supplied to the inverting input terminal, the low level is output from the output terminal out5. The hysteresis generating circuit 40 operates in accordance with the control state of the hysteresis control terminal HC, after directly outputting the input voltage, or adding the voltage Vth1 which is a positive value, or outputting it, or adding the voltage Vth2 which is a negative value. Switch between outputs. In other words, the output voltage of the hysteresis generating circuit 40 is controlled such that Vn2' = Vn2, or Vn2' = Vn2 + Vth1, or Vn2' = Vn2 + Vth2. The hysteresis generating circuit that performs such an operation is known in the art and can be realized, for example, by a resistor, a constant current source, and a switching element.
在以磁滯產生電路40的輸出電壓成為Vn2’=Vn2的方式受到控制的狀態下,比較電路15對輸入至非反相輸入端子的電壓Vn2’=Vn2與輸入至反相輸入端子的電壓Vn1進行比較。因此,進行與第1實施形態的比較電路10相同的動作。若在該控制狀態 下,根據時脈訊號CK1藉由鎖存器LT1來鎖存比較電路15的輸出電壓Vout5,則輸出電壓Vout0成為與圖5的(a)及圖3的(b)所示的Vout0相同的輸出電壓。 In a state where the output voltage of the hysteresis generating circuit 40 is controlled to be Vn2'=Vn2, the comparison circuit 15 applies the voltage Vn2'=Vn2 input to the non-inverting input terminal and the voltage Vn1 input to the inverting input terminal. Compare. Therefore, the same operation as that of the comparison circuit 10 of the first embodiment is performed. If in the control state When the output voltage Vout5 of the comparison circuit 15 is latched by the latch LT1 according to the clock signal CK1, the output voltage Vout0 becomes the same output as Vout0 shown in (a) of FIG. 5 and (b) of FIG. Voltage.
另外,在以磁滯產生電路40的輸出電壓成為Vn2’=Vn2+Vth1的方式受到控制的狀態下,比較電路15對輸入至非反相輸入端子的電壓Vn2’=Vn2+Vth1與輸入至反相輸入端子的電壓Vn1進行比較,在以磁滯產生電路40的輸出電壓成為Vn2’=Vn2+Vth2的方式受到控制的狀態下,比較電路15對輸入至非反相輸入端子的電壓Vn2’=Vn2+Vth2與輸入至反相輸入端子的電壓Vn1進行比較。因此,進行與第1實施形態的比較電路12及比較電路13相同的動作。若在該控制狀態下,根據時脈訊號CK2、時脈訊號CK3藉由鎖存器LT2、鎖存器LT3來鎖存比較電路15的輸出電壓Vout5,則輸出電壓Vout1成為與圖5的(b)、圖5的(c)及圖3的(c)所示的Vout1相同的輸出電壓。邏輯電路20的動作與第1實施形態及第2實施形態相同,輸出電壓Vout可進行零交越檢測,並且可消除由雜訊引起的零交越的影響。 Further, in a state where the output voltage of the hysteresis generating circuit 40 is controlled so as to be Vn2'=Vn2+Vth1, the comparison circuit 15 applies the voltage Vn2'=Vn2+Vth1 input to the non-inverting input terminal and the input to the opposite. The voltage Vn1 of the phase input terminal is compared, and in a state where the output voltage of the hysteresis generating circuit 40 is controlled such that Vn2'=Vn2+Vth2, the comparison circuit 15 applies the voltage Vn2' input to the non-inverting input terminal. Vn2+Vth2 is compared with the voltage Vn1 input to the inverting input terminal. Therefore, the same operations as those of the comparison circuit 12 and the comparison circuit 13 of the first embodiment are performed. If, in the control state, the output voltage Vout5 of the comparison circuit 15 is latched by the latch signal CK2 and the clock signal CK3 by the latch LT2 and the latch LT3, the output voltage Vout1 becomes the (b) of FIG. The same output voltage as Vout1 shown in (c) of FIG. 5 and (c) of FIG. The operation of the logic circuit 20 is the same as that of the first embodiment and the second embodiment, and the output voltage Vout can perform zero-crossing detection and can eliminate the influence of zero-crossing caused by noise.
第3實施形態中,使遲滯產生電路40進行切換來動作,因此與第2實施形態同樣地,相對於第1實施形態而動作速度變慢,但具有藉由減少比較電路的數量而電路規模變小的優點。 In the third embodiment, the hysteresis generating circuit 40 is switched and operated. As in the second embodiment, the operating speed is slower than in the first embodiment, but the circuit scale is reduced by reducing the number of comparison circuits. Small advantage.
藉由以上內容對第3實施形態的零交越檢測電路的動作進行了說明,且與第1實施形態及第2實施形態同樣地示出了以下情況:可進行零交越檢測並且可消除由雜訊引起的零交越的影 響,能夠以簡便的電路構成獲得高精度的零交越檢測結果。 The operation of the zero-crossing detection circuit of the third embodiment has been described above, and similarly to the first embodiment and the second embodiment, it is possible to perform zero-crossing detection and eliminate Zero crossover caused by noise The high-accuracy zero-crossing detection result can be obtained with a simple circuit configuration.
本說明中,為便於說明而設為藉由磁滯產生電路40在輸入端子N2側提供電壓進行相加,但亦可以類似的方式在輸入端子N1側提供電壓進行相加,另外,亦可在輸入端子N1與輸入端子N2兩者側與電壓相加。 In the present description, for convenience of explanation, the voltage is supplied by the hysteresis generating circuit 40 on the input terminal N2 side, but the voltage may be supplied on the input terminal N1 side in a similar manner, and may be added in the same manner. Both the input terminal N1 and the input terminal N2 are added to the voltage.
另外,在第2實施形態及第3實施形態的說明中,作為保持比較電路的輸出電壓的電路而示出了鎖存電路,但只要為進行讀取資料的動作的構成,則未必限制為該構成。 In the description of the second embodiment and the third embodiment, the latch circuit is shown as a circuit that holds the output voltage of the comparison circuit. However, the configuration is not necessarily limited to the configuration of the operation of reading the data. Composition.
另外,第1實施形態、第2實施形態及第3實施形態的說明中,對根據輸出電壓Vout1的高位準或低位準的邏輯狀態來選擇是否將輸出電壓Vout0輸出至電壓Vout的動作進行了說明,但未必限定於此,亦可設為如根據輸出電壓Vout1的邏輯狀態以輸出電壓Vout0的變化時序來控制輸出電壓Vout的動作。另外,亦可設為如下般的動作:在輸出電壓Vout1為高位準的情況下,向Vout僅輸出一次Vout0的自高位準向低位準的遷移,在輸出電壓Vout1為低位準的情況下,向Vout僅輸出一次Vout0的自低位準向高位準的遷移。另外,為便於說明,根據動作狀態而明確記載了各輸出電壓的高位準與低位準,但高位準與低位準可反轉,另外高位準與低位準的組合亦可不同。另外,在本說明中,將電壓Vth1與電壓Vth2作為比較電路的磁滯電壓進行了說明,但只要為進行本說明內所記載的比較電路的動作的構成,則未必限制為該構成。作為一例,亦可為並非在比較電路的內部具有磁滯電壓,而是將基 準電壓供給至比較電路以調整輸出電壓Vout1的反相位準的構成。另外,關於電壓Vth1與電壓Vth2,作為如圖3的(a)所示般時間上不發生變化的一定的電壓進行了說明,但例如在雜訊的大小因電源電壓或溫度等周圍環境而改變的情況下,電壓Vth1或電壓Vth2亦可不為一定的電壓而可變地進行控制。另外,關於比較電路10的磁滯寬度,在未特別提及的情況下是以零為前提進行了說明,但在實際的電路中,因存在非理想成分,磁滯寬度未必為零,有時具有微小的值。在該情況下亦不會有損本發明的效果。另外,在真實電路中,為了消除由電源電壓的變動等引起的雜訊,可使比較電路10具有極小振幅的磁滯功能,或者亦可設置暫時性磁滯功能,或者亦可藉由對比較電路10的輸出進行多次採樣而設置數位形式的濾波器。另外,本說明中,為便於說明,作為輸入訊號而尤其著眼於電壓進行了說明,但顯而易見的是輸入訊號亦可為電流。 In the description of the first embodiment, the second embodiment, and the third embodiment, the operation of selecting whether or not to output the output voltage Vout0 to the voltage Vout according to the logic state of the high or low level of the output voltage Vout1 has been described. However, the operation is not limited thereto, and the operation of controlling the output voltage Vout at the timing of changing the output voltage Vout0 according to the logic state of the output voltage Vout1 may be employed. In addition, when the output voltage Vout1 is at a high level, the transition from the high level to the low level of Vout0 is outputted to Vout once, and when the output voltage Vout1 is at the low level, Vout only outputs the transition from the low level to the high level of Vout0. Further, for convenience of explanation, the high level and the low level of each output voltage are clearly described in terms of the operating state, but the high level and the low level may be reversed, and the combination of the high level and the low level may be different. In the present description, the voltage Vth1 and the voltage Vth2 are used as the hysteresis voltage of the comparison circuit. However, the configuration is not necessarily limited to the configuration as long as the operation of the comparison circuit described in the present specification is performed. As an example, instead of having a hysteresis voltage inside the comparison circuit, the base may be The quasi-voltage is supplied to the comparison circuit to adjust the inverse phase of the output voltage Vout1. Further, although the voltage Vth1 and the voltage Vth2 are described as constant voltages that do not change in time as shown in FIG. 3(a), for example, the size of the noise changes depending on the surrounding environment such as the power supply voltage or the temperature. In the case of the voltage Vth1 or the voltage Vth2, the voltage Vth1 or the voltage Vth2 may be variably controlled without a constant voltage. Further, the hysteresis width of the comparison circuit 10 is described on the premise that it is zero unless otherwise specified. However, in an actual circuit, the hysteresis width is not necessarily zero due to the presence of a non-ideal component, and sometimes Has a small value. Also in this case, the effects of the present invention are not impaired. Further, in the real circuit, in order to eliminate noise caused by fluctuations in the power supply voltage or the like, the comparison circuit 10 can have a hysteresis function of a very small amplitude, or a temporary hysteresis function can be provided, or can be compared by comparison. The output of circuit 10 is sampled multiple times to set up a filter in digital form. In addition, in the description, for convenience of explanation, the voltage is specifically described as an input signal, but it is obvious that the input signal can also be a current.
<本發明的零交越檢測電路的應用例> <Application Example of Zero Crossover Detection Circuit of the Present Invention>
圖8為將本發明的第1實施形態的零交越檢測電路應用於磁力感測裝置的第1應用例的電路圖。作為磁電轉換元件的霍耳(Hall)元件1a的訊號自端子Ba與端子Da輸入至差動放大器2a,差動放大器2a對其進行放大,且差動放大器2a的輸出連接至本發明的零交越檢測電路的輸入端子N1、輸入端子N2。此處,將端子Ba與端子Da的電壓分別設為VBa、VDa,將霍耳元件1a的訊號電壓設為VDa-VBa,將差動放大器2a的放大率設為G。 8 is a circuit diagram showing a first application example in which the zero-crossing detection circuit according to the first embodiment of the present invention is applied to a magnetic force sensing device. The signal of the Hall element 1a as the magnetoelectric conversion element is input from the terminal Ba and the terminal Da to the differential amplifier 2a, the differential amplifier 2a amplifies it, and the output of the differential amplifier 2a is connected to the zero crossing of the present invention. The input terminal N1 and the input terminal N2 of the detection circuit are detected. Here, the voltages of the terminal Ba and the terminal Da are VBa and VDa, the signal voltage of the Hall element 1a is VDa-VBa, and the amplification factor of the differential amplifier 2a is G.
霍耳元件1a的訊號電壓VDa-VBa的大小與符號根據流至霍耳元件1a的電流的方向與所施加的磁場的方向且依據弗萊明左手定則(Fleming's left-hand rule)而變化。假設將在沿紙面的自近前向縱深的方向施加磁場的情況下的訊號電壓VDa-VBa的符號設為正,則在沿紙面的自縱深向近前的方向施加磁場的情況下,訊號電壓VDa-VBa的符號為負。另外,所施加的磁場越大,則訊號電壓VDa-VBa的大小越大。另外,在霍耳元件1a的偏置(offset)電壓為零的理想情況下,施加至霍耳元件1a的磁場為零的情況下的訊號電壓VDa-VBa為零。霍耳元件1a的訊號電壓藉由差動放大器2a而放大,成為Vn2-Vn1=G×(VDa-VBa)...(1)。因此,Vn2-Vn1根據施加至霍耳元件1a的磁場而取正值或負值或零。即,藉由本發明的第1實施形態的零交越檢測電路的動作,可不因雜訊而進行誤動作地以高精度檢測施加至霍耳元件1a的磁場的零交越點。換言之,在檢測搭載有本發明的第1實施形態的零交越檢測電路的感測裝置與磁鐵的相對的位置關係的用途中,可高精度地檢測因相對位置的變換而施加至感測裝置的磁場自S極切換為N極的點、或自N極切換為S極的點。因此,本發明的應用例適宜用於需要高精度地檢測轉子的旋轉位置的無刷馬達中或編碼器中。可應對對高速旋轉的要求,亦不會發生習知的於應對高速化時成為課題的由雜訊引起的誤輸出,而可實現準確的旋轉控制。 The magnitude and sign of the signal voltages VDa-VBa of the Hall element 1a vary according to the direction of the current flowing to the Hall element 1a and the direction of the applied magnetic field and according to the Fleming's left-hand rule. Assuming that the sign of the signal voltage VDa-VBa is positive when a magnetic field is applied in the direction from the near to the front in the depth direction of the paper surface, the signal voltage VDa- is applied in the case where the magnetic field is applied in the direction from the depth to the front of the paper surface. The sign of VBa is negative. In addition, the larger the applied magnetic field, the larger the magnitude of the signal voltages VDa-VBa. Further, in the ideal case where the offset voltage of the Hall element 1a is zero, the signal voltage VDa-VBa when the magnetic field applied to the Hall element 1a is zero is zero. The signal voltage of the Hall element 1a is amplified by the differential amplifier 2a to become Vn2-Vn1=G×(VDa-VBa). . . (1). Therefore, Vn2-Vn1 takes a positive or negative value or zero depending on the magnetic field applied to the Hall element 1a. In other words, according to the operation of the zero-crossing detection circuit of the first embodiment of the present invention, the zero-crossing point of the magnetic field applied to the hall element 1a can be detected with high accuracy without malfunction due to noise. In other words, in the application for detecting the relative positional relationship between the sensing device and the magnet on which the zero-crossing detecting circuit according to the first embodiment of the present invention is mounted, it is possible to accurately detect the change in the relative position and apply it to the sensing device. The magnetic field is switched from the S pole to the N pole point or from the N pole to the S pole. Therefore, the application example of the present invention is suitably used in a brushless motor or an encoder that requires high-precision detection of the rotational position of the rotor. It is possible to cope with the demand for high-speed rotation, and it is possible to achieve accurate rotation control by causing an erroneous output caused by noise in order to cope with the problem of speeding up.
圖9為將本發明的第1實施形態的零交越檢測電路應用於磁力感測裝置的第2應用例的電路圖。霍耳元件1b與差動放大電路2b的連接的構成與第1應用例的霍耳元件1a與差動放大電路2a的連接的構成相同。另外,霍耳元件1c與差動放大電路2c的連接的構成亦與第1應用例的霍耳元件1a與差動放大電路2a的連接的構成相同。相對於差動放大電路2a為差動輸出,差動放大電路2b及差動放大電路2c是單端輸出。作為磁電轉換元件的霍耳元件1b的訊號自端子Bb與端子Db輸入至差動放大器2b,差動放大器2b對其進行放大,且差動放大器2b的輸出連接至本發明的零交越檢測電路的輸入端子N1。另外,作為磁電轉換元件的霍耳元件1c的訊號自端子Bc與端子Dc輸入至差動放大器2c,差動放大器2c對其進行放大,且差動放大器2c的輸出連接至本發明的零交越檢測電路的輸入端子N2。此處,將端子Bb、端子Db、端子Bc、端子Dc的各電壓分別設為VBb、VDb、VBc、VDc,將霍耳元件1b及霍耳元件1c的訊號電壓分別設為VDb-VBb、VDc-VBc,將差動放大器2b及差動放大器2c的放大率均設為G。如此,供給至輸入端子N1的輸入電壓Vn1與供給至輸入端子N2的輸入電壓Vn2如下。 FIG. 9 is a circuit diagram showing a second application example in which the zero-crossing detection circuit according to the first embodiment of the present invention is applied to the magnetic force sensing device. The configuration of the connection between the Hall element 1b and the differential amplifier circuit 2b is the same as the configuration of the connection between the Hall element 1a and the differential amplifier circuit 2a of the first application example. The configuration of the connection between the Hall element 1c and the differential amplifier circuit 2c is also the same as the configuration of the connection between the Hall element 1a and the differential amplifier circuit 2a of the first application example. The differential amplifier circuit 2a is a differential output, and the differential amplifier circuit 2b and the differential amplifier circuit 2c are single-ended outputs. The signal of the Hall element 1b as the magnetoelectric conversion element is input from the terminal Bb and the terminal Db to the differential amplifier 2b, the differential amplifier 2b amplifies it, and the output of the differential amplifier 2b is connected to the zero-crossing detecting circuit of the present invention. Input terminal N1. Further, a signal of the hall element 1c as a magnetoelectric conversion element is input from the terminal Bc and the terminal Dc to the differential amplifier 2c, the differential amplifier 2c amplifies it, and the output of the differential amplifier 2c is connected to the zero crossing of the present invention. The input terminal N2 of the detection circuit. Here, the respective voltages of the terminal Bb, the terminal Db, the terminal Bc, and the terminal Dc are VBb, VDb, VBc, and VDc, and the signal voltages of the Hall element 1b and the Hall element 1c are respectively set to VDb-VBb and VDc. -VBc, the amplification factors of the differential amplifier 2b and the differential amplifier 2c are both set to G. Thus, the input voltage Vn1 supplied to the input terminal N1 and the input voltage Vn2 supplied to the input terminal N2 are as follows.
Vn1=G×(VDb-VBb)...(2) Vn1=G×(VDb-VBb). . . (2)
Vn2=G×(VDc-VBc)...(3)根據式(2)與式(3)而獲得下式。 Vn2=G×(VDc-VBc). . . (3) The following formula is obtained according to the formula (2) and the formula (3).
Vn2-Vn1=G×{(VDc-VBc)-(VDb-VBb)}...(4)因此,Vn2-Vn1根據施加至霍耳元件1b與霍耳元件1c的磁場而取正值或負值或零。即,藉由本發明的第1實施形態的零交越檢測電路的動作,可不因雜訊而進行誤動作地以高精度檢測施加至霍耳元件1b與霍耳元件1c的磁場的差的零交越點。即,可在兩個感測元件的訊號相等的情況下輸出零交越檢測,且可辨別出兩個感測元件中的哪一者的訊號大並加以輸出。本應用例適宜用於例如在產生偏磁場的磁鐵與包含鐵等金屬或磁體的齒輪之間配置磁力感測裝置、並藉由磁力感測裝置檢測齒輪的旋轉的用途中。 Vn2-Vn1=G×{(VDc-VBc)-(VDb-VBb)}. . . (4) Therefore, Vn2-Vn1 takes a positive value or a negative value or zero depending on the magnetic field applied to the Hall element 1b and the Hall element 1c. In other words, the zero crossing detection circuit of the first embodiment of the present invention can detect the zero crossing of the difference between the magnetic field applied to the Hall element 1b and the Hall element 1c with high accuracy without malfunction due to noise. point. That is, zero-crossing detection can be output when the signals of the two sensing elements are equal, and it can be discerned which of the two sensing elements has a large signal and is output. This application example is suitably used, for example, in a configuration in which a magnetic sensing device is disposed between a magnet that generates a bias magnetic field and a gear including a metal such as iron or a magnet, and the rotation of the gear is detected by the magnetic sensing device.
本說明中,為便於說明,將差動放大電路2b及差動放大電路2c設為單端輸出,但亦可為了實現耐雜訊性的提高而設為差動輸出。另外,對霍耳元件為兩個的情況進行了說明,但亦可多於兩個。例如,亦可設為生成兩個霍耳元件的差分訊號1以及與該差分訊號1不同的兩個霍耳元件的差分訊號2,並對差分訊號1與差分訊號2的零交越進行檢測。 In the present description, the differential amplifier circuit 2b and the differential amplifier circuit 2c are single-ended outputs for convenience of explanation, but may be differential outputs in order to improve noise resistance. Further, the case where there are two Hall elements has been described, but there may be more than two. For example, the difference signal 1 of the two Hall elements and the difference signal 2 of the two Hall elements different from the difference signal 1 may be generated, and the zero crossing of the difference signal 1 and the differential signal 2 may be detected.
圖10為將本發明的第2實施形態的零交越檢測電路應用於磁力感測裝置的第3應用例的電路圖。霍耳元件1a與差動放大電路2a的連接的構成與第1應用例的霍耳元件1a與差動放大電路2a的連接的構成相同。作為磁電轉換元件的霍耳元件1a的訊號自端子Ba與端子Da輸入至差動放大器2a,差動放大器2a對其進行放大,且差動放大器2a的輸出連接至本發明的零交越檢 測電路的輸入端子N1、輸入端子N2。與第1應用例的情況同樣地,Vn2-Vn1根據施加至霍耳元件1a的磁場而取正值或負值或零。即,藉由本發明的第2實施形態的零交越檢測電路的動作,可不因雜訊而進行誤動作地以高精度檢測施加至霍耳元件1a的磁場的零交越點。 FIG. 10 is a circuit diagram showing a third application example in which the zero-crossing detection circuit according to the second embodiment of the present invention is applied to a magnetic force sensing device. The configuration of the connection between the Hall element 1a and the differential amplifier circuit 2a is the same as the configuration of the connection between the Hall element 1a and the differential amplifier circuit 2a of the first application example. The signal of the Hall element 1a as the magnetoelectric conversion element is input from the terminal Ba and the terminal Da to the differential amplifier 2a, the differential amplifier 2a amplifies it, and the output of the differential amplifier 2a is connected to the zero cross check of the present invention. The input terminal N1 and the input terminal N2 of the measuring circuit. Similarly to the case of the first application example, Vn2-Vn1 takes a positive value or a negative value or zero depending on the magnetic field applied to the hall element 1a. In other words, according to the operation of the zero-crossing detecting circuit of the second embodiment of the present invention, the zero-crossing point of the magnetic field applied to the hall element 1a can be detected with high accuracy without malfunction due to noise.
圖11為將本發明的第3實施形態的零交越檢測電路應用於磁力感測裝置的第4應用例的電路圖。與圖10的第3應用例的不同在於代替第2實施形態而應用第3實施形態,具體而言為:去除了比較電路14而追加了比較電路15,且在輸入端子N2與比較電路15的非反相輸入端子之間追加了磁滯產生電路40。省略了磁滯產生電路40的磁滯控制端子HC。關於其他的連接及構成,與第3應用例相同。 Fig. 11 is a circuit diagram showing a fourth application example in which the zero-crossing detecting circuit according to the third embodiment of the present invention is applied to a magnetic force sensing device. The third embodiment differs from the third embodiment in FIG. 10 in that a third embodiment is applied instead of the second embodiment. Specifically, the comparison circuit 15 is added and the input terminal N2 and the comparison circuit 15 are added. A hysteresis generating circuit 40 is added between the non-inverting input terminals. The hysteresis control terminal HC of the hysteresis generating circuit 40 is omitted. The other connections and configurations are the same as those in the third application example.
作為磁電轉換元件的霍耳元件1a的訊號自端子Ba與端子Da輸入至差動放大器2a,差動放大器2a對其進行放大,且差動放大器2a的輸出連接至本發明的零交越檢測電路的輸入端子N1、輸入端子N2。與第1應用例及第2應用例的情況同樣地,Vn2-Vn1根據施加至霍耳元件1a的磁場而取正值或負值或零。即,藉由本發明的第3實施形態的零交越檢測電路的動作,可不因雜訊而進行誤動作地以高精度檢測施加至霍耳元件1a的磁場的零交越點。 The signal of the Hall element 1a as the magnetoelectric conversion element is input from the terminal Ba and the terminal Da to the differential amplifier 2a, the differential amplifier 2a amplifies it, and the output of the differential amplifier 2a is connected to the zero-crossing detecting circuit of the present invention. Input terminal N1, input terminal N2. Similarly to the case of the first application example and the second application example, Vn2-Vn1 takes a positive value or a negative value or zero depending on the magnetic field applied to the hall element 1a. In other words, according to the operation of the zero-crossing detection circuit of the third embodiment of the present invention, the zero-crossing point of the magnetic field applied to the hall element 1a can be detected with high accuracy without malfunction due to noise.
本說明中,為便於說明而將磁滯產生電路40連接於差動放大器2a與比較電路15之間,但亦可將磁滯產生電路40連接 於更靠近訊號源之側。具體而言,可將磁滯產生電路40連接於霍耳元件1a與差動放大器2a之間。通常霍耳元件具有電阻成分,因此磁滯產生電路40中不需要電阻。因此,作為一例,磁滯產生電路40可僅包括定電流源與開關元件,從而具有有助於小型化、且藉由使定電流的值與霍耳元件的電阻值連動而可減小溫度所引起的特性偏移等優點。 In the present description, the hysteresis generating circuit 40 is connected between the differential amplifier 2a and the comparison circuit 15 for convenience of explanation, but the hysteresis generating circuit 40 may be connected. On the side closer to the source of the signal. Specifically, the hysteresis generating circuit 40 can be connected between the Hall element 1a and the differential amplifier 2a. Usually, the Hall element has a resistance component, so that no resistance is required in the hysteresis generating circuit 40. Therefore, as an example, the hysteresis generating circuit 40 may include only a constant current source and a switching element, thereby contributing to miniaturization and reducing the temperature by interlocking the value of the constant current with the resistance value of the Hall element. The characteristics caused by the characteristic offset.
圖8~圖11中示出了將本發明的零交越檢測電路應用於磁力感測裝置的例子。於本說明中,為了進行說明而示出了具體的例子,但未必限制為該構成或感測元件,可應用於廣泛的半導體電路及感測電路中。關於第1實施形態、第2實施形態、第3實施形態的零交越檢測電路的情況,亦同樣如此。作為一例,可與消去作為磁電轉換元件的霍耳元件的非理想成分即偏置電壓的旋轉電流(spinning current)電路組合,另外,亦可與消去差動放大器或比較電路的非理想成分即偏置電壓的截波(chopping)動作或自動歸零(auto zero)動作的電路等組合。此處,在與旋轉電流電路或者截波動作或自動歸零動作的電路等組合的情況下,成為離散時間的訊號處理而非連續時間的訊號處理,因此,將比較電路10~比較電路15的各自的輸出藉由組合電路進行演算而自輸出端子out輸出的情況欠佳。如第2實施形態或第3實施形態所示,適宜與鎖存電路等順序電路組合。另外,除磁電轉換元件以外,亦可作為溫度感測元件、加速度感測元件、壓力感測元件等感測元件的零交越檢測電路。 An example in which the zero crossover detecting circuit of the present invention is applied to a magnetic sensing device is shown in Figs. 8 to 11 . In the description, a specific example is shown for the sake of explanation, but it is not necessarily limited to the configuration or the sensing element, and can be applied to a wide range of semiconductor circuits and sensing circuits. The same applies to the case of the zero-crossing detection circuit of the first embodiment, the second embodiment, and the third embodiment. As an example, it may be combined with a spinning current circuit that cancels a bias voltage that is a non-ideal component of a Hall element as a magnetoelectric conversion element, or may be a non-ideal component that eliminates a differential amplifier or a comparison circuit. A combination of a chopping action of a voltage or a circuit of an auto zero action. Here, in combination with a rotating current circuit or a circuit for a chopper operation or an auto-zero operation, etc., the signal processing of discrete time is performed instead of the signal processing of continuous time, and therefore, the comparison circuit 10 to the comparison circuit 15 are It is not preferable that the respective outputs are output from the output terminal out by calculation by the combinational circuit. As described in the second embodiment or the third embodiment, it is preferably combined with a sequential circuit such as a latch circuit. In addition, in addition to the magnetoelectric conversion element, it can also be used as a zero-crossing detection circuit of the sensing element such as a temperature sensing element, an acceleration sensing element, and a pressure sensing element.
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