TW201805600A - Zero-cross detecting circuit and sensor device - Google Patents

Abstract

The present invention provides a zero-cross detecting circuit capable of detecting a zero-cross with high accuracy without being influenced by a noise. The zero-cross detecting circuit comprises: a first comparison circuit; a second comparison circuit having a hysteresis function; and a logic circuit. The first comparison circuit outputs a zero-cross detection result of a first input signal and a second input signal. The second comparison circuit outputs a comparison result of the first and second input signals. The logic circuit provides a means determining whether the zero-cross detection result is reflected to an output based on the zero-cross detection result and the comparison result.

Description

Zero-crossing detection circuit and sensing device

The invention relates to a zero-cross detection circuit and a sensing device, and more particularly to a zero-cross detection circuit that can accurately detect a zero-cross point based on a signal from a sensing element.

Conventionally, various sensing devices are mounted on electronic devices and are effectively used. As an example, an example in which a magnetic force sensing device is used to detect the position of a movable member of a brushless motor can be cited. The brushless motor includes a cylindrical stator and a cylindrical rotor that is provided on the inner or outer periphery of the stator so as to face each other. The rotor rotates freely with respect to the stator around the rotation axis. A magnet for excitation is arranged in the rotor in a circumferential direction, a coil is wound around a stator core of the stator, and a magnetic field generated by passing a current to the coil is used to interact with a magnetic field formed by the magnet for excitation. The rotor rotates.

In order to control the rotation of the rotor, it is necessary to detect the rotational position of the rotor. As a means of position detection, a magnetic force sensing element is generally used. A magnetic sensing element is used to detect the switching between the S pole and the N pole of the magnet, that is, the position of zero crossing, thereby detecting the rotation position of the rotor. In the zero-crossing detection, various methods for making hysteresis characteristics have been studied in order to prevent chattering near the zero-crossing. However, due to the influence of the hysteresis, a deviation occurs between the original zero-crossing position and the zero-crossing detection position detected by the sensing signal, causing problems such as a decrease in the efficiency of the motor, uneven rotation, or vibration. Therefore, there is a need for a zero-crossing detection circuit that does not generate chattering near the zero-crossing and has no hysteresis output.

A circuit diagram of an example of a conventional zero-crossing detection circuit is shown in FIG. 12. The conventional zero-crossing detection circuit includes: an operational amplifier 50 that inputs a detected signal S to an inverting input terminal and outputs the detected signal S as a zero-crossing detection signal fa; and a comparison signal forming circuit 51 that forms a comparison signal h and The non-inverting input terminal provided to the operational amplifier 50, wherein by the zero-crossing detection signal fa, the comparison signal h is opposite to the detected signal S immediately after the zero-crossing detection and has a positive and negative opposite level, and The sequence changes its level and becomes the zero level after a specified time. The comparison signal forming circuit 51 includes a resistor R10, a resistor R11, and a capacitor Ca, and is set to a time constant T = (R10 + R11) · Ca.

The operation of the conventional zero-crossing detection circuit having such a configuration is shown in FIG. 13. If the detected signal S is given to the inverting input terminal of the operational amplifier 50, the operational amplifier 50 compares each bit of the detected signal S with the comparison signal h and outputs a zero-crossing detection signal fa as a comparison result. At time t1, the detected signal S is a positive level, the comparison signal h is a negative level, and the operational amplifier 50 outputs a low-level zero-crossing detection signal fa. After a certain time has elapsed from this state, the comparison signal h changes to a zero level following the level change of the time constant T. If the detected signal S performs zero crossing at time t2, the voltage of the inverting input terminal of the operational amplifier 50 is The positive level becomes the zero level and then changes to the negative level. Thereby, the zero-crossing detection signal fa output from the operational amplifier 50 is inverted to a high level at time t2. At this time, the capacitor Ca is given a high-level zero-crossing detection signal fa, that is, + Vdd, so a voltage C of + 2Vdd appears at the other end of the capacitor Ca. This voltage C is divided by the resistor R10 and the resistor R11, and is supplied to the non-inverting input terminal of the operational amplifier 50 as a comparison signal h. Therefore, immediately after time t2, the operational signal 50 is used to compare the detected signal S that has changed to the negative level with the comparison signal h that has become the positive level. Thereby, even if the noise ns is added to the detected signal S in the vicinity of the zero-crossing and the zero-crossing is forcibly performed, the role of the comparison signal forming circuit 51 is to compare the level of the signal h with respect to the detected signal. S operates in a positive and negative level. Therefore, the zero-crossing detection signal fa output from the operational amplifier 50 does not reverse due to noise ns, and no false detection of zero-crossing occurs. Thereafter, the comparison signal h follows the time constant T and its level slowly decreases, reaching the zero level before reaching the next zero crossing time t3. When the detected signal S is zero-crossed again at time t3, the zero-crossing detection signal fa output from the operational amplifier 50 is inverted and becomes a low level. At this time, the capacitor Ca is given a low-level zero-crossing detection signal fa, that is, the voltage -Vdd, and therefore a voltage C of -2Vdd appears at the other end of the capacitor Ca. This voltage C is divided by the resistor R10 and the resistor R11, and is supplied to the non-inverting input terminal of the operational amplifier 50 as a comparison signal h. Whenever the positive and negative levels of the detected signal change, the above operation is performed to output the zero-crossing detection signal fa. Therefore, even if the zero crossing caused by noise occurs, a zero crossing detection signal that does not cause false detection, that is, chattering, is realized. [Prior Art Literature] [Patent Literature]

[Patent Document 1] Japanese Patent Laid-Open No. 63-75670 [Problems to be Solved by the Invention]

However, in the conventional zero-crossing detection circuit, as described above, it is configured to eliminate the influence of the zero-crossing caused by noise only during the time determined by the time constant T defined by the resistance and the capacitance, and thus there is The following problem: The zero crossing point of the detected signal S cannot be detected in the case where the detected signal S repeatedly performs zero crossing in a time shorter than the time determined by the time constant T. Therefore, for example, in the use in a brushless motor, a request for high-speed rotation cannot be met, and there is a problem that the rotation speed of the brushless motor is limited by a zero-crossing detection circuit. In addition, if the values of the resistance and the capacitance are selected so that the time constant T becomes shorter, there is a problem that noise cannot be eliminated. Therefore, for example, in a brushless motor, there is a problem that a zero-crossing detection circuit performs an erroneous output due to noise, and an accurate rotation control cannot be achieved.

[Means for Solving the Problems] In order to solve such a conventional problem, the zero-crossing detection circuit of the present invention has the following configuration.

The zero-crossing detection circuit of the present invention includes a first comparison circuit to which a first input signal and a second input signal are input, a second comparison circuit to which a first input signal and a second input signal are input, and a hysteresis function, and a logic circuit. And has a structure in which the first comparison circuit outputs a zero-crossing detection result of the first input signal and the second input signal, and the second comparison circuit outputs the first input signal and the second input signal. Comparing the results, the logic circuit determines the output based on the zero-crossing detection result and the comparison result. [Effect of the invention]

According to the zero-crossing detection circuit of the present invention, a zero-crossing point at which an input signal is switched from positive to negative and from negative to positive can be detected with high accuracy, and the influence of the zero-crossing caused by noise can be eliminated. In addition, the zero-crossing detection circuit can be realized with a relatively small circuit scale and a simple structure. Not only can be applied to the listed brushless motors, but also can be widely used to detect the zero-crossing point of common signals such as sensor output.

The zero-crossing detection circuit of the present invention can be widely used as a zero-crossing detection circuit in a semiconductor circuit. Hereinafter, the zero-crossing detection circuit of the present invention will be described with reference to the drawings.

<First Embodiment> FIG. 1 is a circuit diagram of a zero-crossing detection circuit according to a first embodiment. The zero-crossing detection circuit of the first embodiment includes a comparison circuit 10, a comparison circuit 11, and a logic circuit 20.

The comparison circuit 10 includes two input terminals and one output terminal. Specifically, the comparison circuit 10 includes an inverting input terminal, a non-inverting input terminal, and an output terminal out0. In addition, the comparison circuit 11 includes two input terminals and one output terminal. Specifically, the comparison circuit 11 includes an inverting input terminal, a non-inverting input terminal, and an output terminal out1. The inverting input terminal of the comparison circuit 10 and the inverting input terminal of the comparison circuit 11 are commonly connected by an input terminal N1. The non-inverting input terminal of the comparison circuit 10 and the non-inverting input terminal of the comparison circuit 11 are commonly connected by an input terminal N2. The input terminal N1 and the input terminal N2 are respectively supplied with a first input signal and a second input signal. An output terminal out0 of the comparison circuit 10 and an output terminal out1 of the comparison circuit 11 are connected to the logic circuit 20. The logic circuit 20 takes the signal of the output terminal out0 and the signal of the output terminal out1 as inputs, and outputs a logic calculation result from the output terminal out. In the following description, the voltages of the input terminal N1, the input terminal N2, the output terminal out0, the output terminal out1, and the output terminal out are respectively set to the input voltage Vn1, the input voltage Vn2, the output voltage Vout0, the output voltage Vout1, and the output voltage. Vout.

Next, the operation of the zero-crossing detection circuit according to the first embodiment will be described with reference to Figs. 2 and 3. First, the operation of the comparison circuit 10 will be described. The comparison circuit 10 operates as follows: when the voltage supplied to the non-inverting input terminal is higher than the voltage supplied to the inverting input terminal, a high level is output from the output terminal out0, and when it is supplied to the non-inverting input When the voltage of the terminal is lower than the voltage supplied to the inverting input terminal, a low level is output from the output terminal out0. The details of this operation are shown in (a) of FIG. 2. Here, the horizontal axis represents an input voltage difference between the input voltage Vn1 and the input voltage Vn2, and the vertical axis represents each output voltage. As shown in (a) of FIG. 2, the output voltage Vout0 outputs a high level when the input voltage Vn2 is higher than the input voltage Vn1, that is, when Vn2-Vn1> 0. In contrast, when the input voltage Vn2 is lower than the input voltage Vn1, that is, when Vn2-Vn1 <0, the low level is output. The transition of the output voltage Vout0 from the high level to the low level is performed at Vn2-Vn1 = 0. In addition, the transition of the output voltage Vout0 from a low level to a high level is also performed at Vn2-Vn1 = 0.

The operation of the comparison circuit 10 when the input voltage difference Vn2-Vn1 changes with time is shown in FIGS. 3 (a) and 3 (b). Here, the horizontal axis represents the passage of time, and the vertical axis represents the input voltage difference or the output voltage. (A) of FIG. 3 shows a case where the input voltage difference Vn2-Vn1 changes with time. The input voltage difference Vn2-Vn1 can take various values over time. In particular, when Vn2-Vn1 = 0, there will be zero crossing. (B) of FIG. 3 shows a case where the output voltage Vout0 changes with the time change of the input voltage difference Vn2-Vn1. As shown in FIG. 3 (b), the output voltage Vout0 outputs a high level when Vn2-Vn1> 0, and outputs a low level when Vn2-Vn1 <0. When Vn2-Vn1 = 0, that is, when Vn1 = Vn2, the output voltage Vout0 performs zero-crossing detection.

Next, an operation of the comparison circuit 11 will be described. The comparison circuit 11 operates as follows: When the voltage supplied to the non-inverting input terminal is higher than the sum of the voltage supplied to the inverting input terminal and the voltage Vth1, a high level is output from the output terminal out1, and in contrast, when the supply When the voltage to the non-inverting input terminal is lower than the sum of the voltage supplied to the inverting input terminal and the voltage Vth2, a low level is output from the output terminal out1. The details of this operation are shown in (b) of FIG. 2. As shown in FIG. 2 (b), the output voltage Vout1 outputs a high level when the input voltage Vn2 is higher than the sum of the input voltage Vn1 and the voltage Vth1, that is, Vn2-Vn1> Vth1, and the input voltage Vn2 is lower than the input voltage Vn1 and When the voltage Vth2 is summed, that is, when Vn2-Vn1 <Vth2, a low level is output. Here, the voltage Vth1 is a positive value and indicates a hysteresis value on the positive side, and the voltage Vth2 is a negative value and indicates a hysteresis value on the negative side. The transition of the output voltage Vout1 from a high level to a low level is performed at Vn2-Vn1 = Vth2. In addition, the transition of the output voltage Vout1 from a low level to a high level is performed at Vn2-Vn1 = Vth1. When Vn2-Vn1 is between Vth1 and Vth2, a high level or a low level is output according to the immediately preceding state. That is, the comparison circuit 11 operates as a comparison circuit having a hysteresis width | Vth1 | + | Vth2 |.

The operation of the comparison circuit 11 when the input voltage difference Vn2-Vn1 changes over time is shown in FIGS. 3 (a) and 3 (c). (C) of FIG. 3 shows a case where the output voltage Vout1 changes with time change of the input voltage difference Vn2-Vn1 shown in (a) of FIG. 3. When it is time t1, that is, Vn2-Vn1> Vth1, the output voltage Vout1 outputs a high level, and the high level is maintained after the elapse of the following time. As Vn2-Vn1 decreases, when Vn2-Vn1 <Vth2 decreases The output shifted from the high level to the low level will also maintain the low level after the elapse of the following time. With the increase of Vn2-Vn1, when Vn2-Vn1> Vth1 becomes, the transition from the low level to the high level.

Next, an operation of the logic circuit 20 will be described. The logic circuit 20 operates as follows: The logic of the output voltage Vout is determined based on the logic states of the output voltage Vout0 and the output voltage Vout1. In more detail, when Vout1 is at a high level, Vout0 transitions from a high level to a low level by shifting Vout0 from a high level to a low level. If Vout was originally low, Vout would not change. Vout does not change due to the transition of Vout0 from a low level to a high level. In addition, when Vout1 is at the low level, Vout0 is migrated from the low level to the high level by the transition of Vout0 from the low level to the high level. If Vout was originally high, Vout would not change. Vout does not change due to the transition of Vout0 from a high level to a low level. The above operation will be described using FIG. 3.

As described above, FIG. 3 (a), FIG. 3 (b), and FIG. 3 (c) respectively show the time variation of the input voltage difference Vn2-Vn1, the output voltage Vout0, and the output voltage Vout1. (D) of FIG. 3 shows a time change of the output voltage Vout.

In FIGS. 3 (a) to 3 (d), when it is time t1, the output voltage Vout0 and the output voltage Vout1 are at a high level. Thereafter, time elapses and Vn2-Vn1 decreases, and Vout0 shifts from a high level to a low level when a zero crossing is performed. At this time, Vout1 is a high level, so the logic circuit 20 outputs the detection of zero crossing of Vout0 from the high level to the low level to Vout. Thereafter, if time passes and Vn2-Vn1 <Vth2 is reached, Vout1 shifts from a high level to a low level. Thereafter, time elapses and Vn2-Vn1 increases, and Vout0 shifts from a low level to a high level when a zero crossing is performed. At this time, Vout1 is at the low level, so the logic circuit 20 outputs the detection of zero crossing of Vout0 from the low level to the high level to Vout. Thereafter, if time passes and Vn2-Vn1> Vth1 is reached, Vout1 shifts from a low level to a high level. Furthermore, when time elapses thereafter and it is time t2, it will be in the same state as time t1.

When it is time t2, the output voltage Vout0 and the output voltage Vout1 are at a high level. Thereafter, time elapses and Vn2-Vn1 decreases, and Vout0 shifts from a high level to a low level when a zero crossing is performed. At this time, Vout1 is a high level, so the logic circuit 20 outputs the detection of zero crossing of Vout0 from the high level to the low level to Vout. After that, Vn2-Vn1 performs zero crossing twice due to noise ns, and the output voltage Vout0 shifts from the low level to the high level and then to the low level. At this time, Vout1 is at a high level, so the logic circuit 20 operates so as not to output the transition from the low level to the high level of Vout0 to Vout. Therefore, zero-crossing detection due to noise does not occur at the output terminal out. Furthermore, if time passes and Vn2-Vn1 <Vth2 is reached, Vout1 shifts from a high level to a low level. Thereafter, time elapses and Vn2-Vn1 increases, and Vout0 shifts from a low level to a high level when a zero crossing is performed. At this time, Vout1 is at the low level, so the logic circuit 20 outputs the detection of zero crossing of Vout0 from the low level to the high level to Vout. After that, Vn2-Vn1 performs zero crossing twice due to noise ns, and the output voltage Vout0 shifts from the high level to the low level and then to the high level. At this time, Vout1 is at a low level, and therefore operates in a manner that does not output the transition from the high level to the low level of Vout0 to Vout. Therefore, zero-crossing detection due to noise does not occur at the output terminal out. Thereafter, if time passes and Vn2-Vn1> Vth1 is reached, Vout1 shifts from a low level to a high level. Furthermore, when time elapses thereafter and it is time t3, it will be in the same state as time t1 and time 2.

The operation of the zero-crossing detection circuit according to the first embodiment has been described based on the above. The following shows the case where zero-crossing detection can be performed and the influence of zero-crossing caused by noise can be eliminated. Simple circuit configuration to obtain high-precision zero-crossing detection results. By using the zero-crossing detection circuit of this embodiment in a brushless motor, it is possible to meet the requirements for high-speed rotation. The conventional erroneous output due to noise, which is a problem that has been a problem in response to high speed, does not occur, and accurate rotation control can be realized.

In this description, the voltage Vth1 and the voltage Vth2 are described as the hysteresis voltage of the comparison circuit 11, but as shown in the circuit diagram of FIG. 4 and the operation diagram of FIG. 5, the comparison circuit 11 can be divided into a comparison circuit 12 and The comparison circuit 13 determines whether Vn2-Vn1 is greater than or less than the voltage Vth1 by the comparison circuit 12, and determines whether Vn2-Vn1 is greater than or less than the voltage Vth2 by the comparison circuit 13. Here, FIG. 5A shows the operation of the comparison circuit 10, FIG. 5B shows the operation of the comparison circuit 12, FIG. 5C shows the operation of the comparison circuit 13, and FIG. 5D shows the logic The operation of the circuit 20.

<Second Embodiment> Fig. 6 is a circuit diagram of a zero-crossing detection circuit according to a second embodiment. The difference from the first embodiment shown in FIG. 1 is that the comparison circuit 10 and the comparison circuit 11 are removed, the comparison circuit 14 is added, and the latch circuit 30 is added between the comparison circuit 14 and the logic circuit 20. The added elements are structured and connected as described below. In addition, due to the removed elements, the following connection is different from the first embodiment.

The comparison circuit 14 has two input terminals, one output terminal, and one control terminal HC. Specifically, it includes an inverting input terminal, a non-inverting input terminal, an output terminal out4, and a hysteresis control terminal HC. The inverting input terminal of the comparison circuit 14 is connected to the input terminal N1, and the non-inverting input terminal of the comparison circuit 14 is connected to the input terminal N2. The hysteresis control terminal HC of the comparison circuit 14 adjusts the hysteresis voltage of the comparison circuit 14 according to a control signal input to the hysteresis control terminal. The control circuit of the hysteresis control terminal HC is not shown. An output terminal out4 of the comparison circuit 14 is connected to the latch circuit 30. The latch circuit 30 includes a latch LT1, a latch LT2, and a latch LT3, and an output terminal out4 is connected to the data input terminal D of the latch LT1, the latch LT2, and the latch LT3. The data output terminals Q of the latches LT1, LT2, and LT3 are output terminals out0, output terminals out2, and output terminals out3, respectively, and are connected to the logic circuit in the same manner as the first embodiment shown in FIG. 20. The latches LT1, LT2, and LT3 are provided with a clock terminal C, and latch the data input to the data input terminal D according to the clock signal CK1, the clock signal CK2, and the clock signal CK3 and output to Data output terminal Q. The control circuits of the clock signal CK1, the clock signal CK2, and the clock signal CK3 are not shown. The other connections and configurations are the same as those of the first embodiment. In the following description, the voltage of the output terminal out4 is referred to as an output voltage Vout4.

Next, an operation of the zero-crossing detection circuit according to the second embodiment will be described. The comparison circuit 14 operates in such a manner that the operations of the comparison circuit 10 and the comparison circuit 11 of the first embodiment are performed in a time-sharing manner in accordance with a control signal input to the hysteresis control terminal HC. That is, if the comparison circuit 14 is controlled so that the voltage Vth1 and the voltage Vth2 become zero, the comparison circuit 14 operates in the same manner as the comparison circuit 10, and if the control is performed so that the voltage Vth1 and the voltage Vth2 do not become zero, the comparison circuit 14 operates in the same manner as the comparison circuit 12 or the comparison circuit 13. The comparison circuit that performs such an operation is known in the art, and therefore description thereof is omitted. If the comparison circuit 14 is controlled in the same manner as the comparison circuit 10, the output voltage Vout0 of the comparison circuit 14 is latched by the latch LT1 according to the clock signal CK1, and the output voltage Vout0 becomes the same as that of FIG. (A) The same output voltage as Vout0 shown in FIG. 3 (b). When the comparison circuit 14 is controlled in the same manner as the comparison circuit 12 and the comparison circuit 13, the comparison circuit 14 is latched by the latch LT2 and the latch LT3 based on the clock signal CK2 and the clock signal CK3. The output voltage Vout4 is the same as the output voltage Vout1 shown in FIG. 5 (b), FIG. 5 (c), and FIG. 3 (c). The operation of the logic circuit 20 is the same as that of the first embodiment, and the output voltage Vout can perform zero-crossing detection, and the influence of the zero-crossing due to noise can be eliminated.

In the second embodiment, since the comparison circuit 14 is operated in a time-division manner, the operation speed is slower than that in the first embodiment, but there is an advantage that the circuit scale is reduced by reducing the number of comparison circuits.

The operation of the zero-crossing detection circuit according to the second embodiment has been described above, and similarly to the first embodiment, the following cases are shown: zero-crossing detection can be performed and zeros caused by noise can be eliminated. The influence of the crossover can obtain a high-accuracy zero-crossover detection result with a simple circuit configuration.

<Third Embodiment> Fig. 7 is a circuit diagram of a zero-crossing detection circuit according to a third embodiment. The difference from the second embodiment shown in FIG. 6 is that the comparison circuit 14 is removed and the comparison circuit 15 is added, and a hysteresis generating circuit 40 is added between the input terminal N2 and the non-inverting input terminal of the comparison circuit 15. . The added elements are configured and connected as follows. In addition, due to the removed elements, the following connection is different from the second embodiment.

The comparison circuit 15 includes two input terminals and one output terminal. Specifically, the comparison circuit 15 includes an inverting input terminal, a non-inverting input terminal, and an output terminal out5. The inverting input terminal of the comparison circuit 15 is connected to the input terminal N1, and the non-inverting input terminal of the comparison circuit 15 is connected to the output terminal of the hysteresis generating circuit 40. An input terminal N2 is connected to an input terminal of the hysteresis generating circuit 40. An output terminal out5 of the comparison circuit 15 is connected to the latch circuit 30. The hysteresis generating circuit 40 includes a hysteresis control terminal HC, and adjusts a hysteresis voltage based on a control signal. The control circuit of the hysteresis control terminal HC is not shown. The other connections and configurations are the same as those of the second embodiment. In the following description, the connection point between the non-inverting input terminal of the comparison circuit 15 and the output terminal of the hysteresis generation circuit 40 is set to N2 ', the voltage at the connection point N2' is set to Vn2 ', and the output terminal out5 The voltage is set to the output voltage Vout5.

Next, an operation of the zero-crossing detection circuit according to the third embodiment will be described. The comparison circuit 15 operates in the same manner as the comparison circuit 10 of the first embodiment. That is, the comparison circuit 15 operates as follows: When the voltage supplied to the non-inverting input terminal is higher than the voltage supplied to the inverting input terminal, a high level is output from the output terminal out5, and in contrast, when it is supplied to the non-inverting input terminal, When the voltage of the phase input terminal is lower than the voltage supplied to the inverting input terminal, a low level is output from the output terminal out5. The hysteresis generating circuit 40 operates as follows: depending on the control state of the hysteresis control terminal HC, it outputs an input voltage directly, or adds it to a voltage Vth1 that is a positive value, and outputs it, or adds a voltage Vth2 that is a negative value Switch between outputs. That is, the output voltage of the hysteresis generation circuit 40 is controlled so that any of Vn2 '= Vn2, or Vn2' = Vn2 + Vth1, or Vn2 '= Vn2 + Vth2. The hysteresis generating circuit which performs such an operation is a well-known technique, for example, it can be implemented by a resistor, a constant current source, and a switching element.

In a state where the output voltage of the hysteresis generation circuit 40 is controlled such that Vn2 '= Vn2, the comparison circuit 15 applies a voltage Vn2' = Vn2 to the non-inverting input terminal and a voltage Vn1 to the inverting input terminal. Compare. Therefore, the same operation as that of the comparison circuit 10 of the first embodiment is performed. If the output voltage Vout5 of the comparison circuit 15 is latched by the latch LT1 according to the clock signal CK1 in this control state, the output voltage Vout0 becomes as shown in FIG. 5 (a) and FIG. 3 (b). Vout0 has the same output voltage.

In addition, in a state where the output voltage of the hysteresis generation circuit 40 is controlled such that Vn2 '= Vn2 + Vth1, the comparison circuit 15 responds to the voltage Vn2' = Vn2 + Vth1 input to the non-inverting input terminal and the input to inverse The voltage Vn1 of the phase input terminal is compared, and in a state where the output voltage of the hysteresis generating circuit 40 is controlled to Vn2 '= Vn2 + Vth2, the comparison circuit 15 pairs the voltage Vn2' = input to the non-inverting input terminal. Vn2 + Vth2 is compared with the voltage Vn1 input to the inverting input terminal. Therefore, operations similar to those of the comparison circuit 12 and the comparison circuit 13 of the first embodiment are performed. In this control state, if the output voltage Vout5 of the comparison circuit 15 is latched by the latch LT2 and the latch LT3 according to the clock signal CK2 and the clock signal CK3, the output voltage Vout1 becomes the same as that shown in FIG. 5 (b ), Vout1 shown in FIG. 5 (c) and FIG. 3 (c) have the same output voltage. The operation of the logic circuit 20 is the same as that of the first embodiment and the second embodiment. The output voltage Vout can perform zero-crossing detection, and the influence of the zero-crossing due to noise can be eliminated.

In the third embodiment, the hysteresis generating circuit 40 is switched to operate. Therefore, as in the second embodiment, the operation speed is slower than that in the first embodiment, but the circuit scale is reduced by reducing the number of comparison circuits. Small advantages.

The operation of the zero-crossing detection circuit according to the third embodiment has been described based on the above, and similarly to the first and second embodiments, the following cases are shown: zero-crossing detection can be performed and the cause can be eliminated. The effect of the zero-crossing caused by noise can obtain a high-accuracy zero-crossing detection result with a simple circuit configuration.

In this description, the voltage is added to the input terminal N2 side for the sake of explanation. However, the voltage may be added to the input terminal N1 side, and the voltage may be added to both the input terminal N1 and the input terminal N2 side. Add up.

In the description of the second embodiment and the third embodiment, the latch circuit is shown as a circuit that holds the output voltage of the comparison circuit. However, as long as it is configured to perform an operation of reading data, it is not necessarily limited to this. Make up.

In the description of the first embodiment, the second embodiment, and the third embodiment, the operation of selecting whether to output the output voltage Vout0 to the voltage Vout is described based on the logic state of the high level or the low level of the output voltage Vout1. However, it is not necessarily limited to this, and it may be set to control the operation of the output voltage Vout according to the change timing of the output Vout0 according to the logic state of the output voltage Vout1. In addition, it can also be set as follows: when the output voltage Vout1 is at a high level, the transition from Vout0 to the low level is output to Vout only once, and when the output voltage Vout1 is at a low level, Vout only outputs the transition from low level to high level of Vout0 only once. In addition, for convenience of explanation, the high level and the low level of each output voltage are clearly recorded according to the operating state, but the high level and the low level may be reversed, and the combination of the high level and the low level may be different. In this description, the voltage Vth1 and the voltage Vth2 are described as the hysteresis voltage of the comparison circuit. However, the configuration is not necessarily limited to this configuration as long as it is a configuration that performs the operation of the comparison circuit described in this description. For example, a configuration in which the reference voltage is supplied to the comparison circuit instead of having a hysteresis voltage in the comparison circuit may be used to adjust the inverse phase of the output voltage Vout1. In addition, the voltage Vth1 and the voltage Vth2 have been described as constant voltages that do not change over time as shown in FIG. 3 (a). However, the magnitude of noise varies depending on the surrounding environment such as the power supply voltage and temperature. In the case of voltage, the voltage Vth1 or the voltage Vth2 may be variably controlled without being a constant voltage. In addition, the hysteresis width of the comparison circuit 10 has been described on the premise of zero unless specifically mentioned. However, in an actual circuit, the hysteresis width may not be zero due to the presence of non-ideal components. Has a tiny value. Even in this case, the effect of the present invention is not impaired. In addition, in a real circuit, in order to eliminate noise caused by fluctuations in the power supply voltage, the comparison circuit 10 may be provided with a hysteresis function with a very small amplitude, or a temporary hysteresis function may be provided, or the comparison may be performed by comparison. The output of the circuit 10 is sampled multiple times to provide a digital filter. In addition, in this description, for convenience of explanation, the input signal is described with particular attention to voltage, but it is obvious that the input signal may also be a current.

<Application Example of Zero Crossing Detection Circuit of the Present Invention> FIG. 8 is a circuit diagram of a first application example in which the zero crossing detection circuit according to the first embodiment of the present invention is applied to a magnetic force sensing device. The signal of the Hall element 1a as a magnetoelectric conversion element is input from the terminal Ba and the terminal Da to the differential amplifier 2a, which is amplified by the differential amplifier 2a, and the output of the differential amplifier 2a is connected to the zero crossing of the present invention. Input terminal N1 and input terminal N2 of the detection circuit. Here, the voltages of the terminal Ba and the terminal Da are VBa and VDa, the signal voltage of the Hall element 1a is VDa-VBa, and the amplification factor of the differential amplifier 2a is G.

The magnitude and sign of the signal voltage VDa-VBa of the Hall element 1a varies according to the direction of the current flowing to the Hall element 1a and the direction of the applied magnetic field, and according to Fleming's left-hand rule. Assuming that the sign of the signal voltage VDa-VBa when a magnetic field is applied in the direction from the front to the depth in the paper is positive, the signal voltage VDa- is applied when a magnetic field is applied in the direction from the depth to the front of the paper. VBa has a negative sign. In addition, the larger the applied magnetic field, the larger the magnitude of the signal voltage VDa-VBa. In addition, in the ideal case where the offset voltage of the Hall element 1a is zero, the signal voltage VDa-VBa when the magnetic field applied to the Hall element 1a is zero is zero. The signal voltage of the Hall element 1a is amplified by the differential amplifier 2a, and becomes Vn2-Vn1 = G × (VDa-VBa) (1). Therefore, Vn2-Vn1 takes a positive value or a negative value or zero depending on the magnetic field applied to the Hall element 1a. That is, with the operation of the zero-crossing detection circuit according to the first embodiment of the present invention, the zero-crossing point of the magnetic field applied to the Hall element 1a can be detected with high accuracy without malfunction due to noise. In other words, in an application for detecting a relative positional relationship between a sensing device and a magnet equipped with a zero-crossing detection circuit according to the first embodiment of the present invention, it is possible to accurately detect a change in the relative position and apply it to the sensing device. The point at which the magnetic field is switched from the S pole to the N pole, or from the N pole to the S pole. Therefore, the application example of the present invention is suitably used in a brushless motor or an encoder that needs to detect the rotation position of the rotor with high accuracy. It can respond to the requirements for high-speed rotation, and it does not occur the erroneous output caused by noise, which is a problem that is conventionally encountered in response to high-speed operation, and accurate rotation control can be realized.

9 is a circuit diagram of a second application example in which the zero-crossing detection circuit according to the first embodiment of the present invention is applied to a magnetic force sensing device. The configuration of the connection of the Hall element 1b and the differential amplifier circuit 2b is the same as the configuration of the connection of the Hall element 1a and the differential amplifier circuit 2a of the first application example. The configuration of the connection of the Hall element 1c and the differential amplifier circuit 2c is also the same as the configuration of the connection of the Hall element 1a and the differential amplifier circuit 2a of the first application example. In contrast to the differential amplifier circuit 2a, which is a differential output, the differential amplifier circuit 2b and the differential amplifier circuit 2c are single-ended outputs. The signal of the Hall element 1b as a magnetoelectric conversion element is input from the terminal Bb and the terminal Db to the differential amplifier 2b, which is amplified by the differential amplifier 2b, and the output of the differential amplifier 2b is connected to the zero-crossing detection circuit of the present invention. Input terminal N1. In addition, the signal of the Hall element 1c as a magnetoelectric conversion element is input from the terminal Bc and the terminal Dc to the differential amplifier 2c, the differential amplifier 2c amplifies it, and the output of the differential amplifier 2c is connected to the zero-crossing of the present invention. Input terminal N2 of the detection circuit. Here, the voltages of the terminals Bb, Db, Bc, and Dc are VBb, VDb, VBc, and VDc, and the signal voltages of the Hall element 1b and Hall element 1c are VDb-VBb and VDc, respectively. -VBc, where the amplification factor of both the differential amplifier 2b and the differential amplifier 2c is G. In this way, the input voltage Vn1 supplied to the input terminal N1 and the input voltage Vn2 supplied to the input terminal N2 are as follows.

Vn1 = G × (VDb-VBb) (2) Vn2 = G × (VDc-VBc) ... (3) The following formula is obtained from the formulas (2) and (3).

Vn2-Vn1 = G × {(VDc-VBc)-(VDb-VBb)} ... (4) Therefore, Vn2-Vn1 takes a positive or negative value depending on the magnetic field applied to Hall element 1b and Hall element 1c. Value or zero. That is, by operating the zero-crossing detection circuit according to the first embodiment of the present invention, it is possible to detect the zero-crossing of the difference between the magnetic fields applied to the Hall elements 1b and 1c with high accuracy without malfunction due to noise. point. That is, the zero-crossing detection can be output when the signals of the two sensing elements are equal, and it can be discerned which signal of the two sensing elements is large and output. This application example is suitably used in applications where a magnetic force sensing device is arranged between a magnet generating a bias magnetic field and a gear including a metal such as iron or a magnet, and the rotation of the gear is detected by the magnetic force sensing device.

In this description, for convenience of explanation, the differential amplifier circuit 2b and the differential amplifier circuit 2c are set as single-ended outputs, but may be set as differential outputs in order to improve noise resistance. In addition, the case where there are two Hall elements has been described, but more than two may be used. For example, it may be set to generate a differential signal 1 of two Hall elements and a differential signal 2 of two Hall elements different from the differential signal 1 and detect the zero crossing of the differential signal 1 and the differential signal 2.

10 is a circuit diagram of a third application example in which a zero-crossing detection circuit according to a second embodiment of the present invention is applied to a magnetic force sensing device. The configuration of the connection of the Hall element 1a and the differential amplifier circuit 2a is the same as the configuration of the connection of the Hall element 1a and the differential amplifier circuit 2a of the first application example. The signal of the Hall element 1a as a magnetoelectric conversion element is input from the terminal Ba and the terminal Da to the differential amplifier 2a, which is amplified by the differential amplifier 2a, and the output of the differential amplifier 2a is connected to the zero-crossing detection circuit of the invention Input terminal N1, input terminal N2. As in the case of the first application example, Vn2-Vn1 takes a positive value, a negative value, or zero depending on the magnetic field applied to the Hall element 1a. That is, by operating the zero-crossing detection circuit according to the second embodiment of the present invention, the zero-crossing point of the magnetic field applied to the Hall element 1a can be detected with high accuracy without malfunction due to noise.

11 is a circuit diagram of a fourth application example in which a zero-crossing detection circuit according to a third embodiment of the present invention is applied to a magnetic force sensing device. The difference from the third application example in FIG. 10 is that the third embodiment is applied instead of the second embodiment. Specifically, the comparison circuit 14 is removed and the comparison circuit 15 is added, and the input terminal N2 and the comparison circuit 15 are A hysteresis generating circuit 40 is added between the non-inverting input terminals. The hysteresis control terminal HC of the hysteresis generation circuit 40 is omitted. Other connections and configurations are the same as those in the third application example.

The signal of the Hall element 1a as a magnetoelectric conversion element is input from the terminal Ba and the terminal Da to the differential amplifier 2a, which is amplified by the differential amplifier 2a, and the output of the differential amplifier 2a is connected to the zero-crossing detection circuit of the present invention. Input terminal N1, input terminal N2. As in the case of the first application example and the second application example, Vn2-Vn1 takes a positive value, a negative value, or zero depending on the magnetic field applied to the Hall element 1a. That is, with the operation of the zero-crossing detection circuit according to the third embodiment of the present invention, the zero-crossing point of the magnetic field applied to the Hall element 1a can be detected with high accuracy without malfunction due to noise.

In this description, the hysteresis generating circuit 40 is connected between the differential amplifier 2a and the comparison circuit 15 for convenience of explanation, but the hysteresis generating circuit 40 may be connected to a side closer to the signal source. Specifically, the hysteresis generating circuit 40 may be connected between the Hall element 1a and the differential amplifier 2a. Since the Hall element generally has a resistance component, no resistance is required in the hysteresis generating circuit 40. Therefore, as an example, the hysteresis generating circuit 40 may include only a constant current source and a switching element, thereby contributing to miniaturization and reducing the temperature by linking the value of the constant current to the resistance value of the Hall element. Induced characteristic shift and other advantages.

An example in which the zero-crossing detection circuit of the present invention is applied to a magnetic force sensing device is shown in FIGS. 8 to 11. In this description, specific examples are shown for the sake of explanation, but the configuration or the sensing element is not necessarily limited, and can be applied to a wide range of semiconductor circuits and sensing circuits. The same applies to the case of the zero-crossing detection circuit of the first embodiment, the second embodiment, and the third embodiment. As an example, it can be combined with a spinning current circuit that eliminates the non-ideal component of the Hall element as a magnetoelectric conversion element, that is, a bias current, and can also be combined with a non-ideal component that eliminates the non-ideal component of the differential amplifier or the comparison circuit. A circuit such as a chopping operation for setting a voltage or a circuit for an auto zero operation. Here, when it is combined with a rotating current circuit or a circuit of a chopping operation or an auto-zero operation, the signal processing is discrete time rather than continuous time. Therefore, the comparison circuits 10 to 15 The respective outputs are output from the output terminal out by calculation of the combination circuit. As shown in the second embodiment or the third embodiment, it is suitable to be combined with a sequential circuit such as a latch circuit. In addition, in addition to a magnetoelectric conversion element, it can also be used as a zero-crossing detection circuit of a sensing element such as a temperature sensing element, an acceleration sensing element, and a pressure sensing element.

1a, 1b, 1c‧‧‧Hall element
2a, 2b, 2c‧‧‧ Differential amplifier circuit / differential amplifier
10, 11, 12, 13, 14, 15‧‧‧ comparison circuits
20‧‧‧Logic Circuit
30‧‧‧ latch circuit
40‧‧‧hysteresis generating circuit
50‧‧‧ Operational Amplifier
51‧‧‧Comparative signal forming circuit
Ba, Da, Bb, Db, Bc, Dc‧‧‧ terminals
C‧‧‧Voltage
C‧‧‧Clock terminal
Ca‧‧‧Capacitor / Capacitor
CK1, CK2, CK3‧‧‧ clock signal
D‧‧‧Data input terminal
fa‧‧‧zero crossing detection signal
h‧‧‧ comparative signal
HC‧‧‧Control terminal / hysteresis control terminal
Hi‧‧‧High level
Lo‧‧‧ Low level
LT1, LT2, LT3 ‧‧‧ latches
ns‧‧‧noise
N1, N2‧‧‧ input terminals
N2'‧‧‧ connection point
out, out0, out1, out2, out3, out4, out5‧‧‧ output terminals
Q‧‧‧Data output terminal
R10, R11‧‧‧ resistance
S‧‧‧detected signal
t‧‧‧ time passed
t1, t2, t3‧‧‧time
Vn1, Vn2‧‧‧ input voltage
Vn2-Vn1‧‧‧Input voltage difference
Vout‧‧‧Output voltage / voltage
Vout0, Vout1, Vout4, Vout5‧‧‧ output voltage
Vth1, Vth2, Vn2'‧‧‧ voltage

FIG. 1 is a circuit diagram of a zero-crossing detection circuit according to the first embodiment. FIG. 2 is a diagram showing operations of each element of the zero-crossing detection circuit according to the first embodiment. FIG. 3 is a diagram showing the operation of the zero-crossing detection circuit according to the first embodiment. Fig. 4 is a diagram showing another example of a zero-crossing detection circuit according to the first embodiment. FIG. 5 is a diagram showing the operation of each element in another example of the zero-crossing detection circuit according to the first embodiment. Fig. 6 is a circuit diagram of a zero-crossing detection circuit according to a second embodiment. Fig. 7 is a circuit diagram of a zero-crossing detection circuit according to a third embodiment. 8 is a circuit diagram of a first application example in which the zero-crossing detection circuit of the first embodiment is applied to a magnetic force sensing device. 9 is a circuit diagram of a second application example in which the zero-crossing detection circuit of the first embodiment is applied to a magnetic force sensing device. 10 is a circuit diagram of a third application example in which the zero-crossing detection circuit of the second embodiment is applied to a magnetic force sensing device. 11 is a circuit diagram of a fourth application example in which the zero-crossing detection circuit of the third embodiment is applied to a magnetic force sensing device. FIG. 12 is a circuit diagram of a conventional zero-crossing detection circuit. FIG. 13 is a diagram showing the operation of a conventional zero-crossing detection circuit.

10, 11‧‧‧ comparison circuit

20‧‧‧Logic Circuit

N1, N2‧‧‧ input terminals

out, out0, out1‧‧‧ output terminals

Claims (10)

A zero-crossing detection circuit, comprising: a first comparison circuit that receives a first input signal and a second input signal; a second comparison circuit that receives the first input signal and the second input signal, And has a hysteresis function; and a logic circuit, the first comparison circuit outputs a first comparison result of the first input signal and the second input signal, and the second comparison circuit outputs the first input signal and Based on the second comparison result of the second input signal, the logic circuit determines whether to reflect the first comparison result to the output based on the second comparison result. The zero-crossing detection circuit according to item 1 of the scope of patent application, wherein when the second comparison result is the first level and the output of the logic circuit is the first output level, that is, the first condition, The first comparison result shifts from the first level to the second level, and the output of the logic circuit shifts to the second output level, and the second comparison result is the second level and When the output of the logic circuit is the second output level, that is, the second condition, the transition of the first comparison result from the second level to the first level is performed by the first comparison result. The output transitions to the first output level, and the output of the logic circuit does not change except for the first condition and the second condition. The zero-crossing detection circuit according to item 1 of the scope of patent application, wherein the hysteresis width of the first comparison circuit is smaller than that of the hysteresis function of the second comparison circuit. . The zero-crossing detection circuit according to any one of claims 1 to 3, wherein the first comparison circuit and the second comparison circuit include the same comparison circuit, and the zero-crossing detection The circuit includes means for switching the operating states of the first comparison circuit and the second comparison circuit. The zero-crossing detection circuit according to any one of claims 1 to 3, wherein the first comparison circuit and the second comparison circuit include the same comparison circuit, and the zero-crossing detection The circuit includes a voltage adding unit that switches a voltage added to one or both of the first input signal and the second input signal. A zero-crossing detection circuit includes: a first comparison result signal showing the magnitude of a first input signal and a second input signal; a second comparison result signal showing the first input signal and the first input signal The difference between the two input signals is greater than or less than a prescribed value, and the zero-crossing detection circuit outputs a signal based on the first comparison result signal to an output signal based on the second comparison result signal. According to the zero-crossing detection circuit according to any one of claims 1 to 3 and 6, the first input signal and the second input signal are voltages. The zero-crossing detection circuit according to any one of claims 1 to 3 and 6, wherein the first input signal and the second input signal are currents. A sensing device, comprising: a sensing element that outputs a signal according to an intensity of an applied physical quantity; and a zero-crossing detection circuit as described in items 1 to 6 of the scope of patent application for performing the sensing Zero-crossing detection of the signal output from the test element. The sensing device according to item 9 of the scope of patent application, wherein the first input signal is an output signal of a first sensing element, and the second input signal is an output signal of a second sensing element.