TWI669837B - Light emitting device - Google Patents

Light emitting device Download PDF

Info

Publication number
TWI669837B
TWI669837B TW104107889A TW104107889A TWI669837B TW I669837 B TWI669837 B TW I669837B TW 104107889 A TW104107889 A TW 104107889A TW 104107889 A TW104107889 A TW 104107889A TW I669837 B TWI669837 B TW I669837B
Authority
TW
Taiwan
Prior art keywords
type side
electrode pad
light
side electrode
type
Prior art date
Application number
TW104107889A
Other languages
Chinese (zh)
Other versions
TW201603335A (en
Inventor
梅津典雄
松村孝
Original Assignee
日商迪睿合股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日商迪睿合股份有限公司 filed Critical 日商迪睿合股份有限公司
Publication of TW201603335A publication Critical patent/TW201603335A/en
Application granted granted Critical
Publication of TWI669837B publication Critical patent/TWI669837B/en

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/38Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04026Bonding areas specifically adapted for layer connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0556Disposition
    • H01L2224/05568Disposition the whole external layer protruding from the surface
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27Manufacturing methods
    • H01L2224/273Manufacturing methods by local deposition of the material of the layer connector
    • H01L2224/2731Manufacturing methods by local deposition of the material of the layer connector in liquid form
    • H01L2224/27312Continuous flow, e.g. using a microsyringe, a pump, a nozzle or extrusion
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29005Structure
    • H01L2224/29007Layer connector smaller than the underlying bonding area
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/29198Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29199Material of the matrix
    • H01L2224/2929Material of the matrix with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/29198Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29199Material of the matrix
    • H01L2224/29294Material of the matrix with a principal constituent of the material being a liquid not provided for in groups H01L2224/292 - H01L2224/29291
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/29198Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298Fillers
    • H01L2224/29299Base material
    • H01L2224/293Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/3201Structure
    • H01L2224/32012Structure relative to the bonding area, e.g. bond pad
    • H01L2224/32013Structure relative to the bonding area, e.g. bond pad the layer connector being larger than the bonding area, e.g. bond pad
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32104Disposition relative to the bonding area, e.g. bond pad
    • H01L2224/32105Disposition relative to the bonding area, e.g. bond pad the layer connector connecting bonding areas being not aligned with respect to each other
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/32227Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the layer connector connecting to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319Arrangement of the layer connectors prior to mounting
    • H01L2224/83192Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/832Applying energy for connecting
    • H01L2224/83201Compression bonding
    • H01L2224/83203Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83399Material
    • H01L2224/834Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/83438Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/83444Gold [Au] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838Bonding techniques
    • H01L2224/8385Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83851Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester being an anisotropic conductive adhesive
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/27Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00015Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed as prior art
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/12Passive devices, e.g. 2 terminal devices
    • H01L2924/1204Optical Diode
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/12Passive devices, e.g. 2 terminal devices
    • H01L2924/1204Optical Diode
    • H01L2924/12041LED
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/12Passive devices, e.g. 2 terminal devices
    • H01L2924/1204Optical Diode
    • H01L2924/12044OLED
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008Processes
    • H01L2933/0033Processes relating to semiconductor body packages
    • H01L2933/0066Processes relating to semiconductor body packages relating to arrangements for conducting electric current to or from the semiconductor body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/64Heat extraction or cooling elements
    • H01L33/641Heat extraction or cooling elements characterized by the materials

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Led Device Packages (AREA)
  • Led Devices (AREA)
  • Wire Bonding (AREA)

Abstract

本發明於應使用各向異性導電接著膏30將發光元件10無凸塊(bumpless)地覆晶構裝在形成於基板20上之n型側、n型側電極墊21、22的發光裝置100中,可同時解決抑制短路與提高散熱效率之兩個課題。 The present invention is a light-emitting device 100 in which the light-emitting element 10 is bump-mounted on the n-type side, n-type side electrode pads 21, 22 formed on the substrate 20, using the anisotropic conductive adhesive paste 30. In the middle, it can solve two problems of suppressing short circuit and improving heat dissipation efficiency at the same time.

於使用各向異性導電接著膏30將發光元件10無凸塊地覆晶構裝在形成於基板20上之n型側、p型側電極墊21、22而成的發光裝置100中,使n型側、p型側電極墊21、22之寬度與發光元件10之寬度同等或較其窄。 In the light-emitting device 100 in which the light-emitting element 10 is formed on the n-type side and the p-type side electrode pads 21 and 22 formed on the substrate 20 without bumps using the anisotropic conductive adhesive paste 30, n is made. The widths of the side and p-type side electrode pads 21, 22 are equal to or narrower than the width of the light-emitting element 10.

Description

發光裝置 Illuminating device

本發明係關於一種利用各向異性導電接著膏將發光二極體(LED)晶片等發光元件覆晶構裝於基板而成之發光裝置。 The present invention relates to a light-emitting device in which a light-emitting element such as a light-emitting diode (LED) wafer is coated on a substrate by an anisotropic conductive paste.

於將發光二極體(LED)晶片等發光元件構裝於基板之情形時,與Au打線法相比,廣泛應用可期待光提取效率或散熱特性之提高之覆晶法(專利文獻1)。然而,LED晶片等發光元件,通常係於大口徑之半導體晶圓組裝多個發光元件後於切晶(dicing)步驟中被切斷,從而製成作為發光元件之半導體晶片,存在如下問題:若含有導電粒子之各向異性導電接著劑附著於半導體晶片之側面,則因多個導電粒子聚集而成之塊會導致半導體層與電極電連接,而產生短路不良。 When a light-emitting element such as a light-emitting diode (LED) wafer is mounted on a substrate, a flip chip method in which light extraction efficiency or heat dissipation characteristics are expected to be improved is widely used as compared with the Au wire bonding method (Patent Document 1). However, a light-emitting element such as an LED chip is usually formed by dicing a plurality of light-emitting elements on a semiconductor wafer having a large diameter and then cutting it in a dicing step to form a semiconductor wafer as a light-emitting element. When an anisotropic conductive adhesive containing conductive particles is attached to the side surface of the semiconductor wafer, a block in which a plurality of conductive particles are aggregated causes electrical connection between the semiconductor layer and the electrode, resulting in short-circuit failure.

因此,藉由在發光元件或基板預先形成凸塊(bump)而進行覆晶構裝,從而防止產生短路。具體而言,如圖3A(發光裝置之俯視圖)、圖3B(自圖3A之A方向觀察之發光裝置之側視圖)所示,將發光裝置110之晶片本體131背面之n型側元件電極111與p型側元件電極112分別經由各向異性導電接著膏130熱壓接於形成有金凸塊Bp之基板120之表面之n型側電極墊121與p型側電極墊122,藉此進行覆晶構裝。於該情形時,為了確保導通可靠性,一般而言,n型側電極墊121之寬度L1與p型側電極 墊122之寬度L2係構成為大於晶片本體131之寬度L0,且將凸出部分之寬度L1a、L2a、L1b、L2b設為30μm以上且50μm以下程度。 Therefore, the flip-chip mounting is performed by forming a bump in advance on the light-emitting element or the substrate, thereby preventing occurrence of a short circuit. Specifically, as shown in FIG. 3A (a plan view of the light-emitting device) and FIG. 3B (a side view of the light-emitting device viewed from the direction A of FIG. 3A), the n-type side element electrode 111 on the back surface of the wafer body 131 of the light-emitting device 110 is shown. The p-type side element electrode 112 is thermally bonded to the n-type side electrode pad 121 and the p-type side electrode pad 122 which are formed on the surface of the substrate 120 on which the gold bumps Bp are formed via the anisotropic conductive paste 130, respectively. Crystal structure. In this case, in order to ensure the conduction reliability, in general, the width L1 of the n-type side electrode pad 121 and the p-type side electrode The width L2 of the pad 122 is configured to be larger than the width L0 of the wafer main body 131, and the widths L1a, L2a, L1b, and L2b of the convex portions are set to be about 30 μm or more and 50 μm or less.

[專利文獻1]日本特開2007-123613號公報 [Patent Document 1] Japanese Patent Laid-Open Publication No. 2007-123613

然而,於如圖3A般使用凸塊而構成之發光裝置之情形時,雖能夠抑制短路,但金凸塊形成成本非常高,又,由於發出光與熱之發光元件之發光層與基板之距離遠,故而存在散熱特性下降(換言之,熱阻增大)之問題。因此,亦考慮將發光裝置設為無凸塊(bumpless)構造,但該構造雖然有無需金凸塊形成成本之優點與散熱特性提高之優點,但如先前般擔心產生短路。如此,現狀為正尋求同時解決抑制短路與提高散熱特性之兩個課題的無凸塊構造之發光裝置。 However, in the case of a light-emitting device formed by using a bump as shown in FIG. 3A, although the short circuit can be suppressed, the gold bump is formed at a very high cost, and the distance between the light-emitting layer of the light-emitting element that emits light and heat and the substrate is large. Far, there is a problem that the heat dissipation characteristics are degraded (in other words, the thermal resistance is increased). Therefore, it is also considered to make the light-emitting device a bumpless structure. However, this structure has the advantage of not requiring the cost of gold bump formation and the improvement of heat dissipation characteristics, but it is feared that a short circuit occurs as before. As described above, the current state of the art is a light-emitting device having no bump structure that simultaneously solves two problems of suppressing a short circuit and improving heat dissipation characteristics.

本發明之目的在於欲解決習知技術之問題,於應使用各向異性導電接著膏將發光元件無凸塊地覆晶構裝在形成於基板上之電極墊的發光裝置中,可同時解決抑制短路與提高散熱特性之兩個課題。 The object of the present invention is to solve the problems of the prior art, and an anisotropic conductive adhesive paste should be used to form a light-emitting device without bumps on a light-emitting device of an electrode pad formed on a substrate, and the suppression can be simultaneously solved. Short-circuit and two issues of improving heat dissipation characteristics.

本發明人等發現,於使用各向異性導電接著膏將發光元件無凸塊地覆晶構裝在形成於基板上之電極墊而成的發光裝置中,藉由使基板上之電極墊之寬度與發光元件之寬度同等或較其窄,而將自基板上之電極墊與發光元件之間溢出之各向異性導電接著膏保持於較電極墊與發光元件之間隙寬之發光元件與基板表面之間隙,因此可防止將P層與N層之間短路,並且由於係無凸塊地進行覆晶構裝者,故而可壓縮製造成本,且可提 高散熱特性(降低熱阻),從而完成了本發明。 The present inventors have found that the width of the electrode pad on the substrate is made by using an anisotropic conductive paste to laminate the light-emitting element without bumps on the electrode pad formed on the substrate. It is equal to or narrower than the width of the light-emitting element, and the anisotropic conductive paste which overflows between the electrode pad on the substrate and the light-emitting element is held by the light-emitting element and the surface of the substrate which are wider than the gap between the electrode pad and the light-emitting element. a gap, thereby preventing short circuit between the P layer and the N layer, and since the flip chip is mounted without bumps, the manufacturing cost can be compressed, and The present invention has been completed by high heat dissipation characteristics (reducing thermal resistance).

即,本發明係一種發光裝置,其係使用各向異性導電接著膏 將具有半導體之晶片本體之發光元件無凸塊地覆晶構裝在形成於基板上之電極墊而成者,其特徵在於:電極墊之寬度與上述晶片本體之寬度同等或較其窄。 That is, the present invention is a light-emitting device which uses an anisotropic conductive paste A light-emitting element having a semiconductor wafer main body is formed by a bump-free flip-chip mounting on an electrode pad formed on a substrate, wherein the width of the electrode pad is equal to or narrower than the width of the wafer body.

又,本發明係一種發光裝置,其中,上述晶片本體為發光二極體晶片。 Moreover, the present invention is a light-emitting device wherein the wafer body is a light-emitting diode wafer.

又,本發明係一種發光裝置,其中,於將上述晶片本體之寬度設為100之情形時,上述電極墊之寬度為80%以上且100%以下。 Moreover, the present invention is a light-emitting device in which the width of the electrode pad is 80% or more and 100% or less when the width of the wafer body is 100.

又,本發明係一種發光裝置,其中,上述電極墊之寬度方向之邊緣與上述晶片本體之寬度方向之邊緣的間隔為10μm以上且40μm以下。 Moreover, the present invention is a light-emitting device in which the distance between the edge of the electrode pad in the width direction and the edge of the wafer body in the width direction is 10 μm or more and 40 μm or less.

又,本發明係一種發光裝置,於發光元件與搭載裝置之間配置有含有導電粒子之各向異性導電接著膏,上述發光元件藉由上述各向異性導電接著膏被設置於上述搭載裝置,上述搭載裝置具有:基板、及配置於上述基板上之n型側電極墊與p型側電極墊;上述發光元件具有:平面形狀為四邊形形狀之晶片本體、及設置於上述晶片本體之p型側元件電極與n型側元件電極;於上述晶片本體之內部,設置有p型區域與n型區域,形成有pn接面,上述p型側元件電極經由上述導電粒子而電連接於上述p型區域,上述n型側元件電極經由上述導電粒子而電連接於上述n型區域,上述p型側電極墊之表面與上述n型側電極墊之表面位於上述基板表面之上方,上述p型側電極墊與上述n型側電極墊係形成為寬度為固定值之帶狀,上述p型側電極墊之前端與上述n型側電極墊之前端位於上述晶片本體之正下方即正下方區域內,與上述p型側電極墊之前端為相反側之部分、及與 上述n型側電極墊之前端為相反側之部分位於上述正下方區域之外側,上述p型側電極墊之上述寬度係設為上述晶片本體之位於上述p型側電極墊之正上方的第一邊之長度以下之長度,上述n型側電極墊之上述寬度係設為上述晶片本體之位於上述n型側電極墊之正上方的第二邊之長度以下之長度。 Further, the present invention provides a light-emitting device in which an anisotropic conductive paste containing conductive particles is disposed between a light-emitting element and a mounting device, and the light-emitting element is provided on the mounting device by the anisotropic conductive paste. The mounting device includes a substrate and an n-type side electrode pad and a p-type side electrode pad disposed on the substrate, and the light-emitting element includes a wafer body having a quadrangular planar shape and a p-type side member provided on the wafer body An electrode and an n-type side element electrode; a p-type region and an n-type region are provided inside the wafer body, and a pn junction surface is formed, and the p-type side element electrode is electrically connected to the p-type region via the conductive particles; The n-type side element electrode is electrically connected to the n-type region via the conductive particles, and a surface of the p-type side electrode pad and a surface of the n-type side electrode pad are located above the surface of the substrate, and the p-type side electrode pad is The n-type side electrode pad is formed in a strip shape having a fixed width, and the front end of the p-type side electrode pad and the front end of the n-type side electrode pad are located I.e., the bulk of the wafer directly below the region below n, and the p-side pad of the distal end of the electrode of the opposite side portions, and with The portion on the opposite side of the front end of the n-type side electrode pad is located outside the region directly below, and the width of the p-type side electrode pad is the first of the wafer body located directly above the p-type side electrode pad The length of the n-type side electrode pad is equal to or less than the length of the second side of the wafer main body directly above the n-type side electrode pad.

又,本發明係一種發光裝置,其中,上述p型側電極墊之上述寬度係設為較上述晶片本體之位於上述p型側電極墊之正上方的第一邊之長度短,上述n型側電極墊之上述寬度係設為較上述晶片本體之位於上述n型側電極墊之正上方的第二邊之長度短,於上述正下方區域內之上述p型側電極墊與上述n型側電極墊之外側的上述發光元件與上述基板之間,配置有自上述發光元件與上述p型側電極墊之間溢出之上述各向異性導電接著膏、及自上述發光元件與上述n型側電極墊之間溢出之上述各向異性導電接著膏。 Furthermore, the present invention is a light-emitting device, wherein the width of the p-type side electrode pad is shorter than a length of a first side of the wafer body directly above the p-type side electrode pad, the n-type side The width of the electrode pad is shorter than the length of the second side of the wafer body directly above the n-type side electrode pad, and the p-type side electrode pad and the n-type side electrode in the region directly below An anisotropic conductive paste that overflows between the light-emitting element and the p-type side electrode pad, and the light-emitting element and the n-type side electrode pad are disposed between the light-emitting element on the outer side of the pad and the substrate. The above anisotropic conductive paste is overflowed between the pastes.

又,本發明係一種發光裝置,其中,上述第一邊與上述第二邊係以相同長度平行地配置,上述第一邊之兩端位於上述p型側電極墊之正上方之外側,且上述第二邊之兩端位於上述n型側電極墊之正上方之外側。 Furthermore, the present invention is a light-emitting device, wherein the first side and the second side are arranged in parallel in the same length, and both ends of the first side are located on an outer side directly above the p-type side electrode pad, and the above Both ends of the second side are located on the outer side directly above the n-type side electrode pad.

藉由使用各向異性導電接著膏將發光元件無凸塊地覆晶構裝在形成於基板上之電極墊而成的本發明之發光裝置,電極墊之寬度係構成為與發光元件之寬度同等或較其窄。因此,可抑制發生短路,並且可同時實現散熱特性之提高(熱阻之降低)。 The light-emitting device of the present invention in which the light-emitting element is laminated on the electrode pad formed on the substrate by using an anisotropic conductive paste, and the width of the electrode pad is configured to be equal to the width of the light-emitting element. Or narrower than it. Therefore, occurrence of a short circuit can be suppressed, and an improvement in heat dissipation characteristics (reduction in thermal resistance) can be simultaneously achieved.

又,各向異性導電接著膏由於不附著於發光元件之側面,故而不會妨 礙自發光元件之側面放射之光之發射。 Moreover, since the anisotropic conductive paste does not adhere to the side surface of the light-emitting element, it does not matter. The emission of light emitted from the side of the light-emitting element.

100‧‧‧發光裝置 100‧‧‧Lighting device

10‧‧‧發光元件 10‧‧‧Lighting elements

11‧‧‧n型側元件電極 11‧‧‧n type side element electrode

12‧‧‧p型側元件電極 12‧‧‧p-type side element electrode

20‧‧‧基板 20‧‧‧Substrate

21‧‧‧n型側電極墊 21‧‧‧n type side electrode pad

22‧‧‧p型側電極墊 22‧‧‧p type side electrode pad

30‧‧‧各向異性導電接著膏 30‧‧‧ Anisotropic conductive paste

31‧‧‧晶片本體 31‧‧‧ Chip Ontology

Bp‧‧‧金凸塊 Bp‧‧ gold bumps

L0‧‧‧發光元件之寬度 L0‧‧‧Width of light-emitting elements

L1‧‧‧n型側電極墊之寬度 L1‧‧‧n type side electrode pad width

L2‧‧‧p型側電極墊之寬度 L2‧‧‧p type side electrode pad width

圖1A係本發明之發光裝置之俯視圖。 Fig. 1A is a plan view of a light-emitting device of the present invention.

圖1B係自圖1A之A方向觀察之本發明之發光裝置之側視圖。 Fig. 1B is a side view of the light-emitting device of the present invention as seen from the direction A of Fig. 1A.

圖2A係用以說明在搭載基板上之各向異性導電接著膏配置有發光元件之狀態的局部放大剖視圖。 2A is a partially enlarged cross-sectional view for explaining a state in which a light-emitting element is disposed on an anisotropic conductive paste on a mounting substrate.

圖2B係用以說明按壓發光元件時之狀態之局部放大剖視圖。 Fig. 2B is a partially enlarged cross-sectional view for explaining a state in which a light emitting element is pressed.

圖2C係用以說明p型側、n型側元件電極與p型側、n型側基板電極藉由導電粒子而電連接之狀態的局部放大剖視圖。 2C is a partially enlarged cross-sectional view for explaining a state in which the p-side and n-type side element electrodes are electrically connected to the p-type side and the n-type side substrate electrode by conductive particles.

圖2D係用以說明習知技術之發光裝置之元件本體之側面所附著之各向異性導電接著膏的放大圖。 Fig. 2D is an enlarged view showing an anisotropic conductive paste attached to the side of the element body of the light-emitting device of the prior art.

圖3A係習知之發光裝置之俯視圖。 3A is a top plan view of a conventional light emitting device.

圖3B係自圖3A之A方向觀察之習知之發光裝置之側視圖。 Fig. 3B is a side view of a conventional light-emitting device as seen from the direction A of Fig. 3A.

以下,一面參照圖式,一面對本發明之發光裝置進行詳細說明。 Hereinafter, a light-emitting device of the present invention will be described in detail with reference to the drawings.

圖1A係本發明之發光裝置100之俯視圖,圖1B係自圖1A之A方向觀察之本發明之發光裝置100之側視圖。本發明之發光裝置100係將發光元件10無凸塊地覆晶構裝於基板20上而成之發光裝置。詳細而言,發光元件10具有晶片本體31、n型側元件電極11、及p型側元件電極12,且n型側元件電極11與p型側元件電極12係配置於晶片本體31上。 1A is a plan view of a light-emitting device 100 of the present invention, and FIG. 1B is a side view of the light-emitting device 100 of the present invention as seen from the direction A of FIG. 1A. The light-emitting device 100 of the present invention is a light-emitting device in which the light-emitting element 10 is laminated on the substrate 20 without bumps. Specifically, the light-emitting element 10 has a wafer body 31, an n-type side element electrode 11, and a p-type side element electrode 12, and the n-type side element electrode 11 and the p-type side element electrode 12 are disposed on the wafer body 31.

於基板20上,配置n型側電極墊21與p型側電極墊22,由 基板20、n型側電極墊21、及p型側電極墊22形成搭載裝置18。n型側元件電極11與p型側元件電極12係分別經由經硬化之各向異性導電接著膏30而各向異性導電連接於搭載裝置18之n型側電極墊21與p型側電極墊22。 On the substrate 20, an n-type side electrode pad 21 and a p-type side electrode pad 22 are disposed, The substrate 20, the n-type side electrode pad 21, and the p-type side electrode pad 22 form a mounting device 18. The n-type side element electrode 11 and the p-type side element electrode 12 are anisotropically electrically connected to the n-type side electrode pad 21 and the p-type side electrode pad 22 of the mounting device 18 via the cured anisotropic conductive paste 30, respectively. .

對該發光裝置100之製造步驟進行說明。 The manufacturing steps of the light-emitting device 100 will be described.

各向異性導電接著膏30中含有導電粒子36,若將未硬化之各向異性導電接著膏稱為原液,則於在搭載裝置18之表面中位於要固定於搭載裝置18之發光元件10之正背面的n型側電極墊21上與p型側電極墊22上配置原液後,使發光元件10之形成有n型側元件電極11與p型側元件電極12之面與配置於基板20上之原液相對,從而使發光元件10之n型側元件電極11接觸於n型側電極墊21上之原液,使p型側元件電極12接觸於p型側電極墊22上之原液。 The anisotropic conductive paste 30 contains the conductive particles 36. When the uncured anisotropic conductive paste is referred to as a stock solution, the light-emitting element 10 to be fixed to the mounting device 18 is placed on the surface of the mounting device 18. After the stock solution is placed on the n-type side electrode pad 21 on the back surface and the p-type side electrode pad 22, the surface of the light-emitting element 10 on which the n-type side element electrode 11 and the p-type side element electrode 12 are formed is disposed on the substrate 20. The stock solution is opposed to each other such that the n-type side element electrode 11 of the light-emitting element 10 contacts the stock solution on the n-type side electrode pad 21, and the p-type side element electrode 12 is brought into contact with the stock solution on the p-type side electrode pad 22.

圖2A表示該狀態,符號28表示原液,於原液28之接著成分29中分散有導電粒子36。基板20係載置於台51上。 2A shows the state, and reference numeral 28 denotes a stock solution in which conductive particles 36 are dispersed in the subsequent component 29 of the stock solution 28. The substrate 20 is placed on the stage 51.

此處,於在原液28上載置有發光元件10時,若設為晶片本體31之底面與基板20之表面平行,則圖2A中之符號H1表示基板20之表面39至晶片本體31之底面38之距離即晶片本體31之底面38距基板20之表面39之高度。符號Wa、Wb為n型側電極墊21與p型側電極墊22在與基板20平行之方向上距晶片本體31之邊緣的距離。 Here, in the liquid 28 in which the light emitting element 10, if the wafer is set parallel to the bottom surface 31 of the body surface of the substrate 20, the middle of the bottom face 2A symbol H denotes a surface of the substrate main body 20 of the wafer 39 to 31 of FIG. The distance 38 is the height of the bottom surface 38 of the wafer body 31 from the surface 39 of the substrate 20. Symbols Wa and Wb are distances of the n-type side electrode pad 21 and the p-type side electrode pad 22 from the edge of the wafer body 31 in a direction parallel to the substrate 20.

n型側元件電極11與p型側元件電極12之厚度相等,又,n型側電極墊21與p型側電極墊22之厚度亦相等,該晶片本體31之底面 38之高度H1係將n型側電極墊21與p型側電極墊22之厚度P1、由n型側或p型側電極墊21、22與n型或p型側元件電極11、12夾著之原液28之厚度Q1、及n型側元件電極11與p型側元件電極12之厚度E1合計所得之值。 The thickness of the n-type side element electrode 11 and the p-type side element electrode 12 are equal, and the thickness of the n-type side electrode pad 21 and the p-type side electrode pad 22 are also equal, and the height H 1 of the bottom surface 38 of the wafer body 31 will be The thickness P 1 of the n-type side electrode pad 21 and the p-type side electrode pad 22, and the thickness of the stock solution 28 sandwiched between the n-type side or p-type side electrode pads 21, 22 and the n-type or p-type side element electrodes 11, 12 The total value of the thickness E 1 of Q 1 and the n-type side element electrode 11 and the p-type side element electrode 12 is obtained.

n型側元件電極11與p型側元件電極12係對形成於晶片本 體31之表面之導電性薄膜進行蝕刻而形成,若設為n型側元件電極11與p型側元件電極12之厚度E1較n型側電極墊21與p型側電極墊22之厚度P1薄,且於高度方向之距離計算上可忽視,則搭載裝置18之表面39至n型側元件電極11或p型側元件電極12之表面之距離(H1-E1)為與基板20之表面39至晶片本體31之底面38之高度H1相同之值。 The n-type side element electrode 11 and the p-type side element electrode 12 are formed by etching a conductive thin film formed on the surface of the wafer main body 31, and the thickness E of the n-type side element electrode 11 and the p-type side element electrode 12 is set. 1 is thinner than the thickness P 1 of the n-type side electrode pad 21 and the p-type side electrode pad 22, and the distance in the height direction is calculated negligibly, and the surface 39 to the n-type side element electrode 11 or the p-type side of the mounting device 18 is The distance (H 1 -E 1 ) of the surface of the element electrode 12 is the same value as the height H 1 of the surface 39 of the substrate 20 to the bottom surface 38 of the wafer body 31.

再者,亦可於發光元件10之n型側元件電極11上與p型側 元件電極12上配置原液28,且使n型側電極墊21接觸於n型側元件電極11上之原液28,使p型側電極墊22接觸於n型側元件電極12上之原液28。 Furthermore, it can also be on the n-type side element electrode 11 of the light-emitting element 10 and the p-side The stock solution 28 is placed on the element electrode 12, and the n-type side electrode pad 21 is brought into contact with the stock solution 28 on the n-type side element electrode 11, and the p-type side electrode pad 22 is brought into contact with the stock solution 28 on the n-type side element electrode 12.

繼而,將發光元件10與基板20相互按壓。此處,如圖2B所示,藉由按壓構件52將發光元件10向基板20按壓,此時,一面將原液28自n型側元件電極11與n型側電極墊21之間、及p型側元件電極12與p型側電極墊22之間擠出,一面使n型側元件電極11與p型側元件電極12分別接近n型側電極墊21與p型側電極墊22。此時之高度H2變得較載置發光元件10時之高度H1低,n型側電極墊21與p型側電極墊22上之原液28之厚度Q2較原本之厚度Q1減少。 Then, the light-emitting element 10 and the substrate 20 are pressed against each other. Here, as shown in FIG. 2B, the light-emitting element 10 is pressed against the substrate 20 by the pressing member 52. At this time, the stock solution 28 is applied between the n-type side element electrode 11 and the n-type side electrode pad 21, and the p type. The n-type side element electrode 11 and the p-type side element electrode 12 are respectively brought close to the n-type side electrode pad 21 and the p-type side electrode pad 22 while being extruded between the side element electrode 12 and the p-type side electrode pad 22. At this time, the height H 2 becomes lower than the height H 1 when the light-emitting element 10 is placed, and the thickness Q 2 of the stock solution 28 on the n-type side electrode pad 21 and the p-type side electrode pad 22 is smaller than the original thickness Q 1 .

然後,如圖2C所示,n型側元件電極11經由導電粒子36而與n型側電極墊21接觸,p型側元件電極12經由導電粒子36而與p型 側電極墊22接觸。 Then, as shown in FIG. 2C, the n-type side element electrode 11 is in contact with the n-type side electrode pad 21 via the conductive particles 36, and the p-type side element electrode 12 is p-type via the conductive particles 36. The side electrode pads 22 are in contact.

此時,由於導電粒子36之大小小至可忽視之程度,故而於使n型側或p型側元件電極11、12與n型側或p型側電極墊21、22經由導電粒子36連接之情形時,可認為與直接接觸之情形相同,原液28之厚度Q3為零。若忽視n型側或p型側元件電極11、12之厚度E1,則發光元件10與基板20之間之距離即高度H3成為n型側電極墊21與p型側電極墊22之厚度P1At this time, since the size of the conductive particles 36 is as small as negligible, the n-type side or p-type side element electrodes 11, 12 and the n-type side or p-type side electrode pads 21, 22 are connected via the conductive particles 36. In the case, it can be considered that the thickness Q 3 of the stock solution 28 is zero as in the case of direct contact. When the thickness E 1 of the n-type side or the p-type side element electrodes 11 and 12 is ignored, the distance H 3 between the light-emitting element 10 and the substrate 20 becomes the thickness of the n-type side electrode pad 21 and the p-type side electrode pad 22 . P 1 .

原液28之接著成分29含有熱硬化成分,若於n型側元件電 極11與p型側元件電極12經由導電粒子36而接觸於n型側電極墊21與p型側電極墊22的狀態下,對發光元件10與基板20進行加熱而使原液28升溫,則形成硬化之各向異性導電接著膏30,而將發光元件10與基板20相互固定,從而獲得藉由導電粒子36將n型側或p型側元件電極11、12與n型側或p型側電極墊21、22分別電連接的發光裝置100。 The subsequent component 29 of the stock solution 28 contains a thermosetting component, if the n-type side component is electrically When the pole 11 and the p-type side element electrode 12 are in contact with the n-type side electrode pad 21 and the p-type side electrode pad 22 via the conductive particles 36, the light-emitting element 10 and the substrate 20 are heated to raise the temperature of the stock solution 28, thereby forming The hardened anisotropic conductive adhesive paste 30, and the light-emitting element 10 and the substrate 20 are fixed to each other, thereby obtaining the n-side or p-type side element electrodes 11, 12 and the n-type side or p-type side electrode by the conductive particles 36. The light-emitting device 100 is electrically connected to the pads 21 and 22, respectively.

晶片本體31係於內部設置有N型半導體區域與P型半導體 區域之半導體晶圓藉由切斷被分割為複數個而成之半導體晶片,於各晶片本體31之內部,分別設置有N型半導體區域、及與N型半導體區域接觸之P型半導體區域,且分別形成有pn接面。 The wafer body 31 is internally provided with an N-type semiconductor region and a P-type semiconductor The semiconductor wafer in the region is cut into a plurality of semiconductor wafers, and an N-type semiconductor region and a P-type semiconductor region in contact with the N-type semiconductor region are provided inside each of the wafer bodies 31, and A pn junction is formed separately.

各晶片本體31上之n型側元件電極11電連接於N型半導體 區域,p型側元件電極12電連接於P型半導體區域,藉由各向異性導電接著膏30之硬化,從而n型側元件電極11經由導電粒子36而電連接於n型側電極墊21,p型側元件電極12經由導電粒子36而電連接於p型側電極墊22,因此,當對p型側電極墊22與n型側電極墊21之間施加電壓時,電壓經由p型側元件電極12與n型側元件電極11而被施加至P型半導體區域與 N型半導體區域之間,若使pn接面順向偏壓而使電流流入至pn接面,則pn接面附近發光。 The n-type side element electrode 11 on each wafer body 31 is electrically connected to the N-type semiconductor In the region, the p-type side element electrode 12 is electrically connected to the P-type semiconductor region, and is hardened by the anisotropic conductive adhesive paste 30, whereby the n-type side element electrode 11 is electrically connected to the n-type side electrode pad 21 via the conductive particles 36, The p-type side element electrode 12 is electrically connected to the p-type side electrode pad 22 via the conductive particles 36, and therefore, when a voltage is applied between the p-type side electrode pad 22 and the n-type side electrode pad 21, the voltage passes through the p-type side element. The electrode 12 and the n-type side element electrode 11 are applied to the P-type semiconductor region and When the pn junction is biased in the forward direction and the current flows into the pn junction between the N-type semiconductor regions, the vicinity of the pn junction emits light.

基板20例如為板狀之樹脂,n型側電極墊21與p型側電極 墊22係配置於基板20之表面上之金屬膜等導電性膜,n型側電極墊21之表面與p型側電極墊22之表面位於較基板20之表面高出n型側電極墊21與p型側電極墊22之膜厚P1之位置。 The substrate 20 is, for example, a plate-shaped resin, and the n-type side electrode pad 21 and the p-type side electrode pad 22 are disposed on a conductive film such as a metal film on the surface of the substrate 20, and the surface and the p-side of the n-type side electrode pad 21 are provided. The surface of the electrode pad 22 is located higher than the surface of the substrate 20 by the film thickness P 1 of the n-type side electrode pad 21 and the p-type side electrode pad 22.

於忽視導電粒子36之大小之情形時,n型側元件電極11與 n型側電極墊21接觸,p型側元件電極12與p型側電極墊22接觸,但由於n型側電極墊21與p型側電極墊22之膜厚P1並非為零,故而基板20之表面39與晶片本體31之底面38隔開高度H3而形成間隙13,又,於基板20之表面39與n型側元件電極11之表面或p型側元件電極12之表面之間亦形成有間隙。即,發光元件10之表面與基板20之表面39隔開而形成有間隙。 When the size of the conductive particles 36 is ignored, the n-type side element electrode 11 is in contact with the n-type side electrode pad 21, and the p-type side element electrode 12 is in contact with the p-type side electrode pad 22, but since the n-type side electrode pad 21 is The film thickness P 1 of the p-type side electrode pad 22 is not zero, so that the surface 39 of the substrate 20 is separated from the bottom surface 38 of the wafer body 31 by a height H 3 to form a gap 13 and, on the surface 39 and the n-type side of the substrate 20 A gap is also formed between the surface of the element electrode 11 or the surface of the p-type side element electrode 12. That is, the surface of the light-emitting element 10 is spaced apart from the surface 39 of the substrate 20 to form a gap.

如上所述,於n型側元件電極11與p型側元件電極12係配 置於晶片本體31之表面上之導電性薄膜、例如金屬薄膜之情形時,其膜厚E1之值小於n型側電極墊21與p型側電極墊22之膜厚P1之值,和晶片本體31之底面38與n型側電極墊21或p型側電極墊22之間之距離相比,n型側元件電極11之表面或p型側元件電極12之表面與基板20之表面39之間的距離更大(圖2C)。 As described above, when the n-type side element electrode 11 and the p-type side element electrode 12 are disposed on the surface of the wafer main body 31, for example, a metal thin film, the film thickness E 1 is smaller than the n-type side. The value of the film thickness P 1 of the electrode pad 21 and the p-type side electrode pad 22, and the distance between the bottom surface 38 of the wafer body 31 and the n-type side electrode pad 21 or the p-type side electrode pad 22, the n-type side member The distance between the surface of the electrode 11 or the surface of the p-type side element electrode 12 and the surface 39 of the substrate 20 is larger (Fig. 2C).

相對於此,如圖2D所示,於習知技術之發光裝置中,n型 側電極墊121與p型側電極墊122於較發光元件110之外周更靠外側凸出,搭載裝置180之表面139至晶片本體131之底面138之高度H4較本發明之 高度H3小相當於n型側電極墊121與p型側電極墊122之膜厚P1On the other hand, as shown in FIG. 2D, in the light-emitting device of the prior art, the n-type side electrode pad 121 and the p-type side electrode pad 122 protrude outward from the outer periphery of the light-emitting element 110, and the surface of the mounting device 180 is mounted. The height H 4 of the bottom surface 138 of the 139 to the wafer body 131 is smaller than the height H 3 of the present invention, which corresponds to the film thickness P 1 of the n-type side electrode pad 121 and the p-type side electrode pad 122.

而且,由於高度H4較低,故而原液128自發光元件110與n 型側或p型側電極墊121、122之間朝向較發光元件110之外周更外側被擠出。 Further, since the height H 4 is low, the stock solution 128 is extruded from the light-emitting element 110 and the n-type side or the p-type side electrode pads 121 and 122 toward the outer side of the outer periphery of the light-emitting element 110.

由於原液128之黏性高,故而被擠出之原液128中後被擠出之原液128堆疊於先被擠出之原液128上,若被擠出之原液128隆起得較發光元件110之晶片本體131之底面138更高且附著於晶片本體131之側面,則使接著成分129硬化後之導電粒子136之塊成為短路的原因。 Since the viscosity of the stock solution 128 is high, the stock solution 128 which is extruded after the extruded stock solution 128 is stacked on the stock solution 128 which is first extruded, and if the extruded stock solution 128 is raised above the wafer body of the light-emitting element 110. When the bottom surface 138 of 131 is higher and adheres to the side surface of the wafer main body 131, the block of the conductive particles 136 after the curing of the component 129 is short-circuited.

於本案發明中,高度H3高於習知技術之發光裝置之高度 H4,自n型側元件電極11與n型側電極墊21之間、及p型側元件電極12與p型側電極墊22之間擠出之原液28被收容於間隙13,從而不會隆起至發光元件10之側面。 In the invention of the present invention, the height H 3 is higher than the height H 4 of the conventional light-emitting device, from between the n-type side element electrode 11 and the n-type side electrode pad 21, and between the p-type side element electrode 12 and the p-type side electrode. The stock solution 28 extruded between the mats 22 is housed in the gap 13 so as not to rise to the side of the light-emitting element 10.

晶片本體31之平面形狀為四邊呈直角交叉之四邊形,若將 四邊中對向之兩條邊設為一組,則一組之兩條邊之長度相等。 The planar shape of the wafer body 31 is a quadrilateral whose four sides intersect at right angles, if The two sides of the four sides are set to one set, and the two sides of the set are equal in length.

又,一組之兩條邊中,n型側電極墊21位於一邊之正下方,p型側電極墊22位於另一邊之正下方,因此,n型側電極墊21與p型側電極墊22係自一組之兩條邊之正下方之位置進入位於晶片本體31之正下方之正下方區域,且於正下方區域內呈直線狀延伸。 Further, of the two sides of the group, the n-type side electrode pad 21 is located directly under one side, and the p-type side electrode pad 22 is located directly under the other side. Therefore, the n-type side electrode pad 21 and the p-type side electrode pad 22 are The position directly under the two sides of the set enters a region directly below the wafer body 31 and extends linearly in the immediately lower region.

p型側電極墊22與n型側電極墊21不位於另一組之兩邊之下。 The p-type side electrode pad 22 and the n-type side electrode pad 21 are not located under both sides of the other group.

此處,將與n型側電極墊21延伸之方向呈直角之方向之長 度設為n型側電極墊21之寬度L1,將與p型側電極墊22延伸之方向呈直角之方向之長度設為p型側電極墊22之寬度L2,將晶片本體31之位於n 型側電極墊21之正上方或p型側電極墊22之正上方之邊的長度設為發光元件寬度L0。 Here, the length of the direction in which the n-type side electrode pad 21 extends is at right angles The degree is set to the width L1 of the n-type side electrode pad 21, and the length in the direction perpendicular to the direction in which the p-type side electrode pad 22 extends is set to the width L2 of the p-type side electrode pad 22, and the wafer body 31 is located at n. The length of the side directly above the type side electrode pad 21 or directly above the p-type side electrode pad 22 is defined as the light-emitting element width L0.

於本發明之發光裝置100中,將n型側電極墊21之寬度L1 與p型側電極墊22之寬度L2構成為與晶片本體31之寬度L0同等或較其短。藉此,自基板20上之n型側、p型側電極墊21、22與發光元件10之間溢出之各向異性導電接著膏30被保持於較n型側、p型側電極墊21、22與發光元件10之間隙更寬的發光元件10與基板20之表面之間隙13,因此,可防止使P層與N層之間短路,並且由於無凸塊地進行覆晶構裝,故而可壓縮製造成本,且可提高散熱效率(換言之,降低熱阻)。 In the light-emitting device 100 of the present invention, the width L1 of the n-type side electrode pad 21 is used. The width L2 of the p-type side electrode pad 22 is equal to or shorter than the width L0 of the wafer body 31. Thereby, the anisotropic conductive adhesive paste 30 overflowing between the n-type side of the substrate 20 and the p-type side electrode pads 21 and 22 and the light-emitting element 10 is held on the n-type side, the p-type side electrode pad 21, 22, a gap 13 between the light-emitting element 10 and the surface of the substrate 20 which is wider than the gap of the light-emitting element 10, thereby preventing short-circuiting between the P layer and the N layer, and since the flip chip is formed without bumps, The manufacturing cost is reduced, and the heat dissipation efficiency (in other words, the thermal resistance is lowered) can be improved.

其次,上述A方向係n型側電極墊21與p型側電極墊22中之任一者自晶片本體31之邊之正下方之位置朝向內側延伸的方向。 Next, the A direction is a direction in which the n-type side electrode pad 21 and the p-type side electrode pad 22 extend inward from the position immediately below the side of the wafer body 31.

此處,圖1A及圖3A中之n型側、p型側電極墊21、22之寬度方向係橫穿A方向之方向。換言之,n型側、p型側電極墊21、22之寬度方向係於平行於基板20之表面之平面內與A方向呈直角之方向。 Here, the width direction of the n-type side and the p-type side electrode pads 21 and 22 in FIGS. 1A and 3A is a direction crossing the A direction. In other words, the width direction of the n-type side and p-type side electrode pads 21, 22 is in a direction perpendicular to the A direction in a plane parallel to the surface of the substrate 20.

因此,圖1A及圖3A中之A方向可定義為橫穿n型側電極墊21與p型側電極墊22之間之間隙的方向。再者,於圖1A及圖3A中,於基板20上,分別將矩形之p型側電極墊22與n型側電極墊21設置特定之間隔而形成於鄰接之位置,因此,n型側、p型側電極墊21、22之寬度方向成為與A方向大致正交之方向,但於n型側、p型側電極墊21、22之形狀並非矩形而為平行四邊形、梯形、三角形等形狀之情形時,n型側、p型側電極墊21、22之寬度方向未必為與A方向大致正交之方向,亦可為相對於A方向具有傾斜之角度而橫穿之方向。 Therefore, the A direction in FIGS. 1A and 3A can be defined as a direction crossing the gap between the n-type side electrode pad 21 and the p-type side electrode pad 22. In addition, in FIG. 1A and FIG. 3A, the rectangular p-type side electrode pad 22 and the n-type side electrode pad 21 are respectively formed at a predetermined interval on the substrate 20, and therefore, the n-type side, The width direction of the p-type side electrode pads 21 and 22 is substantially perpendicular to the direction A. However, the shape of the n-type side and the p-type side electrode pads 21 and 22 is not rectangular but is a shape of a parallelogram, a trapezoid, or a triangle. In this case, the width direction of the n-type side and p-type side electrode pads 21 and 22 is not necessarily a direction substantially orthogonal to the direction A, and may be a direction crossing the angle with respect to the direction A.

又,作為將n型側電極墊21與p型側電極墊22之寬度L1、 L2構成為較晶片本體31之寬度L0短之程度,由於若過短則有散熱特性下降之傾向,故而於將晶片本體31之寬度L0之長度設為100之情形時,將n型側電極墊21之寬度L1與p型側電極墊22之寬度L2之長度較佳設為80以上且100以下,更佳設為90以上且99以下。 Further, as the width L1 of the n-type side electrode pad 21 and the p-type side electrode pad 22 L2 is configured to be shorter than the width L0 of the wafer main body 31. When the length is too short, the heat dissipation characteristics tend to be lowered. Therefore, when the length L0 of the wafer main body 31 is set to 100, the n-type side electrode pad is used. The length L1 of the 21 and the width L2 of the p-type side electrode pad 22 are preferably 80 or more and 100 or less, and more preferably 90 or more and 99 or less.

於該情形時,發光元件10之晶片本體31懸突(overhang) 至n型側電極墊21與p型側電極墊22之寬度方向一側或兩側,但懸突量(圖1A之L1a、L1b、L2a、L2b)、即n型側、p型側電極墊21、22之寬度方向之邊緣與晶片本體31之寬度方向之邊緣的間隔若過小,則有發光元件10側面之導電接著膏30之爬升量增加之傾向,因此,較佳為0以上且120μm以下,更佳為5μm以上且80μm以下,特佳為10μm以上且40μm以下。 In this case, the wafer body 31 of the light-emitting element 10 overhangs To the one side or both sides of the width direction of the n-type side electrode pad 21 and the p-type side electrode pad 22, but the overhang amount (L1a, L1b, L2a, L2b of FIG. 1A), that is, the n-type side, p-type side electrode pad When the distance between the edge of the width direction of 21 and 22 and the edge of the wafer main body 31 in the width direction is too small, the amount of creep of the conductive paste 30 on the side surface of the light-emitting element 10 tends to increase. Therefore, it is preferably 0 or more and 120 μm or less. More preferably, it is 5 μm or more and 80 μm or less, and particularly preferably 10 μm or more and 40 μm or less.

再者,n型側電極墊21之寬度L1與p型側電極墊22之寬 度L2通常為相同長度,但亦可為不同長度。又,懸突量(L1a、L1b、L2a、L2b)同樣可為互為相同之長度,亦可分別互不相同。通常,就提高製造時之對位等操作之精度、且緩和操作之難易度之方面而言,較佳為將其等之懸突量設為互為相同之量。 Furthermore, the width L1 of the n-type side electrode pad 21 and the width of the p-type side electrode pad 22 Degrees L2 are usually the same length, but can also be of different lengths. Further, the amount of overhang (L1a, L1b, L2a, L2b) may be the same length or may be different from each other. In general, in order to improve the accuracy of the operation such as the alignment at the time of manufacture and to ease the ease of the operation, it is preferable to set the amount of overhangs such as the same amount.

n型側電極墊21之寬度L1與p型側電極墊22之寬度L2如 上所述般設為位於n型側電極墊21之正上方之晶片本體31之邊之長度以下的長度,又,設為位於p型側電極墊22之正上方之晶片本體31之邊之長度以下的長度。 The width L1 of the n-type side electrode pad 21 and the width L2 of the p-type side electrode pad 22 are as The length which is equal to or less than the length of the side of the wafer main body 31 directly above the n-type side electrode pad 21 is set to be the length of the side of the wafer main body 31 directly above the p-type side electrode pad 22. The length below.

n型側電極墊21與p型側電極墊22之前端係於位於晶片本 體31之正下方之正下方區域內互相隔開地配置。 The front side of the n-type side electrode pad 21 and the p-type side electrode pad 22 are attached to the wafer The areas immediately below the body 31 are arranged spaced apart from each other.

此處,如上所述,較理想為n型側電極墊21之寬度L1與p 型側電極墊22之寬度L2設為較位於n型側電極墊21之正上方之晶片本體31之邊之長度短,又,較位於p型側電極墊22之正上方之晶片本體31之邊之長度短,進而,較理想為位於n型側電極墊21之寬度L1之正上方的晶片本體31之邊於寬度L1之兩側凸出,又,位於p型側電極墊22之寬度L2之正上方的晶片本體31之邊於寬度L2之兩側凸出。 Here, as described above, it is preferable that the widths L1 and p of the n-type side electrode pads 21 are The width L2 of the side electrode pad 22 is set to be shorter than the length of the side of the wafer body 31 directly above the n-type side electrode pad 21, and is closer to the side of the wafer body 31 directly above the p-type side electrode pad 22. The length of the wafer body 31 which is located directly above the width L1 of the n-type side electrode pad 21 is convex on both sides of the width L1, and is located at the width L2 of the p-type side electrode pad 22. The sides of the wafer body 31 directly above are convex on both sides of the width L2.

於該情形時,於n型側電極墊21與p型側電極墊22之位於 晶片本體31之正下方區域內的前端部分之外側,除位於晶片本體31之邊之正下方之部分以外,配置有形成於發光元件10與基板20之間之間隙,基板20與發光元件10之間之距離較發光元件10與n型側電極墊21或p型側電極墊22之間之距離長n型側電極墊21或p型側電極墊22之膜厚P1之量。 In this case, the outer side of the front end portion of the n-type side electrode pad 21 and the p-type side electrode pad 22 located directly under the wafer body 31 is disposed except for the portion directly under the side of the wafer body 31. There is a gap formed between the light-emitting element 10 and the substrate 20, and the distance between the substrate 20 and the light-emitting element 10 is longer than the distance between the light-emitting element 10 and the n-type side electrode pad 21 or the p-type side electrode pad 22. The film thickness P 1 of the electrode pad 21 or the p-type side electrode pad 22 is the same.

因此,於按壓發光元件10而使n型側元件電極11經由導電 粒子36與n型側電極墊21接觸,且使p型側元件電極12經由導電粒子36與p型側電極墊22接觸時,位於發光元件10與n型側電極墊21之間之原液28、及位於發光元件10與p型側電極墊22之間之原液28自發光元件10與n型側或p型側電極墊21、22之間被擠出,此時,被擠出之量被收容於發光元件10與基板20之間之間隙13,從而消除原液28於發光元件10之周圍隆起之情況。 Therefore, the n-type side element electrode 11 is made to conduct electricity by pressing the light emitting element 10 When the particles 36 are in contact with the n-type side electrode pad 21 and the p-type side element electrode 12 is brought into contact with the p-type side electrode pad 22 via the conductive particles 36, the stock solution 28 between the light-emitting element 10 and the n-type side electrode pad 21, And the stock solution 28 between the light-emitting element 10 and the p-type side electrode pad 22 is extruded between the light-emitting element 10 and the n-type side or the p-type side electrode pads 21, 22, and at this time, the amount of being squeezed is accommodated. The gap 13 between the light-emitting element 10 and the substrate 20 eliminates the swell of the stock solution 28 around the light-emitting element 10.

於本發明之發光裝置100中,將n型側、p型側電極墊21、 22之寬度構成為與晶片本體31之寬度同等或較其窄,除此以外,可設為與習知之發光裝置之構成要素(例如發光元件之種類、大小、其連接墊之種 類、大小、基板之種類、大小、其上之配線圖案之素材、厚度、各向異性導電接著膏之種類、黏度、所含有之導電粒子36之種類或平均粒徑等)相同之構成。 In the light-emitting device 100 of the present invention, the n-type side, the p-type side electrode pad 21, The width of 22 is equal to or narrower than the width of the wafer main body 31, and can be set as a component of a conventional light-emitting device (for example, the type and size of the light-emitting element, and the kind of the connection pad) The type, size, type and size of the substrate, the material of the wiring pattern thereon, the thickness, the type of the anisotropic conductive paste, the viscosity, the type of the conductive particles 36 contained, or the average particle diameter are the same.

再者,作為本發明之發光裝置100之構成要素之一的發光元 件10,可列舉LED晶片、有機EL晶片、無機EL晶片元件等,其中可較佳地列舉LED晶片。其等當然為無凸塊。 Further, as a light-emitting element which is one of the constituent elements of the light-emitting device 100 of the present invention The member 10 includes an LED chip, an organic EL wafer, an inorganic EL wafer element, and the like, and an LED chip is preferably exemplified. It is of course no bumps.

[實施例] [Examples]

以下,藉由更具體之實施例對本發明進行說明。 Hereinafter, the present invention will be described by way of more specific examples.

實施例1~7 Examples 1 to 7

作為將LED晶片以無凸塊且使電極墊之寬度與發光元件之寬度同等或較其窄之方式覆晶構裝於基板之例,使用以下之基板、LED晶片、各向異性導電接著膏製成圖1A~1B所示之構造之發光裝置。具體而言,自分配器向與LED元件之中央部對應之基板上供給特定量之各向異性導電接著膏,且將LED晶片載置於該各向異性導電接著膏,於溫度230℃、壓力3N/chip、30秒之條件下進行熱壓接,藉此製成發光裝置。 As an example in which the LED wafer is formed on the substrate without bumps and the width of the electrode pad is equal to or narrower than the width of the light-emitting element, the following substrate, LED chip, and anisotropic conductive paste are used. The light-emitting device of the structure shown in Figs. 1A to 1B is formed. Specifically, a specific amount of the anisotropic conductive paste is supplied from the dispenser to the substrate corresponding to the central portion of the LED element, and the LED wafer is placed on the anisotropic conductive paste at a temperature of 230 ° C and a pressure of 3 N. /chip, 30 seconds under the conditions of thermocompression bonding, thereby making a light-emitting device.

再者,將LED元件之寬度方向之邊緣至電極墊之寬度方向 之邊緣的寬度(就實施例之態樣換言之,為LED元件相對於電極墊之懸突量(L1a=L1b=L2a=L2b))示於表1。於表1中記載為△LD。於實施例1~7中,△LD之數值為0或正數。 Furthermore, the edge of the width direction of the LED element is oriented to the width direction of the electrode pad The width of the edge (in the case of the embodiment, in other words, the amount of overhang of the LED element with respect to the electrode pad (L1a = L1b = L2a = L2b)) is shown in Table 1. Table 1 shows ΔLD. In Examples 1 to 7, the value of ΔLD was 0 or a positive number.

<基板> <Substrate>

基底材質:氧化鋁0.6mm厚 Base material: alumina 0.6mm thick

電極墊:銅10μm厚 Electrode pad: copper 10μm thick

電極墊表面處理:鍍Ni3μm厚/Au0.3μm厚 Electrode pad surface treatment: Ni3μm thick / Au0.3μm thick

<LED晶片> <LED chip>

製品名:DA3547,Cree公司製造(美國Cree.Inc.) Product Name: DA3547, manufactured by Cree (Cree.Inc., USA)

尺寸:350μm×470μm×155μmt Size: 350μm × 470μm × 155μmt

<各向異性導電接著膏> <Anisotropic conductive paste>

製品名:SLP-04,Dexerials(股)製造 Product Name: SLP-04, Maderials

比較例1~2 Comparative example 1~2

作為將LED晶片以於電極墊形成凸塊且電極墊之寬度較發光元件之寬度寬之方式覆晶構裝於基板的比較例,關於圖3A~圖3B所示之構造之發光裝置,除使用以下之基板以外,使用與實施例1之情形相同之LED晶片、及各向異性導電接著膏,並反覆進行與實施例1相同之操作,藉此製成發光裝置。 A comparative example in which the LED wafer is formed on the substrate by forming a bump on the electrode pad and the width of the electrode pad is wider than the width of the light-emitting element, and the light-emitting device having the structure shown in FIGS. 3A to 3B is used. An LED chip and an anisotropic conductive paste which are the same as those in the first embodiment were used in the same manner as in the first embodiment, and the same operation as in the first embodiment was repeated to obtain a light-emitting device.

<比較例1中所使用之基材> <Substrate used in Comparative Example 1>

基底材質:氧化鋁0.6mm厚 Base material: alumina 0.6mm thick

電極墊:銅10μm厚 Electrode pad: copper 10μm thick

Au凸塊:直徑80μm、高度15μm Au bump: 80μm in diameter and 15μm in height

Au凸塊數:各電極墊3個 Au bump number: 3 electrode pads

Au凸塊間距:500μm Au bump spacing: 500μm

<比較例2中所使用之基材> <Substrate used in Comparative Example 2>

基底材質:氧化鋁0.6mm厚 Base material: alumina 0.6mm thick

電極墊:銅10μm厚 Electrode pad: copper 10μm thick

Au凸塊:直徑80μm、高度15μm Au bump: 80μm in diameter and 15μm in height

Au凸塊數:各電極墊6個 Au bump number: 6 electrode pads

Au凸塊間距:200μm Au bump spacing: 200μm

再者,將LED元件之寬度方向之邊緣至電極墊之寬度方向之邊緣的寬度(換言之,電極墊自LED元件之寬度方向凸出之量(L1a=L1b=L2a=L2b))示於表1。於表1中記載為△LD。比較例1及2以及以下之比較例3中,△LD之數值必然為負數。 Further, the width of the edge of the LED element in the width direction to the edge of the width direction of the electrode pad (in other words, the amount by which the electrode pad protrudes from the width direction of the LED element (L1a=L1b=L2a=L2b)) is shown in Table 1. . Table 1 shows ΔLD. In Comparative Examples 1 and 2 and Comparative Example 3 below, the value of ΔLD was necessarily a negative number.

比較例3 Comparative example 3

作為基板,使用未形成Au凸塊且與實施例1同樣地實施有電極墊表面處理之基板,除此以外,與比較例1同樣地製成發光裝置。 A light-emitting device was produced in the same manner as in Comparative Example 1, except that the substrate on which the electrode pad surface treatment was performed was carried out in the same manner as in Example 1 except that the Au bump was not formed.

(評價) (Evaluation)

對於實施例以及比較例中製成之發光元件,如以下說明般對「短路不良」與「散熱特性」進行試驗評價。將所獲得之結果示於表1。 The light-emitting elements produced in the examples and the comparative examples were subjected to test evaluation of "short-circuit failure" and "heat dissipation characteristics" as described below. The results obtained are shown in Table 1.

<短路不良> <Bad short circuit>

分別製成100個各實施例及各比較例之發光元件,使用測試機(曲線描繪器TCT-2004,國洋電機工業(股))確認P極側與N極側之間是否產生短路,求出產生了短路之發光元件之比率(短路產生率)。短路產生率較佳為1%以下,更佳為0.5%以下,特佳為0%。 Each of the light-emitting elements of each of the examples and the comparative examples was prepared, and a short circuit was detected between the P-pole side and the N-pole side using a tester (curve tracer TCT-2004, Guoyo Electric Industries Co., Ltd.). The ratio of the short-circuiting light-emitting elements (short-circuit generation rate) is generated. The short-circuit generation rate is preferably 1% or less, more preferably 0.5% or less, and particularly preferably 0%.

<散熱特性> <heat dissipation characteristics>

為了對散熱特性進行評價,依照「JE-DEC標準,JESD51-14」測定各發光元件之熱阻值,求出對照比較例1之熱阻值時之實施例或比較例之發光元件之熱阻值之減少率(熱阻減少率)。減少率較佳為25%以上,更佳為30%以上,特佳為35%以上。 In order to evaluate the heat dissipation characteristics, the thermal resistance values of the respective light-emitting elements were measured in accordance with "JE-DEC standard, JESD 51-14", and the thermal resistance of the light-emitting elements of the examples or the comparative examples when the thermal resistance value of Comparative Example 1 was determined was determined. The rate of decrease of the value (thermal resistance reduction rate). The reduction rate is preferably 25% or more, more preferably 30% or more, and particularly preferably 35% or more.

根據表1可知,於藉由使用各向異性導電接著膏將LED晶 片無凸塊地覆晶構裝在形成於基板上之電極墊而製成發光裝置之情形時,若使電極墊之寬度與發光元件之寬度同等或較其窄,則短路產生率為1%以下且熱阻減少率為20%以上。尤其是若將發光元件相對於基板之電極墊之懸突量設為10μm以上且40μm以下,則短路產生率為0%且熱阻減少率為35%以上,較佳。 According to Table 1, the LED crystal is obtained by using an anisotropic conductive paste. When the film is formed on the substrate without the bumps and is formed on the electrode pad of the substrate to form a light-emitting device, if the width of the electrode pad is equal to or narrower than the width of the light-emitting element, the short-circuit generation rate is 1%. Hereinafter, the thermal resistance reduction rate is 20% or more. In particular, when the amount of overhang of the light-emitting element with respect to the electrode pad of the substrate is 10 μm or more and 40 μm or less, the short-circuit generation rate is 0% and the thermal resistance reduction rate is 35% or more.

另一方面,可知於使用設置有凸塊之基板之比較例1、2之 發光裝置之情形時,雖然短路不良得到改善,但散熱特性未改善。可知於比較例3之發光裝置之情形時,雖然散熱特性得到改善,但短路不良超過1%。 On the other hand, it can be seen that Comparative Examples 1 and 2 using a substrate provided with bumps are known. In the case of the light-emitting device, although the short-circuit defect is improved, the heat dissipation characteristics are not improved. It can be seen that in the case of the light-emitting device of Comparative Example 3, although the heat dissipation characteristics were improved, the short-circuit defect exceeded 1%.

[產業上之可利用性] [Industrial availability]

使用各向異性導電接著膏將發光元件無凸塊地覆晶構裝在形成於基板上之電極墊而成的本發明之發光裝置係將電極墊之寬度構成為 與發光元件之寬度同等或較其窄。因此,作為抑制短路之產生、且提高散熱特性(降低熱阻)之發光裝置是有用的。 A light-emitting device of the present invention in which an anisotropic conductive paste is used to form a light-emitting device without bumps on an electrode pad formed on a substrate, and the width of the electrode pad is configured as It is equal to or narrower than the width of the light-emitting element. Therefore, it is useful as a light-emitting device that suppresses generation of a short circuit and improves heat dissipation characteristics (reducing thermal resistance).

Claims (6)

一種發光裝置,其係使用各向異性導電接著膏將具有半導體之晶片本體之發光元件無凸塊(bumpless)地覆晶構裝在形成於基板上之電極墊而成者,其特徵在於:電極墊之寬度較該晶片本體之寬度窄,該電極墊之寬度方向之邊緣與該晶片本體之寬度方向之邊緣的間隔為10μm以上且40μm以下。 A light-emitting device which uses an anisotropic conductive paste to laminate a light-emitting element having a semiconductor wafer body without bumps on an electrode pad formed on a substrate, characterized in that an electrode The width of the pad is narrower than the width of the wafer body, and the distance between the edge of the electrode pad in the width direction and the edge of the wafer body in the width direction is 10 μm or more and 40 μm or less. 如申請專利範圍第1項之發光裝置,其中,該晶片本體為發光二極體晶片。 The illuminating device of claim 1, wherein the wafer body is a light emitting diode chip. 如申請專利範圍第1或2項之發光裝置,其中,於將該晶片本體之寬度設為100之情形時,該電極墊之寬度為80%以上且100%以下。 The light-emitting device of claim 1 or 2, wherein the width of the electrode pad is 80% or more and 100% or less when the width of the wafer body is 100. 一種發光裝置,於發光元件與搭載裝置之間配置有含有導電粒子之各向異性導電接著膏,該發光元件藉由該各向異性導電接著膏被設置於該搭載裝置,該搭載裝置具有:基板、及配置於該基板上之n型側電極墊與p型側電極墊;該發光元件具有:平面形狀為四邊形形狀之晶片本體、及設置於該晶片本體之p型側元件電極與n型側元件電極;於該晶片本體之內部,設置有p型區域與n型區域,形成有pn接面,該p型側元件電極經由該導電粒子而電連接於該p型區域,該n型 側元件電極經由該導電粒子而電連接於該n型區域,該p型側電極墊之表面與該n型側電極墊之表面位於該基板表面之上方,該p型側電極墊與該n型側電極墊係形成為寬度為固定值之帶狀,該p型側電極墊之前端與該n型側電極墊之前端位於該晶片本體之正下方即正下方區域內,與該p型側電極墊之前端為相反側之部分、及與該n型側電極墊之前端為相反側之部分位於該正下方區域之外側,該p型側電極墊之該寬度係設為較該晶片本體之位於該p型側電極墊之正上方的第一邊之長度短,該n型側電極墊之該寬度係設為較該晶片本體之位於該n型側電極墊之正上方的第二邊之長度短,該p型側電極墊之寬度方向之邊緣與該晶片本體之寬度方向之邊緣的間隔為10μm以上且40μm以下,該n型側電極墊之寬度方向之邊緣與該晶片本體之寬度方向之邊緣的間隔為10μm以上且40μm以下。 In a light-emitting device, an anisotropic conductive paste containing conductive particles is disposed between a light-emitting element and a mounting device, and the light-emitting device is provided on the mounting device by the anisotropic conductive paste, and the mounting device has a substrate And an n-type side electrode pad and a p-type side electrode pad disposed on the substrate; the light-emitting element has a wafer body having a quadrangular planar shape, and a p-type side element electrode and an n-type side disposed on the wafer body a device electrode; a p-type region and an n-type region are disposed inside the wafer body, and a pn junction is formed, and the p-type side element electrode is electrically connected to the p-type region via the conductive particles, the n-type The side element electrode is electrically connected to the n-type region via the conductive particles, and a surface of the p-type side electrode pad and a surface of the n-type side electrode pad are located above the surface of the substrate, the p-type side electrode pad and the n-type The side electrode pad is formed in a strip shape having a fixed width, and the front end of the p-type side electrode pad and the front end of the n-type side electrode pad are located directly under the wafer body, that is, directly below, and the p-type side electrode The portion on the opposite side of the front end of the pad and the portion opposite to the front end of the n-type side electrode pad are located on the outer side of the directly underlying region, and the width of the p-type side electrode pad is set to be larger than the wafer body The length of the first side directly above the p-type side electrode pad is short, and the width of the n-type side electrode pad is set to be longer than the length of the second side of the wafer body directly above the n-type side electrode pad The distance between the edge of the p-type side electrode pad in the width direction and the edge of the wafer body in the width direction is 10 μm or more and 40 μm or less, and the edge of the n-type side electrode pad in the width direction and the width direction of the wafer body The interval between the edges is 10 μm or more and 40 μm . 如申請專利範圍第4項之發光裝置,其中,於該正下方區域內之該p型側電極墊與該n型側電極墊之外側的該發光元件與該基板之間,配置有自該發光元件與該p型側電極墊之間溢出之該各向異性導電接著膏、及自該發光元件與該n型側電極墊之間溢出之該各向異性導電接著膏。 The illuminating device of claim 4, wherein the light-emitting element on the outer side of the p-type side electrode pad and the n-type side electrode pad is disposed between the light-emitting element and the substrate The anisotropic conductive paste that overflows between the device and the p-type side electrode pad, and the anisotropic conductive paste that overflows between the light-emitting element and the n-type side electrode pad. 如申請專利範圍第5項之發光裝置,其中,該第一邊與該第二邊係以相同長度平行地配置,該第一邊之兩端位於該p型側電極墊之正上方 之外側,該第二邊之兩端位於該n型側電極墊之正上方之外側。 The illuminating device of claim 5, wherein the first side and the second side are arranged in parallel with the same length, and the two ends of the first side are located directly above the p-type side electrode pad. On the outer side, both ends of the second side are located on the outer side directly above the n-type side electrode pad.
TW104107889A 2014-03-12 2015-03-12 Light emitting device TWI669837B (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2014048750 2014-03-12
JPJP2014-048750 2014-03-12

Publications (2)

Publication Number Publication Date
TW201603335A TW201603335A (en) 2016-01-16
TWI669837B true TWI669837B (en) 2019-08-21

Family

ID=54071853

Family Applications (1)

Application Number Title Priority Date Filing Date
TW104107889A TWI669837B (en) 2014-03-12 2015-03-12 Light emitting device

Country Status (5)

Country Link
JP (1) JP2015188078A (en)
KR (1) KR102348352B1 (en)
CN (1) CN106233479B (en)
TW (1) TWI669837B (en)
WO (1) WO2015137414A1 (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107170880B (en) * 2017-07-14 2019-09-27 上海天马微电子有限公司 Luminescence unit and display device
JP6942589B2 (en) * 2017-09-27 2021-09-29 旭化成株式会社 Semiconductor light emitting device and ultraviolet light emitting module
CN111179750A (en) * 2019-12-12 2020-05-19 武汉华星光电技术有限公司 Structure of display panel and manufacturing method thereof
TWI773538B (en) * 2021-09-24 2022-08-01 友達光電股份有限公司 Self-luminous device

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1471179A (en) * 2002-07-05 2004-01-28 ��ķ�ɷ����޹�˾ Semiconductor luminescent device

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11168235A (en) * 1997-12-05 1999-06-22 Toyoda Gosei Co Ltd Light emitting diode
JP2007049045A (en) * 2005-08-11 2007-02-22 Rohm Co Ltd Semiconductor light emitting device and semiconductor device using the same
JP4951937B2 (en) 2005-10-28 2012-06-13 日亜化学工業株式会社 Light emitting device
JP5880025B2 (en) * 2011-12-26 2016-03-08 日亜化学工業株式会社 Light emitting device
US8877561B2 (en) * 2012-06-07 2014-11-04 Cooledge Lighting Inc. Methods of fabricating wafer-level flip chip device packages

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1471179A (en) * 2002-07-05 2004-01-28 ��ķ�ɷ����޹�˾ Semiconductor luminescent device

Also Published As

Publication number Publication date
KR102348352B1 (en) 2022-01-10
CN106233479A (en) 2016-12-14
KR20160132917A (en) 2016-11-21
JP2015188078A (en) 2015-10-29
WO2015137414A1 (en) 2015-09-17
CN106233479B (en) 2019-11-22
TW201603335A (en) 2016-01-16

Similar Documents

Publication Publication Date Title
US8889440B2 (en) Light emitting diode optical emitter with transparent electrical connectors
TWI535077B (en) Light emitting?apparatus and light emitting module thereof
TWI669837B (en) Light emitting device
US9755121B2 (en) Method of detaching sealing member of light emitting device
TWI453948B (en) The structure of the press - fit type flip - chip light emitting element and its making method
TWI430717B (en) Substrate strcuture, array of semiconductor devices and semiconductor device thereof
CN107017322A (en) Luminescence component
TWI677111B (en) Wiring substrate body and method of manufacturing the same
JP2007049045A (en) Semiconductor light emitting device and semiconductor device using the same
JP2014157948A (en) Semiconductor light-emitting element and light-emitting device
US20180175237A1 (en) Components comprising a light emitting semiconductor chip
WO2015076281A1 (en) Light-emitting device and light-emitting device manufacturing method
US20160141446A1 (en) Method for manufacturing light emitting device
TWI407536B (en) Method for manufacturing heat dissipation bulk of semiconductor device
JP6147061B2 (en) Flip-chip type semiconductor light emitting device, semiconductor device and manufacturing method thereof
JP2014093318A (en) Semiconductor element and manufacturing method of the same
JP2012178400A (en) Led lamp
TWI550918B (en) Light emitting diode module and method of manufacturing the same
JP2015185685A (en) Light emitting device manufacturing method and light device
TW201427093A (en) LED chip unit and method for manufacturing the same
JP2013120898A (en) Semiconductor device and manufacturing method of the same
JP3617929B2 (en) Semiconductor light emitting device and manufacturing method thereof
US20140170848A1 (en) Method of Forming Substrate
TW201836176A (en) Heat conduction structure of flip-chip LED capable of rapidly guiding waste heat generated in a small space to the outside for heat dissipation through a heat conduction path formed by eutectic soldering
TWI566442B (en) Light emitting chip module,light emitting diode and method of manufacturing the light emitting chip module