TWI666639B - Memory device with dynamic target calibration - Google Patents

Abstract

A memory system includes: a memory array including a plurality of memory cells; and a controller coupled to the memory array, the controller configured to: determine a target quantity change curve including a distributed target Where each of the distribution targets represents a program verification target corresponding to one of the logical values of the memory cells; a feedback metric is determined based on the implementation of a processing level for processing data; and based on the feedback metric The program verification target is adjusted to dynamically generate an updated target.

Description

Memory device with dynamic target calibration

The disclosed embodiments relate to memory devices, and in particular to memory devices having a mechanism for dynamic calibration of program verification targets.

Memory systems can use memory devices to store and access information. The memory device may include a volatile memory device, a non-volatile memory device, or a combination device. Non-volatile memory devices may include flash memory using "NAND" technology or logic gates, "NOR" technology or logic gates, or combinations thereof.

Memory devices (such as flash memory) use electrical energy in conjunction with corresponding threshold levels or processing voltage levels to store and access data. However, the performance or characteristics of flash memory devices change or deteriorate over time or as a result of use. Over time, changes in performance or characteristics conflict with thresholds or processing voltage levels, leading to errors and other performance issues.

Therefore, there is a need for a memory device having a dynamic target calibration mechanism. Given the increasing pressure of commercial competition, as well as the growing consumer expectations and expectations of differentiated market products, there is an increasing desire to find answers to these questions. In addition, the need to reduce costs, improve efficiency and effectiveness, and respond to competitive pressures adds even more pressure to find answers to these questions.

In some embodiments, a memory device includes: a memory array including a plurality of memory cells; and a controller coupled to the memory array, the controller configured to: determine that a distribution is included A target quantity change curve of targets, wherein each of the distribution targets represents a program verification target corresponding to a logical value of the memory cells; a feedback measure is determined based on a processing level implemented for processing data; And dynamically generate an updated target based on adjusting the program verification target according to the feedback measure.

In some embodiments, a memory device includes: a memory array including a plurality of memory cells arranged in a memory page; and a controller coupled to the memory array, the controller is The configuration is: determining a target quantity change curve including one of an edge target and an intermediate target, wherein each of the targets represents a program verification target corresponding to a logical value of the memory cells; based on a corresponding read level The error in voltage determines a feedback metric; and dynamically generates one or more updated targets based on changing one or more of the intermediate targets according to the feedback metric.

In some embodiments, a method is used to operate a memory device including a controller and a memory array. The method includes: determining a target quantity variation curve including one of the distribution targets, wherein each of the distribution targets represents a program verification target corresponding to a logical value of a memory cell; and based on implementing a processing level for processing data, Determine a feedback metric; and use the controller to dynamically generate an updated target for balancing an error metric across multiple page types of the memory cells based on adjusting the program verification target based on the feedback metric.

Related Applications This application contains subject matter related to a US patent application entitled "MEMORY DEVICE WITH DYNAMIC PROGRAMMING CALIBRATION" filed by both Bruce A. Liikanen and Larry J. Koudele. Related applications were assigned to Micron Technology, Inc. and identified by file number 10829-9199.US00. The subject matter of this application is incorporated herein by reference.

This application contains subject matter related to a US patent application entitled "MEMORY DEVICE WITH DYNAMIC PROCESSING LEVEL CALIBRATION" filed by both Bruce A. Liikanen and Larry J. Koudele. Related applications were assigned to Micron Technology, Inc. and identified by file number 10829-9201.US00. The subject matter of this application is incorporated herein by reference.

As described in more detail below, the techniques disclosed herein relate to memory devices, systems with memory devices, and related methods for dynamically calibrating program verification targets for memory devices. After the initial manufacturing or configuration of the memory device, the memory device may use a calibration mechanism to dynamically calibrate one or more distribution targets of one or more page types. The memory device may be configured to dynamically calibrate the program verification target while using (eg, operating) the memory device.

To verify the goal of the calibration procedure, the memory device can collect multiple samples or results, such as data counts or error rates, while calibrating different aspects of the memory device or while using the memory device. The memory device may use the samples or results to calculate a feedback metric (eg, the error rate or the difference in error counts corresponding to the different read level voltages used to collect the samples) when the calibration program verifies the target. Memory devices can dynamically adjust program verification targets using feedback to use a distance between a threshold voltage and a voltage corresponding to an adjacent logic state (known as the read window range or RWB) to span different pages Type balance error rate.

The following embodiments are described in sufficient detail to enable those skilled in the art to make and use the embodiments. However, those skilled in the relevant art will appreciate that the present invention may have additional embodiments and that the present invention may be practiced without certain details of the embodiments described below with reference to FIGS. 1 to 8.

In the embodiments explained below, the memory device is described in the context of a device incorporating a NAND-based non-volatile storage medium (eg, NAND flash memory). However, in addition to or instead of NAND-based storage media, the memory device configured according to other embodiments of the present invention may also include other types of suitable storage media, such as NOR-based storage media, magnetic storage media , Phase change storage media, ferroelectric storage media, etc.

The term "processing" as used herein includes manipulating signals and data, such as writing or programming, reading, erasing, refreshing, adjusting or changing values, calculating results, executing instructions, combining, transmitting, and / or manipulating data structure. The term data structure includes information configured as bits, words or codes, blocks, files, input data, system-generated data (such as calculated or generated data), and program data. In addition, the term "dynamic" as used herein describes a program, function, action, or process that occurs during the operation, use, or deployment of a corresponding device, system, or embodiment and after or concurrently with the operation of a manufacturer or third-party firmware. implementation plan. A program, function, action, or implementation that occurs dynamically can occur after or immediately after design, manufacturing, and initial testing, setup, or configuration.

FIG. 1 is a block diagram of a memory system 100 having a dynamic processing level calibration mechanism configured according to an embodiment of the present invention. The memory system 100 includes a memory device 102. As shown, the memory device 102 includes a memory array 104 (eg, NAND flash memory) and a controller 106. The memory device 102 may operatively couple the memory array 104 to a host device 108 (eg, an upstream central processing unit (CPU)). The memory array 104 may include circuitry configured to store data in the memory array 104 and provide access to data in the memory array 104. The memory array 104 may be provided as a semiconductor, integrated circuit, and / or external removable device in a computer or other electronic device. The memory array 104 includes a plurality of memory regions or memory cells 120. The memory unit 120 may be an individual memory die, a memory plane in a single memory die, a memory die stack vertically connected to a through silicon via (TSV), or the like. In one embodiment, each of the memory cells 120 may be formed from a semiconductor die and configured in a single device package (not shown) along with other memory unit die. In other embodiments, one or more of the memory units 120 may be co-located on a single die and / or distributed across multiple device packages. The memory device 102 and / or the individual memory unit 120 may also include means for accessing and / or programming (e.g., writing) data and other functions (such as for processing information and / or communicating with the controller 106). Other circuit components (not shown), such as multiplexers, decoders, buffers, read / write drivers, address registers, data output / data input registers, etc.

Each of the memory units 120 includes an array of memory cells 122 that store data. The memory cell 122 may include, for example, floating gates, charge traps, phase changes, ferroelectrics, magnetoresistance, and / or other suitable storage elements configured to store data permanently or semi-permanently. The memory cell 122 may be a single crystal memory cell that can be programmed to a target state to represent information. For example, a charge may be placed on or removed from a charge storage structure (eg, a charge trap or floating gate) of the memory cell 122 to remove The cell is programmed to a specific data state. The stored charge on the charge storage structure of the memory cell 122 may indicate a threshold voltage (Vt) of the cell. For example, a single-order cell (SLC) can be programmed to a target state that is one of two different data states that can be represented by a binary unit of 1 or 0.

Some flash memory cells can be programmed to one of two or more data states. For example, a flash memory cell that can be programmed to one of four states (e.g., represented by binary 00, 01, 10, 11) can be used to store 2-bit data and can be referred to as a multilevel cell (MLC). Can program other flash memory cells to any of eight data states (for example, 000, 001, 010, 011, 100, 101, 110, 111), allowing 3-bit data to be stored in a single Cell. These cells can be referred to as third-order cells (TLC). Even higher numbers of data states are possible, such as their data states found in a fourth-order cell (QLC), which can be programmed to 16 data states (e.g., 0000, 0001, 0010, 0011, 0100) , 0101, 0110, 0111, 1000, 1001, 1010, 1011, 1100, 1101, 1110, 1111) for storing 4-bit data. A memory cell 122 capable of storing a higher number of data states can provide higher density memory without increasing the number of memory cells because each cell can represent more than one number (eg, more than one bit).

The memory cells 122 may be arranged in columns (for example, each corresponding to a word line 143) and rows (for example, each corresponding to a bit line). Each word line 143 may include one or more memory pages 124, depending on the number of data states that the memory cells 122 of that word line 143 are configured to store. For example, a single word line of each memory cell 122 (eg, an SLC memory cell configured to store one bit each) configured to store one of two data states may include a single memory page 124. Alternatively, a single word line 143 of each memory cell 122 (e.g., an MLC memory cell configured to store two bits each) configured to store one of the four data states may contain two memories Body Page 124. In addition, within word line 143, pages 124 may be interleaved such that word lines 143 each configured to store one of two data states (e.g., an SLC memory cell) may include word lines 143 -Odd Bit Line Architecture "(for example, where all memory cells 122 in odd rows of a single word line 143 are grouped into a first page, and all memories in even rows of the same word line 143 are grouped Body cells 122 are grouped into a second page). When using even-odd bit line architectures in word lines 143 of memory cells 122 (e.g., memory cells configured as MLC, TLC, QLC, etc.) each configured to store a larger number of data states The number of pages per word line 143 may be even higher (for example, 4, 6, 8, etc.). Each row may include a series-coupled memory cell 122 coupled to a common source. Each string of memory cells 122 may be connected in series between a source selection transistor (eg, a field effect transistor) and a drain selection transistor (eg, a field effect transistor). The source selection transistor may be commonly coupled to a source selection line, and the drain selection transistor may be commonly coupled to a drain selection line.

The memory device 102 may process data using different groups of the memory cells 122. For example, the memory pages 124 of the memory cell 122 may be grouped into a memory block 126. In operation, various memory regions of the memory device 102 (such as by writing to groups of pages 124 and / or memory blocks 126) may be written or otherwise programmed (e.g., erased) data. In NAND-based memory, a write operation typically involves programming a memory cell 122 in a selected memory page 124 using a specific data value (e.g., a string of data bits having a value of logic 0 or logic 1) . An erase operation is similar to a write operation, except that the erase operation reprograms the entire memory block 126 or multiple memory blocks 126 to the same data state (eg, logic 0).

In other embodiments, the memory cells 122 may be configured in groups and / or hierarchies different from the types shown in the illustrated embodiments. In addition, although illustrated in illustrated embodiments having a specific number of memory cells, columns, rows, blocks, and memory cells for illustrative purposes, in other embodiments, the memory cells, columns, rows, The number of blocks and memory units can vary, and the scale can be larger or smaller than that shown in the illustrated examples. For example, in some embodiments, the memory device 100 may include only one memory unit 120. Alternatively, the memory device 100 may include two, three, four, eight, ten, or more (e.g., 16, 32, 64, or more) memory cells 120. Although the memory unit 120 is shown in FIG. 1 as including two memory blocks 126 each, in other embodiments, each memory unit 120 may include one, three, four, eight, or more (Eg, 16, 32, 64, 100, 128, 256, or more) memory blocks. In some embodiments, each memory block 123 may include, for example, 215 memory pages, and each memory page within a block may include, for example, 212 memory cells 122 (eg, a "4k" page).

The controller 106 may be a microcontroller, a dedicated logic circuit (for example, a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc.) or other suitable processors. The controller 106 may include a processor 130 configured to execute instructions stored in memory. In the illustrated example, the memory of the controller 106 includes an embedded memory 132 that is configured to perform operations for controlling the memory system 100 (including managing the memory device 102 and processing memory). Communication between the body device 102 and the host device 108), various programs, logic flows, and routines. In some embodiments, the embedded memory 132 may include a memory register that stores, for example, memory indicators, extracted data, and the like. The embedded memory 132 may also include read-only memory (ROM) for storing microcode. Although the exemplary memory device 102 shown in FIG. 1 has been illustrated as including a controller 106, in another embodiment of the present invention, a memory device may not include a controller and may instead rely on External control (for example, provided by an external host, or provided by a processor or controller separate from the memory device).

In the illustrated example, further organization or details of the memory array 104 are represented by a page map 142. The page map 142 may represent a grouping, address, type, or combination of memory pages 124 of each of the memory blocks 126. For example, each of the memory blocks 126 may include a memory page 124 corresponding to a word line group 144. As another example, the memory page 124 may further correspond to a logical page type 146, such as a next page (LP) 148, a previous page (UP) 150, or an extra page (EP) 152.

The word line group 144 may include a group corresponding to one of the memory pages 124 of one or more word lines 143 used to perform processing functions such as data reading or writing. The word line group 144 may be a group of one of the memory pages 124 for or connected to the word line 143. The word line 143 may correspond to the physical layout or structure of the memory cell 122.

Page type 146 (such as previous page 150, next page 148, and extra page 152) may represent a grouping of bits for memory page 124 in a particular order. The type of page may correspond to one of the logical layouts, structures, or values of the memory cell 122. For example, the next page 148 may represent one of the first information bits stored in the memory page 124 or the memory cell 122 therein. The next page 148 can be used for SLC type cells, MLC type cells, TLC type cells, or combinations thereof. For another example, the previous page 150 may correspond to or represent one of the second information bits stored in the memory page 124 or the memory cell 122 therein. The previous page 150 can be used for TLC or MLC type memory cells 122. For another example, the extra page 152 may represent one of the third information bits stored in the memory page 124 or the memory cell 122 therein, such as the most significant bit or the least significant bit. The extra page 152 can be used for TLC-type memory cells 122.

The memory device 102 may use the processing level 154 to store or access data. The processing level 154 may include a threshold or operating level of voltage or current. The processing level 154 may include a threshold voltage 156, a read level voltage 158, a stylized level voltage 160, a stylized step 162, or a combination thereof. The threshold voltage 156 may be a voltage applied to the control gate, under which the circuit for the memory cell 122 becomes conductive and a current can be measured. The threshold voltage 156 can be affected and controlled by controlling the amount of charge held in a floating gate or charge trap of the memory cell 122. The memory device 102 may store a charge amount into the memory cell 122 based on the programmed level voltage 160 to represent a corresponding data value. The memory device 102 applies a programmed level voltage 160 to a control gate or word line to charge a floating gate or charge trap. Floating gates or charge traps can be electrically isolated, which enables the memory cells to store and retain charge.

The memory device 102 may use stored charges to represent data. For example, storing charge on a floating gate or charge trap can be used to store a bit value of 0 for an SLC type cell. A bit value of 1 may correspond to a floating gate or a charge trap without storing charge for the SLC. In other types of cells, such as MLC, TLC, or QLC, the memory device 102 may store a specific amount of charge on a floating gate or charge trap to represent different bit values. Cells of the MLC type can have 4 different charge states, TLC can have 8 different charge states, and QLC can have 16 different charge states. As discussed above, each of these charge states may correspond to a unique binary value.

The memory device 102 can read or determine the data value stored in the memory cell 122 using the read level voltage 158 corresponding to the data value. The memory device 102 can apply a read level voltage 158 to the control gate and measure the current or voltage across the memory cell to read the data stored in the cell. The charge stored in the floating gate or charge trap can shield or offset the amount of charge placed on the control gate for reading or accessing the stored data. Therefore, when the read level voltage 158 is applied, the measured current or voltage across the memory cell will correspond to the amount of charge stored in the floating gate or charge trap.

During operation of the memory device 102, the electrical characteristics (i.e., charge retention ability) of the device can be changed due to repeated data writing, erasing, and / or reading. Repeated data operations can cause breakdown or wear of structures that electrically isolate floating gates or charge traps (eg, oxide layers). In consideration of changing the electrical characteristics of the memory cell 122, the memory device 102 can shift or calibrate the read level voltage 158.

The programmed level voltage 160 is associated with a read level voltage 158 and a threshold voltage 156. The stylized level voltage 160, read level voltage 158, threshold voltage 156, or a combination thereof may correspond to the number of bits stored in the memory cell 122, the specific content of the data stored in the memory cell 122, Value or a combination thereof.

For example, a memory cell 122 (e.g., an SLC memory cell) configured to store charge in one of two possible states may have a different configuration than a combination configured to store charge in one of four possible states Memory cell 122 (e.g., MLC memory cell) or memory cell 122 (e.g., TLC memory cell) configured to store charge in one of eight possible states Program level, read level and threshold voltage. For various types of memory cells (e.g., SLC, MLC, TLC, QLC, etc.), one of the programmed level voltage 160, read level voltage 158, threshold voltage 156, or a combination thereof can be combined with possible data Each of the values is associated.

The memory device 102 may repeatedly store charges in the memory cell 122 for writing or programming operations, such as incremental step pulse programming (ISPP). The stylized step 162 may include an increment or a voltage value for increasing the stored charge in each iteration. The memory device 102 may reach the programmed level voltage 160 by incrementally storing or increasing the amount of charge corresponding to the programmed step 162.

For example, FIG. 2 illustrates the charges stored on the charge storage structure of a memory cell under various states of this incremental programming operation. When the incremental programming operation starts, the charge 211 stored on the memory cell at time 210 is lower than a desired target state 250. To program the memory cell to the desired target state 250, a series of programmed steps 162 can be used at each of times 220, 230, and 240 to increase the charge stored on the charge storage structure of the cell as a charge, respectively. 222, 232 and 242. After each stylized step 162, the charge stored on the charge storage structure can be verified to determine whether it has reached the desired target state 250. At time 240, as the charge 241 has increased to the desired target state 250, the stylized operation is complete.

To program higher significant bits to a cell that has been programmed with lower significant bits, the number of stylized steps 162 (and verification steps) used in a stylized operation may be larger (e.g., Due to the addition of a smaller charge increment with each stylized pulse), programming more significant bits to a cell can require more time and energy than programming less significant bits.

The processing level 154 may be stored in the memory device 102, the host device 108, or a combination thereof. For example, the memory device 102 may include one or more level registers 164 on the controller 106, a memory array 104, another memory location of the memory device 102, or a combination thereof for storing processing levels. 154. The level register 164 may store a threshold voltage 156, a read level voltage 158, a stylized level voltage 160, a stylized step 162, or a combination thereof. The memory system 100, the controller 106, and / or the host 108 may access the level register 164, write or adjust the values in the level register 164, or a combination thereof. Similarly, the processing level 154 may be stored in the embedded memory of the controller 106, the memory array 104, another memory location of the memory device 102, or a combination thereof.

The memory device 102 may further process errors associated with the storage or access of data. An error may correspond to a bit or unit of bits, such as a codeword, page, or block, that may be introduced during an erase, stylization or write, or read operation. In addition to data processing, data retention can further introduce retention errors. Other sources of error may include program variations, defects, electrical or parasitic capacitive coupling, changes in the characteristics or capabilities of the circuit or its components, or combinations thereof.

The memory device 102 may track an error metric 166. The error metric 166 may represent a degree describing the error, a frequency, a magnitude or magnitude, a size or number, a processing derivation of the error, or a combination thereof. For example, the error metric 166 may include an error count 168, an error rate 170, or a combination thereof. The error count 168 may represent a quantity or magnitude, a degree, a size or number, or a combination thereof that describes the error. For example, the error count 168 may be a one-bit error count (BEC). The error rate 170 may represent a frequency or probability of an error occurrence, a proportional amount or a percentage of the error, or a combination thereof. For example, the error rate 170 may include a one-bit error rate (BER). The error metric 166 may correspond to one or more cells or groups within the memory array 104. For example, the error metric 166 may be directed to one or more of a memory page 124, a memory cell 122, a word line group 144, a die, or a combination thereof. Also for example, the error metric 166 may correspond to a page type 146, such as the next page 148, the previous page 150, or the extra page 152. The error metric 166 may be calculated or tracked by the host device 108, the controller 106, or a combination thereof. The error metric 166 may be stored in the host device 108, the embedded memory of the controller 106, the memory array 104, another memory location of the memory device 102, or a combination thereof.

The memory system 100 may utilize an error recovery mechanism 172 to detect and / or correct errors. The memory system 100 may implement the error recovery mechanism 172 using the host device 108, the controller 106, the memory array 104, or a combination thereof. The error recovery mechanism 172 may include a procedure, function, circuit, or a combination thereof for detecting errors in stored or accessed data and further for correcting errors and recovering the original desired data. Online corrections such as based on or used for one or more codewords and overall data recovery may be examples of error recovery mechanisms 172. For another example, the error recovery mechanism 172 may detect and / or utilize an error correction code (ECC) of a codeword (such as a Hamming code, a Low Density Parity Check (LDPC) code, or a Bose-Chauduri-Hocquenghem (BCH) code). Correct the error.

The memory system 100 may further generate and maintain a background record 174. The background record 174 may include information describing a history of the memory device 102. For example, the background record 174 may track errors, error rates 170, use or implementation of the error recovery mechanism 172, corresponding description or contextual information, a processing result or its representation, or a combination thereof. Also for example, the background record 174 may track processing results, such as data, levels, results, statistical representations, or combinations thereof, associated with dynamic calibration of various aspects or operations of the memory device 102. The background record 174 may be tracked using the controller 106, the host device 108, or a combination thereof. The background record 174 may be stored in the memory array 104, the embedded memory of the controller 106, another memory location of the memory device 102, the host device 108, or a combination thereof.

The memory system 100 may dynamically calculate or adjust the processing level 154 based on the feedback information. For example, the memory system 100 may continuously update the read level voltage 158 using a processing level calibration mechanism 176. For another example, the memory system 100 may use the one-step calibration mechanism 180 to dynamically update or adjust the stylized steps 162. In addition, the memory system 100 may dynamically generate or adjust a distribution target representing a histogram that displays the number of memory cells having a specific measurement value (for example, a threshold voltage level) corresponding to a specific logic value . The measured value can be shifted due to breakdown of the oxide layer. The memory system 100 may use a target calibration mechanism 178 to dynamically adjust the distribution target based on the feedback data to adjust the shift of the measured value. The processing level calibration mechanism 176, the target calibration mechanism 178, and the step calibration mechanism 180 may each be a unique program, method, function, circuit, configuration, or a combination thereof for performing the above-mentioned calibration. Details regarding the processing level calibration mechanism 176, the target calibration mechanism 178, and the step calibration mechanism 180 are discussed below.

3A, 3B, and 3C show graphs relating error counts (shown along the Y-axis) of a memory page to reading voltages (shown along the X-axis) from data read from a cell. 3A, 3B and 3C show a process of processing the level calibration mechanism 176 (FIG. 1). The processing level calibration mechanism 176 can adjust the read level voltage 158 to reduce the error count 168, as shown in FIGS. 3A to 3C. Although the drawings show an embodiment in which the calibration mechanism uses a measured error count to calibrate a read level voltage, in other embodiments, the present invention can be used to consider other measurement characteristics (bit error rate, etc. ) Similarly calibrate other processing levels (eg, stylized voltage, threshold levels, etc.).

For illustrative purposes, the processing level calibration mechanism 176 is described below using the read level voltage 158. However, it should be understood that the processing level calibration mechanism 176 may be implemented for the threshold voltage 156 (FIG. 1), the stylized level voltage 160 (FIG. 1), the stylized step 162 (FIG. 1), or a combination thereof.

FIG. 3A to FIG. 3C show the read level voltage 158 and the sequential changes, adjustments or calibrations of the corresponding samples and results when the processing level calibration mechanism 176 is implemented. The memory system 100 (FIG. 1) may implement a processing level calibration mechanism 176, including repeated changes, adjustments or calibrations of the read level voltage 158. The memory system 100 may further implement the processing level calibration mechanism 176 multiple times within a duration to repeatedly adjust the reading level voltage 158.

FIG. 3A shows an exemplary behavior before the processing level calibration mechanism 176 is implemented or in the absence of the processing level calibration mechanism 176. When the process level calibration mechanism 176 is initiated or implemented, the memory system 100 may use one or more of these components to sample data and generate or update a test measurement set. The test measurement set may include a central result 304, a first offset result 306, a second offset result 308, other results, or a combination thereof. The memory system 100 may generate or update the test measurement set based on using the read level voltage 158 or using a voltage offset from the read level voltage 158 to determine a result corresponding to a set of read operations.

For example, the memory system 100 may determine the center based on determining an error count 168 corresponding to data read or accessed using a read level voltage 158 for a particular page type of one of the examples of the memory page 124 (FIG. 1). Results 304. The center result 304 of the original, unadjusted, or uncalibrated instance corresponding to the read level voltage 158 is represented as "O" in FIG. 3A.

The memory system 100 may similarly determine the first offset result 306 based on determining an error count 168 corresponding to data read or accessed using a first offset level 316. The memory system 100 may similarly determine the second offset result 308 based on determining an error count 168 corresponding to data read or accessed using a second offset level 318. The first offset level 316 is indicated by a vertical dashed line leading from the x-axis to the graph. The corresponding position of the graph is shown as a triangle positioned to the right and above the center result 304 in FIG. 3A. The second offset level 318 is indicated by a vertical dotted line leading from the x-axis to the graph, where the corresponding position on the graph is positioned to the left and below the center result 304 in FIG. 3A.

The first offset level 316 and the second offset level 318 may each be a voltage level for reading or accessing data stored in a corresponding instance of the memory cell 122 (FIG. 1). The first offset level 316 and the second offset level 318 may be different from each other and different from the read level voltage 158. For example, the first offset level 316 may be greater than the read level voltage 158. For another example, the second offset level 318 may be smaller than the read level voltage 158.

For another example, the first offset level 316, the second offset level 318, or a combination thereof may be offset from the read level voltage 158 by an offset measure 320. The offset metric 320 may represent one or more offset levels or an offset from one of the read level voltages 158. The offset metric 320 may further represent a direction or a symbol, a degree or a magnitude, or a combination thereof, from a distance or an offset.

The memory system 100 implementing the level calibration mechanism 176 may select a die, a memory block, a memory page, a trimming or reading level voltage 158 corresponding to a page type of the page, or And other combinations. The selection can be random. In addition, selection can occur as part of an iterative process. The details on selection are discussed below. After the selection, the memory system 100 may at least target the test measurement set sampling center result 304, the first offset result 306, and the second offset result 308. The memory system 100 may use both the first offset level 316 and the second offset level 318 that are offset from the read level voltage 158 in the opposite direction by an offset measure 320. The memory system 100 may use the center result 304, the first offset result 306, and the second offset result 308 to adjust or calibrate the read level voltage 158.

The memory system 100 may adjust, update or calibrate the read level voltage 158 based on comparing or balancing various results. The memory system 100 may further calibrate the read level voltage 158 based on adjusting or updating the offset metric 320. The memory system 100 can dynamically further calibrate the read level voltage 158. The memory system 100 may additionally be used during the manufacture, configuration, or setup of the memory device 102 (FIG. 1) or as part of the manufacture, configuration, or setup of the memory device 102 (FIG. 1). 1) Before the desired deployment or use, the reading level voltage 158 is calibrated using the processing level calibration mechanism 176. Details regarding the processing level calibration mechanism 176 are discussed below.

FIG. 3B shows the read level voltage 158 adjusted or calibrated compared to the read level voltage 158 shown in FIG. 3A. FIG. 3B may represent one of the processing level calibration mechanisms 176 implemented repeatedly during one of the implementations of the processing level calibration mechanism 176 or before the read level voltage 158 has settled or centered along the graph. The read level voltage 158 is shown in FIG. 3B as being lower or further to the left than in FIG. 3A. It should be understood, however, that the read level voltage 158 can be adjusted in any direction and adjusted to any increment or value. The processing level calibration mechanism 176 may, for example, adjust the read level voltage 158 according to the current conditions or characteristics of the memory cell 122 to reduce the error rate or count of the corresponding memory cell 122.

The read level voltage 158 can be calibrated in various ways. For example, the read level voltage 158 may be incremented or shifted by a predetermined amount or increment based on comparing or balancing various results. As another example, the read level voltage 158 may be assigned a predetermined value corresponding to one or more results of the sampling procedure. Also for example, the read level voltage 158 may be replaced by the first offset level 316 or the second offset level 318 based on one or more of these results. Details of the calibration of the read level voltage 158 are discussed below.

Once the read level voltage 158 has been calibrated, the memory system 100 can repeat the process. For example, the memory system 100 may use the updated, adjusted, or calibrated instance of the read level voltage 158 to calculate a new offset level or a combination thereof for processing subsequent or subsequent iterations of the level calibration mechanism 176 Or implementation. The results can be processed and the read level voltage 158 can be further calibrated accordingly. This procedure can be repeated until the read level voltage 158 and the corresponding result satisfy a stop or an interrupt condition. For example, when the read level voltage 158 corresponds to the estimated minimum instance of the error count 168, it corresponds to one of a graph (as shown in FIGS. 3A to 3C) that correlates the error count with the read level The program can be stopped at a minimum point or a center point.

FIG. 3C may illustrate exemplary behaviors after the implementation of the processing level calibration mechanism 176 or for subsequent or subsequent implementations of the processing level calibration mechanism 176. As shown, the implementation of the processing level calibration mechanism 176 may adjust or calibrate the read level voltage 158 to be located at a threshold distance or a bottom or minimum of one of the graphs that correlate the error count to the read level or Inside. The processing level calibration mechanism 176 utilizes the central result 304 corresponding to the read level voltage 158 and one or more offset results corresponding to the respective results to provide the benefit of reducing errors introduced by the read. The processing level calibration mechanism 176 can find different reading level voltages 158 to reduce reading errors based on repeatedly testing different possible values of the reading level voltage 158 and comparing corresponding error counts.

The memory system 100 may further calculate an error difference metric 322. The error difference measure 322 is a comparison between the center result 304 and one or more of the offset results. The error difference metric 322 may be a distance or a difference between the error counts 168 including a combination of the results of the center result 304, the first offset result 306, and the second offset result 308. For example, the memory system 100 may calculate an error difference measure 322 as a difference between the central result 304 and an average of the first offset result 306 and the second offset result 308. For another example, the memory system 100 may calculate an error difference metric based on a difference metric between the center result 304 and the first offset result 306, a difference metric between the center result 304 and the second offset result 308, or a combination thereof. 322. The error difference metric 322 may be a feedback metric for one of one or more institutions. For example, a one-bit quasi-calibration feedback metric 302 (ie, a value, a result, a metric, or a combination thereof that is further used as an input for one or more of the calibration processing levels 154) may include an error difference metric 322. For another example, the error difference metric 322 may be a feedback metric for implementing the target calibration mechanism 178 (FIG. 1), the step calibration mechanism 180 (FIG. 1), or a combination thereof. Details on the error difference measure 322 are discussed below.

4A, 4B and 4C show a process of the target calibration mechanism 178 (FIG. 1). The target calibration mechanism 178 may adjust a desired distribution of one of the program verification levels according to the current behavior of the memory cells. 4A, 4B, and 4C correspond to one TLC page including or corresponding to the next page 148, the previous page 150, and the additional page 152 (all shown in FIG. 1). Example illustrations show the number of occurrences of a particular trim level along a vertical direction or axis. Example illustrations show voltage levels along a horizontal direction or axis.

FIG. 4A shows an example of a target quantity curve 402 of the memory system 100 (FIG. 1). For a given set of memory cells 122 (Figure 1) (such as a page, a logical or stored value, a word line group, a word line, a die, or a combination thereof), the target quantity change curve 402 is a processing bit The target 154 (such as the threshold voltage 156 or the read level voltage 158) (both in FIG. 1) is one of the target or expected results. For example, the target quantity variation curve 402 may include a program verification (PV) target, a desired Gray code distribution, a desired write distribution, or a combination thereof.

The memory system 100 may use the target quantity variation curve 402 to control the behavior, operation, or procedure of the memory device 102 (FIG. 1). The target quantity variation curve 402 may specify a desired or target quantity or quantity corresponding to one of the processing levels 154 (Figure 1) of the voltage level, page type 146 (Figure 1), or a combination thereof. The memory system 100 may further use the target calibration mechanism 178 (FIG. 1) to further adjust or calibrate the target quantity variation curve 402. The target quantity change curve 402 may include a distribution target 404 of each logical value or one of corresponding voltage levels. The distribution target 404 may correspond to a desired number or occurrence of a set of processing levels 154 corresponding to a particular content value, page type 146, or a combination thereof. Each instance of the distribution target 404 may correspond to a unique instance of a possible content value. The voltage level corresponding to the distribution target 404 may represent a satisfactory or desired range of one of the processing levels 154 of the corresponding data value.

For a TLC page such as illustrated in FIGS. 4A-4C, each of the memory cells 122 can store three bits. Three bit storage can be equal to eight possible content values 0 to 7 or bit values "000", "001", "010", "011", "100", "101", "110" and "111" ". Each of the possible content values is identified using level recognition, such as L0 to L1 in FIGS. 4A to 4C. Assignment of a predetermined bit value to a specific voltage range may be performed by the memory system 100, a developer or manufacturer, a standard or a template, or a combination thereof. The target quantity variation curve 402 may further include or represent a distribution valley 406. The distribution valley 406 is one of a relationship between adjacent distribution targets. The distribution trough 406 may represent a cross, a distance, an overlap, or a combination thereof between two adjacent distribution targets. The distribution valley 406 may be between two adjacent instances of the distribution target 404, at the boundary of the two adjacent instances of the distribution target 404, or a combination thereof. The distribution trough 406 may be where one or more of the distribution targets 404 cross a threshold level or number, where multiple target levels meet or overlap, or a combination thereof.

For a TLC page such as illustrated in Figures 4A to 4C, there may be 8 valley values. Each of the distribution troughs 406 is identified using trough recognition, such as v1 to v7 in FIGS. 4A to 4B (not shown in FIG. 4C). Each valley value may correspond to a unique division or threshold for one of the next page 148, the previous page 150, and the extra page 152, which may be used to determine the content stored in the corresponding cell. Each of the distribution valley values 406 can be used to determine the next page 148, the previous page 150, the extra page 152, the bit value at the corresponding position, or a combination thereof. The assignment or correlation between the distribution trough 406 and the unique value and / or page type 146 may be based on one of a predetermined order, sequence, configuration, or combination of various bit value assignments.

The memory system 100 may use the edge target 408 as a reference point and dynamically adjust the intermediate target 409. The edge target 408 represents an example of a distribution target 404 corresponding to the lowest and highest voltage levels. The intermediate target 409 includes an example of a distributed target 404 between the edge targets 408. The memory system 100 may implement a target calibration mechanism 178 to adjust or balance the intermediate target 409 or the corresponding distribution valley 406.

FIG. 4B shows a one-bit quasi-distribution curve 410. The level distribution curve 410 may be a histogram showing a plurality of memory cells 122 having a specific measured value (for example, the threshold voltage 156 in FIG. 1). The level distribution curve 410 may represent an actual count of one of the memory cells 122 or a current state. The target quantity change curve 402 can be used to control or adjust a program or level to control or manage the level distribution curve 410. For example, the level distribution curve 410 may include an actual program verification status, an actual Gray code distribution, an actual write distribution, or a combination thereof. The memory system 100 can determine and track various information of the level distribution curve 410. The level distribution curve 410 may change over time and due to use. Due to a change, a corresponding update or change of the processing level 154, or a combination thereof, the level distribution curve 410 may further deviate from the target quantity change curve 402. The memory system 100 may use the target calibration mechanism 178 to adjust or calibrate the target quantity variation curve 402 accordingly.

FIG. 4C illustrates the adjustment, update or calibration of the target quantity variation curve 402. The memory system 100 implementing the target calibration mechanism 178 may generate an adjusted target 420 for replacing one or more of the previous targets. In FIG. 4C, a previous target, such as originally depicted in FIG. 4A, is shown using dashed lines, and the adjusted target 420 is shown using dashed lines. The memory system 100 may generate an adjusted target based on shifting or moving one or more previous targets higher or lower in the voltage level (such as left or right as shown in FIGS. 4A to 4C). 420. The memory system 100 may generate an adjusted target 420 based on the target adjustment value 422. The target adjustment value 422 may represent a direction, a magnitude or a magnitude, or a combination thereof, corresponding to a change in the voltage level of the distribution target 404. The target adjustment value 422 may further correspond to a change in the depth, magnitude, degree or amount of the corresponding distribution valley 406, or a combination thereof. The memory system 100 may implement a target calibration mechanism 178 and adjust the target quantity variation curve 402 to balance the distribution target 404, the distribution valley 406, or a combination thereof across various bit values. Details regarding the error difference measurement 322 and the target calibration mechanism 178 are discussed below.

The error difference measure 322 provides a depth or a magnitude of the distribution valley 406 and a quantified representation of the corresponding RWB. The target calibration mechanism 178 uses the error difference metric 322 as a feedback metric to adjust or balance one or more instances of the distribution target 404 to provide the benefits of uniform use and wear of the memory device 102 to extend the life of the memory cell 122.

5A and 5B are exemplary illustrations of the process of the step calibration mechanism 180 (FIG. 1). Exemplary illustrations represent the amount of charge stored in a memory cell along a vertical direction or axis. Example illustrations show time along a horizontal direction or axis.

FIG. 5A illustrates a programmed operation of a memory cell before the step calibration mechanism 180 (FIG. 1) is implemented. The memory system 100 (FIG. 1) can be programmed or written by storing a target charge quantity in a memory cell, where the target quantity value or level represents a specific content or bit value. The memory system 100 can be programmed or written to the programmed level voltage 160 by storing an amount of charge (FIG. 1). The memory system 100 may be programmed or written by storing incremental charge amounts in the memory cells in an iterative process (such as for ISPP). For example, the memory system 100 may repeatedly apply multiple pulses for increasing the charge stored in the memory cells. The memory system 100 may use the stylized step 162 to incrementally increase the stored charge until the stored amount or level matches the stylized level voltage 160. The memory system 100 can be programmed and verified for each pulse or repeatedly. 5A is repeatedly shown as "I1", "I2", and "I3".

A stylized time 502 is a duration associated with reaching the stylized level voltage 160. The programmed time 502 may be associated with the number of iterations required to reach the programmed level voltage 160, a programmed step 162 for each iteration, or a combination thereof. The memory system 100 may implement a step calibration mechanism 180 to dynamically adjust or calibrate the stylized steps 162. The memory system 100 may dynamically increase or decrease the programming step 162, which will correspondingly increase or decrease the programming time 502. Details regarding the step calibration mechanism 180 are discussed below.

FIG. 5B illustrates a stylized operation after the step calibration mechanism 180 (FIG. 1) is implemented. For comparison, previous levels and steps such as in FIG. 5A are shown with dashed lines. The step calibration mechanism 180 can generate an adjusted step 504. Adjusted step 504 is a calibrated or changed instance of one of stylized steps 162 used to replace stylized step 162. The adjusted step 504 may be larger or smaller than the stylized step 162.

Dynamically generating the adjusted step 504 to increase the stylized step 162 provides the benefit of reducing the stylized time 502. The increase of the stylized step 162 can reduce the number of pulses or iterations required to reach the stylized level voltage 160, thereby reducing the amount of corresponding time. Therefore, the dynamic calibration and adjustment of the stylized steps 162 improves the overall efficiency of the memory system 100.

In addition, the adjusted step 504 may be generated based on a trigger measure or an implementation measure or a processing result representing the error recovery mechanism 172 (FIG. 1). Considerations that trigger the error recovery mechanism 172 when generating the adjusted step 504 provide a reduction in the stylized time 502 without increasing the error metric 166 (Figure 1). Details regarding the step calibration mechanism 180 are discussed below.

FIG. 6 is a flowchart illustrating an exemplary method 600 of operation of the memory system 100 (FIG. 1) according to an embodiment of the present invention. The method 600 may include implementation of a processing level calibration mechanism 176 (FIG. 1). It may be, for example, a processing circuit for one of the memory device 102 or the host device 108 (such as the controller 106, the memory array 104, the processor for the host device 108, some of it, or a combination thereof (all in FIG. 1) ) Perform or implement a process level calibration mechanism 176. The processing level calibration mechanism 176 may include a configuration of the controller 106, the memory array 104, the host device 108, or a combination thereof. The processing level calibration mechanism 176 may further include stored in the controller 106, the memory array 104, the host device 108, or a combination thereof, or accessed using one of the controller 106, the memory array 104, the host device 108, or a combination thereof. Or multiple methods, procedures, steps or instructions, information, or combinations thereof.

The processing level calibration mechanism 176 may be utilized or implemented to adjust the processing level 154 (FIG. 1), such as a read level voltage 158 (FIG. 1). The processing level calibration mechanism 176 may begin based on determining or identifying a sampling trigger 620. The sampling trigger 620 may indicate a state, a signal, a configuration, or a result used to prompt or start processing the level calibration mechanism 176. For example, the sampling trigger 620 may include a signal or a command from the host device 108 (FIG. 1), such as an interrupt service routine. For another example, the sampling trigger 620 may include a specific state of the memory device 102, the memory system 100, or a combination thereof, such as power on or power off. Also for example, the sampling trigger 620 may include a specific number of operations or procedures, a time of day, or a combination thereof.

At block 602, the processing level calibration mechanism 176 may select one of the memory pages 124 (FIG. 1), a fully-programmed memory page for grouping the memory cells 122 (FIG. 1) for processing. The selected page may correspond to one or more page types based on cell types, such as SLC, MLC, and TLC. The selected page may further correspond to one of the word line groups 144 and a word line. It can be selected randomly, repeatedly, or a combination thereof. In general, page selection can be random based on one of the memory blocks 126 (FIG. 1) within each die being randomly selected for each outer iteration. In addition, the memory system 100 may select one of the fully programmed memory blocks 126. The selection of the grouping of the memory cells 122 can be accomplished in various ways.

For example, the memory system 100 may randomly select one of the memory pages 124 based on randomly selecting one of the memory blocks 126 containing the memory page. The memory system 100 may use a read level voltage 158 corresponding to the next word line group corresponding to the next page 148 (Figure 1), the previous page 150 (Figure 1), the extra page 152 (Figure 1), or a combination thereof. Selected pages 124 are repeatedly sampled. Therefore, the memory system 100 may select all trimming or processing levels 154 of all page types of each word line group for the same page. For another example, the memory system 100 may randomly select a page based on randomly selecting one of the memory blocks 126 containing the selected page. Once the block is selected, the page can be selected randomly for each sampling procedure. In other words, the processing level calibration mechanism 176 can choose to make the trimming of different page types of each word line group for random pages sampled.

At block 604, the processing level calibration mechanism 176 may obtain one or more of the processing levels 154 that are trimmed or determined to correspond to the memory page 124. For example, the controller 106, the host device 108, or a combination thereof may access the level register 164 (FIG. 1) to obtain one or more of the trimming or decision processing levels 154. As a more specific example, the controller 106 may determine a read level voltage 158 corresponding to the next page 148, the previous page 150, the extra page 152, or a combination thereof for accessing the stored information according to the selected page.

At block 606, the processing level calibration mechanism 176 may provide one or more offset processing values. For example, the controller 106, the host device 108, or a combination thereof may calculate the first offset level 316 (FIG. 3) and the second offset level 318 based on the read level voltage 158 and the offset measure 320 (FIG. 3). (Figure 3) or a combination thereof. As a more specific example, the controller 106 may access offset metrics 320 stored in embedded memory therein, received from the host, stored on the memory array 104, or a combination thereof. The controller 106 may calculate the first offset level 316 based on adding the offset measure 320 to the read level voltage 158 or based on shifting from the read level voltage 158 in one direction according to the offset measure 320. The controller 106 may further calculate the second offset level 318 based on subtracting the offset measure 320 from the read level voltage 158 or based on shifting from the read level voltage 158 in the opposite direction according to the offset measure 320.

At block 608, the processing level calibration mechanism 176 may sample according to one or more levels. For example, the controller 106, the host device 108, or a combination thereof may determine that one or more results corresponding to one or more of the processing levels 154 or their (or) offsets, such as a read level voltage 158 together with Offset level 316, second offset level 318, or a combination thereof.

As a more specific example, the controller 106, the host device 108, or a combination thereof may use the read level voltage 158 to determine the center result 304 (FIG. 3) for processing the data of the memory cell 122 corresponding to the selected page. The memory system 100 can use the central result 304 to read the stored data. The memory system 100 may use ECC to implement an error correction / detection mechanism on the accessed data to handle any errors corresponding to the read level voltage 158. The memory system 100 may determine an error count 168 (FIG. 1) corresponding to the read level voltage 158 to determine the central result 304.

Continuing the example, the memory system 100 may similarly calculate an error count 168 corresponding to the first offset level 316, the second offset level 318, or a combination thereof. The memory system 100 may determine that the first offset result 306 (FIG. 3) is an error count 168 due to data accessed using the first offset level 316. The memory system 100 may determine that the second offset result 308 (FIG. 3) is an error count 168 due to data accessed using the second offset level 318. The memory system 100 can perform four reads from the same read threshold or the same MLBi trim register.

The memory system 100 may store one or more error counts or results, corresponding levels, or combinations thereof. The memory system 100 may store the central result 304, the first offset result 306, the second offset result 308, the corresponding processing level, or a combination thereof in the embedded memory of the controller 106, the memory array 104, and the host device. 108 or a combination thereof.

At block 610, the processing level calibration mechanism 176 may evaluate the result of adjusting or calibrating the processing level 154. For example, the memory system 100 may evaluate the results by calculating a level calibration feedback metric 302 (FIG. 3) based on the center result 304, the first offset result 306, the second offset result 308, or a combination thereof. The memory system 100 may calculate a level calibration feedback measure 302 including a one-level adjustment measure 622, an error difference measure 322 (FIG. 3), or a combination thereof. The level calibration feedback metric 302 may indicate a larger value between the first offset result 306 and the second offset result 308, and the difference between the first offset result 306 and the second offset result 308 relative to the center result 304. A larger value or a combination thereof.

As a more specific example, the memory system 100 may determine the level adjustment measure 622 as an indication or a result based on the comparison center result 304, the first offset result 306, the second offset result 308, or a combination thereof. As a further specific example, the memory system 100 may determine that the level adjustment measure 622 is a difference between the first offset result 306 and the second offset result 308, or the first offset result 306 and the second offset result 306. The larger one of the offset results 308 indicates.

As a more specific example, the memory system 100 may calculate an error difference metric 322 based on two or more of the combined center result 304, the first offset result 306, and the second offset result 308. As a further specific example, the memory system 100 may calculate an error difference measure 322 as a difference between the first offset result 306 and the center result, a difference between the second offset result 308 and the center result 304, or the like combination.

Continuing the example, the memory system 100 may also calculate the error difference measure 322 as a combination of the central result 304 and one of the first offset result 306 and the second offset result 308 (such as its mathematical derivation, its logical combination, or its statistical representation). Or average). The processing level calibration mechanism 176 may include a method, a formula, a program, a circuit, or a combination thereof that is configured to calculate an error difference metric 322 based on the error count resulting from the sampling steps represented in block 608.

At block 612, the processing level calibration mechanism 176 may determine that one of the processing levels 154 is updated. The memory system 100 may generate an updated level 624 based on various results. The updated level 624 reads a new adjusted or calibrated value of one of the level voltages 158. The updated level 624 can replace the previous use case of the read level voltage 158. The memory system 100 may generate the updated level 624 in various ways. For example, the controller 106, the host device 108, or a combination thereof may generate an updated level 624 based on various results. As a more specific example, the memory system 100 may generate the updated level 624 as the read level voltage 158, the first offset level 316, or the second offset level 318 corresponding to the lowest instance of the error count 168. . As a more specific example, the memory system 100 may generate the updated level 624 as a result of a weighted average of one of the read level voltage 158, the first offset level 316, and the second offset level 318. Each weighted average is based on the error count 168 or the corresponding instance of the result.

For another example, when more than one test level results in the same bit error rate, the memory system 100 may select a lower threshold value as the updated level 624. As a more specific example, if both the read level voltage 158 and the lower offset level correspond to the same error rate, the memory system 100 may select the lower offset level as the updated level 624.

Also for example, the controller 106, the host device 108, or a combination thereof may generate the updated level 624 based on adjusting the processing level 154 according to various results. The memory system 100 may generate updated levels based on the level adjustment metric 622 and read level voltage 158 used to generate the samples (such as by shifting or incrementing the read level voltage 158 based on the level adjustment metric 622). 624.

Also for example, the controller 106, the host device 108, or a combination thereof may be based on the error difference measure 322 (such as by based on a history or previous instance of various read levels and corresponding error counts, various read levels and corresponding error counts) , Or a combination thereof, calculates the updated level 624 as a prediction or an estimate corresponding to one of the lowest estimated error counts) to generate the updated level 624. As a more specific example, the memory system 100 may utilize a curve fitting or estimation function, a slope calculation, or a combination thereof to estimate the level corresponding to the minimum error count.

The memory system 100 may generate updated levels 624 for subsequent processing of the data of the memory page 124. The memory system 100 may further generate updated levels 624 for balancing the first offset result 306 and the second offset result 308. The memory system 100 may generate an updated level 624 to seek to center the read level voltage 158 at the minimum error count as shown in FIG. 4B, so that the first offset result 306 and the second offset result 308 The corresponding instances are similar in magnitude or within one of the thresholds of each other.

The memory system 100 may determine whether the processing level 154 for the sampling procedure is centered. For example, the memory system 100 may generate a centered state 626 based on a trend, pattern, or behavior of the read level voltage 158. The centered state 626 indicates a judgment or a result that indicates that one of the read level voltage 158 or the adjustment of the read level voltage 158 is at or near the minimum error count as shown in FIG. 3C.

The memory system 100 may generate the centered state 626 in various ways. For example, if the updated level 624 is the same as or within the threshold level of the read level voltage 158, the centered state 626 may indicate that the read level voltage 158 used is centered. For another example, the centered state 626 may indicate that the read level voltage 158 before the current iteration is the lowest based on comparing the current count and previous or previous error counts or results. The centered state 626 indicates that the read level voltage 158, the updated level 624, or a combination thereof is at one of the targets or desired instances of the processing level 154.

For another example, the memory system 100 may generate a centered state 626 based on a previously changed direction 628 and a currently changed direction 630. The previous change direction 628 is used to read a pattern, a trend, a behavior, or a combination thereof of one of the previous examples of the level voltage 158. The previously changed direction 628 may include one of the slopes of one or more instances of the read level voltage 158 before the current iteration or one of its symbols. The memory system 100 may calculate the previous change direction 628 based on at least one previous instance of the processing level 154 and the current instance of the processing level 154.

The current change direction 630 is a pattern, a trend, a behavior, or a combination thereof for reading a current instance of the level voltage 158, the updated level 624, or a combination thereof. The previous change of direction 628 may include a previous instance of the read level voltage 158 relative to the read level voltage 158 or a slope or a sign between the read level voltage 158 and the updated level 624. The memory system 100 may calculate a current change direction 630 based on the current read level voltage 158 and the updated level 624.

The memory system 100 may generate a centered state 626 based on comparing the current direction of change 630 with the previous direction of change 628. The memory system 100 may generate a centered state 626 when the current direction of change 630 and the previous direction of change 628 indicate an error count 168 across one of repeated patterns or behavior changes. For example, when the current change direction 630 and the previous change direction 628 are different, for example, when the sampling result is shaken near the minimum point shown in FIG. 3C or when the minimum point is passed, the memory system 100 may generate a centered state 626.

The memory system 100 may further utilize other parameters to generate the centered state 626. For example, the memory system 100 may be based on one or more slopes between the central result 304 and the first result 306, between the central result 304 and the second result 308, between the first result 306 and the second result 308, or the like The combination produces a centered state 626. For another example, the memory system 100 may generate a centered state 626 based on a pattern or trend of various slopes or results corresponding to adjustment or calibration over time. The memory system 100 may use the centered state 626 as a flag to interrupt the offset calculation, sampling, evaluation, and update steps. Instead, the memory system 100 may store the final updated level 624 in a level register 164 corresponding to the evaluated memory page 124.

For subsequent implementations of the processing level calibration mechanism 176, the memory system 100 may remove the centered state 626 based on the initial comparison of the read level voltage 158 and the updated level 624. When the read level voltage 158 and the updated level 624 are the same or within a predetermined threshold, the memory system 100 maintains the centered state 626. When the read level voltage 158 and the updated level 624 are different or further separated beyond a predetermined threshold, the memory system 100 may cancel or remove the centered state 626.

The memory system 100 may use the updated level 624, the centered state 626, or a combination thereof to keep each of the processing levels 154 or thresholds centered. The updated level 624 provides the benefit of improved performance for minimizing the bit error rate during operation of the memory system 100. The updated level 624 and the processing level calibration mechanism 176 can dynamically update the read level voltage 158 to adjust for any changes or wear during the desired use period after the manufacture, initial configuration and deployment of the memory device 102 And calibration.

At block 614, the processing level calibration mechanism 176 may calculate a gain control 632. The gain control 632 is configured to dynamically adjust a distance between the read level voltage 158 and the first offset level 316, and the gain between the read level voltage 158 and the second offset level 318. A parameter of an offset measure 320 from a distance or a combination thereof. The gain control 632 may be used by the processing level calibration mechanism 176 to effectively widen or narrow an interval or distance between the center sample and the low / high sample by controlling the offset measure 320. A deviation or offset from the read level voltage 158 set to a non-optimal voltage may increase the error count 168. Therefore, the gain control 632 may be calculated based on the restoration limit 634 so that the first offset result 306 and the second offset result 308 will remain below the restoration limit 634.

The controller 106, the host device 108, or a combination thereof may calculate the gain control 632 based on the feedback metric 302, such as the error difference metric 322. The memory system 100 may calculate the gain control 632 in various ways. For example, the memory system 100 may calculate the gain control 632 based on iteratively increasing or decreasing by one increment based on the comparison error difference measure 322 and a predetermined threshold or range. As another example, the memory system 100 may calculate the gain control 632 based on a predetermined list or table including one of various possible values of the gain control 632 according to the corresponding value of the error difference measure 322. For another example, the memory system 100 may calculate the gain control 632 using a predetermined equation using the error difference measure 322 as an input.

As a more specific example, the memory system 100 may determine the number of reads in which the error difference measure 322 exceeds or meets a predetermined threshold. The memory system 100 may combine or aggregate the error difference measure 322 based on one of a mathematical combination, a statistical combination, or a logical combination based on the error difference measure 322 of the die. The combined or aggregated metrics can be used as inputs to a predetermined threshold, list or table, or equation to calculate gain control 632.

The gain control 632 can be calculated based on the target quantity change curve 402 (FIG. 4). The gain control 632 may be further calculated in an iterative manner. The gain control 632 may be calculated according to a relationship between the gain control 632 and the level distribution curve 410 (FIG. 4) as represented by a predetermined equation, table, list, threshold or range, mechanism, or a combination thereof. The gain control 632 may be calculated to affect the distribution valley 406 (FIG. 4) based on its relationship to one of the sampled data as represented by a predetermined equation, table, list, threshold, or range, mechanism, or a combination thereof. The gain control 632 may be calculated to have samples between one of the minimum and a maximum of the error difference metric 322. In addition, the gain control 632 may be calculated based on a restoration limit 634. The recovery limit 634 is a constraint on the recoverability of the data of the error recovery mechanism 172 (Figure 1). The recovery limit 634 may be based on ECC. The recovery limit 634 may describe one of the number of errors that the memory system 100 can handle or correct.

The memory system 100 may calculate an offset metric 320 based on the gain control 632. The memory system 100 may adjust or update the offset metric 320 based on combining the offset metric 320 and the gain control 632 or adjusting the offset metric 320 according to the gain control 632. For example, the memory system 100 may use the gain control 632 as an offset or a factor. For another example, the memory system 100 may increase or decrease the offset measure 320 according to the number of increments or direction specified by the gain control 632. For another example, the memory system 100 may use the gain control amount 632 as an input to a predetermined table or equation to calculate the offset measure 320.

The calculation, adjustment, or update of the offset metric 320, the gain control 632, or a combination thereof may be based on the centered state 626. The calculation, adjustment, or update of the offset measure 320, gain control 632, or a combination thereof may occur when calibrating all trimmings in a die, when a minimum or threshold number of samples have been taken, or a combination thereof. The sampling result, updated level 624, centered state 626, gain control 632, level calibration feedback measure 302, its processing or statistical results, or a combination thereof may be stored in the memory device 102, the host device 108, or the combination thereof in. The stored information can be repeatedly or implemented across the processing level calibration mechanism 176.

For example, the processing level calibration mechanism 176 may utilize one or more circuits. As a more specific example, one iteration may correspond to one sample trimming all read levels of all the die associated with the processing level calibration mechanism 176. The update or adjustment of the read level voltage 158 may occur based on an iteration count reaching a predetermined threshold. Each trim can get an update after it has been sampled a predetermined number of times. The iteration may be further repeated according to each die or the entire group of memory arrays 104.

FIG. 6 shows, for example, an outer circuit and an inner circuit. The memory system 100 may select a die or a memory page for the external circuit. The inner loop can sample, evaluate the results and determine the update of the read level voltage 158 for a selected trim or page type. The outer loop can grade the results from the inner loop from multiple different blocks over a duration. Once enough internal loop measurements have been made, the external loop can adjust or calibrate the read level voltage 158. The inner loop, outer loop, or both work together to repeatedly adjust the read level voltage 158 until the centered state 626 of each of the page types 146 on a selected page or die.

For another example, the processing level calibration mechanism 176 may be implemented multiple times within a duration. Each implementation of the process level calibration mechanism 176 may be iterative with or without any separate internal iterative process. The memory system 100 may store information for or resulting from implementations of the processing level calibration mechanism 176.

The memory system 100 may store various kinds of information repeatedly or store various kinds of information for access by other organizations such as the target calibration mechanism 178 (FIG. 1), the step calibration mechanism 180 (FIG. 1), or a combination thereof. For example, the memory system 100 may store an error count 168 for each page type 146 of each word line group 144 during the sampling phase, after the centered state 626, or a combination thereof, or process results or representations. For another example, the memory system 100 may store a gain control 632, an error difference measure 322, or a combination thereof. The memory system 100 may implement the target calibration mechanism 178, the step calibration mechanism 180, or a combination thereof after the processing level calibration mechanism 176 or a part or iteration thereof is implemented, or based on the implementation of the processing level calibration mechanism 176 or a part or iteration thereof. .

The memory system 100 may use the processing level calibration mechanism 176 to initialize the processing level 154, dynamically calibrate the processing level 154, or a combination thereof. The memory system 100 may implement a processing level calibration mechanism 176 as part of the manufacture or configuration of the memory device 102 prior to the deployment or intended use of the memory device 102. The memory system 100 may further dynamically implement the processing level calibration mechanism 176 and dynamically update the processing level 154 during the deployment or intended use of the memory device 102 and after the manufacturing or configuration of the memory device 102.

For example, the memory system 100 may initialize and adjust a read level voltage 158 that exceeds a manufacturing level 640. The manufacturing level 640 may be an example of a processing level 154 that is initially provided or configured for manufacturing the memory device 102, such as a read level voltage 158. The manufacturing level 640 may be a factory preset value or a configuration preset value considering an ideal or an estimated behavior or characteristic of the memory cell 122 instead of an actual behavior or characteristic.

The memory system 100 may use the method 600 to adjust the manufacturing level 640 to the optimal reading level voltage 158 for each instance of the memory device 102. The memory system 100 can select, obtain trimming, calculate complementary levels associated with trimming, sample, evaluate results, and determine updates from the manufacturing level 640, as described above. The level corresponding to the centered state 626 may be one of the initialized instances of the read level voltage 158 for deployment, sale, shipment, or intended use.

For initialization, the memory system 100 may identify a manufacturing level 640 that represents a processing level 154 that was originally determined during the manufacturing of the memory array 104. The memory system 100 may use the identification of the manufacturing level 640 as the sampling trigger 620 to perform the steps described above.

The memory system 100 may initially calibrate the processing level 154 before use or deployment of the memory array 104 and before dynamically generating the updated level 624. The memory system 100 may initially determine the central result 304 using the manufacturing level 640 of the selected memory cell 122. The memory system 100 may initially determine an offset result using an offset level different from the manufacturing level 640. The memory system 100 may generate a processing level 154 based on adjusting the manufacturing level 640 according to the central result 304 and the offset result, and replace the manufacturing level 640 for the deployment or intended use of the memory array 104. The memory system 100 may be initialized based on performing the operations described above at an acceleration rate that is faster than one rate that is designed for post-deployment implementation.

After initialization and deployment, and during desired use, the memory system 100 may further implement a processing level calibration mechanism 176 to dynamically calibrate and optimize the processing level 154. The memory system 100 may continue to track various data and statistical data associated with the use of the memory device 102, the processing level calibration mechanism 176, or a combination thereof. The memory system 100 may use the tracking data to continuously calibrate the processing level 154.

The dynamic calibration of the read level voltage 158 provides the benefit of improving the overall BER of the memory device 102. Each sample initiated by the processing level calibration mechanism 176 can return data for a specific die and a specific page type threshold. In many of these operations, the information returned can be aggregated and fed back into a closed loop system.

The dynamic calibration of the read level voltage 158 provides the benefit of reducing the periodic read level calibration or trimming of a large number of die. This is expected to eliminate or reduce the sudden or sharp drop in the performance of the memory device 102 during calibration.

Dynamic calibration of the read level voltage 158 and maintaining the read level voltage 158 at a median value provides a reduction in triggering of the error recovery mechanism 172 in cases where normal ECC of the in-line hardware can be used and data cannot be corrected in other ways The benefits of the event. The reduction in trigger events can further improve the performance of the memory device 102 as a whole.

The gain control 632 provides further accuracy when centering the read level voltage 158. Gain control 632 can be used to accurately set the offset metric 320, which can result in improving the interval between the offset level and the read level voltage 158. The improved interval improves the tracking of the error count while remaining within the recovery limit 634.

For illustrative purposes, the flowchart shown in FIG. 6 has been described in conjunction with one of the sequences and procedures illustrated above. However, it should be understood that the method 600 may be different. For example, the calculation of gain control as represented by block 614 may be an iterative process. Also for example, the gain control may be calculated before the evaluation result as represented in block 610 or as part of the evaluation result as represented in block 610. As another example, the method 600 may further include one of a voting system for triggering a processing level update in block 612, for calculating a gain control in block 614, or a combination thereof.

FIG. 7 is a flowchart illustrating a further exemplary method 700 of operation of the memory system 100 (FIG. 1) according to an embodiment of the present invention. The method 700 may include an implementation of a target calibration mechanism 178 (FIG. 1). The target calibration mechanism 178 may continuously modify a program verification (PV) target position.

It may be, for example, a processing circuit (such as the controller 106, a memory array 104 (e.g., a die or cell)) for one of the memory device 102 or the host device 108, a processor for the host device 108, or a combination thereof ( (Both in FIG. 1)) perform or implement the target calibration mechanism 178. The target calibration mechanism 178 may include a configuration of the controller 106, the memory array 104, the host device 108, or a combination thereof. The target calibration mechanism 178 may further include stored in the controller 106, the memory array 104, the host device 108, or a combination thereof, or accessed using one or more of the controller 106, the memory array 104, the host device 108, or a combination thereof. Methods, procedures, steps or instructions, information, or combinations thereof.

The target calibration mechanism 178 may be utilized or implemented to adjust a target quantity curve 402 such as one or more of the distribution targets 404, one or more of the distribution valleys 406, or a combination thereof (all in FIG. 4). Target calibration mechanism 178 or a portion thereof may be triggered or initiated based on a target processing cycle 712. The target processing cycle 712 is set for the duration or a specific time of the target calibration mechanism 178 or one of its iterations or parts. The target processing cycle 712 may be based on a state, a signal, a configuration, or a processing value or result of the memory device 102. For example, the target processing cycle 712 may include or be based on a drive fill interval.

Target calibration mechanism 178 or a portion thereof may be triggered or initiated based on processing level calibration mechanism 176 (FIG. 1) or method 600 (FIG. 6) as represented in block 702. The target calibration mechanism 178 may be implemented based on the implementation or completion of the process level calibration mechanism 176 or one or more iterations or after the implementation or completion of the process level calibration mechanism 176 or one or more iterations. For example, the target calibration mechanism 178 or a portion thereof may begin based on the centered state 626 (FIG. 6) resulting from the processing level calibration mechanism 176. The target calibration mechanism 178 may use the results or by-products (such as level calibration feedback measure 302 (Figure 3) or error measure 166) of the processing level calibration mechanism 176 to continuously calibrate the processing level 154 (Figure 1) or its processing results. (Figure 1)) as a feedback metric.

In addition, the implementation or completion of the target calibration mechanism 178 or portions thereof may re-trigger or initiate processing of the level calibration mechanism 176. The target calibration mechanism 178 can dynamically update the target quantity curve 402 that can be used to recalibrate the processing level 154 (FIG. 1). For example, the memory system 100 may reset, clear, or remove the centered state 626 based on the implementation of the target calibration mechanism 178. For another example, the process level calibration mechanism 176 may be implemented regardless of whether or not any initialization is performed from the target calibration mechanism 178 or without any initialization from the target calibration mechanism 178.

At block 702, the target calibration mechanism 178 can obtain a target quantity curve 402 for one of the groups of the memory cells 122 (FIG. 1). For example, the memory cell 122 may be selected in various ways for the target calibration mechanism 178. In one embodiment, the memory system 100 may select a memory cell 122 corresponding to a die. Also for example, the target calibration mechanism 178 may be implemented in or by the die. For another example, regardless of the page map 142 (FIG. 1), the target calibration mechanism 178 may be independently implemented within each of the word line groups 144 (FIG. 1).

For a selected grouping of memory cells 122, the memory system 100 may determine, for example, by accessing or reading, the target stored in the embedded memory of the controller 106, the memory array 104, the host device 108, or a combination thereof One of the current corresponding instances of the quantitative change curve 402. The memory system 100 can further determine based on the background record 174 (FIG. 1) containing the necessary information.

The memory system 100 may determine a target quantity variation curve 402 including a distribution target 404 representing a behavior or a state associated with the processing level 154 of the memory cell 122, such as an intermediate target 409 (Figure 4) and an edge target 408 (Figure 4), the distribution trough 406 or a combination thereof. The distribution targets 404 may each correspond to a specific instance of the page type 146 (FIG. 1) of the memory cell 122, a specific content or bit value, or a combination thereof.

The distribution valley value 406 may represent a distance between adjacent instances of the distribution target 404. The distribution trough 406 may further represent the distance between processing levels 154 between neighboring instances of page type 146, neighboring instances of specific content or bit values, or combinations thereof.

At block 704, the target calibration mechanism 178 may process the distribution target 404 based on a feedback metric. For example, the memory system 100 may classify the distribution target 404 or its equivalent based on the feedback metric. In one embodiment, the memory system 100 may determine a feedback parameter corresponding to the memory cell 122, such as by accessing or reading. The memory system 100 may determine a feedback parameter resulting from the use of the processing level 154 or the implementation of the processing level calibration mechanism 176 or based on the calculation of the use of the processing level 154 or the implementation of the processing level calibration mechanism 176. For example, the memory system 100 may determine the feedback parameters and implement the target calibration mechanism 178 based on the centered state 626 reflecting the stability or optimization of the processing level 154, as discussed above.

In another embodiment, the memory system 100 may determine feedback parameters associated with the processing level 154 of dynamically calibrating the memory cell 122, such as an error metric 166, a level calibration feedback metric 302, or a combination thereof. For example, the memory system 100 can read or access the error count 168 (Figure 1), the central result 304 (Figure 3), the error difference measure 322 (Figure 3), the level distribution curve 410 (Figure 4), or a combination thereof .

For another example, the memory system 100 may determine feedback parameters including an error difference measure 322 calculated based on an error measure 166 corresponding to the processing level 154 of the memory cell 122 (such as based on the implementation of the processing level calibration mechanism 176 or a modification thereof). The memory system 100 can read or access error difference measures calculated based on one of the error measures 166 associated with the center of the offset sample and an average value, the average value across pages or cells, or a combination thereof 322. The memory system 100 may determine an error difference measure 322 or an average value thereof corresponding to each of the distribution targets 404.

The error difference metric 322 may correspond to the distribution valley 406 or the characteristics of the distribution valley 406, RWB, or a combination thereof. The memory system 100 may determine the error difference measure 322 or its derivative as one of a trough depth 714. The trough depth 714 represents a magnitude or a degree associated with each of the distribution troughs 406. The trough depth 714 may quantitatively represent a magnitude or a degree of the distance between the distribution targets 404. The trough depth 714 may further represent or correspond to the RWB of each of the processing level 154 or the distribution target 404.

The memory system 100 may further process the target quantity change curve 402. In one embodiment, the memory system 100 processes the target quantity variation curve 402 based on the level calibration feedback measure 302 (such as based on the error difference measure 322, the error measure 166 or the central result 304, or a combination thereof).

The memory system 100 may determine a target performance curve 716 representing a related characteristic or description of one of the distribution targets 404, the distribution valley 406, or a combination thereof. For example, the memory system 100 may determine that the target performance curve 716 is one of the distribution target 404, the distribution valley 406, or a combination thereof according to the level calibration feedback measure 302 or a sorted list.

At block 706, the target calibration mechanism 178 may identify a particular page for adjusting the distribution target 404. The memory system 100 can identify a high performance page 718 and a low performance page 720. The memory system 100 may identify the high performance page 718 and the low performance page 720 based on the target performance curve 716. The memory system 100 may alternatively identify high performance pages 718 and low based on a comparison of the error difference measure 322, the error measure 166, or a combination thereof corresponding to a distribution target 404, a distribution trough 406, or a combination thereof such as a target performance curve 716 Performance page 720. The memory system 100 can identify a high-performance page 718 and a low-performance page 720 each as a specific instance of a page type 146 corresponding to the highest or lowest instance of the level calibration feedback metric 302, a specific bit or content value, and a distribution target 404 or a specific instance of intermediate target 409, or a combination thereof.

In a particular example, the high performance page 718 may include one or more of the distribution targets 404 corresponding to the lowest value of the error difference measure 322, the lowest value of the error count 168, or the central result 304, or a combination thereof. The low performance page 720 may be a distribution target 404 corresponding to the highest value of the error difference measure 322, the highest value of the error count 168, or the central result 304, or a combination thereof.

High performance page 718 may represent a specific logical page of "lower demand", and low performance page 720 may represent a specific logical page of "higher demand". The high-performance page 718 and the low-performance page 720 may be based on the associated RWB of the distribution valley 406 of the same page type within the word line group 144. The highest demand trough for a page type may be the trough that dominates the error count 168 or causes a greater BER loss than any other trough. The memory system 100 may use the error difference metric 322 to determine a higher demand trough and a lower demand trough, a demand sequence, as represented by the target performance curve 716.

The high performance page 718 and the low performance page 720 identified using the level calibration feedback metric 302 provide the benefit of improving the accuracy of balancing the BER across different page types. The magnitude of the error difference measure 322 reliably characterizes the width of the distribution trough 406 or the trough depth 714, and therefore reliably characterizes the RWB. For example, a higher value of the error difference measure 322 corresponds to a narrower valley value and a smaller RWB.

Using an error difference metric calculated based on three samples resulting from the dynamic calibration read level and controlled using gain control 632 (Figure 6) provides the benefit of improving the accuracy of balancing BER across different page types. The gain control 632 can effectively calibrate the error difference metric 322, making it easier to distinguish between a shallow valley value and a deep valley value. The gain control 632 can maintain the distance between the center samples and the low and high samples for improved resolution. The gain control 632 can prevent the difference in the sample value from being too low, making the difference difficult to distinguish, and prevent the overall instance of the error recovery mechanism 172 (Figure 1) from being triggered by making the sample difference too high, and make the feedback value meaningless. Provide a valid value for the error difference measure 322.

At block 708, the target calibration mechanism 178 may adjust the PV target represented by the target quantity variation curve 402. The memory system 100 may adjust or calibrate the target quantity variation curve 402 by adjusting one or more of the distribution targets 404, one or more of the distribution valley values 406, or a combination thereof.

The memory system 100 may generate an adjusted target 420 for replacing one or more of the distribution targets 404 and effectively shifting one or more of the distribution targets 404. The adjusted target 420 is the desired amount or occurrence of the group associated with the page type, bit, or content value, or a combination thereof, where the voltage level is different from the corresponding distribution target 404. The adjusted target 420 may include an instance of a distribution target 404 having a changed or adjusted distribution amount or shape, a corresponding voltage level, or a combination thereof.

The memory system 100 may generate the adjusted target 420 (FIG. 4C) based on the implementation of the processing level calibration mechanism 176 to dynamically generate the updated level 624 (FIG. 6) and dynamically calibrate the processing level 154. The memory system 100 may generate an adjusted target 420 based on or based on the error difference metric 322.

The memory system 100 may generate the adjusted target 420 based on changing or shifting one or more instances of the distribution target 404, the distribution valley 406, or a combination thereof according to the error difference metric 322. For example, the memory system 100 may generate an adjusted target 420 corresponding to or used to replace the target of the high performance page 718, the low performance page 720, or a combination thereof. Also for example, the memory system 100 may generate an adjusted target 420 for controlling or balancing the distribution valley 406, valley depth 714, or a combination thereof corresponding to the high-performance page 718, the low-performance page 720, or a combination thereof.

The memory system 100 may generate an adjusted target 420 for a memory cell 122 selected as discussed above. Regardless of the page map 142, the memory system 100 may generate the adjusted target 420 within the die, within the word line group 144, or a combination thereof.

The memory system 100 may generate the adjusted target 420 in various ways. The memory system 100 may use the edge target 408 as a reference point and adjust the intermediate target 409 without adjusting the edge target 408.

The memory system 100 may also generate an adjusted target 420 based on a dead-band zone 722. The invalid band 722 may represent a threshold range of the error measure 166 corresponding to the processing level 154 of the distribution target 404. The memory system 100 may generate the adjusted target 420 based on comparing the invalid band 722 and the error metric 166.

For example, the memory system 100 may generate an adjusted target 420 corresponding to or used to calibrate the intermediate target 409, the high performance page 718, the low performance page 720, or a combination thereof. As a more specific example, when the corresponding distribution target 404 contains a BER outside the invalid band 722, the memory system 100 may generate an adjusted target 420.

The memory system 100 may also generate an adjusted target 420 based on a page type 146 balance error measure 166 across the memory cells 122. The memory system 100 may generate an adjusted target 420 that balances the page types 146 across the memory cells 122 and achieves similar levels of BER, error count, trough depth 714, or combinations thereof.

The memory system 100 may also generate the adjusted target 420 based on shifting or moving the distribution target 404 according to the target adjustment value 422 (FIG. 4). As a more specific example, the memory system 100 may shift the high performance page 718 and the low performance page 720 by increasing or decreasing the corresponding voltage level and its threshold value to reach the target adjustment value 422.

The memory system 100 may calculate the target adjustment value 422 based on a predetermined increment or granularity. The memory system 100 may further calculate the target adjustment value 422 based on determining a voltage magnitude or amount corresponding to one of a combination of the valley depth 714 between the high performance page 718 and the low performance page 720. The memory system 100 may calculate the target adjustment value 422 as an adjustment amount estimated to balance the valley depth 714 or the RWB between the high performance page 718 and the low performance page 720.

The memory system 100 may further calculate the target adjustment value 422 of the target quantity change curve 402 as a net zero sum. The target adjustment values 422 of the high performance page 718 and the low performance page 720 may be complementary, where the sum of these values is zero. For example, the target adjustment value 422 may represent a distance or magnitude that is reduced or obtained from the high performance page 718 and given or added to one of the low performance pages 720. The valley value corresponding to the high performance page 718 and its associated RWB can be reduced, and the same decrease can be used to increase the valley value corresponding to the low performance page 720 and its associated RWB.

Thus, the memory system 100 may generate an adjusted target 420 corresponding to the target adjustment value 422 for different page types 146 balance error measure 166, trough depth 714, or combinations thereof, across the memory cells 122. For TLC, the memory system 100 may generate an adjusted target 420 corresponding to a target adjustment value 422 of the BER for balancing and equalizing LP 148 (Figure 1), UP 150 (Figure 1), and EP 152 (Figure 1). .

The memory system 100 may generate an adjusted target 420 to further perform BER leveling based on the error count 168 and based on the matching RWB. The memory system 100 may generate an adjusted target 420 based on an error count 168 that matches a central sample (such as the central result 304) across the distributed target 404. The memory system 100 may further generate an adjusted target 420 based on matching the error difference measure 322 across the distributed targets 404.

As an illustrative example, the central sample can be used as a feedback metric to equalize the LP / UP / XP error rate by moving the PV target accordingly. In addition, in addition to the central sample, the valley depth can be matched for each page type. The memory system 100 implements the target calibration mechanism 178 to equalize the read threshold level of the RWB and balance the page type of the BER.

The memory system 100 can maintain a constant RWB, but manages adjustments to improve BER and page type BER matching. The memory system 100 may use the PV target of the edge target 408 as a fixed target, such as the targets labeled as L1 and L7 PV targets in FIG. 4A. Adjustments to PV targets of the intermediate target 409, such as the targets labeled L2 to L6 in FIG. 4A, can be managed such that the page type BER is continuously matched.

Continuing the illustrative example, the memory system 100 may set a reference page type 724 and iteratively match other page types. Using TLC as an example, the reference page type 724 may be one of LP 148, UP 150, or EP 152.

For an example of the target processing cycle 712, the memory system 100 can match the reference page type 724 and a first page type 726. The first page type 726 is different from the reference page type 724. Accordingly, the memory system 100 may generate an adjusted target 420 corresponding to the reference page type 724 and the first page type 726.

For another example of the target processing cycle 712, the memory system 100 can match the reference page type 724 and a second page type 728. A second page type 728 is different from both the reference page type 724 and the first page type 726. Accordingly, the memory system 100 may generate an adjusted target 420 corresponding to the reference page type 724 and the second page type 728.

As an illustrative example, the memory system 100 may generate the adjusted target 420 based on the page type 146 of the low performance page 720 determined to correspond to the worst case BER. When the worst case BER is outside the invalid band 722, the memory system 100 may generate an adjusted target 420 for implementing a net-zero PV target change.

When the reference page type 724 corresponds to an error count 168 that is lower than the first page type 726, the reference page type 724 or its associated valley value can be discarded or reduced by the target adjustment value 422. The low performance page 720 of the first page type 726 or its associated valley value may receive or increase the PV margin by the target adjustment value 422. The target adjustment value 422 may be one or more of predetermined increments, or one value dynamically calculated for averaging the PV tolerance between two page types.

In one embodiment, the memory system 100 may generate an adjusted target 420 for replacing the distribution target 404 corresponding to the reference page type 724 of L3 / L4 as illustrated in FIG. 4A. The adjusted target 420 may be based on reducing the PV margin of the distribution target 404 of L3 / L4 by one step or increment, thereby reducing the corresponding valley value v4. The adjusted target 420 may be further used to replace the distribution target 404 corresponding to the first page type 726 of L1 / L2 or L5 / L6 as shown in FIG. 4A. The adjusted target 420 may be based on increasing the PV tolerance of the distribution target 404 of L1 / L2 or L5 / L6 by one step or increment, thereby increasing the corresponding valley value v2 or v6.

When L3 / L4 is given to L1 / L2, the distribution targets 404 of L2 and L3 can increase in value and shift rightward relative to the illustrations in FIGS. 4A to 4C. When L3 / L4 is given to L5 / L6, the distribution targets 404 of L4 and L5 can decrease in value and shift left relative to the illustrations in FIGS. 4A to 4C.

When the reference page type 724 corresponds to an error count 168 higher than the first page type 726, the reference page type 724 or its associated valley value can be increased or increased by the PV margin by the target adjustment value 422. The high-performance page 718 of the first page type 726 or its associated trough value may abandon or reduce the PV margin by the target adjustment value 422.

In one embodiment, the memory system 100 may generate an adjusted target 420 based on increasing the PV tolerance of the distribution target 404 of L3 / L4 by one step or increment, thereby increasing the corresponding valley value v4. The adjusted target 420 may be further based on reducing the PV tolerance of the distribution target 404 of L1 / L2 or L5 / L6 by a step or increment, thereby reducing the corresponding valley value v2 or v6.

When L3 / L4 is taken from L1 / L2, the distribution targets 404 of L2 and L3 can decrease in value and shift to the left relative to the illustrations in FIGS. 4A to 4C. When L3 / L4 is taken from L5 / L6, the distribution targets 404 of L4 and L5 can increase in value and shift rightward relative to the illustrations in FIGS. 4A to 4C.

In one embodiment, the memory system 100 may similarly generate the adjusted target 420 based on the page type 146 of the low performance page 720 determined to correspond to the worst case BER. When the worst case BER is outside the invalid band 722, the memory system 100 may generate an adjusted target 420 for implementing a net-zero PV target change for the intermediate target 409. The memory system 100 may further generate an adjusted target 420 based on the target performance curve 716 based on an average of one of the error difference measures 322.

When the reference page type 724 corresponds to an error count 168 or error difference metric 322 that is lower than the second page type 728, the reference page type 724 or its associated trough value may abandon or reduce the PV tolerance by the target adjustment value 422. The low performance page 720 of the second page type 728 or its associated valley value may receive or increase the PV margin by the target adjustment value 422.

In one embodiment, the memory system 100 may generate an adjusted target 420 for replacing the distribution target 404 corresponding to the reference page type 724 of L3 / L4. The adjusted target 420 may be based on reducing the PV margin of the distribution target 404 of L3 / L4 by one step or increment, thereby reducing the corresponding valley value v4. The adjusted target 420 may be further used to replace the distribution target 404 corresponding to the second page type 728 of L2 / L3, L4 / L5, or L6 / L7. The adjusted target 420 may be based on increasing the PV tolerance of the distribution target 404 of L2 / L3, L4 / L5, or L6 / L7 by a step or increment, thereby increasing the corresponding valley value v3, v5, or v7.

When L3 / L4 is administered to L2 / L3, the distribution target 404 of L3 may increase in value and shift rightward relative to the illustrations in FIGS. 4A to 4C. When L3 / L4 is given to L4 / L5, the distribution target 404 of L4 can decrease in value and shift to the left. When L3 / L4 is administered to L6 / L7, the distribution targets 404 of L4, L5, and L6 can decrease in value and shift to the left.

When the reference page type 724 corresponds to an error count 168 or error difference metric 322 that is higher than the second page type 728, the reference page type 724 or its associated valley value may increase or increase the PV margin by the target adjustment value 422. The high-performance page 718 of the second page type 728 or its associated trough value can be waived or reduced by a target adjustment value 422 such as by one or more increments or calculated for use on two page types. The PV tolerance between the two is averaged.

In one embodiment, the memory system 100 may generate the adjusted target 420 based on increasing the PV margin of the distribution target 404 of L3 / L4 by one step or increment to increase the corresponding valley value v4. The adjusted target 420 may be further based on reducing the PV tolerance of the distribution target 404 of L2 / L3, L4 / L5, or L6 / L7 by a step or increment, thereby increasing the corresponding valley value v3, v5, or v7.

When L3 / L4 is taken from L2 / L3, the distribution target 404 of L3 can decrease in value and shift to the left relative to the illustrations in FIGS. 4A to 4C. When L3 / L4 is taken from L4 / L5, the distribution target 404 of L4 can increase in value and shift to the right. When L3 / L4 is taken from L6 / L7, the distribution targets 404 of L4, L5, and L6 can increase in value and shift to the right.

The memory system 100 may use the target calibration mechanism 178 to initialize the target quantity change curve 402, and dynamically calibrate the target quantity change curve 402 or a combination thereof. The memory system 100 may implement the target calibration mechanism 178 as part of the manufacture or configuration of the memory device 102 prior to the deployment or intended use of the memory device 102. The memory system 100 may further dynamically implement the target calibration mechanism 178 and dynamically generate the adjusted target 420 during the deployment or desired use of the memory device 102 and after the manufacture or configuration of the memory device 102 and dynamically update Target quantity change curve 402.

For example, the memory system 100 may start with each PV target in a preset state as defined by a NAND factory setting or a manufacturing target 730. The manufacturing target 730 may be an example of a target quantity curve 402 originally provided or configured for manufacturing the memory device 102. The manufacturing target 730 may be a factory preset value or a configuration preset value considering an ideal or an estimated behavior or characteristic of the memory cell 122 instead of an actual behavior or characteristic. The factory target may be different for each instance of the word line group 144.

The memory system 100 may use the method 700 to adjust the manufacturing target 730 to a target quantity variation curve 402 that is optimal for each instance of the memory device 102. The memory system 100 may obtain the target from the manufacturing target 730, process the target, identify related pages or valley values, and adjust the target, as described above. The target at the end of the initial implementation of the target calibration mechanism 178 may be one of the initialization instances of the target quantity variation curve 402 for deployment, sales, shipment, or desired use. Thereafter, the memory system 100 may further continue to dynamically implement the target calibration mechanism 178.

For initialization, the memory system 100 may identify a manufacturing target 730 that represents a target quantity variation curve 402 that was originally determined during the manufacturing of the memory array 104. The memory system 100 may use the identification of the manufacturing target 730 as a trigger to implement the steps described above.

The memory system 100 may initially calibrate the target quantity curve 402 before using or deploying the memory array 104 and before dynamically generating the adjusted target 420. The memory system 100 can initially adjust the read level voltage 158 based on the central result 304 and the offset result (such as by implementing a processing level calibration mechanism 176). The memory system 100 may initially determine the level calibration feedback metric 302 based on implementing the read level voltage 158 after the initial adjustment. The memory system 100 may generate a target quantity variation curve 402 based on changing the distribution target 404 of the manufacturing target 730 according to the feedback metric as discussed above.

The memory system 100 may be initialized based on performing the operations described above at an acceleration rate that is faster than one rate that is designed for post-deployment implementation. The memory system 100 can implement the processing level calibration mechanism 176, the target calibration mechanism 178, the step calibration mechanism 180 (FIG. 1), or a combination thereof at an accelerated rate within a short period of time in the factory, so that each word line group Group 144 will have improved and aggregated read thresholds before running customer firmware.

The adjusted or calibrated instance of the target quantity change curve 402 (where the adjusted target 420 has replaced the corresponding distribution target 404) can be used to further trigger the processing level calibration mechanism 176. For example, the target calibration mechanism 178 may be used as an external circuit, and the processing level calibration mechanism 176 may be used as an internal circuit. The processing level calibration mechanism 176 may further update the processing level 154 according to or in response to a dynamic update or calibration of the target quantity change curve 402.

Allowing one of the PV target changes using the target calibration mechanism 178 may require stylizing most of the blocks in a die with the same PV target. Thus, an almost complete refresh of block stylization may be required. The memory system 100 can maintain a minimum set of one of two different PV target stylized block groups accordingly. The memory system 100 may further operate appropriately using a single set of processing thresholds for reading the threshold calibration mechanism 176 to minimize BER diversity.

The memory system 100 may store various types of information repeatedly or store various types of information for access by other organizations, such as the processing level calibration mechanism 176, the step calibration mechanism 180 (FIG. 1), or a combination thereof. For example, the memory system 100 may store a target quantity variation curve 402 or a threshold value of each page type 146 of each word line group 144. For another example, the memory system 100 may store a target performance curve 716.

Based on the implementation of the target calibration mechanism 178, the memory system 100 may implement the step calibration mechanism 180. For example, the memory system 100 may use the RWB and BER equalization of the cross-page type to dynamically adjust the stylized step 162 (FIG. 1) of the stylized memory cell 122. Details regarding the step calibration mechanism 180 are discussed below.

Generate an adjusted target 420 for dynamically calibrating the target quantity variation curve 402 based on the error measure 166, error difference measure 322, or a combination thereof to provide increased durability of each NAND die in a system product (more overall stylization / erasing (Except cycle). Dynamic balancing ensures that any page type will not dominate the end-of-life criterion, which proved to be an excessive trigger on rate tail behavior. The BER of each page type can be maintained approximately the same throughout the life of a system product, and the BER standard deviation is further minimized.

An adjusted target 420 for dynamically updating the target quantity variation curve 402 based on one of the feedback metrics associated with the error metric 166 provides the benefit of providing a balanced page type BER. The memory system 100 may utilize the error metric 166 due to the processing level calibration mechanism 176 as a feedback metric, which may be used as a processing metric for dynamically balancing the BER. In addition, the reuse of the processing results from the processing level calibration mechanism 176 enables the target calibration mechanism 178 to be implemented with a very modest amount of additional firmware and additional burden.

For illustrative purposes, the flowchart has been described in conjunction with one of the sequences and procedures illustrated above. It should be understood, however, that the method 700 may be different. For example, blocks 702 to 708 may be an iterative process having a feedback loop from blocks 708 to 702. For another example, the method 700 may include filling a pair of complementary page matching one of the reference page type 724 and the first page type 726 for one drive and one of the pair of matching reference page type 724 and the second page type 728 for a subsequent drive fill.

FIG. 8 is a flowchart illustrating another exemplary method 800 for operating the memory system 100 (FIG. 1) according to an embodiment of the present invention. The method 800 may include implementation of a step calibration mechanism 180 (FIG. 1). The step calibration mechanism 180 may continuously modify the stylized step 162 (FIG. 1) based on a feedback metric associated with the operation of the memory device 102 (FIG. 1). The step calibration mechanism 180 can continuously adjust or calibrate the NAND page programming time 502 throughout the life of the memory device 102 (FIG. 5).

For example, a processing circuit (such as a controller 106, a memory array 104 (such as a die or cell)) for one of the memory device 102 or the host device 108, a processor for the host device 108, a portion thereof, or the like The combination (both in FIG. 1)) performs or implements the step calibration mechanism 180. The step calibration mechanism 180 may include a configuration of the controller 106, the memory array 104, the host device 108, or a combination thereof. The step calibration mechanism 180 may further include stored in the controller 106, the memory array 104, the host device 108, or a combination thereof, or accessed using one of the controller 106, the memory array 104, the host device 108, or a combination thereof, or Multiple methods, procedures, steps or instructions, information, or combinations thereof. A step calibration mechanism 180 may be utilized or implemented to adjust a programmed step 162, such as for an ISPP-based programmed memory cell 122 (FIG. 1). The memory system 100 can determine and use the background record 174 (FIG. 1) of the step calibration mechanism 180. The memory system 100 implements a step calibration mechanism 180 that can calibrate the stylized step 162 as a feedback metric based on a background record 174, such as for background scan data or its derivation.

The memory system 100 may determine a background record 174 during operation of the memory device 102, such as represented by block 802. The memory system 100 can determine the background record 174 in various ways. For example, the memory system 100 may determine the background record 174 during the operation of the memory device 102 based on storing or tracking information, performance, or status associated with data processing. The memory system 100 may store or track error metrics 166 (Figure 1) associated with or resulting from the use of stylized steps 162 during operation of the memory array 104, such as an error count 168 (Figure 1) or an error rate 170 ( Figure 1) or its processing results.

The memory system 100 may track error metrics 166 associated with one or more codewords 820, and the stylized steps 162 are used to write data. An increase in stylized step 162 may result in an increased BER. The background scan can read the codeword 820 while searching for "bad data". Error metrics 166 may be determined and tracked, such as one of the number of bit errors. The memory system 100 may also use a hierarchical tracking error metric 166 for different numbers of errors. As a more specific example, the memory system 100 may track error metrics 166 using a histogram type format.

The memory system 100 may implement a step calibration mechanism 180 by using the memory cells 122 of each die, according to the memory cells 122 of each die, or within the memory cells 122 of each die. For example, the memory system 100 may implement the step calibration mechanism 180 using a control circuit that controls each die or within each die. For another example, the memory system 100 may further implement the step calibration mechanism 180 without being limited to, and not adjusted by or according to the word line group 144 (FIG. 1). Compared with the target calibration mechanism 178 (FIG. 1), the step calibration mechanism 180 can be performed by the die stylized step size adjustment instead of the word line group 144.

The step calibration mechanism 180 or a portion thereof may be triggered or initiated based on the step processing cycle 822. The memory system 100 implements the target calibration mechanism 178 to adjust the stylized step 162 during or for the step processing cycle 822. The step processing period 822 is set to be used to implement the step calibration mechanism 180 or one of its iterations or a duration or a specific time. The step processing cycle 822 may be based on a state, a signal, a configuration, or a processing value or result of the memory device 102. For example, the step processing cycle 822 may include or be based on a drive fill interval. For another example, compared to the target processing cycle 712 (FIG. 7), the step processing cycle 822 may be the same type, simultaneous or interleaved therewith, or a combination thereof.

The target calibration mechanism for continuous PV target verification as indicated in block 806 may be based on a processing level calibration mechanism 176 (Figure 1) or method 600 (Figure 6) for continuous process level calibration as indicated in block 804 178 (FIG. 1) or method 700 (FIG. 7), or a combination thereof to further trigger or initiate the step calibration mechanism 180 or a portion thereof. For example, step calibration mechanism 180 may be implemented based on implementing processing level calibration mechanism 176 to dynamically calibrate processing level 154 (FIG. 1) including read level voltage 158 (FIG. 1). The step calibration mechanism 180 may be implemented based on the centered state 626 (FIG. 6) of the read level voltage 158.

For example, the step calibration mechanism 180 may be implemented based on the implementation of the target calibration mechanism 178 to dynamically calibrate the target quantity variation curve 402 (FIG. 4). When all relevant trimmings are centered as indicated by the centered state 626 of the read level voltage 158 of the die or a combination thereof, the step calibration mechanism 180 may be implemented based on the target calibration mechanism 178 being implemented more than a predetermined threshold number.

Further, the step calibration mechanism 180 may be implemented less frequently than the target calibration mechanism 178. The delay rate or implementation of the step calibration mechanism 180 can ensure that the processing level 154 is stable in other situations, and further ensure that background records have been collected 174 after the dynamic calibration of the read level voltage 158, PV target, or a combination thereof Sufficient data points.

At block 808, the step calibration mechanism 180 may process the background record 174 for use in calibrating the stylized step 162. The memory system 100 may process background records 174, such as structurally manipulating data, logically manipulating data, mathematically manipulating data, or a combination thereof. For example, the memory system 100 may generate a cumulative distribution function (CDF) 824 based on processing the background record 174. The CDF 824 may represent one of the statistical probabilities associated with the error metric 166. The CDF 824 may represent the probability that the error measure 166 is less than or equal to a certain value. The CDF 824 may be generated based on or against a regularized background record 174.

The memory system 100 may generate the CDF 824 in various ways. For example, the memory system 100 may repeatedly update the CDF 824 and maintain the CDF 824 permanently. As background records 174 are continuously determined, the memory system 100 may update the CDF 824. For another example, the memory system 100 may generate a CDF 824 for each iteration or implementation of the step calibration mechanism 180 to calibrate the stylized steps 162 instead of repeatedly updating the CDF 824 and maintaining the CDF 824 non-permanently.

For another example, the memory system 100 may further generate an adjusted function result 828 based on the further processing of the CDF 824. The adjusted function result 828 may represent a processing result from further manipulation or processing of one of the CDF 824 or the background record 174, such as by shifting, logical or mathematical operations, reconstructing or formatting the CDF 824 or the background record 174.

The adjusted function result 828 may include a waterfall organization or format of one of the CDF 824 or the background record 174. Furthermore, the adjusted function result 828 may include one or more predetermined values in combination with the CDF 824 or the background record 174, such as a multiplication factor or an addition offset.

At block 810, the step calibration mechanism 180 may calculate a trigger for updating or calibrating one of the stylized steps 162. The memory system 100 may derive triggers based on processing feedback data, such as for background scan data. The memory system 100 may derive a trigger based on calculating a trigger metric 830.

The trigger measure 830 is a representation of one of the current operating states of the memory cell 122 relative to one of the error recovery mechanism 172 (FIG. 1) and the stylized step 162. The trigger metric 830 may estimate the implementation of the error recovery mechanism 172, such as for its likelihood or its frequency. The trigger metric 830 may further represent an additional burden or distance from implementing the error recovery mechanism 172. The trigger metric 830 may be calculated based on the background record 174 or its processing result, such as the CDF 824 or the adjusted function result 828.

The memory system 100 may calculate the trigger metric 830 in various ways. For example, the trigger metric 830 may include a trigger rate 832, a trigger tolerance 834, or a combination thereof.

The trigger rate 832 is an estimate of the frequency or probability of implementing the error recovery mechanism 172. The trigger rate 832 may further estimate one of the error metrics 166 for various conditions or situations, such as based on changing the stylized step 162. The trigger rate 832 may represent one of the BER predictions. For example, the trigger rate 832 may be associated with an uncorrectable bit error rate (UBER). Also for example, the trigger rate 832 may be based on the error ECC bits associated with the error recovery mechanism 172, a rate or a metric of the codeword 820, or a combination thereof.

The memory system 100 may use an estimation mechanism 836 to calculate the trigger rate 832. The estimation mechanism 836 may include a program, a method, a circuit, a configuration, a function, or a combination thereof for predicting further behavior or pattern based on a given data set. For example, the estimation mechanism 836 may include a program, a method, a circuit, a configuration, a function, or a program for implementing a line-fitting algorithm such as a linear or logarithmic pattern, a statistical possibility calculation, or a combination thereof. And other combinations.

The memory system 100 may calculate the trigger rate 832 based on using the background record 174 or its derivation (such as CDF 824 or adjusted function result 828) as input to the estimation mechanism 836. The memory system 100 may predict or estimate a frequency or a probability of performing the error recovery mechanism 172, a prediction of the error count 168, or a combination thereof based on a pattern or a trend prediction of the background record 174.

The trigger tolerance 834 is a representation of a relationship between the implementation of the error recovery mechanism 172 and the error metric 166 corresponding to the stylized step 162. For example, the trigger tolerance 834 may represent a distance between the system trigger condition 838 and the error count 168 for implementing one of the error recovery mechanisms 172. The system trigger condition 838 may include a predetermined condition for initiating the error recovery mechanism 172, such as one of the number of error bits or one of the bad or incorrect instances of the codeword 820. The improved performance associated with the stylized time 502 may be constrained by a trigger margin 834, which may be a measure of the system product ECC recovery rate.

The memory system 100 may calculate a trigger margin 834 based on the system trigger condition 838 and the error metric 166. For example, the memory system 100 may calculate a trigger margin 834 based on a relationship or a distance (such as a ratio or a difference between values) between the system trigger condition 838 and the error count 168. The error count 168 may represent a number of bit errors below a predetermined threshold used to initiate a change in one of the stylized steps 162. For another example, the memory system 100 may calculate the trigger margin 834 based on a logarithmic representation of the system trigger condition 838 and the error count 168.

The memory system 100 may calculate a trigger metric 830 directly from the error count 168. For the trigger metric 830, the memory system 100 may use available data instead of performing a one-line fit and predict such as exceeding the amount of data collected compared to the trigger rate 832.

At block 812, the step calibration mechanism 180 may determine one or more threshold values for evaluating the trigger metric 830. The memory system 100 may determine a threshold based on the determination trigger control curve 840.

The trigger control curve 840 is used to evaluate the trigger metric 830 and update or change the stylized step 162 to calibrate a predetermined threshold or range. The trigger control curve 840 may include a limit, a threshold, or a range of a trigger rate 832, a trigger tolerance 834, or a combination thereof. For example, the trigger control curve 840 may include a probability, an error rate or an error magnitude, or a combination thereof, used to initiate the update of the stylized step 162.

The memory system 100 may change the value of the stylized step 162 based on comparing the trigger measurement 830 and the trigger control curve 840. A developer or a designer, a manufacturer, a user, the memory system 100 or a combination thereof may predetermined trigger the control curve 840 outside the step processing cycle 822.

The memory system 100 can determine the trigger control curve 840 by accessing the trigger control curve 840 stored in the host device 108 or the memory device 102. The memory system 100 may further determine the trigger control curve 840 based on adjusting the value of the trigger control curve 840 according to a lag parameter 842. The hysteresis parameter 842 is a parameter used to control the repeated pattern when the stylized step 162 is updated. The hysteresis parameter 842 can be configured to minimize jitter that continuously changes the stylized step 162 in the opposite direction. The hysteresis parameter 842 can be used to maintain the stylized step 162 when the condition is a dividing line or near a limit. The hysteresis parameter 842 may generate an invalid band in which no updates are made. The hysteresis parameter 842 may be a value associated with the trigger control curve 840, such as based on using a mathematical derivative of a factor, an offset, or a combination thereof associated with the trigger control curve 840. Similar to the trigger control curve 840, the hysteresis parameter 842 may be predetermined outside the step processing period 822.

The memory system 100 may adjust the trigger control curve 840 based on the hysteresis parameter 842. For example, the memory system 100 may combine a predetermined value of the trigger control curve 840 with a hysteresis parameter 842 to adjust or further determine the trigger control curve 840. The predetermined value of the trigger control curve 840 may be a threshold value. When the hysteresis parameter 842 is set or exists, the trigger control curve 840 may be a range centered on the initial threshold, where the range size is based on the hysteresis parameter 842. This range may be calculated based on increasing and decreasing the initial threshold value according to the lag parameter 842 (such as by multiplying / dividing or adding / subtracting the lag parameter 842 or its processing derivative with the initial threshold).

At block 814, the step calibration mechanism 180 may calibrate the stylized steps 162. The memory system 100 may calibrate the stylized step 162 based on generating a new value or instance of the adjusted step 844 as a stylized step 162 to replace its existing value. The adjusted step 844 may be used to provide a calibrated value of one of the stylized steps 162. The memory system 100 may calibrate the stylized steps 162 based on the trigger control curve 840 and trigger metrics 830, such as for a trigger rate 832 or a trigger tolerance 834. The memory system 100 may generate an adjusted step 844 for calibrating the stylized step 162 based on comparing the trigger control curve 840 and the trigger metric 830. For example, the memory system 100 may generate an adjusted step 844 for increasing the stylized step 162 when the trigger rate 832 is less than the trigger control curve 840. The memory system 100 may generate an adjusted step 844 for reducing the stylized step 162 when the trigger rate 832 is greater than the trigger control curve 840. When the trigger rate 832 is equal to the trigger control curve 840 or within a range of the trigger control curve 840 based on the hysteresis parameter 842, the memory system 100 may maintain the stylized step 162.

As another example, the memory system 100 may generate an adjusted step 844 for increasing the stylized step 162 when the trigger tolerance 834 is greater than the trigger control curve 840. The memory system 100 may generate an adjusted step 844 for reducing the stylized step 162 when the trigger tolerance 834 is less than the trigger control curve 840. When the trigger rate 832 is equal to the trigger control curve 840 or within a range of the trigger control curve 840 based on the hysteresis parameter 842, the memory system 100 may maintain the stylized step 162.

The memory system 100 may generate the adjusted step 844 as a positive value or a negative value for adjusting one or more predetermined increments of the stylized step 162. The memory system 100 may further generate an adjusted step 844 based on a combination of the trigger control curve 840 and the trigger metric 830 (such as based on a difference, a ratio, or an average). The memory system 100 may further generate an adjusted step 844 for increasing or decreasing the stylized time 502 associated with the stylized step 162. The memory system 100 may reduce the programming time 502 by increasing the programming step 162 and increase the programming time 502 by reducing the programming step 162. In addition, the memory system 100 may further generate an adjusted step 844 for increasing or decreasing the error metric 166 associated with the stylized step 162. The memory system 100 may reduce the stylized step 162 to reduce the error measure 166, and increase the stylized step 162 at the cost of increasing the error measure 166.

The memory system 100 may generate an adjusted step 844 for balancing the programmed time 502 and error metrics 166 associated with the programming of data into the memory array 104. The memory system 100 may generate an adjusted step 844 to improve the stylized time 502 while maintaining an acceptable error level as represented by the trigger control curve 840. The memory system 100 may generate a time 502 for improving the stylized time 502 while maintaining trigger metrics 830 (such as a fixed error rate or a fixed error tolerance represented by the trigger control curve 840) during operation or use of the memory array 104. Adjusted step 844.

The memory system 100 may use the step calibration mechanism 180 to initialize the stylized steps 162, dynamically calibrate the stylized steps 162, or a combination thereof. The memory system 100 may implement the step calibration mechanism 180 as part of the manufacture or configuration of the memory device 102 before the memory device 102 is deployed or intended for use. The memory system 100 may further dynamically implement the step calibration mechanism 180 and dynamically generate an adjusted step 844 and dynamically during the deployment or intended use of the memory device 102 and after the manufacture or configuration of the memory device 102. Update stylized step 162.

For example, the memory system 100 may begin when each stylized step is in a preset state as defined by a NAND factory setting or a manufacturing step 846. The manufacturing step 846 may be an example of a stylized step 162 originally provided or configured for manufacturing the memory device 102. The manufacturing step 846 may be a factory preset value or a configuration preset value that considers an ideal or an estimated behavior or characteristic of the memory cell 122 instead of an actual behavior or characteristic.

The memory system 100 may use the method 800 to adjust the manufacturing step 846 to the stylized step 162 to balance the errors and the programming time of each instance of the memory device 102. The memory system 100 may perform the operations described above since the manufacturing step 846. The stylized step value at the end of the initial implementation of the step calibration mechanism 180 may be an initialization instance of one of the stylized steps 162 for deployment, sale, shipment, or a desired use. For initialization, the memory system 100 may identify a manufacturing step 846 that represents a stylized step 162 that was originally determined during the manufacturing of the memory array 104. The memory system 100 may use the identification of the manufacturing step 846 as a trigger to implement the steps described above.

The memory system 100 may initially calibrate the stylized steps 162 before use or deployment of the memory array 104 and before dynamically generating the adjusted steps 844. The memory system 100 can initially adjust the read level voltage 158 based on the central result 304 (FIG. 3) and the offset result (such as by implementing a processing level calibration mechanism 176). The memory system 100 may initially further adjust the PV target, such as by implementing a target calibration mechanism 178. Data can be loaded or written into the memory circuit during the process using manufacturing step 846.

The memory system 100 may initially determine a background record 174 associated with the manufacturing step 846 and calculate a trigger metric 830 based on the background record 174. The memory system 100 may generate a stylized step 162 based on the trigger metric 830 for updating and replacing the manufacturing step 846 as described above.

The memory system 100 may be initialized based on performing the operations described above at an acceleration rate that is faster than one rate that is designed for post-deployment implementation. The memory system 100 may implement the processing level calibration mechanism 176, the target calibration mechanism 178, the step calibration mechanism 180 (FIG. 1), or a combination thereof at an accelerated rate within a short period of time in the factory, so that the memory cell 122 There will be improved and aggregated stylized steps before running customer firmware.

The memory system 100 can then further dynamically implement the step calibration mechanism 180 thereafter. The memory system 100 may further use the manufacturing step 846 as one of the minimum thresholds of the stylized step 162. After the manufacture of the memory device 102, the memory system 100 will initially likely increase the stylized step 162. Throughout the lifetime or use of the memory device 102, the memory system 100 will likely reduce the stylized steps 162 to adjust the physical wear or degradation of the memory array 104. The memory system 100 may use the manufacturing step 846 as a lower limit or minimum instance of the stylized step 162 for dynamic calibration. The memory system 100 may dynamically generate an adjusted step 844 for maintaining the stylized step 162 greater than or equal to the manufacturing step 846.

Adjusted or calibrated instances of stylized step 162 (where adjusted step 844 replaces previous instances or values of stylized step 162) can be used to further trigger processing of level calibration mechanism 176, target calibration mechanism 178, or the like combination. For example, the memory system 100 may readjust the read level voltage 158 according to the newly programmed step 162. For another example, the memory system 100 may readjust the target quantity variation curve 402 according to the new stylized step 162. The memory system 100 may further utilize the balanced error rate and RWB across pages to calibrate the stylized steps 162.

The memory system 100 may store various types of information repeatedly or store various types of information for access by other organizations, such as the processing level calibration mechanism 176, the target calibration mechanism 178, or a combination thereof. For example, the memory system 100 may store a cumulative distribution function, a trigger metric 830, an adjusted step 844, or a combination thereof. The use of the adjusted function result 828 based on the trigger measurement 830 processed by the background record 174 provides the ability to dynamically calibrate the stylized steps 162. Dynamically and continuously calibrating the stylized steps 162 throughout the lifetime of the memory cell 122 is completely different from what is currently known or expected by a person of ordinary skill. The dynamic and continuous calibration of the stylized step 162 can improve system performance by increasing the short programming time 502 by trade-off unnecessary performance or excessive performance of error characteristics.

Generating an adjusted step 844 for dynamically calibrating the stylized step 162 provides the benefit of improving system product performance throughout the lifetime of the memory array 104. The adjustment of the stylized step 162 specifically improves the stylized time 502 for real-time and actual conditions or states of the memory array 104. Using an adjusted step 844 that is dynamically generated using a trigger metric 830 processed using a background-based record 174 using an adjusted function result 828 provides the benefit of increasing accuracy representing the instant and actual condition or state of the memory array 104. An accurate representation of the trigger metric 830 can be used to update the stylized time 502 while maintaining acceptable error levels.

For illustrative purposes, the flowchart has been described in conjunction with one of the sequences and procedures illustrated above. It should be understood, however, that the method 800 may be different. For example, blocks 808 to 814 may be an iterative process having a feedback loop (not shown) from block 814 to block 808. As another example, blocks 812 and 814 can be combined into one step.

FIG. 9 is a schematic diagram of a system including a memory device according to an embodiment of the present invention. Any of the aforementioned memory devices described above with reference to FIGS. 1 to 7 may be incorporated into any of a number of larger and / or more complex systems, a representative example of which is shown in FIG. 9 A system 980 is shown schematically. The system 980 may include a memory device 900, a power supply 982, a driver 984, a processor 986, and / or other subsystems or components 988. The memory device 900 may include features substantially similar to their memory devices described above with reference to FIGS. 1-7 and may therefore include various features for performing a direct read request from a host device. The resulting system 980 may perform any of a variety of functions, such as memory storage, data processing, and / or other suitable functions. Accordingly, the representative system 980 may include, but is not limited to, handheld devices (eg, mobile phones, tablet computers, digital readers, and digital audio players), computers, vehicles, appliances, and other products. The components of the system 980 may be housed in a single unit or distributed across multiple interconnected units (eg, through a communication network). The components of system 980 may also include remote devices and any of a variety of computer-readable media.

From the foregoing, it will be understood that specific embodiments of the invention have been described herein for illustrative purposes, but various modifications can be made without departing from the invention. In addition, specific aspects of the new technology described in the context of a particular embodiment may also be combined or eliminated in other embodiments. In addition, although the advantages associated with specific embodiments of the new technology have been described in the context of their embodiments, other embodiments may also exhibit these advantages and not all embodiments need to exhibit these advantages in order to fall into this Within the scope of invention. Accordingly, the invention and related technologies may encompass other embodiments not explicitly shown or described herein.

100‧‧‧Memory System

102‧‧‧Memory device

104‧‧‧Memory Array

106‧‧‧controller

108‧‧‧ host device

120‧‧‧Memory Unit

122‧‧‧Memory Cell

124‧‧‧Memory Page

126‧‧‧Memory Block

130‧‧‧ processor

132‧‧‧ Embedded Memory

142‧‧‧Page Map

143‧‧‧Word line

144‧‧‧Word line group

146‧‧‧Logical page type

148‧‧‧Next (LP)

150‧‧‧Previous (UP)

152‧‧‧extra pages (EP)

154‧‧‧Processing level

156‧‧‧Threshold voltage

158‧‧‧Read level voltage

160‧‧‧ stylized level voltage

162‧‧‧ stylized steps

164‧‧‧bit quasi-register

166‧‧‧Incorrect measurement

168‧‧‧Error count

170‧‧‧ error rate

172‧‧‧Error Recovery Agency

174‧‧‧Background

176‧‧‧ Processing level calibration mechanism

178‧‧‧Target Calibration Agency

180‧‧‧step calibration mechanism

210‧‧‧time

211‧‧‧charge

220‧‧‧time

222‧‧‧ charge

230‧‧‧time

232‧‧‧ charge

240‧‧‧time

242‧‧‧ charge

250‧‧‧ Expected target state

302‧‧‧level calibration feedback measurement

304‧‧‧ Center Results

306‧‧‧First offset result

308‧‧‧Second offset result

316‧‧‧First offset level

318‧‧‧second offset level

320‧‧‧offset measure

322‧‧‧Error Difference Measurement

402‧‧‧Target quantity change curve

404‧‧‧Distribution target

406‧‧‧Distribution valley

408‧‧‧Edge target

409‧‧‧ intermediate target

410‧‧‧level distribution curve

420‧‧‧ adjusted target

422‧‧‧ target adjustment value

502‧‧‧ stylized time

504‧‧‧Adjusted step

600‧‧‧ Method

602‧‧‧box

604‧‧‧box

606‧‧‧block

608‧‧‧box

610‧‧‧block

612‧‧‧box

614‧‧‧box

620‧‧‧Sampling trigger

622‧‧‧level adjustment measure

624‧‧‧ update level

626‧‧‧ centered

628‧‧‧ Previously changed direction

630‧‧‧Currently changing direction

632‧‧‧Gain Control

634‧‧‧ Recovery limit

640‧‧‧ manufacturing level

700‧‧‧ Method

702‧‧‧box

704‧‧‧box

706‧‧‧block

708‧‧‧block

712‧‧‧ target processing cycle

714‧‧‧valley depth

716‧‧‧ target effectiveness curve

718‧‧‧High Performance Page

720‧‧‧ Low Performance Page

722‧‧‧Invalid zone

724‧‧‧Reference page type

726‧‧‧First Page Type

728‧‧‧Second page type

730‧‧‧Manufacturing target

800‧‧‧ Method

802‧‧‧box

804‧‧‧box

806‧‧‧block

808‧‧‧box

810‧‧‧box

812‧‧‧box

814‧‧‧box

820‧‧‧codeword

822‧‧‧step processing cycle

824‧‧‧ Cumulative Distribution Function (CDF)

828‧‧‧ adjusted function result

830‧‧‧Trigger measurement

832‧‧‧Trigger rate

834‧‧‧Trigger tolerance

836‧‧‧estimation agency

838‧‧‧System trigger condition

840‧‧‧Trigger control curve

842‧‧‧lag parameter

844‧‧‧Adjusted step

846‧‧‧Manufacturing steps

900‧‧‧Memory device

980‧‧‧ system

982‧‧‧Power

984‧‧‧Drive

986‧‧‧ processor

988‧‧‧Other subsystems or components

FIG. 1 is a block diagram of a memory system having a dynamically programmed calibration mechanism configured according to an embodiment of the present invention.

FIG. 2 illustrates the charges stored on the charge storage structure of a memory cell under various states of an incremental programming operation.

3A, 3B, and 3C illustrate an example of a process of the processing level calibration mechanism in FIG. 1.

4A, 4B, and 4C illustrate an example of a process of the target calibration mechanism in FIG. 1.

5A and 5B illustrate an example of a process of the target calibration mechanism in FIG. 1.

FIG. 6 is a flowchart illustrating an exemplary method of operating the memory system in FIG. 1 according to an embodiment of the present invention.

FIG. 7 is a flowchart illustrating a further exemplary method of operating the memory system in FIG. 1 according to an embodiment of the present invention.

FIG. 8 is a flowchart illustrating another exemplary method of operating the memory system in FIG. 1 according to an embodiment of the present invention.

FIG. 9 is a schematic diagram of a system including a memory device according to an embodiment of the present invention.

Claims (24)

A memory device includes: a memory array including a plurality of memory cells; and a controller coupled to the memory array, the controller configured to: determine a target including a distributed target Quantitative change curve, in which each of the distribution targets represents a program verification target corresponding to a logical value of the memory cells, a feedback metric is determined based on a processing level implemented for processing data, and according to the feedback Measure and dynamically adjust the program verification goals. As in the memory device of claim 1, wherein the controller is further configured to determine the feedback metric based on an error count associated with a read level voltage. As in the memory device of claim 1, wherein the controller is further configured to dynamically adjust the program verification target based on adjusting a distance between adjacent program verification targets. For example, the memory device of claim 1, wherein the controller is further configured to dynamically adjust the program verification target so as to balance an error metric across multiple page types of the memory cells. As in the memory device of claim 1, wherein the controller is further configured to dynamically adjust the program verification target based on a net-zero change of the target quantity variation curve and across the program verification target. A memory device includes: a memory array including a plurality of memory cells arranged in a memory page; and a controller coupled to the memory array, the controller configured to: The judgment includes a target quantity change curve of one of the edge target and the intermediate target, wherein each of the targets represents a program verification target corresponding to a logical value of the memory cells, based on an incorrect determination corresponding to a read level voltage A feedback metric, and dynamically adjusting the target quantity curve based on adjusting one or more of the intermediate targets according to the feedback metric. If the memory device of claim 6, wherein the controller is further configured to determine the feedback measure, the feedback measure includes one of the error count calculations based on the read level voltage and a different read level voltage Error difference measure. If the memory device of claim 7, wherein the error difference measure is calculated based on a difference between a first error count and a second error count, wherein the first error count corresponds to the read level voltage and the second error The count corresponds to the different read level voltages offset from the read level voltage. The memory device of claim 6, wherein the controller is further configured to dynamically adjust the target quantity curve based on the feedback metric determined after calibrating the read level voltage of the memory cells. The memory device as claimed in claim 6, wherein the controller is further configured to implement a one-step calibration mechanism based on the adjusted target quantity variation curve, wherein the step calibration mechanism generates a program for dynamically adjusting a stylized step program. One of these memory cells is adjusted in steps. The memory device as claimed in claim 6, wherein the controller is configured to dynamically adjust the target quantity curve independently for each word line group. For example, the memory device of claim 6, wherein the controller is further configured to dynamically adjust the target quantity variation curve so as to balance the error measure and the valley depth across the page types of the memory cells, where the error measures are Each corresponds to a read level voltage of a specific value associated with one of the page types, and wherein the valley depths characterize the distance between adjacent program verification targets. If the memory device of claim 6, wherein the controller is further configured to: determine a reference page type representing one of the page types representing the memory cells; determine a second page type; and The target processing cycle dynamically adjusts one or more of the intermediate targets corresponding to the reference page type, the second page type, or both. For example, the memory device of claim 13, wherein the controller is further configured to: determine a third page type different from one of the reference page type and the second page type; and generate a response for a subsequent processing cycle One or more of these intermediate targets are dynamically changed further at the reference page type, the third page type, or both. If the memory device of claim 6, wherein the controller is further configured to: identify one of the high-performance pages having the lowest occurrence rate of the errors among the page types; identify the high-performance page among the page types And one of the intermediate targets corresponding to the high-performance page, the low-performance page, or a combination thereof is dynamically changed. The memory device of claim 6, wherein the plurality of memory cell lines are non-volatile. If the memory device of claim 1, wherein: the program verification target controls the resulting distribution of processing levels associated with the logical value of the memory cells; and the controller is configured to: verify the target according to the program Determine the feedback measure resulting from the implementation of the processing level; and update the processing levels based on the adjusted program verification target. A method of operating a memory device including a controller and a memory array, the method includes: determining a target quantity variation curve including a distribution target, wherein each of the distribution targets represents a corresponding one in the memory array; A program verification target of a logical value of a memory cell; determining a feedback metric based on a processing level implemented to process data; and using the controller to dynamically change the program verification target based on the feedback metric The target quantity curve is adjusted for balancing an error measure across multiple page types of the memory cells. The method of claim 18, further comprising implementing a step calibration mechanism, wherein the step calibration mechanism generates an adjusted step for dynamically adjusting a stylized step to program one of the memory cells. The method of claim 18, further comprising: calibrating a read level voltage of one of the memory cells; and wherein: calibrating the feedback measure during or after the calibration of the read level voltage. The method of claim 18, wherein the target quantity change curve includes an edge target and an intermediate target, wherein the edge targets correspond to the distribution targets of a highest voltage level and a lowest voltage level, and the intermediate targets Are the distribution targets between the edge targets; the feedback measure corresponds to an error associated with a read level voltage; and dynamically adjusting the target quantity change curve includes updating one or more intermediate targets according to the feedback measure . The method of claim 21, further comprising determining the feedback metric, the feedback metric including calculating an error difference metric based on a difference between a first error count and a second error count, wherein the first error count corresponds to the The read level voltage and the second error count correspond to different read level voltages offset from the read level voltage. The method of claim 21, wherein dynamically adjusting the target quantity change curve includes: determining a reference page type that represents one of the page types of the memory cells; determining a second page type; and processing for a target Periodically, the target quantity curve corresponding to the reference page type, the second page type, or both is dynamically adjusted based on adjusting one or more of the program verification targets. The method of claim 23, wherein dynamically adjusting the target quantity change curve includes: determining a third page type different from the reference page type and the second page type; and for a subsequent processing cycle, corresponding to the reference Further adjustments to the page type, the third page type, or both are one or more of the program verification goals.