KR20090048130A

KR20090048130A - Programming method of non volatile memory devic

Info

Publication number: KR20090048130A
Application number: KR1020070114354A
Authority: KR
Inventors: 김병렬
Original assignee: 주식회사 하이닉스반도체
Priority date: 2007-11-09
Filing date: 2007-11-09
Publication date: 2009-05-13

Abstract

A program method of a nonvolatile memory device according to an embodiment of the present invention may include performing a program operation on the basis of a first program voltage, performing a verify operation for confirming whether the program is completed, Measuring the number of verified cells among the cells included; setting a step voltage to a first step voltage when the number of verified cells is less than or equal to a first threshold; Setting a step voltage to a second step voltage that is greater than one threshold and less than or equal to a second threshold, and wherein the second step is greater than the second threshold when the number of the verified cells is greater than the second threshold. Setting a step voltage to a third step voltage smaller than a voltage, and adding the set step voltage to the first program voltage to generate a program voltage. And resetting, it characterized in that it comprises the step of repeating the program operates according to the program the reset voltage.

Validated Cell, Step Voltage

Description

Programming method of nonvolatile memory device

The present invention relates to a program method of a nonvolatile memory device.

Recently, there is an increasing demand for a nonvolatile memory device that can be electrically programmed and erased and that does not require a refresh function to rewrite data at regular intervals.

In order to store specific data for each cell, such a nonvolatile memory device performs a program operation by applying a high voltage of approximately 20V to the gate of each cell.

As a result of the program operation, each cell is charged with charge, and when the charge is charged to have a threshold voltage of a certain level or more, the program operation is considered to be completed. ISPP (Incremental Step Pulse Programming) method is used for the program operation. That is, the program operation is performed by sequentially increasing the step voltage of a predetermined level with respect to the program start voltage.

However, since the step voltage level is fixed regardless of the program progress state, the overall program time is difficult to shorten.

An object of the present invention is to provide a program method of a nonvolatile memory device in which a step voltage is variably applied in order to shorten the program time of the nonvolatile memory device.

The program method of the nonvolatile memory device of the present invention for achieving the above object comprises the steps of performing a program operation on the basis of a first program voltage, performing a verify operation for confirming whether the program is completed, Measuring the number of verified cells among the cells included in the page on which the program operation is performed; setting the step voltage to the first step voltage when the number of the verified cells is equal to or less than a first threshold value; Setting a step voltage to a second step voltage smaller than the first step voltage when the number of completed cells is greater than the first threshold value and is less than or equal to the second threshold value, and wherein the number of the verified cells is equal to the second threshold value. Setting a step voltage to a third step voltage smaller than the second step voltage if larger than the step voltage; and setting the step voltage to the first program voltage. Comprising the steps of: adding the pressure to reset the program voltage, it characterized in that it comprises the step of repeating the program operates according to the program the reset voltage.

The program method of the nonvolatile memory device of the present invention may further include performing a program operation based on a first program voltage, performing a verify operation to confirm whether the program is completed, and performing the program operation. Measuring the number of verified cells among the cells included in the page, setting a step voltage with a smaller voltage as the number of verified cells increases, and adding the set step voltage to the first program voltage. Resetting the program voltage and repeating the program operation according to the reset program voltage.

According to the above-described configuration of the present invention, it is possible to variably apply a step voltage which is fixedly applied during a program operation according to the progress state of the program. That is, a large step voltage is applied to the first part of a program operation with a small number of verified cells and a small step voltage is applied to a second part of a program operation with a large number of verified cells. Accordingly, the program time can be shortened as compared with the conventional one.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. The present invention is not limited to the embodiments disclosed below, but will be implemented in various different forms, only these embodiments are intended to complete the disclosure of the present invention, and fully scope the scope of the invention to those skilled in the art. It is provided to inform you. Like numbers refer to like elements in the figures.

1 is a circuit diagram showing a configuration of a nonvolatile memory device to which the present invention is applied.

The nonvolatile memory device 100 includes a memory cell array 110 including a plurality of memory cells, and a page buffer 120 connected to the memory cells to program specific data or to read data stored in the memory cells. It includes.

The memory cell array 110 may input / output memory cells MC0 to MCn for storing data, word lines WL <0: n> for selecting and activating the memory cells, and data of the memory cells. And a plurality of bit lines BLe and BLo, wherein the plurality of word lines and the plurality of bit lines are arranged in a matrix form.

The memory cell array 110 includes a drain select transistor DST connected between a bit line and a memory cell, and a source select transistor SST connected between a common source line and a memory cell. In addition, a plurality of memory cells connected in series between the source select transistor SST and the drain select transistor DST may be referred to as a cell string 112.

Gates of the memory cells are connected to word lines, and a set of memory cells commonly connected to the same word line is called a page (page 114). A plurality of strings connected to each bit line are connected in parallel to a common source line to form a block.

The page buffer 120 includes a bit line selector 130 for selectively connecting a bit line connected to a specific cell with a sensing node, a sensing node precharge unit 140 for applying a high level power voltage to the sensing node; A data latch unit 150 for temporarily storing data to be programmed in a specific cell or temporarily storing data read from a specific cell, a data setting unit 160 for inputting data to be stored in the data latch unit, and a level of the sensing node A sensing node sensing unit 170 for applying a ground voltage to a specific node of the data latching unit, a data transmitting unit 180 for applying data stored in the data latching unit to the sensing node, and the data latching unit 150 stored in the data latching unit 150. It includes a verification signal output unit 190 for notifying whether the verification is completed according to the data.

The bit line selector 130 may include an NMOS transistor N136 connecting the even bit line BLe and the sensing node SO in response to a first bit line select signal BSLe, and a second bit line select signal. And an NMOS transistor N138 connecting the odd bit line BLo and the sensing node SO in response to BSLo.

In addition, the bit line selector 130 connects the even bit line BLe and the variable voltage input terminal in response to a variable voltage input terminal applying a variable voltage VIRPWR having a specific level and a first discharge signal DISCHe. And an NMOS transistor N134 for connecting the odd bit line BLo and a variable voltage input terminal in response to a second discharge signal DISCHo.

The sensing node precharge unit 140 applies a high level voltage VDD to the sensing node SO in response to a precharge signal Prechb. To this end, it includes a PMOS transistor (P130) connected between the power supply voltage terminal (VDD) and the sensing node. Accordingly, a high level power supply voltage is applied to the sensing node SO in response to a low level precharge signal.

The data latch unit 150 temporarily stores data to be programmed in a specific cell or temporarily stores data read from a specific cell. To this end, the output terminal of the first inverter IV152 is connected to the input terminal of the second inverter IV154, and the output terminal of the second inverter IV154 is connected to the input terminal of the first inverter IV152. .

In this case, a node to which the output terminal of the first inverter IV152 and the input terminal of the second inverter IV154 are connected is called a first node Q, and the output terminal of the second inverter IV154 and the first inverter IV152 are connected. The node to which the input terminal of) is connected is called a second node Qb.

For example, when high level data is applied to the first node Q, the corresponding data is inverted by the second inverter and low level data is applied to the second node Qb, which is again applied to the first inverter. This results in a data storage effect in which the high level data applied to the first node Q is maintained as it is. Conversely, when low level data is applied to the first node Q, the corresponding data is inverted by the second inverter, and high level data is applied to the second node Qb, which is again caused by the first inverter. The data storage effect in which the low-level data applied to the first node Q is maintained as it is is reversed.

The data setting unit 160 applies a ground voltage to the first data setting transistor N162 and a second node Qb to apply a ground voltage to the first node Q of the data latch unit 150. The second data setting transistor N164 is included.

The first data setting transistor N162 is connected between the sensing node sensing unit 170 and the first node, and is grounded by the sensing node sensing unit 170 in response to a first data setting signal RESET. A voltage is applied to the first node.

In addition, the second data setting transistor N164 is connected between the sensing node sensing unit 170 and the second node, and the sensing node sensing unit 170 is transferred in response to a second data setting signal SET. Apply a ground voltage to the second node.

The sensing node sensing unit 170 applies a ground voltage to the data setting unit 160 according to the voltage level of the sensing node. To this end, it includes an NMOS transistor (N170) connected between the data setting unit 160 and the ground terminal.

Therefore, the ground voltage is applied to the data setting unit according to the voltage level of the sensing node. Only when the sensing node has a high level, the ground voltage is applied to the data setting unit. At this time, when the high level first data setting signal RESET is applied, the ground voltage is applied to the first node Q, which is considered to be low level data applied to the first node. However, when the high level second data setting signal SET is applied, the ground voltage is applied to the second node Qb, which is considered to be applied to the first node.

The data transmitter 180 selectively applies data stored in the first node Q of the data latch unit 150 to the sensing node. To this end, it includes a data transfer transistor (N180) for selectively connecting the first node (Q) and the sensing node.

The verification signal output unit 190 outputs a signal indicating whether verification is completed according to data stored in the first node Q of the data latch unit 150. To this end, it includes a PMOS transistor (P190) for transmitting a high-level power supply voltage terminal to the verification signal output terminal (nWDO) according to the signal of the first node (Q).

According to an exemplary embodiment, an NMOS transistor may be used to transfer a high level power supply voltage terminal to the verification signal output terminal nWDO according to the signal of the second node Qb.

In such a program operation of the nonvolatile memory device, an incremental step pulse programming (ISPP) method is generally used. It will be described in detail through the drawings.

2 is a diagram illustrating an ISPP program method of a nonvolatile memory device.

In the figure, a program voltage pulse applied to a word line, a threshold voltage change state of each cell according to the application of the program voltage, and a change state of data stored in a latch of a page buffer are simultaneously shown.

The program voltage applied to the word line is applied in such a manner as to continuously increase the program start voltage Vstart in the form of a pulse by the step voltage Vstep. After the application of the program voltage of one pulse, the verification voltage is applied to determine whether the program is completed.

According to the application of the program voltage, the threshold voltage of the corresponding cell is increased, but the threshold voltages of all the cells do not increase equally. As shown, a cell having a relatively fast rising speed of a threshold voltage (hereinafter, referred to as a fast cell) and a cell having a relatively slow rising speed (hereinafter, referred to as a slow cell) coexist. In the case of the fast cell, when the program pulse is applied twice, the program has already been programmed above the verify voltage, and the data stored in the latch is changed from 0 to 1. However, in the case of a slow cell, a program pulse is applied three times to make a program, and data stored in the latch is changed. In this way, application of the program pulse is stopped after all data stored in the latch is changed.

In such an ISPP program method, a method in which the step voltage is fixed to one voltage is usually used. Therefore, the step voltage applied at the beginning of the program operation with many unprogrammed cells and the latter part of the program operation with many programmed cells becomes the same. Such a configuration applies a program pulse that rises constantly regardless of the program progress state of the cell, so that the time required for completion of the program is difficult to be shortened. Accordingly, the present invention intends to use a program method for supplying the step voltage in accordance with the program progress state of the cell.

3 is a flowchart illustrating a program method of a nonvolatile memory device according to an exemplary embodiment of the present invention.

First, a program start voltage is set to perform a program operation according to the ISPP (step 210).

Generally, a high voltage of about 10 to 15V is used as the program start voltage, and it may be changed according to an embodiment.

Next, a program operation is performed based on the set program start voltage (step 220).

The program operation is performed by applying a program voltage to a word line connected to a cell to be programmed and applying a program protection voltage to the remaining word lines.

Next, according to the program operation, a verification operation for checking whether a program is completed is performed to determine whether verification is completed (step 222).

Whether the verification is completed is performed using the verification signal output unit 190 of FIG. 1.

This will be described with reference to FIG. 1 again.

The data stored in a particular cell depends on the data stored in the data latch unit 150. In general, when the low level data is stored in the first node Q, the corresponding cell becomes a program target, and when the high level data is stored, the cell becomes a program prohibition target (or an erase target). Prior to the program operation, low level or high level data is stored in the first node according to externally input data.

In this state, the program operation is performed, and the threshold voltage of the specific cell is increased according to the application of the program pulse. In the case of a program target cell, the program may be completed by applying one program pulse, but in some cases, the program target cell may not be completed. This is the same phenomenon as the above-mentioned fast cell and slow cell occurs. In this case, whether the program is completed or not is determined based on whether a current path from the sensing node to the cell string is formed by applying a verification voltage to the word line of the corresponding cell.

That is, when the cell is programmed above the verify voltage, the threshold voltage is high so that the cell is not turned on. Thus, the current path is not formed and the high level voltage precharged to the sensing node is maintained.

However, if the cell is not programmed to the verification voltage, the cell is turned on, forming a current path from the sensing node to the cell string, and the charges precharged on the sensing node flow to the common source line connected to ground. The sensing node transitions to a low level voltage.

That is, the voltage level of the sensing node is changed according to whether or not a specific cell is programmed.

Now, the voltage level applied to the sensing node is sensed, which is performed through the sensing node sensing unit 170 and the data setting unit 160 of FIG. 1.

When a specific cell is programmed and a high level voltage is applied to the sensing node, the NMOS transistor N170 of the sensing node sensing unit 170 is turned on to transfer the ground voltage to the data setting unit 160. As the data setting signal SET is applied, the low level data stored in the first node Q (in which the low level data is stored in the case of a program target) is changed to the high level.

However, when a low level voltage is applied to the sensing node because no specific cell is programmed, the sensing node sensing unit 170 does not operate so that data is not changed. That is, the low level data stored in the first node Q is maintained as it is. Therefore, it is possible to determine whether the verification is completed based on the data stored in the first node (Q). That is, when all data stored in the first node Q of all page buffers connected to a specific page become high level data according to the repetition of the program operation, it is determined that verification is completed.

When the program is completed as a result of the determination, the program operation is terminated.

However, if there is any cell that is not programmed above the verify voltage even in the program target cell, the program pulse is repeatedly applied. In the present invention, the program pulse is applied by increasing the step voltage. Instead of increasing the fixed step voltage, the step voltage is varied according to the program state of all cells. In one embodiment, the number of verified cells is measured, and a step voltage is applied differently according to the number.

To this end, the number of verified cells is measured (step 230).

The object to be measured becomes the page on which the program is currently running. As mentioned above, when a program of a specific cell is completed, high level data is stored in the first node. Based on that, the number of verified cells is measured.

Typically, one page contains 2112 cells. Among them, 2048 cells are normal cells and 64 cells are redundancy cells prepared in case a normal cell fails. Therefore, it can be seen that a total of 2048 cells stored in one page. In this case, the numerical values are not intended to limit the present invention, and are given as examples for simplicity of description.

A method of measuring the number of the verified cells will be described in more detail.

4 is a diagram illustrating a concept of a method for measuring the number of verified cells according to an embodiment of the present invention.

In the present invention, the number of verified cells is measured by using a bitwise and operation.

As shown, data stored in the first node of each page buffer are simultaneously output to form 32-bit data. When high level data is stored in the first node, the output data is assumed to be '1'.

Therefore, the number of 1s in the output data may be regarded as the number of verified cells. In the figure, it can be seen that there are a total of 15 verified cells.

Bitwise multiplication is used for this calculation.

That is, by multiplying 32-bit operation data in which the first bit is 1 and all the others are 0 with respect to the output data, it may be determined whether the first bit of the output data is 1. If the product is 1, the first bit of output data is 1; if the product is 0, the first bit of output data is zero.

Next, the output data is multiplied by the operation data in which only the second bit is one and all the others are zero. As shown, the second bit of the output data is zero, so the product is zero.

In this manner, the operation is performed while shifting the operation data such as the number of bits of the output data by one bit. The operation is repeated by the number of bits of the output data. After performing the bit-by-bit multiplication operation such that the output values are all added, it is possible to determine how many 1's are in the output data, that is, how many cells have been verified.

The following is actual programming code for obtaining the number of verified cells using the above method. This code considers 2048 normal cells and 64 redundancy cells.

// Function to count the number of 1s in one int data (32bit).

int count_one (int data)

int count, i, a;

// Variable counting one.

count = 0;

// Variable that stores the value to determine whether the value of the corresponding position is 1 through actual data and bitwise and operation.

// initial value is 00000000000000000000000000000001 => decimal number 1.

a = 1;

for (i = 0; i <32; i ++)

// If the value is not 0 by bitwise and calculating the data and a value received as function arguments, count increases.

if ((data & a)! = 0) count ++;

// multiplies a by 2 and shifts 1 by 1 bit left shift.

a = a * 2;

// Repeat 32 times because it is 32 bit.

// return count value.

return count;

int main (void)

int count, num, i, j;

int dat;

FILE * fp;

// file pointer

fp = fopen ("data.out", "rb");

// Variable to count the number of pages.

num = 0;

// page 0 to page 9

for (j = 0; j <10; j ++)

// Set initial value of number 1.

count = 0;

for (i = 0; i <(2048 / sizeof (int)); i ++)

// Read 4 bytes from input file and store in dat.

fread (& dat, 4, 1, fp);

// Accumulate and add results by calling a function that counts 1

count + = count_one (dat);

// Repeat as divided by 2048 bits per page and int size of 32 bits.

// output content.

printf ("page% d's number of 1 is% d (% d%)", num, count, (int) (count * 100/16384));

// Reset the default number of 1s for the redundancy zone.

count = 0;

// same as above data area. Here, the size of red. Is 64 bit.

for (i = 0; i <(64 / sizeof (int)); i ++)

fread (& dat, 4, 1, fp);

count + = count_one (dat);

printf ("redundancy of page% d's number of 1 is% d (% d%)", num, count, (int) (count * 100/512));

// next page.

num ++;

// close the file.

fclose (fp);

// End.

return 0;

Now, a detailed circuit to which the algorithm can be applied is presented.

5 is a circuit diagram illustrating an adder for measuring the number of verified cells according to an embodiment of the present invention.

The adder is a total of 11 flip-flops in series. When all the cells included in the aforementioned page are programmed, a total of 2048 1 data will be output. Therefore, the maximum value of the number of verified cells that can be obtained from the algorithm is 2048. Therefore, a total of 11 flip-flops are connected in series according to this maximum value. (2 ^ 11 = 2048)

A clock having a predetermined period is input to the first flip-flop 510, and output data of a page buffer is sequentially input in synchronization with the clock.

Each flip-flop outputs '1' when '1' data is input at the falling edge of the clock, and maintains its previous state when '0' data is input.

The result is expressed as AX <10> AX <9> ....... AX <0>, which is a binary value.

Referring to FIG. 3 again, how to use the measured number of verified cells will be described.

First, it is determined whether the measured number of verified cells is equal to or less than a first threshold (step 240).

Preferably, the first threshold is set to a value corresponding to 30% of the total number of cells included in the page. For example, if 2048 cells are included in one page, it is set as 633.

If the result of the determination is that the number of the verified cells is less than or equal to the first threshold value, the step voltage is set as the first step voltage (step 242).

In this case, the first step voltage is characterized in that a predetermined amount increased than the step voltage is normally applied. The fact that the number of verified cells is less than or equal to the first threshold indicates that it is the beginning of the program operation. Therefore, the step voltage is increased so that the program pulse is increased.

If the number of verified cells is greater than the first threshold as a result of the determination, it is determined whether the measured number of verified cells is less than or equal to the second threshold (step 244).

In this case, the second threshold value is larger than the first threshold value, and preferably, a value corresponding to 70% of the total number of cells included in the page. For example, if a page contains 2048 cells, it is set to 1478.

As a result of the determination, when the number of the verified cells is greater than the first threshold value and less than the second threshold value, the step voltage is set as the second step voltage (step 246).

At this time, the second step voltage is set to be smaller than the first step voltage, it is characterized in that a predetermined amount increased than the step voltage is normally applied.

If the number of verified cells is greater than the second threshold as a result of the determination, the step voltage is set as the third step voltage (step 248).

At this time, the third step voltage is set smaller than the second step voltage.

The first to third step voltages have the following relationship.

First Step Voltage> Second Step Voltage> Third Step Voltage

Preferably, the first step voltage is the third step voltage + 1V, the second step voltage = the third step voltage + 0.5V. On the other hand, the third step voltage is set to 0.5V.

In the present invention, the threshold value is set to two, and a total of three step voltages are applied. However, in some embodiments, the threshold value may be further subdivided to apply more various step voltages. In addition, the numerical value defining the threshold value can be adjusted differently according to the designer's intention.

Next, the program pulse is reset according to the set step voltage (step 250).

The program pulse reset is performed by adding the set program step voltage to a program pulse applied in a previous program operation.

If immediately after the initial program start voltage is applied, the first, second or third step voltage is added to the program start voltage.

Next, it is determined whether the reset program pulse exceeds the maximum value set as the threshold (step 260).

If the determination result is smaller than the maximum value, the program operation is repeatedly performed based on the reset program pulse.

However, if the determination result is larger than the maximum value, program failure processing is performed (step 262).

This is to limit the magnitude of the program pulse.

In summary, the number of verified cells is measured, and the magnitude of the step voltage added to the program pulse is supplied according to the value. According to such a configuration, a larger step voltage is applied to the beginning of the program operation in which the number of verified cells is relatively small, thereby increasing the program speed and reducing the overall program time.

Claims

Performing a program operation based on the first program voltage;

Performing a verification operation for confirming whether the program is completed;

Measuring the number of verified cells among cells included in the page on which the program operation is performed;

Setting a step voltage to a first step voltage when the number of the verified cells is less than or equal to a first threshold value;

Setting a step voltage to a second step voltage smaller than the first step voltage when the number of the verified cells is greater than the first threshold value and is less than or equal to the second threshold value;

Setting a step voltage to a third step voltage smaller than the second step voltage when the number of the verified cells is greater than the second threshold value;

Resetting a program voltage by adding the set step voltage to the first program voltage;

And repeating a program operation according to the reset program voltage.

The method of claim 1, wherein performing the verify operation comprises terminating a program operation when the program is completed.

The nonvolatile memory device of claim 1, wherein the measuring of the number of verified cells comprises adding the number of cells in which the first data is stored to a data latch unit of the nonvolatile memory device. Program method.

The method of claim 1, wherein measuring the number of verified cells comprises: outputting data of the page;

Providing operation data having the same number of bits as the output data and having only one bit as the number of bits;

Bitwise ANDing each of the operation data and the output data;

And calculating the number of verified cells by summing the output values by multiplying each bit.

The method of claim 1, further comprising providing a value corresponding to 30% of the number of cells included in the page as a first threshold value.

The method of claim 1, further comprising providing a value corresponding to 70% of the number of cells included in the page as a second threshold value.

The method of claim 1, wherein resetting the program voltage further comprises performing a program failure processing when the reset program voltage exceeds a predetermined level.

Performing a program operation based on the first program voltage;

Setting a step voltage to a smaller voltage as the number of verified cells increases;

And repeating a program operation according to the reset program voltage.

The method of claim 8, wherein the setting of the step voltage comprises: setting the step voltage as the first step voltage when the number of the verified cells is less than or equal to a first threshold value;

And setting the step voltage to a third step voltage smaller than the second step voltage when the number of the verified cells is greater than the second threshold value.

The nonvolatile memory device of claim 8, wherein the measuring of the number of verified cells comprises adding the number of cells in which the first data is stored in a data latch unit of the nonvolatile memory device. Program method.

The method of claim 8, wherein measuring the number of verified cells comprises: outputting data of the page;

Bitwise ANDing each of the operation data and the output data;