TWI660576B - Doherty power amplifier combiner with tunable impedance termination circuit - Google Patents
Doherty power amplifier combiner with tunable impedance termination circuit Download PDFInfo
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/02—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
- H03F1/0205—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers
- H03F1/0288—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers using a main and one or several auxiliary peaking amplifiers whereby the load is connected to the main amplifier using an impedance inverter, e.g. Doherty amplifiers
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/56—Modifications of input or output impedances, not otherwise provided for
- H03F1/565—Modifications of input or output impedances, not otherwise provided for using inductive elements
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/189—High-frequency amplifiers, e.g. radio frequency amplifiers
- H03F3/19—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
- H03F3/24—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages
- H03F3/245—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages with semiconductor devices only
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/72—Gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2200/00—Indexing scheme relating to amplifiers
- H03F2200/111—Indexing scheme relating to amplifiers the amplifier being a dual or triple band amplifier, e.g. 900 and 1800 MHz, e.g. switched or not switched, simultaneously or not
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2200/00—Indexing scheme relating to amplifiers
- H03F2200/451—Indexing scheme relating to amplifiers the amplifier being a radio frequency amplifier
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
- H03F2203/72—Indexing scheme relating to gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal
- H03F2203/7209—Indexing scheme relating to gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal the gated amplifier being switched from a first band to a second band
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Abstract
本發明揭示具有可調阻抗終端電路之杜赫功率放大器組合器。一信號組合器可包含具有一第一線圈及一第二線圈之一平衡-不平衡變壓器電路。可在一第一埠與一第二埠之間實施該第一線圈。可在一第三埠與一第四埠之間實施該第二線圈。可藉由一第一電容器來耦合該第一埠與該第三埠。可藉由一第二電容器來耦合該第二埠與該第四埠。該第一埠可經組態以接收一第一信號。該第四埠可經組態以接收一第二信號。該第二埠可經組態以產生該第一信號與該第二信號之一組合。該信號組合器可包含將該第三埠耦合至一接地之一終端電路。該終端電路可包含一可調阻抗電路。 The invention discloses a Douhe power amplifier combiner with an adjustable impedance termination circuit. A signal combiner may include a balanced-unbalanced transformer circuit having a first coil and a second coil. The first coil may be implemented between a first port and a second port. The second coil may be implemented between a third port and a fourth port. The first port and the third port can be coupled by a first capacitor. The second port and the fourth port can be coupled by a second capacitor. The first port can be configured to receive a first signal. The fourth port can be configured to receive a second signal. The second port may be configured to generate a combination of the first signal and the second signal. The signal combiner may include a terminating circuit coupling the third port to a ground. The termination circuit may include an adjustable impedance circuit.
Description
本申請案主張2014年8月13日申請之標題為TUNABLE WIDE-BAND HYBRID-BASED DOHERTY COMBINER WITH WIDE-BAND HARMONIC REJECTION之美國臨時申請案第62/036,854號之優先權,該案之全部內容以引用的方式明確併入本文中。 This application claims the priority of U.S. Provisional Application No. 62 / 036,854, entitled TUNABLE WIDE-BAND HYBRID-BASED DOHERTY COMBINER WITH WIDE-BAND HARMONIC REJECTION, filed on August 13, 2014, the entire contents of which are incorporated by reference The way is explicitly incorporated into this article.
本發明大體上係關於射頻(RF)信號組合器。 The present invention relates generally to radio frequency (RF) signal combiners.
用於4G LTE(長期演進)應用之多模式/多頻帶(MMMB)功率放大器模組(PAM)較佳地在後退條件中操作以在維持高功率附加效率(PAE)的同時可滿足高峰值對平均功率比(PAPR)規格。相較於用於後退條件下之效率增強之包絡追蹤PAM,杜赫PAM能夠憑藉大幅減小之系統複雜性及減小校準及數位預失真(DPD)規格滿足具有後退條件下之高線性之高效率。然而,典型杜赫功率放大器架構之帶寬歸因於現有杜赫功率組合器之窄頻帶性質而受到限制。 Multi-Mode / Multi-Band (MMMB) Power Amplifier Modules (PAMs) for 4G LTE (Long Term Evolution) applications preferably operate in back-off conditions to meet high peak pairing while maintaining high power added efficiency (PAE) Average power ratio (PAPR) specifications. Compared to envelope tracking PAM for enhanced efficiency in back-off conditions, Douglas PAM can meet the high linearity under back-off conditions with significantly reduced system complexity and reduced calibration and digital pre-distortion (DPD) specifications effectiveness. However, the bandwidth of a typical Doherty power amplifier architecture is limited due to the narrow-band nature of existing Doherty power combiners.
根據一些實施方案,本發明係關於一種包含具有一第一線圈及一第二線圈之一平衡-不平衡變壓器電路之信號組合器。在一第一埠與一第二埠之間實施該第一線圈。在一第三埠與一第四埠之間實施該 第二線圈。藉由一第一電容器耦合該第一埠與該第三埠。藉由一第二電容器耦合該第二埠與該第四埠。該第一埠經組態以接收一第一信號。該第四埠經組態以接收一第二信號。該第二埠經組態以產生該第一信號與該第二信號之一組合。該信號組合器進一步包含將該第三埠耦合至一接地之一終端電路。該終端電路包含一可調阻抗元件。 According to some embodiments, the present invention relates to a signal combiner including a balanced-unbalanced transformer circuit having a first coil and a second coil. The first coil is implemented between a first port and a second port. Implementing this between a third port and a fourth port The second coil. The first port and the third port are coupled by a first capacitor. The second port and the fourth port are coupled by a second capacitor. The first port is configured to receive a first signal. The fourth port is configured to receive a second signal. The second port is configured to generate a combination of the first signal and the second signal. The signal combiner further includes a terminating circuit coupling the third port to a ground. The termination circuit includes an adjustable impedance element.
在一些實施例中,該信號組合器可進一步包含一控制器,該控制器經組態以接收一頻帶選擇信號且基於該頻帶選擇信號調諧該可調阻抗電路。在一些實施例中,該控制器可經進一步組態以調諧該第一電容器或該第二電容器之至少一者。 In some embodiments, the signal combiner may further include a controller configured to receive a band selection signal and tune the adjustable impedance circuit based on the band selection signal. In some embodiments, the controller may be further configured to tune at least one of the first capacitor or the second capacitor.
在一些實施例中,該第一埠可經組態以自一杜赫功率放大器(PA)接收一載波放大信號且該第四埠可經組態以自該杜赫PA接收一峰值放大信號。在一些實施例中,該可調阻抗電路包含複數個電容器。該複數個電容器之各者可具有約等於二乘以π乘以該杜赫PA之一各自操作頻率乘以耦合至該杜赫PA之一負載之一特性阻抗之一倒數之一電容。在一些實施例中,該信號組合器可包含一控制器,該控制器經組態以接收指示一操作頻率之一頻帶選擇信號且調諧該可調阻抗電路以具有約等於二乘以π乘以該操作頻率乘以耦合至該杜赫PA之一負載之一特性阻抗之一倒數之一電容。在一些實施例中,該控制器可經進一步組態以調諧該第一電容器及該第二電容器以具有約等於該可調阻抗電路之該電容之一半之一電容。 In some embodiments, the first port may be configured to receive a carrier amplified signal from a Doherty power amplifier (PA) and the fourth port may be configured to receive a peak amplified signal from the Doherty PA. In some embodiments, the adjustable impedance circuit includes a plurality of capacitors. Each of the plurality of capacitors may have a capacitance approximately equal to two times pi times one of the respective operating frequency of the Douch PA and one of the inverse of a characteristic impedance coupled to a load of the Douch PA. In some embodiments, the signal combiner may include a controller configured to receive a frequency band selection signal indicative of an operating frequency and tune the adjustable impedance circuit to have an approximately equal to two times π times by The operating frequency is multiplied by a reciprocal of a capacitance coupled to a characteristic impedance of a load coupled to the Duch PA. In some embodiments, the controller may be further configured to tune the first capacitor and the second capacitor to have a capacitance approximately equal to one-half of the capacitance of the adjustable impedance circuit.
在一些實施例中,該第一埠可經組態以自一杜赫功率放大器(PA)接收一峰值放大信號且該第四埠可經組態以自該杜赫PA接收一載波放大信號。在一些實施例中,該可調阻抗電路可包含複數個電感器。該複數個電感器之各者可具有約等於耦合至該杜赫PA之一負載之一特性阻抗除以二乘以π乘以該杜赫PA之一各自操作頻率之一電感。在一些實施例中,該信號組合器可包含一控制器,該控制器經組態以接 收指示一操作頻率之一頻帶選擇信號且調諧該可調阻抗電路以具有約等於耦合至該杜赫PA之一負載之一特性阻抗除以二乘以π乘以該操作頻率之一電感。 In some embodiments, the first port may be configured to receive a peak amplified signal from a Doherty power amplifier (PA) and the fourth port may be configured to receive a carrier amplified signal from the Doherty PA. In some embodiments, the adjustable impedance circuit may include a plurality of inductors. Each of the plurality of inductors may have an inductance approximately equal to a characteristic impedance of a load coupled to the Duch PA divided by two times π times the respective operating frequency of one of the Duch PAs. In some embodiments, the signal combiner may include a controller configured to connect to Receive a frequency band selection signal indicating an operating frequency and tune the adjustable impedance circuit to have an inductance approximately equal to a characteristic impedance of a load coupled to the Douhe PA divided by two times π times the operating frequency.
在一些實施例中,該可調阻抗匹配電路可包含並聯連接之複數個阻抗元件,該複數個阻抗元件之各者包含串聯連接之一阻抗及一開關。 In some embodiments, the adjustable impedance matching circuit may include a plurality of impedance elements connected in parallel, and each of the plurality of impedance elements includes an impedance and a switch connected in series.
在一些實施例中,該終端電路可進一步包含一諧波抑制電路,該諧波抑制電路經組態以減小該第二埠處之一或多個諧波之強度。在一些實施例中,該諧波抑制電路可包含串聯連接之複數個諧振元件,該複數個諧振元件之各者包含並聯連接之一電感器及一電容器。在一些實施例中,該複數個諧振元件之各者可具有約等於該信號組合器之一操作頻率之一倍數之一諧振頻率。在一些實施例中,該複數個諧振元件之各者可具有約等於該信號組合器之一各自操作頻率之兩倍之一諧振頻率。在一些實施例中,在該第三埠與該可調阻抗電路之間實施該諧波抑制電路。 In some embodiments, the termination circuit may further include a harmonic suppression circuit configured to reduce the intensity of one or more harmonics at the second port. In some embodiments, the harmonic suppression circuit may include a plurality of resonance elements connected in series, and each of the plurality of resonance elements includes an inductor and a capacitor connected in parallel. In some embodiments, each of the plurality of resonant elements may have a resonant frequency approximately equal to a multiple of an operating frequency of the signal combiner. In some embodiments, each of the plurality of resonant elements may have a resonant frequency that is approximately equal to twice the respective operating frequency of one of the signal combiners. In some embodiments, the harmonic suppression circuit is implemented between the third port and the adjustable impedance circuit.
在一些實施方案中,本發明係關於一種包含經組態以接納複數個組件之一封裝基板之一功率放大器模組。該功率放大模組包含在該封裝基板上實施之一信號組合器。該信號組合器包含具有一第一線圈及一第二線圈之一平衡-不平衡變壓器電路。在一第一埠與一第二埠之間實施該第一線圈。在一第三埠與一第四埠之間實施該第二線圈。藉由一第一電容器耦合該第一埠與該第三埠。藉由一第二電容器耦合該第二埠與該第四埠。該第一埠經組態以接收一第一信號。該第四埠經組態以接收一第二信號。該第二埠經組態以產生該第一信號與該第二信號之一組合。該信號組合器進一步包含將該第三埠耦合至一接地之一終端電路。該終端電路包含一可調阻抗電路。 In some embodiments, the invention relates to a power amplifier module including a package substrate configured to receive one of a plurality of components. The power amplifier module includes a signal combiner implemented on the package substrate. The signal combiner includes a balanced-unbalanced transformer circuit having a first coil and a second coil. The first coil is implemented between a first port and a second port. The second coil is implemented between a third port and a fourth port. The first port and the third port are coupled by a first capacitor. The second port and the fourth port are coupled by a second capacitor. The first port is configured to receive a first signal. The fourth port is configured to receive a second signal. The second port is configured to generate a combination of the first signal and the second signal. The signal combiner further includes a terminating circuit coupling the third port to a ground. The termination circuit includes an adjustable impedance circuit.
在一些實施例中,該PA模組可進一步包含在該封裝基板上實施 之一控制器,該控制器經組態以接收一頻帶選擇信號且基於該頻帶選擇信號調諧該可調阻抗電路。 In some embodiments, the PA module may further include an implementation on the package substrate. A controller configured to receive a band selection signal and tune the adjustable impedance circuit based on the band selection signal.
在一些實施方案中,本發明係關於一種包含經組態以產生一射頻(RF)信號之一收發器之無線裝置。該無線裝置包含與該收發器通信之一功率放大器(PA)模組。該PA模組包含一輸入電路,該輸入電路經組態以接收該RF信號且將該RF信號分裂為一第一部分及一第二部分。該PA模組進一步包含一杜赫PA,該杜赫PA具有耦合至該輸入電路以接收該第一部分之一載波放大路徑及耦合至該輸入電路以接收該第二部分之一峰值放大路徑。該PA模組進一步包含耦合至該杜赫放大器電路之一輸出電路。該輸出電路包含具有一第一線圈及一第二線圈之一平衡-不平衡變壓器電路。在一第一埠與一第二埠之間實施該第一線圈。在一第三埠與一第四埠之間實施該第二線圈。藉由一第一電容器耦合該第一埠與該第三埠。藉由一第二電容器耦合該第二埠與該第四埠。該第一埠經組態以經由該載波放大路徑接收一第一信號。該第四埠經組態以經由該峰值放大路徑接收一第二信號。該第二埠經組態以產生該第一信號與該第二信號之一組合以作為一經放大RF信號。該PA模組進一步包含將該第三埠耦合至一接地之一終端電路。該終端電路包含一可調阻抗電路。該無線裝置進一步包含與該PA模組通信之一天線。該天線經組態以促進該經放大RF信號之發送。 In some embodiments, the invention relates to a wireless device including a transceiver configured to generate a radio frequency (RF) signal. The wireless device includes a power amplifier (PA) module in communication with the transceiver. The PA module includes an input circuit configured to receive the RF signal and split the RF signal into a first part and a second part. The PA module further includes a Doherty PA having a carrier amplification path coupled to the input circuit to receive the first part and a peak amplification path to the input circuit to receive the second part. The PA module further includes an output circuit coupled to the Doher amplifier circuit. The output circuit includes a balanced-unbalanced transformer circuit having a first coil and a second coil. The first coil is implemented between a first port and a second port. The second coil is implemented between a third port and a fourth port. The first port and the third port are coupled by a first capacitor. The second port and the fourth port are coupled by a second capacitor. The first port is configured to receive a first signal through the carrier amplification path. The fourth port is configured to receive a second signal through the peak amplification path. The second port is configured to generate a combination of the first signal and the second signal as an amplified RF signal. The PA module further includes a terminating circuit coupled to the third port to a ground. The termination circuit includes an adjustable impedance circuit. The wireless device further includes an antenna for communicating with the PA module. The antenna is configured to facilitate transmission of the amplified RF signal.
在一些實施例中,該無線裝置可進一步包含一控制器,該控制器經組態以接收一頻帶選擇信號且基於該頻帶選擇信號調諧該可調阻抗電路。 In some embodiments, the wireless device may further include a controller configured to receive a frequency band selection signal and tune the adjustable impedance circuit based on the frequency band selection signal.
本發明係關於2015年7月13日申請之標題為CIRCUITS,DEVICES AND METHODS RELATED TO COMBINERS FOR DOHERTY POWER AMPLIFIERS之美國專利申請案第14/797,261號,且該案之全部內容以引用的方式併入本文中。 This invention relates to U.S. Patent Application No. 14 / 797,261, entitled CIRCUITS, DEVICES AND METHODS RELATED TO COMBINERS FOR DOHERTY POWER AMPLIFIERS, filed on July 13, 2015, and the entire contents of that case are incorporated herein by reference. in.
100‧‧‧功率放大器(PA) 100‧‧‧ Power Amplifier (PA)
100a‧‧‧功率放大器(PA) 100a‧‧‧ Power Amplifier (PA)
100b‧‧‧功率放大器(PA) 100b‧‧‧Power Amplifier (PA)
100c‧‧‧功率放大器(PA) 100c‧‧‧Power Amplifier (PA)
100d‧‧‧功率放大器(PA) 100d‧‧‧Power Amplifier (PA)
102‧‧‧預驅動器放大器 102‧‧‧ pre-driver amplifier
104‧‧‧除法器 104‧‧‧Divider
110‧‧‧載波放大路徑 110‧‧‧Carrier amplification path
112‧‧‧衰減器 112‧‧‧ Attenuator
114‧‧‧放大級 114‧‧‧Magnification
116‧‧‧驅動器級 116‧‧‧Driver level
118‧‧‧偏壓電路 118‧‧‧ bias circuit
120‧‧‧輸出級 120‧‧‧ output stage
122‧‧‧偏壓電路 122‧‧‧ bias circuit
130‧‧‧峰值放大路徑 130‧‧‧peak amplification path
132‧‧‧相移電路 132‧‧‧phase shift circuit
134‧‧‧放大級 134‧‧‧magnification
136‧‧‧驅動器級 136‧‧‧Driver level
138‧‧‧偏壓電路 138‧‧‧ bias circuit
140‧‧‧輸出級 140‧‧‧output stage
142‧‧‧偏壓電路 142‧‧‧ bias circuit
144‧‧‧組合器 144‧‧‧Combiner
221‧‧‧變壓器 221‧‧‧Transformer
222‧‧‧第一電容器 222‧‧‧First capacitor
223‧‧‧第二電容器 223‧‧‧Second capacitor
231‧‧‧第一埠 231‧‧‧Port I
232‧‧‧第二埠 232‧‧‧Second Port
233‧‧‧第三埠 233‧‧‧Third Port
234‧‧‧第四埠 234‧‧‧Fourth Port
251‧‧‧平衡-不平衡變壓器 251‧‧‧balanced-unbalanced transformer
254‧‧‧信號組合器 254‧‧‧Signal combiner
300‧‧‧信號組合器 300‧‧‧Signal combiner
301‧‧‧第一線圈 301‧‧‧first coil
302‧‧‧第二線圈 302‧‧‧Second Coil
311‧‧‧第一埠 311‧‧‧First port
312‧‧‧第二埠 312‧‧‧Second Port
313‧‧‧第三埠 313‧‧‧Third Port
314‧‧‧第四埠 314‧‧‧Fourth Port
321‧‧‧第一電容器 321‧‧‧first capacitor
322‧‧‧第二電容器 322‧‧‧Second capacitor
323‧‧‧第三電容器 323‧‧‧Third capacitor
331‧‧‧第一輸入埠 331‧‧‧first input port
332‧‧‧第二輸入埠 332‧‧‧Second Input Port
333‧‧‧輸出埠 333‧‧‧Output port
400‧‧‧信號組合器 400‧‧‧Signal combiner
401‧‧‧第一線圈 401‧‧‧first coil
402‧‧‧第二線圈 402‧‧‧Second Coil
411‧‧‧第一埠 411‧‧‧First Port
412‧‧‧第二埠 412‧‧‧Second Port
413‧‧‧第三埠 413‧‧‧Third Port
414‧‧‧第四埠 414‧‧‧Fourth Port
421‧‧‧第一電容器 421‧‧‧First capacitor
422‧‧‧第二電容器 422‧‧‧Second capacitor
423‧‧‧電感器 423‧‧‧Inductor
431‧‧‧第一輸入埠 431‧‧‧First input port
432‧‧‧第二輸入埠 432‧‧‧second input port
433‧‧‧輸出埠 433‧‧‧Output port
500‧‧‧信號組合器 500‧‧‧Signal combiner
501‧‧‧第一線圈 501‧‧‧first coil
502‧‧‧第二線圈 502‧‧‧Second Coil
511‧‧‧第一埠 511‧‧‧First Port
512‧‧‧第二埠 512‧‧‧Second Port
513‧‧‧第三埠 513‧‧‧Third Port
514‧‧‧第四埠 514‧‧‧Fourth Port
520‧‧‧控制器 520‧‧‧controller
521‧‧‧第一電容器 521‧‧‧First capacitor
522‧‧‧第二電容器 522‧‧‧Second capacitor
523‧‧‧可調阻抗電路 523‧‧‧Adjustable impedance circuit
531‧‧‧第一輸入埠 531‧‧‧first input port
532‧‧‧第二輸入埠 532‧‧‧second input port
533‧‧‧輸出埠 533‧‧‧Output port
610a‧‧‧阻抗 610a‧‧‧Impedance
610b‧‧‧阻抗 610b‧‧‧Impedance
610c‧‧‧阻抗 610c‧‧‧Impedance
610d‧‧‧阻抗 610d‧‧‧Impedance
612a‧‧‧開關 612a‧‧‧Switch
612b‧‧‧開關 612b‧‧‧Switch
612c‧‧‧開關 612c‧‧‧Switch
612d‧‧‧開關 612d‧‧‧Switch
623‧‧‧可調阻抗電路 623‧‧‧Adjustable impedance circuit
700‧‧‧信號組合器 700‧‧‧Signal combiner
724‧‧‧諧波抑制電路 724‧‧‧Harmonic suppression circuit
810a‧‧‧電容器 810a‧‧‧Capacitor
810b‧‧‧電容器 810b‧‧‧Capacitor
810c‧‧‧電容器 810c‧‧‧Capacitor
810d‧‧‧電容器 810d‧‧‧Capacitor
812a‧‧‧電感器 812a‧‧‧Inductor
812b‧‧‧電感器 812b‧‧‧Inductor
812c‧‧‧電感器 812c‧‧‧Inductor
812d‧‧‧電感器 812d‧‧‧Inductor
900‧‧‧模組/虛線盒 900‧‧‧Module / Dotted Box
902‧‧‧封裝基板 902‧‧‧ package substrate
904‧‧‧FE-PMIC組件 904‧‧‧FE-PMIC component
906‧‧‧功率放大器總成 906‧‧‧Power Amplifier Assembly
907‧‧‧組合器 907‧‧‧Combiner
908‧‧‧匹配組件 908‧‧‧ matching components
910‧‧‧多工器總成 910‧‧‧Multiplexer Assembly
912‧‧‧天線開關模組(ASM) 912‧‧‧Antenna Switch Module (ASM)
914‧‧‧SMT裝置 914‧‧‧SMT device
1000‧‧‧無線裝置 1000‧‧‧ wireless device
1002‧‧‧使用者介面 1002‧‧‧user interface
1004‧‧‧記憶體 1004‧‧‧Memory
1006‧‧‧功率管理組件 1006‧‧‧Power Management Module
1008‧‧‧基帶子系統 1008‧‧‧Baseband Subsystem
1010‧‧‧收發器 1010‧‧‧ Transceiver
1012a‧‧‧雙工器 1012a‧‧‧Duplexer
1012b‧‧‧雙工器 1012b‧‧‧Duplexer
1012c‧‧‧雙工器 1012c‧‧‧Duplexer
1012d‧‧‧雙工器 1012d‧‧‧Duplexer
1014‧‧‧天線開關 1014‧‧‧Antenna switch
1016‧‧‧天線 1016‧‧‧ Antenna
1020a‧‧‧匹配電路 1020a‧‧‧matching circuit
1020b‧‧‧匹配電路 1020b‧‧‧matching circuit
1020c‧‧‧匹配電路 1020c‧‧‧matching circuit
1020d‧‧‧匹配電路 1020d‧‧‧matching circuit
RF_IN‧‧‧輸入埠 RF_IN‧‧‧Input port
RF_OUT‧‧‧輸出埠 RF_OUT‧‧‧Output port
圖1展示一功率放大器(PA)之一例示性架構,其中可實施具有如在本文中描述之一或多個特徵之一杜赫組合器。 FIG. 1 shows an exemplary architecture of a power amplifier (PA) in which a Duch combiner having one or more features as described herein can be implemented.
圖2A及圖2B展示可被用作一杜赫組合器之一混合電路之一實例。 2A and 2B show an example of a hybrid circuit that can be used as a Dohert combiner.
圖3展示在一些實施例中,一信號組合器包含具有一電容器之一終端電路。 FIG. 3 shows that in some embodiments, a signal combiner includes a termination circuit having a capacitor.
圖4展示在一些實施例中,一信號組合器包含具有一電感器之一終端電路。 FIG. 4 shows that in some embodiments, a signal combiner includes a termination circuit having an inductor.
圖5展示在一些實施例中,一信號組合器包含具有一可調阻抗電路之一終端電路。 FIG. 5 shows that in some embodiments, a signal combiner includes a termination circuit having an adjustable impedance circuit.
圖6展示在一些實施例中,一可調阻抗電路可包含並聯連接之複數個阻抗元件。 FIG. 6 shows that in some embodiments, an adjustable impedance circuit may include a plurality of impedance elements connected in parallel.
圖7展示在一些實施例中,一信號組合器包含具有一諧波抑制電路之一終端電路。 FIG. 7 shows that in some embodiments, a signal combiner includes a termination circuit having a harmonic suppression circuit.
圖8展示在一些實施方案中,一諧波抑制電路可包含串聯連接之複數個諧振元件。 FIG. 8 shows that in some embodiments, a harmonic suppression circuit may include a plurality of resonant elements connected in series.
圖9描繪具有如在本文中描述之一或多個特徵之一模組。 FIG. 9 depicts a module having one or more features as described herein.
圖10描繪具有在本文中描述之一或多個特徵之一無線裝置。 FIG. 10 depicts a wireless device having one or more of the features described herein.
在本文中提供之標題(若存在)僅為方便起見,且未必影響本發明之範疇或意義。 The headings, if any, provided herein are for convenience only and do not necessarily affect the scope or meaning of the invention.
在本文中,描述藉由提出用於一杜赫功率放大器架構之一基於寬頻帶可調混合之組合器來處理在用於一MMMB PAM之4G LTE標準之線性要求下維持高PAE之問題的電路、系統及方法。使用杜赫功率放大器之負載調變係在功率後退條件下維持高效率之另一方法。在此 方法中,使用兩個並聯PAM(一載波放大器及一峰值放大器)。峰值放大器調變由載波放大器所見之負載,且因此允許載波放大器保持高效率、飽和操作(即使在後退處)。可使用具有匹配至一特定頻率之一阻抗之阻抗匹配網路來達成此負載調變。因此,對於不具有一可調阻抗電路之一MMMB PAM,可使用若干杜赫PAM(其等之各者需要兩個放大器)來覆蓋若干頻帶,此可使實施方案變得昂貴及/或不實際。 In this article, a circuit is described that addresses the problem of maintaining high PAE under the linear requirements of the 4G LTE standard for a MMMB PAM by proposing one of the wideband tunable hybrid-based combiners for a Doherty power amplifier architecture , Systems and methods. Load modulation using Douhe power amplifiers is another method to maintain high efficiency under power back-off conditions. here In the method, two parallel PAMs (a carrier amplifier and a peak amplifier) are used. The peak amplifier modulates the load seen by the carrier amplifier, and therefore allows the carrier amplifier to maintain high efficiency, saturated operation (even at the fallback). This load modulation can be achieved using an impedance matching network with an impedance matched to a specific frequency. Therefore, for one MMMB PAM without an adjustable impedance circuit, several Duch PAMs (each of which requires two amplifiers) can be used to cover several frequency bands, which can make the implementation expensive and / or impractical .
圖1展示一功率放大器(PA)100之一例示性架構,其中可實施具有如在本文中描述之一或多個特徵之一杜赫組合器。所展示之架構係一杜赫PA架構。儘管在此一杜赫PA架構之內容脈絡中描述各種實例,但將理解,亦可在其他類型之PA系統中實施本發明之一或多個特徵。 FIG. 1 shows an exemplary architecture of a power amplifier (PA) 100 in which a Duch combiner having one or more features as described herein can be implemented. The architecture shown is a Duch PA architecture. Although various examples are described in the context of this Doherty PA architecture, it will be understood that one or more features of the present invention may also be implemented in other types of PA systems.
例示性PA 100經展示包含用於接收待放大之一RF信號之一輸入埠(RF_IN)。可在被分割為一載波放大路徑110及一峰值放大路徑130之前,藉由一預驅動器放大器102來部分放大此一輸入RF信號。可藉由一除法器104來達成此一分割。 The exemplary PA 100 is shown to include an input port (RF_IN) for receiving an RF signal to be amplified. The input RF signal may be partially amplified by a pre-driver amplifier 102 before being divided into a carrier amplification path 110 and a peak amplification path 130. This division can be achieved by a divider 104.
在圖1中,載波放大路徑110經展示包含一衰減器112及共同指示為114之放大級。放大級114經展示包含一驅動器級116及一輸出級120。驅動器級116經展示以一偏壓電路118加偏壓,且輸出級120經展示以一偏壓電路122加偏壓。在一些實施例中,可存在更多或更少放大級。在本文中描述之各種實例中,放大級114有時經描述為一放大器;然而,將理解,此一放大器可包含一或多個級。 In FIG. 1, the carrier amplification path 110 is shown to include an attenuator 112 and an amplification stage collectively designated 114. The amplifier stage 114 is shown to include a driver stage 116 and an output stage 120. The driver stage 116 is shown biased with a bias circuit 118 and the output stage 120 is shown biased with a bias circuit 122. In some embodiments, there may be more or fewer amplification stages. In the various examples described herein, the amplification stage 114 is sometimes described as an amplifier; however, it will be understood that such an amplifier may include one or more stages.
在圖1中,峰值放大路徑130經展示包含相移電路132及共同指示為134之放大級。放大級134經展示包含一驅動器級136及一輸出級140。驅動器級136經展示以一偏壓電路138加偏壓,且輸出級140經展示以一偏壓電路142加偏壓。在一些實施例中,可存在更多或更少放大級。在本文中描述之各種實例中,放大級134有時經描述為一放大 器;然而,將理解,此一放大器可包含一或多個級。 In FIG. 1, the peak amplification path 130 is shown to include a phase shift circuit 132 and an amplification stage collectively designated as 134. The amplifier stage 134 is shown to include a driver stage 136 and an output stage 140. The driver stage 136 is shown biased with a bias circuit 138, and the output stage 140 is shown biased with a bias circuit 142. In some embodiments, there may be more or fewer amplification stages. In the various examples described herein, the amplification stage 134 is sometimes described as an amplification However, it will be understood that such an amplifier may include one or more stages.
圖1進一步展示載波放大路徑110及峰值放大路徑130可藉由一組合器144來組合,從而在一輸出埠(RF_OUT)處產生一經放大RF信號。在本文中,更詳細描述關於組合器144之實例。舉例而言,組合器144可經實施為圖3、圖4、圖5或圖7之組合器中之一者。 FIG. 1 further shows that the carrier amplification path 110 and the peak amplification path 130 can be combined by a combiner 144 to generate an amplified RF signal at an output port (RF_OUT). In this document, examples regarding the combiner 144 are described in more detail. For example, the combiner 144 may be implemented as one of the combiners of FIG. 3, FIG. 4, FIG. 5, or FIG. 7.
圖2A及圖2B展示可被用作一杜赫組合器之一混合電路之一實例。此一混合電路可經組態以尤其適用於諸如RFIC(射頻積體電路)、MMIC(單片微波積體電路)及其他RF模組之應用。圖2A展示此一混合電路之一示意性表示,且圖2B展示混合電路之一例示性佈局。 2A and 2B show an example of a hybrid circuit that can be used as a Dohert combiner. This hybrid circuit can be configured to be particularly suitable for applications such as RFIC (radio frequency integrated circuit), MMIC (monolithic microwave integrated circuit) and other RF modules. FIG. 2A shows a schematic representation of such a hybrid circuit, and FIG. 2B shows an exemplary layout of the hybrid circuit.
圖2A及圖2B之混合電路可經實施為基於平衡-不平衡變壓器之一半集總90度混合物。歸因於所使用平衡-不平衡變壓器之緊湊性質,可在諸如矽、GaAs及IPD(積體被動裝置)基板(例如,玻璃或矽)之絕緣/半絕緣基板上容易地實施此一設計。 The hybrid circuit of FIGS. 2A and 2B may be implemented as a half-lumped 90-degree mixture based on a balun transformer. Due to the compact nature of the balun used, this design can be easily implemented on insulating / semi-insulating substrates such as silicon, GaAs, and IPD (Integrated Passive Device) substrates (eg, glass or silicon).
因此,在圖2A中,一信號組合器244經展示包含一第一埠231、一第二埠232、一第三埠233及第四埠234。一第一電容器222耦合第一埠231與第二埠232。一第二電容器223耦合第三埠233與第四埠234。信號組合器244亦包含具有分別耦合至信號組合器244之四個埠231至234之四個埠之一變壓器221。在圖2B中,一實質上類似信號組合器254經圖解說明以包含具有一第一線圈及一第二線圈之一平衡-不平衡變壓器251。 Therefore, in FIG. 2A, a signal combiner 244 is shown to include a first port 231, a second port 232, a third port 233, and a fourth port 234. A first capacitor 222 is coupled to the first port 231 and the second port 232. A second capacitor 223 is coupled to the third port 233 and the fourth port 234. The signal combiner 244 also includes a transformer 221 having four ports coupled to the four ports 231 to 234 of the signal combiner 244, respectively. In FIG. 2B, a substantially similar signal combiner 254 is illustrated to include a balanced-unbalanced transformer 251 having a first coil and a second coil.
在圖2A及圖2B之實例中,可在隔離埠(例如,第三埠231)處提供一特定終端以達成杜赫作用。在本文中更詳細描述終端之實例。 In the example of FIG. 2A and FIG. 2B, a specific terminal may be provided at the isolated port (for example, the third port 231) to achieve the Duch effect. Examples of terminals are described in more detail herein.
在一些實施例中,可展示此一特定終端可經實施為一電容(例如,電容器),其之電抗在量值上等於系統之特性阻抗。因此,此一電容可經表達為C=1/(2πfZ0),其中f係杜赫PA之操作頻率且Z0係耦合 至杜赫PA之一負載之一特性阻抗。 In some embodiments, it can be shown that this particular terminal can be implemented as a capacitor (eg, a capacitor) whose reactance is equal in magnitude to the characteristic impedance of the system. Therefore, this capacitor can be expressed as C = 1 / (2πfZ 0 ), where f is the operating frequency of the Douhe PA and Z 0 is a characteristic impedance coupled to a load of the Douhe PA.
圖3展示在一些實施例中,一信號組合器300包含具有一電容器323之一終端電路。信號組合器300包含:一第一輸入埠331,其可經組態以接收一杜赫PA之一載波放大信號;一第二輸入埠332,其可經組態以接收一杜赫PA之一峰值放大信號;及一輸出埠333,其輸出在第一輸入埠331及第二輸入埠432處接收之信號之一組合。信號組合器300包含具有一第一線圈301及一第二線圈302之一變壓器(例如,一平衡-不平衡變壓器),在一第一埠311與一第二埠312之間實施第一線圈301,在一第三埠313與一第四埠314之間實施第二線圈302。藉由一第一電容器321耦合第一埠311與第三埠313且藉由一第二電容器322耦合第二埠312與第四埠314。第三埠313經由一終端電路耦合至接地,終端電路在圖3中包含一第三電容器323。在一些實施方案中,第一電容器321及第二電容器322之電容相等。在一些實施方案中,第三電容器323之電容係第一電容器321及/或第二電容器322之電容之兩倍。 FIG. 3 shows that in some embodiments, a signal combiner 300 includes a termination circuit having a capacitor 323. The signal combiner 300 includes: a first input port 331 that can be configured to receive a carrier amplified signal of a Douhe PA; a second input port 332 that can be configured to receive one of a Douhe PA A peak amplified signal; and an output port 333 that outputs a combination of signals received at the first input port 331 and the second input port 432. The signal combiner 300 includes a transformer (for example, a balanced-unbalanced transformer) having a first coil 301 and a second coil 302. The first coil 301 is implemented between a first port 311 and a second port 312. A second coil 302 is implemented between a third port 313 and a fourth port 314. The first port 311 and the third port 313 are coupled by a first capacitor 321 and the second port 312 and the fourth port 314 are coupled by a second capacitor 322. The third port 313 is coupled to the ground through a termination circuit. The termination circuit includes a third capacitor 323 in FIG. 3. In some embodiments, the capacitances of the first capacitor 321 and the second capacitor 322 are equal. In some embodiments, the capacitance of the third capacitor 323 is twice the capacitance of the first capacitor 321 and / or the second capacitor 322.
在一些實施方案中,第三電容器323之電容約等於二乘以π乘以杜赫PA之一操作頻率乘以耦合至杜赫PA之一負載之一特性阻抗之一倒數(例如,C=1/(2πfZ0),其中f係杜赫PA之操作頻率且Z0係耦合至杜赫PA之一負載之一特性阻抗。 In some embodiments, the capacitance of the third capacitor 323 is approximately equal to two times π times one of the operating frequency of the Douhe PA times one of the inverse of a characteristic impedance of a load coupled to the Douhe PA (eg, C = 1 / (2πfZ 0 ), where f is the operating frequency of Duch PA and Z 0 is a characteristic impedance coupled to a load of Duch PA.
可展示,具有L=Z0/(2πf)之一電感終端之一替代組態可以一類似方式提供杜赫組合器功能性。在此情況中可互換載波及峰值放大器之埠位置。 It can be shown that an alternative configuration with an inductance terminal of L = Z 0 / (2πf) can provide the Duch combiner functionality in a similar way. In this case, the port positions of the carrier and the peak amplifier are interchangeable.
圖4展示在一些實施例中,一信號組合器400包含具有一電感器423之一終端電路。圖4之信號組合器400包含:一第一輸入埠431,其可經組態以接收一杜赫PA之一載波放大信號;一第二輸入埠432,其可經組態以接收一杜赫PA之一峰值放大信號;及一輸出埠433,其輸出在第一輸入埠431及第二輸入埠432處接收之信號之一組合。信號組 合器400包含具有一第一線圈401及一第二線圈402之一變壓器(例如,一平衡-不平衡變壓器),在一第一埠411與一第二埠412之間實施第一線圈401,在一第三埠413與一第四埠414之間實施第二線圈402。藉由一第一電容器421耦合第一埠411與第三埠413且藉由一第二電容器422耦合第二埠412與第四埠414。第三埠413經由一終端電路耦合至接地,終端電路在圖4中包含一電感器423。 FIG. 4 shows that in some embodiments, a signal combiner 400 includes a termination circuit having an inductor 423. The signal combiner 400 of FIG. 4 includes: a first input port 431 which can be configured to receive a carrier amplified signal of a Douhe PA; a second input port 432 which can be configured to receive a Douhe A peak amplified signal of PA; and an output port 433 that outputs a combination of signals received at the first input port 431 and the second input port 432. Signal group The coupler 400 includes a transformer (for example, a balanced-unbalanced transformer) having a first coil 401 and a second coil 402. A first coil 401 is implemented between a first port 411 and a second port 412. A second coil 402 is implemented between a third port 413 and a fourth port 414. The first port 411 and the third port 413 are coupled by a first capacitor 421 and the second port 412 and the fourth port 414 are coupled by a second capacitor 422. The third port 413 is coupled to the ground through a termination circuit. The termination circuit includes an inductor 423 in FIG. 4.
在一些實施方案中,電感器423之電感約等於耦合至杜赫PA之一負載之一特性阻抗除以二乘以π乘以杜赫PA之一操作頻率(例如,二乘以π乘以杜赫PA之一操作頻率乘以耦合至杜赫PA之一負載之一特性阻抗之一倒數)(例如,L=Z0/(2πf),其中f係杜赫PA之操作頻率且Z0係耦合至杜赫PA之一負載之一特性阻抗。 In some embodiments, the inductance of the inductor 423 is approximately equal to a characteristic impedance of a load coupled to the Douhe PA divided by two times π times one of the Douhe PA operating frequencies (e.g., two times π times Double PA) One operating frequency of the Hertz PA is multiplied by one of the inverse of one of the characteristic impedances coupled to one of the loads of the Doherty PA) (for example, L = Z 0 / (2πf), where f is the operating frequency of the Doherty PA and Z 0 is coupled One of the characteristic impedances of a load to Duch PA.
可針對作為一多模式/多頻帶(MMMB)功率放大器模組(PAM)之部分之多個模式或多個操作頻率使用一信號組合器。因此,在一些實施方案中,不同於一單一電容器或單一電感器(如在圖3及圖4中展示),一可調阻抗電路可經使用且調諧至用於各種頻率及/或組態之各種阻抗。 A signal combiner can be used for multiple modes or multiple operating frequencies as part of a multi-mode / multi-band (MMMB) power amplifier module (PAM). Therefore, in some implementations, unlike a single capacitor or a single inductor (as shown in Figures 3 and 4), an adjustable impedance circuit can be used and tuned to various frequencies and / or configurations Various impedances.
圖5展示在一些實施例中,一信號組合器500包含具有一可調阻抗電路523之一終端電路。圖5之信號組合器500包含:一第一輸入埠531,其可經組態以接收一杜赫PA之一載波放大信號(或在一替代實施方案中,一杜赫PA之一峰值放大信號);一第二輸入埠532,其可經組態以接收一杜赫PA之一峰值放大信號(或在替代實施方案中,一杜赫PA之載波放大信號);及一輸出埠533,其輸出在第一輸入埠531及第二輸入埠532處接收之信號之一組合。信號組合器500包含具有一第一線圈501及一第二線圈502之一變壓器(例如,一平衡-不平衡變壓器),在一第一埠511與一第二埠512之間實施第一線圈501,在一第三埠513與一第四埠514之間實施第二線圈502。藉由一第一電容器521耦合第 一埠511與第三埠513且藉由一第二電容器522耦合第二埠512與第四埠514。第三埠513經由一終端電路耦合至接地,終端電路在圖5中包含一可調阻抗電路523。 FIG. 5 shows that in some embodiments, a signal combiner 500 includes a termination circuit having an adjustable impedance circuit 523. The signal combiner 500 of FIG. 5 includes: a first input port 531 that can be configured to receive a carrier amplified signal of a Doherty PA (or in an alternative embodiment, a peak amplified signal of a Doherty PA) ); A second input port 532, which can be configured to receive a peak amplified signal of a Douhe PA (or in an alternative embodiment, a carrier amplified signal of a Douhe PA); and an output port 533, which A combination of signals received at the first input port 531 and the second input port 532 is output. The signal combiner 500 includes a transformer (for example, a balanced-unbalanced transformer) having a first coil 501 and a second coil 502. The first coil 501 is implemented between a first port 511 and a second port 512. A second coil 502 is implemented between a third port 513 and a fourth port 514. The first capacitor 521 is coupled to the first capacitor A port 511 and a third port 513 are coupled to the second port 512 and the fourth port 514 through a second capacitor 522. The third port 513 is coupled to the ground through a termination circuit. The termination circuit includes an adjustable impedance circuit 523 in FIG. 5.
信號組合器500被一控制器520控制,控制器520經組態以接收指示系統(信號組合器500係其之部分)之一當前操作頻率之一頻帶選擇信號。控制器520經進一步組態以基於頻帶選擇信號調諧可調阻抗電路523。在一些實施方案中,控制器520經進一步組態以調諧第一電容器521或第二電容器522之至少一者。 The signal combiner 500 is controlled by a controller 520 configured to receive a band selection signal indicating a current operating frequency of one of the indication systems (of which the signal combiner 500 is a part). The controller 520 is further configured to tune the adjustable impedance circuit 523 based on the band selection signal. In some implementations, the controller 520 is further configured to tune at least one of the first capacitor 521 or the second capacitor 522.
在一些實施方案中,第一埠511經組態以自一杜赫PA接收一載波放大信號(例如,經由第一輸入埠531),且第四埠514經組態以自杜赫PA接收一峰值放大信號(例如,經由第二輸入埠532)。因此,控制器520可經組態以調諧可調阻抗電路523,以具有約等於二乘以π乘以操作頻率(如藉由頻帶選擇信號所指示)乘以經耦合至杜赫PA之一負載之一特性阻抗之一倒數之一電容。控制器520可進一步調諧第一電容器521及/或第二電容器522,以具有約等於可調阻抗電路523之電容之一半之一電容。 In some implementations, the first port 511 is configured to receive a carrier amplification signal from a Douhe PA (eg, via the first input port 531), and the fourth port 514 is configured to receive a carrier signal from the Douhe PA. The peak amplified signal (eg, via the second input port 532). Therefore, the controller 520 can be configured to tune the adjustable impedance circuit 523 to have a load approximately equal to two times π times the operating frequency (as indicated by the band selection signal) multiplied by one of the loads coupled to the Duch PA. One of the characteristic impedances is one of the penultimate capacitors. The controller 520 may further tune the first capacitor 521 and / or the second capacitor 522 to have a capacitance approximately equal to one and a half of the capacitance of the adjustable impedance circuit 523.
在一些實施方案中,第一埠511經組態以自一杜赫PA接收一峰值放大信號(例如,經由第一輸入埠531),且第四埠514經組態以自杜赫PA接收一載波放大信號(例如,經由第二輸入埠532)。因此,控制器520可經組態以調諧可調阻抗電路523以具有約等於經耦合至杜赫PA之一負載之一特性阻抗除以二乘以π乘以操作頻率(如藉由頻帶選擇信號所指示)之一電感。 In some embodiments, the first port 511 is configured to receive a peak amplified signal from a Doherty PA (eg, via the first input port 531), and the fourth port 514 is configured to receive a peaked signal from the Doherty PA. The carrier amplifies the signal (for example, via the second input port 532). Therefore, the controller 520 can be configured to tune the adjustable impedance circuit 523 to have a characteristic impedance approximately equal to one of the loads coupled to the Douhe PA divided by two times π times the operating frequency (e.g., by a band selection signal (Indicated)).
圖6展示在一些實施例中,一可調阻抗電路623可包含經並聯連接之複數個阻抗元件。經並聯連接之阻抗元件之各者包含經串聯連接之一阻抗610a至610d及一開關612a至612d。阻抗610a至610d可包含一或多個電阻器、電容器及/或電感器。開關612a至612d可被一控制器 (例如,圖5之控制器520)控制為一打開狀態或一關閉狀態,以調諧可調阻抗電路623以具有一特定阻抗。 FIG. 6 shows that in some embodiments, an adjustable impedance circuit 623 may include a plurality of impedance elements connected in parallel. Each of the impedance elements connected in parallel includes an impedance 610a to 610d and a switch 612a to 612d connected in series. The impedances 610a to 610d may include one or more resistors, capacitors, and / or inductors. Switches 612a to 612d can be controlled by a controller (For example, the controller 520 of FIG. 5) is controlled to be an open state or a closed state to tune the adjustable impedance circuit 623 to have a specific impedance.
在一些實施方案中,可調阻抗電路623係包含經組態以在一或多個操作頻率下操作之一杜赫PA之一系統的部分。因此,阻抗610a至610d可包含複數個電容器,複數個電容器之各者具有約等於二乘以π乘以一杜赫PA之一各自操作頻率乘以經耦合至杜赫PA之一負載之一特性阻抗之一倒數之一電容。阻抗610a至610d可替代性地(或另外)包含複數個電感器,複數個電感器之各者具有約等於經耦合至杜赫PA之一負載之一特性阻抗除以二乘以π乘以杜赫PA之一各自操作頻率之一電感。 In some implementations, the adjustable impedance circuit 623 is a portion of a system configured to operate one of the Douch PAs at one or more operating frequencies. Therefore, the impedances 610a to 610d may include a plurality of capacitors, each of the plurality of capacitors having a characteristic that is approximately equal to one of two times π times one of a Douhe PA and an operating frequency of one of the loads coupled to the Douhe PA One of the reciprocals of the impedance. The impedances 610a to 610d may alternatively (or additionally) include a plurality of inductors, each of the plurality of inductors having a characteristic impedance approximately equal to one of the loads coupled to one of the Duch PAs divided by two times pi times du One of the Hertz PAs operates at one frequency and one of the inductors.
圖7展示在一些實施例中,一信號組合器700包含具有一諧波抑制電路724之一終端電路。圖7之信號組合器700實質上類似於圖5之信號組合器500,除了圖7之信號組合器700包含在第三埠513與可調阻抗電路523之間實施之一諧波抑制電路724以外。 FIG. 7 shows that in some embodiments, a signal combiner 700 includes a termination circuit having a harmonic suppression circuit 724. The signal combiner 700 of FIG. 7 is substantially similar to the signal combiner 500 of FIG. 5, except that the signal combiner 700 of FIG. 7 includes a harmonic suppression circuit 724 implemented between the third port 513 and the adjustable impedance circuit 523. .
諧波抑制電路724經組態以減小第二埠512(及因此輸出埠533)處之一或多個諧波的強度。當第一輸入埠531經組態以接收一載波放大信號且第二輸入埠532經組態以接收一峰值放大信號時,載波放大信號及峰值放大信號可包含經放大之RF信號的非所要諧波。諧波抑制電路724經組態以減小輸出埠533處之此等諧波的強度。 The harmonic suppression circuit 724 is configured to reduce the intensity of one or more harmonics at the second port 512 (and therefore the output port 533). When the first input port 531 is configured to receive a carrier amplified signal and the second input port 532 is configured to receive a peak amplified signal, the carrier amplified signal and the peak amplified signal may include undesired harmonics of the amplified RF signal. wave. The harmonic suppression circuit 724 is configured to reduce the intensity of these harmonics at the output port 533.
圖8展示在一些實施方案中,一諧波抑制電路823可包含經串聯連接之複數個諧振元件。諧振元件之各者包含經並聯連接之一電感器812a至812d及一電容器810a至810d。複數個諧振元件之各者可具有約等於系統(諧波抑制電路823係其之一部分)之一操作頻率(一組操作頻率之一者)之一倍數之一諧振頻率。舉例而言,在一些實施方案中,複數個諧振元件之各者具有約等於信號組合器之一各自操作頻率之兩倍之一諧振頻率。因此,若包含諧波抑制電路823之系統經組態以在 一第一頻率、第二頻率及第三頻率中之一或多者下操作,則諧振元件可具有第一頻率之兩倍、第二頻率之兩倍及第三頻率之兩倍之各自諧振頻率。 FIG. 8 shows that in some embodiments, a harmonic suppression circuit 823 may include a plurality of resonant elements connected in series. Each of the resonance elements includes an inductor 812a to 812d and a capacitor 810a to 810d connected in parallel. Each of the plurality of resonance elements may have a resonance frequency approximately equal to a multiple of an operating frequency (one of a group of operating frequencies) of the system (a part of the harmonic suppression circuit 823). For example, in some implementations, each of the plurality of resonant elements has a resonant frequency approximately equal to twice the respective operating frequency of one of the signal combiners. Therefore, if the system containing the harmonic suppression circuit 823 is configured to When one or more of a first frequency, a second frequency, and a third frequency are operated, the resonant element may have respective resonant frequencies that are twice the first frequency, twice the second frequency, and twice the third frequency. .
圖9展示在一些實施例中,可在一模組中完整或部分實施一些或所有組態(例如,在圖1、圖2A、圖2B及圖3至圖8中展示之組態)。此一模組可為(例如)一前端模組(FEM)。在圖9之實例中,一模組900可包含一封裝基板902,且數個組件可被安裝於此一封裝基板902上。舉例而言,可在封裝基板902上及/或內安裝及/或實施一FE-PMIC組件904、一功率放大器總成906(其可包含具有一可調阻抗電路之一組合器907)、一匹配組件908及一多工器總成910。諸如數個SMT裝置914及一天線開關模組(ASM)912之其他組件亦可被安裝於封裝基板902上。儘管所有各種組件經描繪為佈局於封裝基板902上,但將理解,可在其他組件上方實施一些組件。 FIG. 9 shows that in some embodiments, some or all configurations may be implemented in whole or in part in a module (eg, the configurations shown in FIGS. 1, 2A, 2B, and 3 to 8). This module may be, for example, a front-end module (FEM). In the example of FIG. 9, a module 900 may include a package substrate 902, and several components may be mounted on the package substrate 902. For example, a FE-PMIC component 904, a power amplifier assembly 906 (which may include a combiner 907 with an adjustable impedance circuit), and / or may be installed and / or implemented on and / or within the package substrate 902, a The matching component 908 and a multiplexer assembly 910. Other components such as several SMT devices 914 and an antenna switch module (ASM) 912 can also be mounted on the package substrate 902. Although all the various components are depicted as being laid out on a package substrate 902, it will be understood that some components may be implemented over other components.
在一些實施方案中,具有在本文中描述之一或多個特徵之一裝置及/或一電路可包含於諸如一無線裝置之一RF電子裝置中。可在無線裝置中以如在本文中描述之一模組化形式或其之某組合直接實施此一裝置及/或一電路。在一些實施例中,此一無線裝置可包含(例如)一蜂巢式電話、一智慧型電話、具有或不具有電話功能性之一手持式無線裝置、一無線平板電腦等等。 In some embodiments, a device and / or a circuit having one or more of the features described herein may be included in an RF electronic device such as a wireless device. Such a device and / or a circuit may be implemented directly in a wireless device in a modular form or some combination thereof as described herein. In some embodiments, the wireless device may include, for example, a cellular phone, a smart phone, a handheld wireless device with or without phone functionality, a wireless tablet, and the like.
圖10描繪具有在本文中描述之一或多個有利特徵之一例示性無線裝置1000。在具有如在本文中描述之一或多個特徵之一模組之內容脈絡中,大體上可藉由一虛線盒900描繪此一模組,且模組可經實施為(例如)一前端模組(FEM)。 FIG. 10 depicts an exemplary wireless device 1000 having one or more advantageous features described herein. In the context of a module having one or more features as described herein, such a module can generally be depicted by a dashed box 900, and the module can be implemented, for example, as a front-end module Group (FEM).
參考圖10,功率放大器(PA)100a至100d可自一收發器1010接收其等各自RF信號,收發器1010按已知方式組態及操作以產生待放大及發送之RF信號且處理所接收信號。收發器1010經展示與一基帶子 系統1008互動,基帶子系統1008經組態以提供適用於一使用者之資料及/或語音信號與適用於收發器1010之RF信號之間的轉換。收發器1010亦可與一功率管理組件1006通信,功率管理組件1006經組態以管理用於無線裝置1000之操作之功率。此功率管理亦可控制基帶子系統1008及模組900之操作。 10, power amplifiers (PA) 100a to 100d may receive their respective RF signals from a transceiver 1010, which is configured and operated in a known manner to generate RF signals to be amplified and transmitted and process the received signals . Transceiver 1010 is shown with a baseband System 1008 interacts, and baseband subsystem 1008 is configured to provide conversion between data and / or voice signals suitable for a user and RF signals suitable for transceiver 1010. The transceiver 1010 may also communicate with a power management component 1006, which is configured to manage power for operation of the wireless device 1000. This power management can also control the operation of the baseband subsystem 1008 and the module 900.
基帶子系統1008經展示連接至一使用者介面1002以促進提供至使用者及從使用者接收之語音及/或資料之各種輸入及輸出。基帶子系統1008亦可連接至一記憶體1004,記憶體1004經組態以儲存資料及/或指令以促進無線裝置之操作及/或提供用於使用者之資訊之儲存。 The baseband subsystem 1008 is shown connected to a user interface 1002 to facilitate various inputs and outputs of voice and / or data provided to and received from the user. The baseband subsystem 1008 may also be connected to a memory 1004, which is configured to store data and / or instructions to facilitate the operation of the wireless device and / or provide storage of information for the user.
在例示性無線裝置1000中,PA 100a至100d之輸出經展示匹配(經由各自匹配電路1020a至1020d)及路由至其等各自雙工器1012a至1012d。此等經放大且濾波之信號可透過一天線開關1014路由至一天線1016(或多個天線)以用於發送。在一些實施例中,雙工器1012a至1012d可允許使用一共同天線(例如,1016)同時實行發送及接收操作。在圖10中,所接收信號經展示路由至「Rx」路徑(未展示),「Rx」路徑可包含(例如)一低雜訊放大器(LNA)。 In the exemplary wireless device 1000, the outputs of the PAs 100a to 100d are shown matched (via respective matching circuits 1020a to 1020d) and routed to their respective duplexers 1012a to 1012d. These amplified and filtered signals can be routed through an antenna switch 1014 to an antenna 1016 (or multiple antennas) for transmission. In some embodiments, the duplexers 1012a to 1012d may allow a common antenna (eg, 1016) to perform transmission and reception operations simultaneously. In FIG. 10, the received signal is routed to the "Rx" path (not shown). The "Rx" path may include, for example, a low noise amplifier (LNA).
數個其他無線裝置組態可利用在本文中描述之一或多個特徵。舉例而言,一無線裝置並不需為一多頻帶裝置。在另一實例中,一無線裝置可包含額外天線(諸如分集式天線)及額外連接性特徵(諸如Wi-Fi、藍芽及GPS)。 Several other wireless device configurations may utilize one or more of the features described herein. For example, a wireless device need not be a multi-band device. In another example, a wireless device may include additional antennas (such as diversity antennas) and additional connectivity features (such as Wi-Fi, Bluetooth, and GPS).
除非內容脈絡另外明確要求,否則貫穿描述及申請專利範圍,字詞「包括(comprise)」、「包括(comprising)」及類似物應被解釋為一包含性含義,而非一排他性或窮盡性含義;即,「包含但不限於」之涵義。如在本文中通常使用之字詞「耦合」係指可直接連接或藉由一或多個中間元件連接之兩個或兩個以上元件。另外,當在此申請案中使用字詞「本文中」、「上文」、「下文」及類似輸入字詞時,應係指此 申請案之一整體而非此申請案之任何特定部分。在內容脈絡允許之處,上文描述中之使用單數或複數之字詞亦可分別包含複數或單數。參考兩個或兩個以上項目之一清單之字詞「或」涵蓋字詞之所有下列解釋:清單中之任何項目、清單中之所有項目及清單中之項目之任何組合。 Unless the context clearly requires otherwise, the words "comprise", "comprising", and the like shall be interpreted as an inclusive meaning, rather than an exclusive or exhaustive meaning, throughout the description and patent application. ; That is, the meaning of "including but not limited to." The term "coupled" as commonly used herein refers to two or more elements that can be directly connected or connected through one or more intermediate elements. In addition, when the words "in this text", "above", "below" and similar input words are used in this application, they shall mean this One of the applications as a whole rather than any specific part of the application. Where the context permits, words using the singular or plural number in the above description may also include the plural or singular number respectively. Reference to the word "or" in a list of two or more items covers all of the following interpretations of the word: any item in the list, all items in the list, and any combination of items in the list.
本發明之實施例之上文實施方式不旨在係窮盡性或將本發明限於上文揭示之精確形式。如熟習相關技術者將認識到,雖然僅出於闡釋性目的在上文描述本發明之特定實施例及實例,但各種等效修改可處於本發明之範疇內。舉例而言,雖然按一給定順序呈現程序或區塊,但替代實施例可按一不同順序實行具有步驟之常式或採用具有區塊之系統,且可刪除、移動、添加、細分、組合及/或修改一些程序或區塊。可以各種不同方式實施此等程序或區塊之各者。而且,雖然程序或區塊有時經展示為依序實行,但此等程序或區塊可替代性地並行實行或可在不同時間實行。 The above implementations of the embodiments of the invention are not intended to be exhaustive or to limit the invention to the precise forms disclosed above. As those skilled in the relevant art will appreciate, although specific embodiments and examples of the invention are described above for illustrative purposes only, various equivalent modifications may be within the scope of the invention. For example, although programs or blocks are presented in a given order, alternative embodiments may implement a routine with steps or a system with blocks in a different order, and may delete, move, add, subdivide, combine And / or modify some programs or blocks. Each of these programs or blocks can be implemented in a variety of different ways. Moreover, although programs or blocks are sometimes shown as being performed sequentially, such programs or blocks may alternatively be performed in parallel or at different times.
在本文中提供之本發明之教示可應用至其他系統(不必係上文描述之系統)。在上文描述之各種實施例之元件及動作可經組合以提供進一步實施例。 The teachings of the invention provided herein can be applied to other systems (it need not be the systems described above). The elements and actions of the various embodiments described above may be combined to provide further embodiments.
雖然已描述本發明之一些實施例,但僅藉由實例呈現此等實施例,且不旨在限制本發明之範疇。確實,在本文中描述之新穎方法及系統可體現為各種其他形式;此外,可在不脫離本發明之精神之情況下在本文中描述之方法及系統之形式中作出各種省略、替換及改變。隨附申請專利範圍及其等之等效物旨在涵蓋將屬於本發明之範疇及精神之此等形式或修改。 Although some embodiments of the invention have been described, these embodiments are presented by way of example only and are not intended to limit the scope of the invention. Indeed, the novel methods and systems described herein may be embodied in various other forms; moreover, various omissions, substitutions, and changes may be made in the forms of the methods and systems described herein without departing from the spirit of the invention. The scope of the accompanying patent application and equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the invention.
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US10355647B2 (en) | 2019-07-16 |
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HK1216462A1 (en) | 2016-11-11 |
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