TWI653821B - Circular super low voltage-controlled oscillator for chip circuit - Google Patents

Abstract

The invention relates to an ultra-low voltage annular voltage controlled oscillator for a chip circuit, which comprises a two-stage delay unit, wherein the oscillator comprises two delay units connected end to end, and adjusts the delay time of the delay unit by adjusting the delay unit. frequency. The two-stage annular voltage controlled oscillator of the invention adopts a substrate feedforward bias structure to reduce the threshold voltage of the transistor, reduce the power supply voltage, reduce power consumption, and has a large tuning range, and is particularly suitable for low power supply voltage operation. system.

Description

Ultra low voltage ring voltage controlled oscillator for chip circuit

The invention relates to the field of oscillators, and more particularly to an ultra-low voltage two-stage annular voltage controlled oscillator.

The voltage controlled oscillator is an important component of the analog circuit and the digital circuit. There are many different implementations of voltage controlled oscillators. The ring oscillator occupies a smaller wafer area and has a larger adjustment range than a conventional LC oscillator. If the ring oscillator consists of two stages of delay, it can operate at high frequencies and provide quadrature output.

In modern CMOS processes, the technical feature size and supply voltage need to be scaled down to maintain device stability. For a ring oscillator, it is difficult to operate normally at a supply voltage of 0.5V due to the high threshold voltage of the transistor. The substrate connection forward biasing of MOS transistors is an effective way to reduce the threshold voltage of the transistor. In design, substrate forward biasing techniques are applied to delay cells with local positive feedback.

Therefore, the prior art needs to be greatly improved.

The technical problem to be solved by the present invention is to provide an ultra-low voltage toroidal voltage-controlled oscillator for the above-mentioned defects of the prior art, comprising: a two-stage delay unit, wherein the oscillator adjusts the operating frequency by adjusting the delay time of the delay unit; The unit includes PMOS transistors M1, M2, M3, M4, NMOS transistors M5, M6, M7, M8, and a load capacitance C _L .

In the ultra-low voltage toroidal voltage controlled oscillator according to the present invention, the substrates of the PMOS transistors M2 and M4 are grounded, the substrates of the PMOS transistors M1 and M3 are connected to the control voltage Vc, and the gates of the PMOS transistors M1 and M3 are grounded. The PMOS transistors M1 and M3 are connected to the VDD, the PMOS transistors M1 and M3 are connected to the gates and drains of the PMOS transistors M2 and M4, and the NMOS transistor M5 and the NMOS transistor M6 are used as the positive phases of the delay unit, respectively. And the inverting differential input terminal, the source and the drain of the NMOS transistor M7 and the NMOS transistor M8 are respectively connected to the source and the drain of the NMOS transistor M5 and the NMOS transistor M6, and the gate of the NMOS transistor M7 is connected to the drain of the NMOS transistor M6. The gate of the NMOS transistor M8 is connected to the drain of the NMOS transistor M5; the drain of the NMOS transistor M5 is used as an inverting output terminal, the drain of the NMOS transistor M6 is used as a positive phase output terminal, and the output terminal is connected to the load capacitor C. _L ; the substrate end of the NMOS transistor is connected to the bias voltage V _B .

The ultra low voltage annular voltage controlled oscillator embodying the invention has the following beneficial effects: adopting a substrate forward bias structure, reducing the threshold voltage of the transistor, reducing the power supply voltage, and reducing power consumption; the two-stage structure, the circuit structure is simple, and the area Smaller, easier to implement and integrate; the two-stage ring oscillator circuit has a large tuning range compared to the LC oscillator structure.

FIG schematic 1MOS transistor threshold voltage with the substrate supply voltage V _c; Figure 2A is a schematic extra low voltage VCO ring structure; FIG. 2B is a schematic configuration of a unit delay ultra-low pressure loop voltage controlled oscillator; FIG. 3 is a pressure and Schematic diagram of controlling the frequency change of the oscillator.

In order to further clarify and understand the structure, the use and the features of the present invention, the preferred embodiment is described in detail with reference to the following drawings:

Please refer to FIG. 1 , which is a graph of the threshold voltage of the MOS transistor as a function of the substrate voltage V _c . The substrate forward bias technique can effectively reduce the threshold voltage of the MOS transistor.

Taking the 0.18um RF CMOS process as an example, the threshold voltages of NMOS and PMOS transistors are about +/- 0.5V. When the supply voltage is 0.5V, this threshold voltage will greatly limit the performance of the circuit. The threshold voltage can be lowered by the substrate of the forward bias MOS transistor. In the 0.18um RF CMOS process, the sensitive analog circuit is isolated from the substrate noise by using a deep N-well, so both the NMOS transistor and the PMOS transistor connected to the substrate can be forward biased through the substrate. Threshold voltage.

The substrate forward biased PMOS transistor threshold voltage (V _thp ) can be expressed as:

|V _thp0 | is |V _thp | when the source lining voltage (V _sb ) is 0, γ is the body effect coefficient, and | φ _f | is the Fermi potential. Therefore, the threshold voltage |Vt _h | decreases as V _sb increases, and the PMOS transistor threshold voltage varies with the substrate bias voltage as shown in FIG. 1 . As can be seen from FIG. 1, when the substrate bias voltage of the PMOS transistor changes from 500 mV to 0 V, the threshold voltage of the PMOS transistor changes from -500 mV to -366 mV. When the NMOS transistor substrate bias supply voltage V _c changes from 0V to 0.5V, the threshold voltage of the NMOS transistor (V _thn) changes from 531mV to 423mV. This is very effective for MOS transistors operating at ultra-low supply voltages.

Referring to Figure 2A, the ultra-low voltage toroidal voltage controlled oscillator structure consists of two identical delay units. The delay unit is shown in Figure 2B. The substrates of the PMOS transistors M2 and M4 are grounded, the substrates of the PMOS transistors M1 and M3 are connected to the control voltage Vc, the gates of the PMOS transistors M1 and M3 are grounded, and the sources of the PMOS transistors M1 and M3 are connected to the VDD. The drains of M1 and M3 are connected to the gates and drains of PMOS transistors M2 and M4; the NMOS transistors M5 and NMOS transistors M6 are used as the positive and negative differential inputs of the delay unit, respectively, NMOS transistor M7 and NMOS transistor. The source and drain of M8 are respectively connected to the source and drain of NMOS transistor M5 and NMOS transistor M6, the gate of NMOS transistor M7 is connected to the drain of NMOS transistor M6, and the gate of NMOS transistor M8 is connected to NMOS transistor M5. The drain of the NMOS transistor M5 serves as an inverting output terminal, the drain of the NMOS transistor M6 serves as a positive phase output terminal, and the output terminal is connected to the load capacitor C _L ; and each NMOS transistor M5, M6, M7, M8 The substrate terminal is connected to the bias voltage V _B .

Please refer to FIG. 2B, which is an ultra-low voltage toroidal voltage controlled oscillator delay unit structure. The invention proposes a ring oscillator designed in a specific implementation based on a 0.18 um RF process. Figure 3 shows the frequency variation range of the voltage controlled oscillator when the control voltage changes. As it can be seen from Figure 3, when the control supply voltage V _c changes from 0V to 0.5V, the operating frequency of the VCO is adjusted range from 88MHz to 392MHz, VCO gain -608MHz / V.

Through the design of the above embodiment, the present invention can adopt the substrate forward bias structure, reduce the threshold voltage of the transistor, reduce the power supply voltage, and reduce the power consumption; the two-stage structure, the circuit structure is simple, the area is small, and the implementation is easy. With integration.

The above-mentioned embodiments are not intended to limit the scope of the present invention, and various simple modifications and modifications made by those skilled in the art in accordance with the scope of the invention and the description of the invention should still be made without departing from the spirit of the invention. It is included in the scope of the following patent application.

Claims (1)

An ultra-low voltage toroidal voltage controlled oscillator for a chip circuit, comprising: a two-stage delay unit, wherein the oscillator adjusts an operating frequency by adjusting a delay time of the delay unit, and the delay unit comprises PMOS transistors M1, M2, M3, M4, NMOS transistors M5, M6, M7, M8, and load capacitance C _L ; wherein the substrates of the PMOS transistors M2, M4 are grounded, the substrates of the PMOS transistors M1, M3 are connected to the control voltage Vc, and the PMOS transistors M1, M3 The gate is grounded, the PMOS transistors M1 and M3 are connected to VDD, the PMOS transistors M1 and M3 are connected to the gates and drains of the PMOS transistors M2 and M4, and the NMOS transistor M5 and the NMOS transistor M6 are used as delay units, respectively. The positive and negative differential input terminals, the source and drain of the NMOS transistor M7 and the NMOS transistor M8 are respectively connected to the source and drain of the NMOS transistor M5 and the NMOS transistor M6, and the NMOS transistor M7 is connected to the NMOS transistor. The drain of M6, the gate of NMOS transistor M8 is connected to the drain of NMOS transistor M5, the drain of NMOS transistor M5 is used as the inverting output terminal, and the drain of NMOS transistor M6 is used as the positive phase output terminal, and the output terminal is connected. Load capacitance C _L , and substrate termination of each NMOS transistor M5, M6, M7, M8 Connected to the bias voltage V _B .