CN207442806U

CN207442806U - A kind of ultralow pressure two-stage annular voltage controlled oscillator for chip circuit

Info

Publication number: CN207442806U
Application number: CN201721599971.8U
Authority: CN
Inventors: 蔡水河
Original assignee: Changzhou Xinsheng Micro Structure Electronic Co Ltd
Current assignee: Changzhou Xinsheng Semiconductor Co.,Ltd.; Changzhou Xinsheng Semiconductor Technology Co ltd
Priority date: 2017-11-27
Filing date: 2017-11-27
Publication date: 2018-06-01
Anticipated expiration: 2027-11-27

Abstract

The utility model is related to a kind of ultralow pressure two-stage annular voltage controlled oscillators for chip circuit, it is characterized in that, including two-stage delay cell, the oscillator includes two end to end delay cells, and working frequency is adjusted by the time delay for adjusting delay cell；Delay cell includes PMOS transistor M1, M2, M3, M4, NMOS tube M5, M6, M7, M8 and load capacitance C_L.The utility model two-stage annular voltage controlled oscillator using substrate feedforward bias structure, reduces transistor threshold voltage, reduces supply voltage, reduce power consumption, while has larger tuning range, the system particularly suitable for low supply voltage work.

Description

A kind of ultralow pressure two-stage annular voltage controlled oscillator for chip circuit

Technical field

The utility model is related to oscillator technique field, more specifically to a kind of ultralow pressure for chip circuit Two-stage annular voltage controlled oscillator.

Background technology

Voltage controlled oscillator is the important composition module of analog circuit and digital circuit.There are many kinds of different for voltage controlled oscillator Realization method, ring oscillator occupy smaller chip area and the adjusting with bigger compared with traditional LC oscillators Scope.If ring oscillator is made of two-stage delay, then it can work in high frequency, and provide orthogonal output.

In modern CMOS processes, technology feature sizes and supply voltage need proportional diminution to maintain the stabilization of device Property.For ring oscillator, due to the high threshold voltage of transistor, it is difficult the normal work under the supply voltage of 0.5V Make.The substrate connection forward bias of MOS transistor is the effective ways for reducing transistor threshold voltage.In the design, substrate is being just It is applied to biasing technique in the delay cell with local positive feedback.

Therefore, the prior art is urgently greatly improved.

Utility model content

The technical issues of the utility model solves be, for the prior art it is above-mentioned the defects of, provide a kind of for core The ultralow pressure two-stage annular voltage controlled oscillator of piece circuit, including：Including two end to end delay cells, the oscillator leads to Overregulate the time delay adjustment working frequency of delay cell；Delay cell includes PMOS transistor M1, M2, M3, M4, NMOS tube M5, M6, M7, M8 and load capacitance CL.

In ultralow pressure two-stage annular voltage controlled oscillator described in the utility model, the substrate of PMOS transistor M2, M4 connects Ground, the substrate connection control voltage Vc of PMOS transistor M1, M3, the grounded-grid of PMOS transistor M1, M3, PMOS transistor M1, M3 source electrode connect VDD, the grid of PMOS transistor M1, M3 drain electrode connection PMOS transistor M2, M4 and drain electrode；NMOS transistor M5 and NMOS transistor M6 is respectively as the positive of delay cell and reverse phase differential input end, NMOS transistor M7 and NMOS crystal Source-drain electrode of the source-drain electrode of pipe M8 respectively with NMOS transistor M5 and NMOS transistor M6 is connected, and NMOS transistor M7 grids connect The drain electrode of NMOS transistor M6, the grid of NMOS transistor M8 connect the drain electrode of NMOS transistor M5；The drain electrode of NMOS transistor M5 As reversed-phase output, the drain electrode of NMOS transistor M6 is as positive output end, output termination load capacitance CL；NMOS transistor Substrate terminal connection bias voltage VB.

Implement the ultralow pressure two-stage annular voltage controlled oscillator for chip circuit of the utility model, have below beneficial to effect Fruit：Using forward substrate bias structure, transistor threshold voltage is reduced, reduces supply voltage, reduces power consumption；Two-layer configuration, electricity Line structure is simple, and area is smaller, it is easy to accomplish with integrating；Compared with LC oscillator structures, two-stage ring oscillator circuit has Big tuning range.

Description of the drawings

Below in conjunction with accompanying drawings and embodiments, the utility model is described in further detail, in attached drawing：

Fig. 1 metal-oxide-semiconductors threshold voltage is with Substrate bias voltage change schematic diagram；

Fig. 2 is ultralow pressure two-stage annular voltage controlled oscillator VCO structure charts；

Fig. 3 is ultralow pressure two-stage annular voltage controlled oscillator delay cell structure chart；

Fig. 4 is pressuring controlling oscillator frequency with control voltage change schematic diagram.

Specific embodiment

Referring to Fig. 1, for metal-oxide-semiconductor threshold voltage with Substrate bias voltage change schematic diagram.Forward substrate bias technology can To effectively reduce the threshold voltage of MOS transistor.

By taking 0.18um RF CMOS technologies as an example, the about +/- 0.5V of threshold voltage of NMOS and PMOS transistor, when power supply electricity Press for 0.5V when, this threshold voltage can limiting circuit significantly performance.It can be dropped by the substrate of forward bias MOS transistor Low threshold voltage.Under 0.18um RF CMOS technologies, by using deep N-well by sensitive analog circuit and substrate noise every From so either the NMOS transistor of substrate connection or PMOS transistor can reduce threshold value by forward substrate bias Voltage.

The PMOS transistor threshold voltage (Vthp) of forward substrate bias can be expressed as：

|V_thp0| it is source lining voltage (V_sb) be 0 when | V_thp|, γ is body-effect coefficient,It is Fermi potential.Therefore, threshold value Voltage | V_th| with V_sbIncrease and reduce, PMOS transistor threshold voltage is as shown in Figure 1 with Substrate bias voltage change.By Fig. 1 is understood, when the Substrate bias voltage of PMOS transistor changes from 500mV to 0V, the threshold voltage of PMOS transistor from- 500mV to -366mV changes.When the Substrate bias voltage Vc of NMOS transistor changes from 0V to 0.5V, the threshold of NMOS transistor Threshold voltage (Vthn) changes from 531mV to 423mV.This is operated in MOS transistor largely effective under ultra-low power supply voltage.

It is end to end, identical by two referring to Fig. 2, for ultralow pressure two-stage annular voltage controlled oscillator VCO structure charts Delay cell forms.

Referring to Fig. 3, it is ultralow pressure two-stage annular voltage controlled oscillator delay cell structure chart.It is brilliant that delay cell includes PMOS Body pipe M1, M2, M3, M4, NMOS tube M5, M6, M7, M8 and load capacitance CL.The present invention proposes the ring oscillator of design, tool Body is designed when implementing based on 0.18um RF techniques.The Substrate ground of PMOS transistor M2, M4, PMOS transistor M1, M3 Substrate connection control voltage Vc, the grounded-grid of PMOS transistor M1, M3, PMOS transistor M1, M3 source electrode meet VDD, and PMOS is brilliant The grid of body pipe M1, M3 drain electrode connection PMOS transistor M2, M4 and drain electrode；NMOS transistor M5 and NMOS transistor M6 make respectively For the positive of delay cell and reverse phase differential input end, the source-drain electrode of NMOS transistor M7 and NMOS transistor M8 respectively with NMOS Transistor M5 is connected with the source-drain electrode of NMOS transistor M6, and NMOS transistor M7 grids meet the drain electrode of NMOS transistor M6, NMOS The grid of transistor M8 connects the drain electrode of NMOS transistor M5；The drain electrode of NMOS transistor M5 is as reversed-phase output, NMOS crystal The drain electrode of pipe M6 is as positive output end, output termination load capacitance CL；The substrate terminal connection bias voltage VB of NMOS transistor.

Referring to Fig. 4, for pressuring controlling oscillator frequency with control voltage change schematic diagram.Fig. 4 gives control voltage change When, the frequency range of voltage controlled oscillator.From fig. 4, it can be seen that as control voltage V_cWhen changing from 0V to 0.5V, the VCO Working frequency adjustable range be from 392MHz to 88MHz, VCO gain be -608MHz/V.

The utility model can be accomplished, using forward substrate bias structure, to reduce crystal by the design of above example Pipe threshold voltage reduces supply voltage, reduces power consumption；Two-layer configuration, circuit structure is simple, and area is smaller, it is easy to accomplish with collection Into.

The utility model is described according to specific embodiment, but it will be understood by those skilled in the art that is not departing from During the scope of the utility model, various change and equivalent substitution can be carried out.In addition, to adapt to the specific field of the utility model technology It closes, many modifications can be carried out to the utility model without departing from its protection domain.Therefore, the utility model is not limited to public herein The specific embodiment opened, and including all embodiments for dropping into claims.

Claims

1. a kind of ultralow pressure two-stage annular voltage controlled oscillator for chip circuit, which is characterized in that end to end including two Delay cell, the oscillator by adjust delay cell time delay adjust working frequency；Delay cell includes PMOS Transistor M1, M2, M3, M4, NMOS tube M5, M6, M7, M8 and load capacitance C_L。

2. ultralow pressure two-stage annular voltage controlled oscillator according to claim 1, which is characterized in that PMOS transistor M2, M4 Substrate ground, PMOS transistor M1, M3 substrate connection control voltage Vc, the grounded-grid of PMOS transistor M1, M3, PMOS Transistor M1, M3 source electrode connects VDD, the grid of PMOS transistor M1, M3 drain electrode connection PMOS transistor M2, M4 and drain electrode；NMOS Transistor M5 and NMOS transistor M6 respectively as the positive of delay cell and reverse phase differential input end, NMOS transistor M7 and Source-drain electrode of the source-drain electrode of NMOS transistor M8 respectively with NMOS transistor M5 and NMOS transistor M6 is connected, NMOS transistor M7 Grid connects the drain electrode of NMOS transistor M6, and the grid of NMOS transistor M8 connects the drain electrode of NMOS transistor M5；NMOS transistor M5 Drain electrode as reversed-phase output, the drain electrode of NMOS transistor M6 is as positive output end, output termination load capacitance C_L；NMOS The substrate terminal connection bias voltage V of transistor_B。