TWI653813B - Forced zero voltage switching flyback converter and using method - Google Patents

Abstract

A flyback converter is configured with forced zero voltage switching (ZVS) time control by detecting the positive current stroke of the secondary winding as a synchronous rectifier turn-off trigger. At the end of the switching cycle, the synchronous rectifier switch is turned on, or the on-time is extended to form a current ripple on the secondary winding current. The control circuit of the flyback converter detects a positive current stroke on the secondary winding current to open the synchronous rectifier and initiate the next switching cycle. At this point, the voltage on the primary switch is discharged and the primary switch is turned on at zero drain to source voltage. In other embodiments, zero voltage switching under the off transient of the primary switch is achieved by a primary switch coupling capacitor or by a primary winding coupling capacitor, or both.

Description

Forced zero voltage switch flyback converter and operation method thereof

The invention relates to the field of flyback converters.

A flyback converter is an isolated power converter that is commonly used for galvanically isolated AC to DC and DC to DC conversion between an input and one or more outputs. More specifically, the flyback converter is a step-up converter with an inductor split that forms a transformer that multiplies the voltage ratio by the additional advantage of the insulation. Synchronous rectification is often used to replace diode rectifiers to increase efficiency. Figure 1 shows an example of a flyback converter using synchronous rectification. As shown in Figure 1, a typical structure of a flyback converter includes a primary switch (SW), a primary transformer winding coupled to transformer Lm, and a synchronous rectifier switch (SR) coupled to the secondary transformer winding of transformer Lm. The input voltage VIN is supplied through the primary winding and the primary switch. The control voltage VGS controls the primary switch to be turned on and off, and conducts the primary current Ipri. The primary switch and the synchronous rectifier are supplemented in operation, one switch is turned on and the other switch is turned off. The conduction periods of the primary switch SW and the synchronous rectifier SR do not overlap. The current flow at the secondary side is referred to as the secondary current Isec, which charges the output capacitor C3 and provides an output voltage Vo. In some cases, an active clamp can be configured at the secondary side, and when the primary switch SW is open, the voltage at the 汲 terminal of the primary switch SW is embedded.

Figure 2 shows an example signal waveform for operating the flyback converter of Figure 1 in a constant frequency, continuous conduction mode (CF CCM). Figure 3 shows the constant frequency, discontinuous conduction mode (CF Example signal waveform of the flyback converter shown in Figure 1 under DCM). The operation mode shown in Figure 1 for the flyback converter, Figure 2 and Figure 3 is described in detail in the following paper: Design Considerations and Performance Evaluation of Synchronous Rectification in MTZhang, MMJovanovic and FCLee Flyback Converters Applied Power Electronics Conference and Exhibition, 1997, APEC '97 Conference Proceedings 1997, pp. 623-630, Volume 2. In short, when operating in the CCM operating mode, the secondary current Isec does not reach the zero current value until the next switching cycle is initiated (primary switch SW is turned on), as shown in FIG. On the other hand, when operating in the DCM mode of operation, the secondary current Isec reaches a zero current value before the next switching cycle is initiated, as shown in FIG.

When the switching transition occurs at a non-zero voltage of the power switch, a power loss occurs in the flyback converter. A zero voltage switch (ZVS) is configured in the flyback converter to complete the switch at zero voltage for high efficiency. Different techniques for configuring zero voltage switching have been proposed. For example, the Zhang paper proposes that a variable frequency (VF) ZVS DCM mode of operation can be configured in the flyback converter shown in FIG. Figure 4 replicates Figure 5 of the Zhang paper and shows an example signal waveform for the flyback converter operation shown in Figure 1 in the VF ZVS DCM mode of operation. Specifically, to obtain ZVS at the primary switch, the conduction period of the synchronous rectifier (SR) is extended, or the off-time of the synchronous rectifier is delayed by a period of time Tdelay until the secondary current Isec has reached the zero current value. With the extended on-time Tdelay, a negative secondary current is established on the secondary transformer winding, as shown by the current IZVS in FIG. As long as the energy stored in the magnetizing inductance Lm of the negative secondary current IZVS is sufficient to discharge the primary switching parasitic capacitance (shown as Cl in Figure 1) to zero voltage, ZVS can be implemented in the flyback converter. However, with the extended SR conduction time, the switching frequency of the flyback converter is variable as a function of load modulation. No variable frequency operation is required, especially when avoiding electromagnetic interference (EMI) distribution.

The invention discloses a method for operating a flyback converter, the flyback converter comprising a transformer having a primary winding receiving an input voltage and a secondary winding providing an output voltage, the primary switch being coupled to the primary winding, the synchronous rectifier coupled to a secondary winding, the method comprising: turning on the first duration of the primary switch at the beginning of the switching cycle; turning on the first on-time of the synchronous rectifier; sensing the secondary current flowing in the secondary winding; reaching according to the secondary current Zero current value, disconnecting the synchronous rectifier; monitoring the output voltage in the discontinuous conduction mode; turning on the second on-time of the synchronous rectifier according to the output voltage being less than the reference voltage; sensing the secondary winding during the second on-time The secondary current flowing in the secondary current includes a current ripple having a negative current stroke and a positive current stroke; and the secondary rectifier having a positive current value according to the second on-time, disconnecting the synchronous rectifier.

The method further includes: according to the off period of the primary switch, the next switching period is started by repeating the turning on of the primary switch, and the primary switch is turned on at the zero voltage of the switch.

The method further includes sensing the primary current according to the second rectifier being turned on according to the synchronous rectifier; and starting the next switching cycle by repeating the turning on of the primary switch according to the primary current exceeding the threshold.

Wherein, turning on the synchronous rectifier for the first on-time includes turning on the synchronous rectifier after a non-overlapping time.

The method further includes coupling the first capacitor across the primary switch; and coupling the first capacitor according to crossing the primary switch, and disconnecting the primary switch at the primary switch zero voltage.

Therein, the method further includes connecting a second capacitor across the primary winding of the transformer; and coupling the second capacitor according to crossing the primary winding, and disconnecting the primary switch at a primary switch zero voltage.

Wherein, at the beginning of the switching cycle, turning on the primary switch for the first duration comprises: turning on the primary switch for a fixed on-time at the beginning of the switching cycle.

The invention also discloses a method for operating a flyback converter, the flyback converter comprising a transformer having a primary winding receiving an input voltage and a secondary winding providing an output voltage, the primary switch being coupled to the primary winding, the synchronous rectifier coupling To the secondary winding, the method includes: turning on the first duration of the primary switch at the beginning of the switching cycle; turning on the first on-time of the synchronous rectifier; and sensing the secondary flowing in the secondary winding in the critical conduction mode Current; according to the secondary current reaching a zero current value, extending the on-time of the synchronous rectifier by a second on-time; during the second on-time, sensing the secondary current flowing in the secondary winding, the secondary current including having a negative Current ripple of the current stroke and the positive current stroke; and breaking the synchronous rectifier according to the secondary current having a positive current value according to the second on-time.

The method further includes: starting the next switching cycle by repeating the turning-off of the primary switch according to the off-time of the primary switch.

The method further includes sensing the primary current according to the second rectifier being turned on according to the synchronous rectifier; and starting the next switching cycle by repeating the turning on of the primary switch according to the primary current exceeding the threshold.

Wherein, the first on-time of the synchronous rectifier is turned on, including after a non-overlapping period, the synchronous rectifier is turned on.

The method further includes coupling the first capacitor across the primary switch; and coupling the first capacitor across the primary switch, and turning off the primary switch at zero voltage of the primary switch.

Therein, the method further includes connecting a second capacitor across the primary winding of the transformer; and coupling the second capacitor according to the primary winding across the transformer to disconnect the primary switch at zero voltage of the primary switch.

Wherein, at the beginning of the switching period of the first on-time, the primary switch is turned on, including: turning on the primary switch for a fixed on-time at the beginning of the switching period.

The invention further discloses a flyback converter comprising: a transformer having a primary winding receiving an input voltage and a secondary winding providing an output voltage; a primary switch coupled to the primary winding; and a primary coupled to the secondary winding a synchronous rectifier; an output capacitor coupled across the secondary winding; a controller coupled to generate a control signal to drive the primary switch and the synchronous rectifier; and a positive current sensing circuit to sense a secondary current flowing in the secondary winding, A secondary current having a positive current value is detected to generate a detection signal, wherein the controller generates a control signal that alternately turns the primary switch and the synchronous rectifier on and off in one switching cycle, and the synchronous rectifier turns on the first connection during the switching cycle The pass time, according to detecting that the secondary current reaches a zero current value, the controller generates a control signal, turns on the synchronous rectifier second on time during the switching cycle, and the positive current detecting circuit senses the secondary current in the second on time. A detection signal is generated based on the detection of a secondary current having a positive current value, and the root Detection signal, the switching cycle, the synchronous rectifier turned off.

Wherein, the controller runs the flyback converter in the discontinuous conduction mode, and the controller generates a control signal, according to detecting that the secondary current reaches a zero current value, disconnects the synchronous rectifier, and the controller continues to monitor the output voltage according to the output voltage equal to or Below the reference voltage, the controller generates a control signal that turns on the second on-time of the synchronous rectifier during the switching cycle.

Wherein, the controller runs the flyback converter in the critical conduction mode, and the controller generates a control signal to extend the second on-time of the on-time of the synchronous rectifier during the switching period according to the detection that the secondary current reaches a zero current value.

Wherein, according to the off time of the primary switch, the next switching cycle is started by repeating the turning on of the primary switch, and the primary switch is turned on at the zero voltage of the switch.

Wherein, according to the synchronous rectifier turning on the second on-time, the controller senses the primary current, and according to the primary current exceeding the threshold, the next switch is activated by repeating the turning on of the primary switch cycle.

Therein, a first capacitor coupled across the primary switch is also included, wherein the primary switch is turned off at zero voltage of the primary switch in accordance with coupling the first capacitor across the primary switch.

Therein, a second capacitor coupled across the primary winding of the transformer is also included, wherein the primary switch is turned off at zero voltage of the primary switch in accordance with coupling the second capacitor across the primary winding.

Wherein, the controller generates a control signal to cause the primary switch to be turned on for a fixed on-time.

(ZVS) ‧ ‧ zero voltage switch

(DCM) ‧‧‧ discontinuous conduction mode

(CRI) ‧‧‧critical conduction mode

(10)‧‧‧Reciprocating converter

(Q1)‧‧‧Primary switch

(Q2)‧‧‧Synchronous rectifier

(12) ‧‧‧Voltage node

(18)‧‧‧ Grounding node

(16)‧‧‧ Output node

(15) ‧‧‧ nodes

(20) ‧‧‧Drive load

(25)‧‧‧Active Clamp Circuit

(D1)‧‧‧ body diode

(30)‧‧‧Primary controller

(40) ‧‧‧secondary controller

(45) ‧‧‧Positive current detection circuit

The following detailed description and the accompanying drawings set forth various embodiments of the invention. Figure 1 shows an example of a flyback converter using synchronous rectification.

2 shows an example signal waveform of the flyback converter of FIG. 1 operating in a fixed frequency, continuous conduction mode (CF CCM).

Figure 3 shows an example signal waveform for the flyback converter of Figure 1 operating in a fixed frequency, discontinuous conduction mode (CF DCM).

Figure 4 replicates Figure 5 of the Zhang paper, showing an example signal waveform of the flyback converter shown in Figure 1 in the VF ZVS DCM mode of operation.

Figure 5 shows a schematic diagram of a flyback converter configuration forced zero voltage switching (ZVS) timing control in an embodiment of the invention.

Figure 6 shows a timing diagram of the normal operation of a forced ZVS mode of operation, in some examples.

Figure 7 is a timing diagram showing the waveform of the flyback converter signal operating in forced ZVS timing control with a positive current synchronous rectification shutdown trigger in an embodiment of the present invention.

Figures 8(a) through 8(c) show an alternative embodiment of the invention for a primary switch with forced zero Schematic diagram of a flyback converter for voltage switch (ZVS) timing control.

Figure 9 shows a schematic diagram of a flyback converter for a primary switch disconnect transient with a zero voltage switch (ZVS) in an embodiment of the invention.

Figure 10 is a flow diagram showing a forced ZVS timing control method with a positive current synchronous rectification shutdown trigger in an embodiment of the invention.

Figure 11 is a flow diagram showing a forced ZVS timing control method with a positive current synchronous rectification shutdown trigger in an alternate embodiment of the present invention.

Figure 12 is a flow diagram showing a forced ZVS timing control method with a positive current synchronous rectification shutdown trigger in an alternate embodiment of the present invention.

The invention can be embodied in a variety of ways, including as a process; a device; a system; and/or a material composition. In this specification, these implementations or any other manners that may be employed by the present invention may be referred to as techniques. In general, the order of the process steps can be varied within the scope of the invention.

The detailed description of the one or more embodiments of the invention and the drawings illustrate the principles of the invention. Although the present invention has been proposed together with the embodiments, the scope of the present invention is not limited to any embodiments. The scope of the invention is to be limited only by the scope of the appended claims. In the following description, various specific details are set forth to provide a thorough understanding of the invention. The details are intended to be illustrative, and the invention may be practiced without departing from the Detailed Description. For the sake of brevity, the technical materials well-known in the related art are not described in detail in order to avoid unnecessary confusion to the present invention.

According to an embodiment of the invention, by detecting a positive current stroke of the secondary winding current, For synchronous rectification shutdown triggers, the flyback converter is configured with forced zero voltage switching (ZVS) timing control. The flyback converter can operate in discontinuous conduction mode (DCM) or critical conduction mode (CRI). In DCM mode, the synchronous rectifier switch that has been disconnected according to the load rule is turned on again at the end of the switching cycle, generating current ripple on the secondary winding current. In the CRI mode, the on-time of the synchronous rectifier switch is extended to the secondary winding current zero crossing, and current ripple is generated in the secondary winding current. The current ripple on the secondary winding current includes a negative current stroke and a positive current stroke. The control current of the flyback converter detects the positive current stroke on the secondary winding current ripple as a trigger, breaking the synchronous rectifier and starting the next switching cycle. At this point, the voltage on the primary switch has been discharged and the primary switch can be turned on at zero to the source voltage, thus avoiding switching losses.

The forced ZVS flyback converter of the present invention has several advantages over the conventional operating system. Specifically, with the positive secondary winding current as the synchronous rectification shutdown trigger, the flyback converter can operate in either fixed frequency or fixed frequency discontinuous conduction mode (CF DCM), eliminating the need for EMI considerations. In one example, the on-time of a synchronous rectifier that conforms to the load rule can be modulated while the switching frequency remains constant. In addition, the flyback converter achieves an increase in efficiency by ensuring that the primary switch is switched at zero voltage.

Figure 5 shows a schematic diagram of a flyback converter with forced zero voltage switching (ZVS) timing control in an embodiment of the invention. Referring to Figure 5, flyback converter 10 includes a primary switch Q1 (SW) coupled to the primary transformer winding of transformer TR and a synchronous rectifier switch Q2 (SR) coupled to the secondary transformer winding of transformer TR. The input voltage VIN is coupled across the primary winding and the primary switch between the input voltage node 12 and the ground node 18. Input decoupling capacitor Cin can be coupled to input voltage node 12. The primary switch is controlled to be turned "on" and "off" by the control voltage VGS1 to conduct the primary current Ipri to flow in the primary transformer winding. The synchronous rectifier switch is switched on by the control voltage VGS2 And disconnected to conduct secondary current Isec to flow in the secondary transformer windings. In the present description, the term "primary current" refers to the current flowing in the primary transformer winding of the transformer TR, and "secondary current" and "secondary winding current" are used to refer to the current flowing in the winding of the secondary transformer. The output capacitor COUT is coupled across the secondary winding and the synchronous rectifier, that is, between the output node 16 and the ground node 18. An output voltage VOUT is generated at the output node 16 to drive the load 20. In some embodiments, the active clamp circuit 25 can be located at the primary side, clamping the voltage at the extreme (node 14) of the primary switch Q1 when the primary switch Q1 is open.

In an embodiment of the invention, primary switch Q1 and synchronous rectifier Q2 are both power switches, typically MOSFET devices. In the present embodiment, both the primary switch Q1 and the synchronous rectifier Q2 are made using NMOS transistors. The NMOS transistor of primary switch Q1 has a 汲 terminal coupled to the transformer (node 14), a source terminal coupled to ground (node 18), and a gate terminal driven by control voltage VGS1. As an NMOS transistor, the primary switch Q1 also has an associated parasitic capacitance Coss1 across the drain and source terminals of the transistor. The NMOS transistor of primary switch Q1 also has a parasitic body diode D1 that spans the drain and source terminals of the transistor. In the present description, the parasitic capacitance Coss1 and the body diode D1 are shown as being connected across the dotted line of the NMOS switch Q1 to illustrate that the capacitance Coss1 is not an additional capacitor element, but is coupled to the NMOS transistor, but a parasitic capacitance, as an NMOS transistor structure. In part, body diode D1 is simply a parasitic diode rather than an additional diode component. At the secondary side, the NMOS transistor of synchronous rectifier switch Q2 has a 汲 terminal coupled to the transformer (node 15), a source terminal coupled to ground (node 18), and a gate terminal driven by control voltage VGS2. As an NMOS transistor, the synchronous rectifier switch Q2 has an associated parasitic capacitance Coss2 and a parasitic body diode D2, both across the drain and source terminals of the transistor. Again, the parasitic capacitance Coss2 and the body diode D2 are shown as being connected across the NMOS switch Q2 with a dashed line to illustrate that both the capacitance Coss2 and the diode D2 are An element coupled to an NMOS transistor, rather than a parasitic element that is part of an NMOS transistor structure.

Both the primary switch and the synchronous rectifier are driven by respective control circuits that control the switching on and off operations of the switch. Specifically, the primary side controller 30 is coupled to drive the gate terminal of the primary switch Q1, coupled to the secondary terminal controller 40, to drive the gate terminal of the synchronous rectifier Q2. The primary side controller 30 and the secondary side controller 40 can be fabricated in different ways depending on the control system required for the flyback converter 10. In other words, the flyback converter 10 is a power phase and different control systems can be used to control the flyback converter power phase. In actual operation, the switching of the primary switch is synchronized to the switching of the synchronous rectifier. In most configurations, the primary side controller can be the primary controller, the secondary side controller is the slave controller, or the secondary side controller is the primary controller, and the primary side controller is the slave controller. The main controller is usually configured as a PWM controller. Examples of control systems that may be used in flyback converter 10 include voltage mode control, peak current mode control, and input voltage feedforward control. Each control system uses a different feedback signal to control the stable output voltage and provide load modulation. The particular configuration of the control system in the flyback converter 10 is not critical to the implementation of the present invention. Those skilled in the art will recognize that forced ZVS timing control can be used in any control system to initiate a zero voltage switch at the primary switch to eliminate switching losses. In this description, a primary side controller and a secondary side controller are proposed. In other embodiments, the primary side controller and the primary side controller can be fabricated as a separate controller or control circuit that produces control signals for the primary switch and the synchronous rectifier switch.

In an embodiment of the invention, the flyback converter power stage is configured with a fixed on-time (COT) control system in the primary side controller, with the secondary side acting as the primary controller. The secondary controller is a PWM controller that modulates the output voltage VOUT. Under the COT control system, the primary switch is turned on for a fixed on-time. Then, the opening time of the primary switch is not fixed, but is sensed to output. The secondary side controller of the voltage is controlled. Under the COT control system, the flyback converter can operate in discontinuous mode with variable switching frequency. The secondary side controller is configured with forced ZVS timing control in accordance with the present invention, turning on the synchronous rectifier for a short period of time, discharging the drain voltage at the primary switch, and turning off the synchronous rectifier when a positive secondary current stroke is detected. In some embodiments, the primary side controller is configured for automatic synchronization, the primary controller detects the primary side current signal, indicating that the synchronous rectifier is off, using the detected current signal, turning on the primary switch, and starting the next switching cycle.

In an embodiment of the invention, the secondary side controller 40 is configured with forced ZVS timing control by monitoring the secondary current flowing through the synchronous rectifier Q2. Using a different current sensing technique, a current sense signal VCS_sec representing the current flowing through the synchronous rectifier Q2 is generated to sense the secondary current. For example, at node 15, the secondary current can be sensed. For example, the secondary winding current can be sensed using a series resistor or through an auxiliary winding on the secondary winding. The coupled positive current detecting circuit 45 receives the current sensing signal VCS_sec, detects a positive current stroke on the secondary current ripple, and acts as a trigger to turn off the synchronous rectifier Q2, which will be described in detail below.

The usual mode of operation of the flyback converter 10 will be described with reference to the timing diagram shown in FIG. Referring to Figure 6, the flyback converter 10 can be controlled using the various control systems described above. Regardless of which control system is used, the primary switch SW and the synchronous rectifier SR complement each other during operation, and when one switch is turned on, the other switch is turned off (curve 102). The conduction periods of the primary switch SW and the synchronous rectifier SR do not overlap. When the primary switch SW is turned on, the primary winding of the transformer TR is connected to the input voltage VIN, and the primary current Ipri (curve 104) linearly increases as the magnetic flux in the transformer increases. The energy is stored in the transformer TR. At this time, the voltage VSEC generated in the secondary winding has an opposite polarity to the primary winding, causing the body diode D2 of the synchronous rectifier SR to be reverse biased. Without the secondary current Isec (curve 106) flowing, the charge stored on the output capacitor COUT provides the load 20. As the primary switch SW is turned on, the primary is turned on. The drain-to-source voltage VDS(SW) of the SW (curve 108), at node 14, is at or near zero volts. At the same time, the secondary voltage VSEC (curve 110) of the synchronous rectifier SR (node 15) is also the drain-to-source voltage VDS(SR) of the synchronous rectifier, driven to a positive voltage, which is the ratio of the input voltage VIN.

After the on-time of the primary switch has elapsed, the primary switch is turned off and the synchronous rectifier is turned on after the non-overlap time. When the primary switch is turned off, the primary current Ipri is lowered and the magnetic flux is reduced. The voltage on the secondary winding is reversed such that the secondary voltage has a positive polarity at the same end, or has a negative polarity at the drain of the synchronous rectifier (node 15), thereby forward biasing the body diode D2 of the synchronous rectifier SR. Therefore, the current flowing through the secondary winding acts as the secondary current Isec. The secondary current Isec is increased to the peak current value. After the non-overlap time, the synchronous rectifier SR is turned on, conducting the secondary current Isec, helping to transfer stored energy from the transformer core to the output capacitor COUT. The output capacitor COUT is charged again and supplied to the load 20. The charge on output capacitor COUT maintains output voltage VOUT (node 16). When the primary switch SW is turned off, the drain-to-source voltage VDS(SW) of the primary switch SW (node 14) swings to a high voltage value. In some examples, a voltage clamping circuit (eg, active clamp circuit 25) is used to embed the gate voltage at the primary switch to a maximum allowable voltage value to protect the primary switch.

The control system configured in the flyback converter includes a feedback control loop that monitors the output voltage VOUT. The control system used controls the on-time of the synchronous rectifier or the off-time of the primary switch to maintain the output voltage at the desired voltage value under different load conditions. During the specified time, the primary or secondary controller of the flyback converter initiates the next switching cycle by opening the synchronous rectifier and turning on the primary switch. Repeat the above procedure.

In the above description, the flyback converter operates in DCM mode and the secondary current reaches a zero current value during the switching cycle. In other embodiments, the flyback converter can be in a critical current mode Or run in critical conduction mode (CRI). In the critical current mode, the synchronous rectifier on-time is stopped according to the secondary current Isec falling to the zero current value, as indicated by the dotted line in FIG. In actual operation, the zero crossing of the secondary current Isec is detected, and the synchronous rectifier on-time is terminated by Isec zero-cross detection. The forced ZVS timing control of the present invention can be used in a flyback converter configuration with a discontinuous conduction mode or a critical conduction mode, as will be described in more detail below.

At the beginning of each switching cycle, when the primary switch is turned on, the drain voltage at the primary switch is at a high voltage value. When the primary switch with high buckling voltage is turned on, the flyback converter is subjected to unnecessary power loss. Therefore, the zero voltage switch (ZVS) configured in the flyback converter results in switching transients at zero bucker voltage for high efficiency. Different systems can also be used to implement TVS in the art. FIG. 6 shows the result of arranging ZVS in the flyback converter 10. Specifically, when ZVS is configured, the drain-to-source voltage VDS(SW) of the primary switch SW (node 108) drops to zero volts before the primary switch SW is turned on, as indicated by the dotted circle in FIG. . In this case, the power loss at the primary switch during switching transients can be avoided.

In an embodiment of the invention, the flyback converter 10 is configured with forced zero voltage switching (ZVS) timing control by detecting a positive current stroke of the secondary current as a synchronous rectifier turn-off trigger. 7 is a timing diagram showing signal waveforms of a flyback converter in forced ZVS timing control with a positive current synchronous rectifier turn-off flip-flop in an embodiment of the present invention. Referring to Figure 7, the flyback converter 10 operates in a discontinuous conduction mode (DCM) with the primary switch being turned "on" for a specified on time TON and a specified off time TOFF. In DCM mode, you can configure a fixed frequency operation. The switching frequency can be fixed to a fixed switching time TSW. The flyback converter 10 can be controlled with different control systems to maintain output voltage and load modulation. Regardless of which control system is used, both the primary switch SW and the synchronous rectifier SR can be configured with one switch turned on while the other switch is turned off (curve 102). The conduction periods of the primary switch SW and the synchronous rectifier SR do not overlap.

When the switching period (T1) is started, the primary switch SW is turned on for a period of time TON. The primary switch Ipri is established (curve 104) and the energy is stored in the transformer TR. At the same time, there is no secondary current Isec flowing (curve 106) and the charge stored on output capacitor COUT is supplied to load 20. The drain-to-source voltage VDS(SW) of the primary switch SW (curve 108), at node 14, is at or near zero volts. At the same time, the secondary voltage VSEC (curve 110) of the synchronous rectifier SR (node 15), which is also the drain-to-source voltage VDS(SR) of the synchronous rectifier, is driven to a voltage proportional to the input voltage VIN.

After the on-period TON of the primary switch is over (T2), the primary switch SW is turned off, and after a non-overlap time (T2 to T3), the synchronous rectifier is turned on. When the primary switch is turned off, the primary current Ipri decreases and the magnetic flux decreases. The voltage on the secondary winding is reversed such that the secondary voltage Vsec has a positive polarity at the point end or a negative polarity at the drain of the synchronous rectifier (node 15). The negative polarity of the voltage Vsec causes the body diode D2 of the synchronous rectifier SR to be forward biased, and the current flowing through the secondary winding as the secondary current Isec. The secondary current Isec is increased to the peak current value. At the end of the non-overlap time (T3), the synchronous rectifier SR turns "on" and conducts the secondary current Isec, helping to transfer stored energy from the transformer core to the output capacitor COUT. The output capacitor COUT is charged again and supplied to the load 20. The charge on output capacitor COUT maintains output voltage VOUT (node 16). When the primary switch SW is turned off, the drain-to-source voltage VDS(SW) of the primary switch SW (node 14) swings to a high voltage value, and the voltage clamp circuit embeds a high voltage value to protect the primary switch SW.

The control system configured in the flyback converter includes a feedback control loop that monitors the output voltage VOUT. The control system used controls the on-time of the synchronous rectifier or the off-time of the primary switch to maintain the output voltage at the desired voltage value under different load conditions. During the specified time, the primary or secondary controller of the flyback converter initiates the next switching cycle by opening the synchronous rectifier and turning on the primary switch. Specifically, in the DCM mode of operation, the switching period TSW junction The secondary current Isec drops to zero (T4) before the beam. The synchronous rectifier SR is turned off (T4), and the flyback converter 10 operates when the primary switch SW and the synchronous rectifier SR are turned off (T4 to T5). During this period, the drain voltage VDS(SW) of the primary switch fluctuates, and the secondary voltage VSEC or the drain voltage VDS(SR) of the synchronous rectifier switch also fluctuates.

In an embodiment of the invention, the forced ZVS timing control is configured to turn the synchronous rectifier SR back on again at the end of the switching cycle. The flyback converter operates at a fixed frequency DCM, and the end of each switching cycle is deterministic. Forced ZVS timing control can be configured to insert a brief on-time of the synchronous rectifier before the end of each switching cycle. Therefore, at T5, the forced ZVS timing control operates, turning the synchronous rectifier SR back on for a short time (T5-T6). The synchronous rectifier is switched on again ("second on-time"), introducing negative current ripples in the secondary current. The negative current ripple in the secondary current causes the resonant energy to build up in the transformer TR, with which the drain voltage on the primary switch is driven down.

Specifically, when the synchronous rectifier is turned on again for the second on-time and the secondary current reaches the zero current value, a negative current with current ripple is formed on the secondary current Isec due to the parasitic capacitance on the synchronous rectifier and the primary switch. . Referring to Figure 5, the parasitic capacitance Coss1 on the primary switch Q1 is connected in parallel with the parasitic capacitance Coss2 on the synchronous rectifier switch Q2. The parallel connection of parasitic capacitances Coss1 and Coss2 (Coss1∥Coss2) results in the formation of negative current ripples on the secondary current Isec, as shown by curve 106 in FIG.

When the synchronous rectifier SR is turned on during the second on time, the secondary current Isec becomes negative and the negative energy is stored on the secondary winding. The negative energy stored on the transformer is transferred to the primary winding, causing current to flow in the primary switch, thereby driving the primary switch's drain-to-source voltage to zero voltage. In some examples, the incoming current flows through the parasitic body diode of the primary switch, discharging the total capacitance at the primary switch, thereby bringing the drain voltage to zero volts.

In forced ZVS timing control, the time to keep the synchronous rectifier SR turned on is determined. The energy required for ZVS. However, it is not necessary to keep the secondary turn-on time of the synchronous rectifier SR too long, otherwise the switching frequency of the flyback converter will be limited. The conventional ZVS method detects the primary switching drain voltage and turns off the synchronous rectifier SR when the primary switching drain voltage is equal to or lower than zero voltage. However, this approach typically requires the use of high voltage components to sense the primary switch drain voltage, so this configuration is typically costly and impractical.

Under the forced ZVS timing control of the present invention, the negative current ripple generated on the secondary current operates to resonate until the resonant current ripple is established within the positive current stroke. More specifically, when the synchronous rectifier SR is turned on at time T5, the secondary current Isec is driven to a negative current value, indicated by a dashed circle 112. The energy in the transformer generated by the negative current value is used to reduce the drain voltage VDS(SW) of the primary switch to zero voltage. At the same time, the parasitic capacitances Coss1 and Coss2 generate secondary current Isec resonance, which produces current ripple or vibration on the secondary current. The magnitude of the current ripple or vibration is very large, causing the secondary current to resonate back to a positive current value, as indicated by the dashed circle 114 in the figure. Under the forced ZVS timing control of the present invention, a positive current stroke of the secondary current is detected for triggering the synchronous rectifier SR to open. After the synchronous rectifier SR is turned off, the remaining secondary current will be conducted by the body diode of the synchronous rectifier.

More specifically, the forced ZVS timing of the present invention continuously turns on the second on-time of the synchronous rectifier at the end of the switching cycle. The secondary current resonates due to the parasitic capacitances Coss1 and Coss2 of the primary switch and the synchronous rectifier switch. The secondary current establishes a negative current with current ripple. The current ripple on the secondary current includes a negative current stroke and a positive current stroke. With a negative current stroke, energy is supplied to drive the primary switch drain voltage to zero for zero voltage switching. The positive current stroke acts as a trigger and disconnects the synchronous rectifier. After the synchronous rectifier is turned off, the control circuit waits for the off time TOFF, turns on the primary switch, and starts the next switching cycle. The primary to source voltage of the primary switch is at zero volts. Repeat the above procedure.

In the forced ZVS timing control of the present invention, the second on-time of the synchronous rectifier is not fixed, the second on-time is determined by the current ripple on the secondary current, and the positive current stroke on the secondary current is used as a trigger. Switch off the synchronous rectifier. The configuration of the forced timing control of the present invention can sense the drain voltage at the primary switch without requiring a high voltage component. Conversely, the secondary side controller senses the secondary current, detects a positive current stroke, and triggers the end of the second on-time of the synchronous rectifier. In some embodiments, as shown in FIG. 5, the flyback converter 10 includes a current sensing circuit that senses a secondary current (not shown) and a positive current detecting circuit 45 for use in the second During the on time, a signal indicative of positive current stroke detection is generated. The detection signal generated by the positive current detecting circuit 45 can be used in the secondary side controller 40 to generate the control signal VGS2 to turn off the synchronous rectifier. In some embodiments, the positive current detection circuit 45 can be configured as a comparator that compares the signal indicative of the sensed secondary current with a reference signal that detects a positive current value. For example, the sense secondary current can be converted to a voltage value VCS_sec, which is compared to the reference voltage to detect a positive current value.

Figure 7 shows forced ZVS timing control for a flyback converter operating in a fixed frequency discontinuous conduction mode. As described above, the forced ZVS timing control can be configured in the flyback converter, and the flyback converter operates in the variable frequency critical conduction mode. In critical conduction mode, the synchronous rectifier turn-off time is determined by the zero-crossing detection of the secondary current. When a secondary current cross zero current value point is detected, the secondary side controller will generate a control signal to turn off the synchronous rectifier. However, when forced ZVS timing control is configured, the synchronous rectifier does not turn off at the zero current crossing of the secondary current, but extends for a short period of time. The extended on-time is the same as the second on-time in DCM mode, the negative current with current ripple is established on the secondary current, the positive current stroke on the secondary current acts as a trigger, and the synchronous rectifier is turned off . In the present description, the delay to the on-time in the critical conduction mode and the second on-time in the discontinuous conduction mode are referred to as the same time, at which time the secondary current reaches zero. At the current value, the synchronous rectifier is turned on.

In the above embodiment, the forced ZVS timing control is configured for the turn-on transient of the primary switch, that is, when the primary switch is turned on, the zero voltage switch at the primary switch is implemented. In other embodiments, a zero voltage switch can be configured to implement a zero voltage switch at the primary switch for the turn-off transient of the primary switch, that is, when the primary switch is open. In an embodiment of the invention, the flyback converter can be equipped with a zero voltage switch for the primary switch turn-on transient and a zero voltage switch for the primary switch turn-off transient. 8(a) through 8(c) show schematic diagrams of a flyback converter configuration for a primary switch with forced zero voltage switching (ZVS) timing control in an alternative embodiment of the invention. 8(a)-8(c), in addition to the need for additional capacitor elements to configure the ZVS for the primary switch-off transient, the configuration of the flyback converters 50a-c and the flyback transformation shown in FIG. The device 10 is the same. Specifically, the flyback converters 50a-c utilize the forced ZVS timing control described above to implement a primary zero voltage switch for the turn-on transient of the primary switch. Similar elements in Figures 5 and 8(a)-(c) will be given reference numerals and will not be described again. Referring first to Figure 8(a), a zero voltage switch is configured for the turn-off transient of the primary switch Q1 in the flyback converter 50a, and the capacitor C11 is coupled in parallel with the primary switch Q1. That is, it is connected between node 14 (the drain of switch Q1) and 18 (ground). When the primary switch Q1 is turned on, the drain-to-source voltage Vds of the primary switch is at zero voltage. When the primary switch Q1 is turned off, the capacitor C11 prevents the drain-to-source voltage Vds from changing immediately. Capacitor C11 maintains the drain-to-source Vds at zero voltage during the off time such that primary switch Q1 opens before the drain-to-source voltage Vds changes. In this case, the zero voltage switch at the primary switch is turned off.

Referring to Figure 8(b), in other embodiments, the flyback converter 50b is provided with a snubber capacitor Csnb coupled to the primary side of the transformer TR to configure a zero voltage switch for the off transient of the primary switch Q1. That is, the capacitor Csnb is connected at node 12 (input voltage Vin) and node 14 (primary switch) Between the extremes). In this case, the snubber capacitor Csnb is used as a non-destructive voltage spike absorber to clamp the voltage generated by the leakage inductance of the transformer TR. In addition, the function of the capacitor Csnb is to ensure that the primary switch Q1 has a zero voltage switch when it is turned on and off. During the primary switch-on transient, the energy stored in capacitor Csnb is again cycled into the input voltage node before the primary switch is turned "on". When the primary switch is turned off, the capacitor Csnb operates in the same manner as capacitor C11 in Figure 8(a), preventing the voltage at the primary switch 汲 terminal (node 14) from switching too fast, thus ensuring the primary switch turn-off transient. Zero voltage switch at the time.

Finally, in the above embodiment, the flyback converter 50 includes a capacitor C11 or a capacitor Csnb. In other embodiments, the flyback converter can be configured with capacitor C11 and capacitor Csnb. Referring to Fig. 8(c), the flyback converter 50c is fabricated using a capacitor C11 and a capacitor Csnb. Capacitors C11 and Csnb operate in the same manner as described above to ensure zero voltage switching at least when primary switch Q1 is turned off.

In the embodiment shown in Figures 8(a) through 8(c), the configuration of the flyback converters 50a-c is a forced ZVS timing control system using zero voltage switching at the primary switching transient, and a primary switch disconnection instant Capacitor C11 or Csnb (or both) for time-varying zero voltage switching. In other embodiments of the invention, the configuration of the flyback converter can use any other zero voltage switching system that turns on the transient with the primary switch, and the capacitor C11 or Csnb for the zero voltage switching of the primary switch disconnect transient (or Both have). Figure 9 shows a schematic diagram of a flyback converter for a zero voltage switch (ZVS) for primary switch disconnect transients in an embodiment of the invention. Referring to Fig. 9, the flyback converter 60 is arranged in the same manner as the flyback converters 50a-c shown in Figs. 8(a)-8(c), but has no positive current detecting circuit for configuring the above primary switch. Turn on the transient forced ZVS timing control system. Conversely, the flyback converter 60 can be configured with any other zero voltage switching system currently known or under development to achieve primary switching turn-on transients. Zero voltage switch. For example, the flyback converter 60 can be configured with the variable frequency (VF) ZVS DCM system mentioned in the above-mentioned Zhang paper to achieve a zero voltage switch of the primary switch-on transient.

At the same time, the produced flyback converter 60 is provided with a capacitor C11 coupled in parallel with the primary switch Q1. Capacitor C11 maintains the drain-to-source voltage Vds at zero voltage when the transient is turned off, allowing the primary switch Q1 to be turned off before the drain-to-source voltage Vds changes. In this case, the ZVS disconnection at the primary switch is achieved. In the present embodiment, the flyback converter 60 also has a buffered capacitor Csnb coupled to the primary side of the transformer TR. The function of the capacitor Csnb is to ensure zero voltage switching of the primary switch Q1 when the transient is switched on and off. During the primary switch-on transient, the energy stored in capacitor Csnb is cycled into the input voltage node before the primary switch is turned "on". When the primary switch is turned off, the capacitor Csnb operates in the same manner as capacitor C11, preventing the voltage at the primary switch 汲 terminal (node 14) from switching too fast, thus ensuring zero voltage switching at the primary switch open transient. .

In FIG. 9, the flyback converter 60 includes capacitors C11 and Csnb. In other embodiments of the invention, flyback converter 60 may be fabricated using only capacitor C11 or only capacitor Csnb to achieve at least an open transient to the primary switch, a zero voltage switch at the primary switch. The use capacitor C11 and capacitor Csnb shown in Fig. 9 are for illustrative purposes only and are not intended to be limiting.

As described above, the flyback converter with the primary switch and the synchronous rectifier is alternately turned on and off during one switching cycle. The controller generates a time signal that synchronizes the switching of the primary switch and the synchronous rectifier. For example, when the synchronous rectifier is turned off, the primary side controller must be notified to turn on the primary switch. In a conventional flyback converter, a photocoupler or an isolating transformer is used to control the time signal. However, these circuit components are very expensive and take up a large amount of circuit area.

In an embodiment of the invention, the flyback converter implements an automatic synchronization method for controlling the time signal. In forced ZVS operation, the synchronous rectifier is turned on for a second on-time and then turned off. When the synchronous rectifier is turned off at the second on-time, the secondary current is transferred to the primary transformer winding such that the primary current is free to cross the body diode D1 of the primary switch Q1. The automatic synchronization method of the present invention senses the primary current and detects the freewheeling current after the second on-time of the synchronous rectifier is activated. After detecting the freewheeling current after the second on-time of the synchronous rectifier is initiated, the automatic synchronization method generates a current sensing signal indicating that the synchronous rectifier is off. The primary side controller can use the current sense signal as a control time signal to turn on the primary switch for the next switching cycle. In some embodiments, the freewheeling current is sensed by sensing a current value above a certain threshold.

In an alternative embodiment of the invention, the flyback converter is configured with output voltage sensing at the primary side of the transformer. Specifically, in forced ZVS operation, the synchronous rectifier is turned on for a second on-time and then turned off. When the synchronous rectifier is turned on at the second on time, the voltage on the primary transformer blocks the output voltage Vout. Therefore, the primary side controller can sample the voltage on the primary winding of the transformer during the second on-time of the synchronous rectifier as an indication of the output voltage and control the duty cycle of the primary switch using the sampled voltage value. The output voltage sensing method of the present invention is extremely useful for voltage mode control and maintains a stable output voltage at the output of the flyback converter.

Figure 10 shows a flow chart of a forced ZVS time control method with a positive current synchronous rectifier turn-off trigger in an embodiment of the invention. The forced ZVS method can be configured in a flyback converter, such as the flyback converters 10 and 50 shown in Figures 5 and 8. Referring to Figure 10, the forced ZVS method 200 initiates a switching cycle by turning on the primary switch (202). The method 200 turns off the primary switch after the turn-on time TON (204). The method 200 turns on the synchronous rectifier after the non-overlapping gap time (206). The method 200 senses the secondary current, and the method 200 turns off the synchronous rectifier (208) based on the secondary current reaching a zero current value. The method 200 continues to monitor the output voltage and the flyback converter operates in a discontinuous conduction mode (210). The method senses the output voltage VOUT to determine when the output voltage VOUT is less than the reference voltage VREF (212). When the output voltage VOUT is equal to or less than the reference voltage VREF, the method 200 turns on the synchronous rectifier second on time and continues to monitor the secondary current (214). Method 200 performs detection when the secondary current has a positive current value (216). Method 200 turns off synchronous rectifier (218) based on the secondary current having a positive current value. The method 200 waits for the turn-off time of the primary switch (220) to end, the next switch cycle repeats, and the method 200 repeats at 202 to turn the primary switch on.

Figure 11 shows a flow chart of a forced ZVS time control method with a positive current synchronous rectifier turn-off trigger in an alternate embodiment of the present invention. Specifically, FIG. 11 shows that in the embodiment of the present invention, the automatic synchronization method is used in the forced ZVS time control method. Referring to Figure 11, the forced ZVS method 250 initiates a switching cycle by turning on the primary switch (252). The method 250 turns off the primary switch after the turn-on time TON (254). The method 250 turns the synchronous rectifier on after the non-overlapping gap time (256). Method 250 senses the secondary current, and based on the secondary current reaching a zero current value, method 250 opens the synchronous rectifier (258). The method 250 continues to monitor the output voltage and the flyback converter operates in a discontinuous conduction mode (260). The method senses the output voltage VOUT to determine that when the output voltage VOUT is less than the reference voltage VREF, the method 250 turns on the synchronous rectifier second on-time and continues to monitor the secondary current (264). Method 250 performs a detection when the secondary current has a positive current value (266). Method 250 turns off synchronous rectifier (268) based on the secondary current having a positive current value. Method 250 senses the primary current and detects that the primary current value is above a specified threshold, indicating that the synchronous rectifier has been turned off (270). Method 250 repeats at 252 based on the sensed primary current being above a specified threshold, turning the primary switch on for the next switching cycle.

Figure 12 is a flow diagram showing a forced ZVS time control method with a positive current synchronous rectifier turn-off trigger in an alternate embodiment of the present invention. The forced ZVS method can be configured in a flyback converter, such as the flyback converters 10 and 50 shown in Figures 5 and 8. See Figure 12, forced ZVS method The switching cycle is initiated by turning on the primary switch (302). The method 300 turns off the primary switch after the on time TON (304). The method 300 turns on the synchronous rectifier after the non-overlapping gap time (306). Method 300 detects that the secondary current reaches a zero current value and the flyback converter operates in a critical conduction mode (308). The method 300 maintains the synchronous rectifier on for a second on-time and continues to monitor the secondary current (310). Method 300 performs detection when the secondary current has a positive current value (312). Method 300 turns off synchronous rectifier (314) based on the secondary current having a positive current value. Method 300 senses the primary current and detects that the primary current value is above a specified threshold, indicating that the synchronous rectifier is open (316). Based on the sensed primary current being above a specified threshold, method 300 repeats at 302 to turn the primary switch on for the next switching cycle.

Automatic synchronization is configured in the embodiment shown in FIG. In other embodiments, the forced ZVS time control method can be used for a flyback converter in critical conduction mode without the use of an automatic synchronization method.

Although the embodiments have been described in detail above for the sake of clarity, the present invention is not limited to the details described above. There are many alternatives for implementing the invention. The examples herein are for illustrative purposes only and are not intended to be limiting.

Claims (16)

A method of operating a forced zero voltage switching flyback converter, the converter comprising a transformer having a primary winding receiving an input voltage and a secondary winding providing an output voltage, the primary switch being coupled to the primary winding, the synchronous rectifier coupling To the secondary winding, the method includes: turning on the first duration of the primary switch at the beginning of the switching cycle; turning on the first on-time of the synchronous rectifier; sensing the secondary current flowing in the secondary winding; The current reaches the zero current value, and the synchronous rectifier is turned off; in the discontinuous conduction mode, the output voltage is monitored; according to the output voltage being less than the reference voltage, the synchronous rectifier is turned on for the second on time; and during the second on time, the sensing is performed. a secondary current flowing in the secondary winding, the secondary current comprising a current ripple having a negative current stroke and a positive current stroke; and a secondary current having a positive current value according to the second on-time, disconnecting the synchronous rectifier; crossing a primary switch coupling a first capacitor; a first capacitor coupled in parallel with the primary switch and depending on the primary switch Coupling the first capacitor, disconnecting the primary switch at the primary switch zero voltage; coupling the second capacitor across the primary winding of the transformer; the second capacitor is connected between the input voltage and the 汲 terminal of the primary switch, and according to the primary The winding, coupled to the second capacitor, opens the primary switch at zero voltage of the primary switch. The method of claim 1, further comprising: starting the next switch according to the off period of the primary switch, and starting the next one by repeating the turning on of the primary switch During the switching cycle, the primary switch is turned on at zero voltage of the switch. The method of claim 1, further comprising: sensing the primary current according to the synchronous rectifier being turned on for the second on-time; and starting the next switching cycle by repeating the turning on of the primary switch according to the primary current exceeding the threshold . The method of claim 1, wherein turning on the synchronous rectifier for the first on-time comprises turning the synchronous rectifier on after a non-overlapping time. The method of claim 1, wherein the first duration of the primary switch is turned on at the beginning of the switching cycle, comprising: turning the primary switch on for a fixed on-time at the beginning of the switching cycle. A method of operating a forced zero voltage switching flyback converter, the converter comprising a transformer having a primary winding receiving an input voltage and a secondary winding providing an output voltage, the primary switch being coupled to the primary winding, the synchronous rectifier coupling To the secondary winding, the method includes: turning on the first duration of the primary switch at the beginning of the switching cycle; turning on the first on-time of the synchronous rectifier; and sensing the flow in the secondary winding in the critical conduction mode Secondary current; according to the secondary current reaching zero current value, extending the on-time of the synchronous rectifier by the second on-time; during the second on-time, sensing the secondary current flowing in the secondary winding, the secondary current includes a current ripple having a negative current stroke and a positive current stroke; and a secondary current having a positive current value according to the second on-time, opening the synchronous rectifier; coupling the first capacitor across the primary switch; and depending on crossing the primary switch a first capacitor is coupled to disconnect the primary switch at zero voltage of the primary switch; A second capacitor is coupled across the primary winding of the transformer; and the second capacitor is coupled according to the primary winding across the transformer, and the primary switch is turned off at zero voltage of the primary switch. The method of claim 6, further comprising: starting the next switching cycle by repeating the turning on of the primary switch according to the off time of the primary switch. The method of claim 6, further comprising: sensing the primary current according to the synchronous rectifier being turned on for the second on-time; and starting the next switching cycle by repeating the turning on of the primary switch according to the primary current exceeding the threshold . The method of claim 6, wherein the first on-time of the synchronous rectifier is turned on, including after a non-overlapping period, the synchronous rectifier is turned on. The method of claim 6, wherein turning on the primary switch at the beginning of the switching period of the first on-time comprises: turning on the primary switch for a fixed on-time at the beginning of the switching cycle. A flyback converter includes: a transformer having a primary winding receiving an input voltage and a secondary winding providing an output voltage; a primary switch coupled to the primary winding; and a synchronous rectifier coupled to the secondary winding; An output capacitor coupled across the secondary winding and the synchronous rectifier; a controller coupled to generate a control signal to drive the primary switch and the synchronous rectifier; and a positive current sensing circuit to sense secondary current flowing in the secondary winding, according to the detection To a secondary current with a positive current value, generating a detection signal, The controller generates a control signal, alternately turns on and off the primary switch and the synchronous rectifier in one switching cycle, and the synchronous rectifier turns on the first on-time in the switching cycle, and controls the secondary current to reach a zero current value according to the detected The controller generates a control signal, and turns on the second on-time of the synchronous rectifier during the switching period, the positive current detecting circuit senses the secondary current in the second on-time, and generates a detection signal according to the detection of the secondary current having the positive current value. And according to the detection signal, during the switching period, the synchronous rectifier is turned off, a first capacitor coupled across the primary switch, wherein the primary switch is turned off at zero voltage of the primary switch according to coupling the first capacitor across the primary switch, A second capacitor coupled across the primary winding of the transformer, wherein the primary switch is turned off at zero voltage of the primary switch in accordance with coupling the second capacitor across the primary winding. The flyback converter of claim 11, wherein the controller runs the flyback converter in the discontinuous conduction mode, the controller generates a control signal, and disconnects the synchronous rectifier according to the detection that the secondary current reaches a zero current value. The controller continues to monitor the output voltage. According to the output voltage being equal to or lower than the reference voltage, the controller generates a control signal to turn on the second on-time of the synchronous rectifier during the switching period. The flyback converter of claim 11, wherein the controller runs the flyback converter in the critical conduction mode, and the controller generates a control signal, according to detecting that the secondary current reaches a zero current value, during the switching period, Extend the on-time of the synchronous rectifier for the second on-time. The flyback converter of claim 11, wherein the next switching cycle is initiated by repeating the turning-off of the primary switch according to the off time of the primary switch, the primary switch being turned on at the zero voltage of the switch. The flyback converter of claim 11, wherein the controller senses the primary current according to the synchronous rectifier being turned on for the second on time, and repeats the primary according to the primary current exceeding the threshold The switch is turned on to start the next switching cycle. The flyback converter of claim 11, wherein the controller generates a control signal to cause the primary switch to be turned on for a fixed on time.