TWI652819B - A heat-dissipating package having graphene for power amplifier chip - Google Patents

Abstract

A graphene heat dissipating structure for a power amplifier chip, comprising a collector heterojunction transistor and a graphene layer having a non-uniform doped collector, the upper collector heterojunction transistor comprising a substrate, a sub-shot a pole, an emitter, an insulating layer and a plurality of stacked structures, the hole walls of the substrate define a perforation, the stacked structure is disposed on the insulating layer and the position corresponds to the perforation, and the stacked structure comprises a gradual base, a gradation layer, and a non-uniform doping set a pole, a cover layer and a collector electrode, and a space layer is disposed between the emitter, the insulating layer and the gradual base of each stacked structure, and the graphene layer covers the lower surface of the substrate, the hole wall of the substrate, and the sealing segment of the secondary emitter The heat dissipation capability of the heat dissipation assembly is good, and the thermal runaway and collapse effects of the power amplifier can be avoided, and the performance of the power amplifier in the wireless communication industry can be improved.

Description

Graphene heat dissipation assembly for power amplifier wafers

The present invention relates to a heat dissipating structure for a power amplifier wafer, and more particularly to a graphene heat dissipating structure for a power amplifier wafer.

Power Amplifier is an important component in RF transmission circuits. Its main function is to amplify the signal and usually design it at the front end of the antenna emitter. At present, semiconductor components used in power amplifiers are quite diverse. Among them, Heterojunction Bipolar Transistor (HBT) has advantages of high operating frequency, high power, low noise, high speed, high current density, and good linearity. It has become the mainstream technology of power amplifiers and is widely used in various wireless communication components.

With the increasing popularity of wireless communication and the development of miniaturized communication equipment, the production of power amplifiers will be more dense, but in the limited space high-frequency operation will be accompanied by a large amount of thermal energy, even the current mainstream heterojunction Crystal power amplifiers are also difficult to avoid thermal runaway and crash effects, which affect the normal operation of the power amplifier.

This "Prior Art" section is only intended to aid in understanding the present invention, and thus the disclosure of the prior art may include prior art that is not known to those of ordinary skill in the art. In addition, the content disclosed in the "Prior Art" does not represent the problem to be solved by the content or one or more embodiments of the present invention, nor does it mean that those having ordinary knowledge in the technical field before the application of the present invention Know or recognize.

The object of the present invention is to provide a graphene heat dissipating structure, which has good heat dissipation capability, thereby effectively avoiding thermal runaway and collapse effects of the power amplifier, so that the power amplifier can be applied to a limited space and a high frequency working environment.

In order to achieve the above object, the technical means adopted by the present invention is such that the graphene heat dissipating structure comprises an upper collector type heterojunction transistor and a graphene layer. The upper collector heterojunction transistor comprises a substrate, a secondary emitter, an emitter, an insulating layer and a plurality of stacked structures. The substrate includes an upper surface, a lower surface opposite to the upper surface, and a hole wall; the hole wall connects the upper surface and the lower surface, and the hole wall defines a perforation. The secondary emitter is stacked on the upper surface, and the secondary emitter has a sealing section, and the sealing section closes one end of the perforation. The emitter is superposed on the secondary emitter. The insulation is laminated on the emitter. The stacked structures are spaced apart on the insulating layer and correspond to the perforations, and each stacked structure comprises a gradual base, a gradation layer, a non-uniform doped collector, a cover layer and a collector electrode, a gradual base, a gradation layer, and a non- The uniformly doped collector, the cover layer and the collector electrode are sequentially stacked on the emitter, and the non-uniformly doped collector comprises a first doped layer and a second doped layer, the first doped layer and the second doped layer The impurity layer is sequentially stacked on the graded layer, and the doping concentration of the second doped layer is lower than the doping concentration of the first doped layer, and the capping layer is disposed on the second doped layer. A space layer is disposed between the emitter, the insulating layer, and the graded base of each stacked structure. The graphene layer covers the lower surface, the pore walls and the sealing segments.

In an embodiment of the invention, the substrate, the graded base and the non-uniformly doped collector comprise gallium arsenide (GaAs), the emitter comprises indium phosphide (InGaP), and the collector electrode comprises indium gallium arsenide (InGaAs) ).

In an embodiment of the invention, the indium contained in the emitter is 45% to 55% based on indium and gallium contained in the emitter.

In an embodiment of the invention, the insulating layer comprises hafnium oxide (SiO ₂ ).

In an embodiment of the invention, the heat dissipating structure having the upper collector type heterojunction transistor and the graphene further comprises a collector wiring layer stacked on the collector layer and the collector electrode of each stacked structure.

In an embodiment of the invention, the collector wiring layer comprises gold, that is, the collector wiring layer may be made of a gold-containing material, such as pure gold or a gold-containing alloy.

In an embodiment of the invention, the upper collector heterojunction transistor may be of the NPN type or the PNP type.

In an embodiment of the invention, the upper collector heterojunction transistor is of the NPN type, and the characteristic contact resistance of the gradual base is 1×10 ^-7 Ω-cm ² to 3×10 ^-6 Ω-cm ² .

In an embodiment of the invention, the upper collector heterojunction transistor is of a PNP type, and the characteristic contact resistance of the graded base is 1×10 ^-7 Ω-cm ² to 5×10 ^-7 Ω-cm. ² .

By using the graphene layer, the heat dissipating structure of the invention has a good heat dissipating effect, so that the thermal energy can be effectively discharged outward when the heat energy is generated, and the overall temperature of the heat dissipating structure is lowered, thereby avoiding thermal runaway of the power amplifier. The occurrence of the collapse effect is beneficial to the application of power amplifiers in limited space and high frequency environments.

The above and other objects, features and advantages of the present invention will become more <RTIgt;

The above and other technical contents, features and advantages of the present invention will be apparent from the following detailed description of the preferred embodiments. The directional terms mentioned in the following embodiments, for example, up, down, etc., refer only to the direction of the additional drawing. Therefore, the directional terminology used is for the purpose of illustration and not limitation.

Example 1 Graphene heat dissipation structure

Referring to FIG. 1 , in the present embodiment, the graphene heat dissipation structure of the present invention comprises an upper collector heterojunction transistor 10 , a collector wiring layer 20 and a graphene layer 30 .

Referring to FIG. 1 , the upper collector heterojunction transistor includes a substrate 11 , a secondary emitter 12 , an emitter 13 , an insulating layer 14 , a plurality of stacked structures, and a spatial layer 16 . The substrate 11 includes an upper surface 111, a lower surface 112 opposite to the upper surface 111, and a hole wall 113. The hole wall 113 connects the upper surface 111 and the lower surface 112, and the hole wall 113 defines a through hole 114, and both ends of the through hole 114 are adjacent to the upper surface 111 and the lower surface 112. The sub-emitter 12 is superposed on the upper surface 111, and the sub-emitter 12 has a sealing section 121 that closes one end of the perforation 114 and the upper surface 111. The emitter 13 is superposed on the secondary emitter 12. The insulating layer 14 is stacked on the emitter 13.

Referring to FIG. 1 , the stacked structures are spaced apart from each other through the insulating layer 14 , and the stacked structures are located directly above the through holes 114 ; in other words, the stacked structures correspond to the positions of the through holes 114 . Each stack structure includes a graded base 151, a graded layer 152, a non-uniformly doped collector 153, a cover layer 154, and a collector electrode 155. The graded base 151 is stacked on the emitter 13 and the graded layer 152 is stacked on the graded base. On the pole 151, the non-uniformly doped collector 153 is stacked on the graded layer 152, the cover layer 154 is stacked on the non-uniformly doped collector 153, and the collector electrode 155 is stacked on the cover layer 154. Further, the non-uniformly doped collector 153 includes a first doped layer 153A and a second doped layer 153B. The first doped layer 153A is stacked on the graded layer 152, and the second doped layer 153B is stacked on the first layer. On a doped layer 153A, and the doping concentration of the second doping layer 153B is higher than the doping concentration of the first doping layer 153A, the capping layer 154 is stacked on the second doping layer 153B. Further, the gradation base 151, the gradation layer 152, the non-uniform doped collector 153, the cap layer 154, and the collector electrode 155 are in contact with the insulating layer 14.

Referring to FIG. 1 , the space layer 16 is disposed between the emitter 13 , the insulating layer 14 and the grading base 151 of each stacked structure, and the stacked structure and the collector wiring layer 20 are simultaneously stacked on the insulating layer 14 and the stacked structures. On the collector electrode 155.

Referring to FIG. 1, the graphene layer 30 covers the lower surface 112, the hole wall 113 and the sealing segment 121, and the graphene layer 30 is made of graphene.

In this embodiment, the substrate 11, the graded base 151 and the non-uniformly doped collector 153 are made of gallium arsenide, the emitter 13 is made of indium gallium phosphide, and the collector electrode 155 is made of arsenic. Made of indium gallium, the insulating layer 14 is made of cerium oxide (SiO ₂ ), and the collector wiring layer 20 is made of a gold alloy. The upper collector heterojunction transistor 10 is of the NPN type, that is, the non-uniform doped collector 153 is N-type, the graded base 151 is P-type, and the emitter 13 is N-type.

In the present embodiment, the gallium arsenide/indium gallium phosphide (GaAs/InGaP) material system used in the upper collector heterojunction transistor 10 is disordered by lattice matching with gallium arsenide (disorderd). Indium gallium phosphide; that is, in the present embodiment, the indium gallium phosphide of the emitter 13 is disordered. The indium contained in the emitter 13 accounts for 50% of the total amount of indium and gallium contained in the emitter 13.

In this embodiment, the graded base 151 made of gallium arsenide can reduce the base transit time to achieve high speed performance, and the non-uniformly doped collector 153 (the first doped with different doping concentrations) The impurity layer 153A and the second doping layer 153B) can redistribute the electric field to promote current processing capability, and the insulating layer 14 made of cerium oxide can reduce interconnect parasitic capacitance and contribute to the second metal. The flattening of the process.

In the present embodiment, the graphene layer 30 is formed on the lower surface 112, the hole wall 113, and the sealing section 121 by chemical vapor deposition. Further, the characteristic contact resistance of the graded base 151 is 3 × 10 ^-6 ohm-cm 2 (Ω-cm ² ).

Example 2 Graphene heat dissipation structure

This embodiment is the same as Embodiment 1. However, this embodiment differs from Embodiment 1 in that, in this embodiment, the upper collector type heterojunction transistor 10 is of a PNP type, that is, non-uniformly doped. The impurity collector 153 is P-type, the gradual base 151 is N-type, the emitter 13 is P-type, and the gradual base 151 has a characteristic contact resistance of 5×10 ^-7 Ω-cm ² .

Comparative example: heat-dissipating structure without graphene

This comparative example is the same as that of the first embodiment except that the comparative example is different from the first embodiment in that the heat dissipating structure having no graphene of the comparative example does not have the graphene layer 30, that is, the comparative example. The lower surface 112 of the substrate 11 having no heat dissipation of graphene, the hole wall 113 of the substrate 11, and the sealing segment 121 of the secondary emitter 12 are not covered with the graphene layer 30.

Test Example 1 Raman Spectral Analysis

Raman spectroscopy analysis of the graphene layer 30 provided on the lower surface 112 of the substrate 11, the hole wall 113 of the substrate 11, and the sealing segment 121 of the sub-emitter 12 of the graphene heat-dissipating structure of Example 1 in this test example To examine the quality of the graphene layer 30. The Raman spectrum of the graphene layer 30 of the graphene heat dissipating structure of Example 1 obtained in this test example is shown in Fig. 2.

Referring to FIG. 2, the graphene layer 30 of the graphene heat dissipating structure of Embodiment 1 has a distinct characteristic peak 2D (between 2500 cm ^-1 and 2800 cm ^-1 ) and a characteristic peak G (at 1600 cm ^{- 1} ), and the intensity of the characteristic peak 2D is significantly larger than the characteristic peak G (at 1600 cm ^-1 ), and thus it can be seen that the graphene layer 30 of the graphene heat-dissipating structure of Example 1 does have good quality.

Test Example 2 Metallographic analysis

In the test example, the graphene layer 30 of the graphene heat-dissipating structure of Example 1 was subjected to metallographic observation to examine the bonding strength of the graphene layer 30 and the substrate 11. An optical micrograph of the graphene layer 30 of the graphene heat dissipating structure of Example 1 obtained in the present test example is shown in Fig. 3. It can be observed from FIG. 3 that the graphene layer 30 of the heat dissipating structure of Embodiment 1 does not have a significant peeling or bulging condition, that is, the graphene layer 30 is well adhered to the substrate 11, thereby showing that graphene The bonding of the layer 30 to the substrate 11 is good.

Test Example 3 Thermal Characteristics Analysis In this test example, the thermal characteristics of the graphene heat dissipating structure of Example 1 and the heat dissipating structure of the comparative example without graphene were analyzed by ANSYS analysis to obtain the temperature distribution of the two after the same input heat energy. Figure to compare the heat dissipation between the two. The temperature distribution obtained in this test example is shown in Figs. 4A and 4B.

4A is a temperature distribution diagram of the graphene heat dissipation structure of the first embodiment, and FIG. 4B is a temperature distribution diagram of the heat dissipation structure of the comparative example 1 having no graphene. Comparing FIG. 4A and FIG. 4B, when The same thermal energy is input from the top (non-uniformly doped collector 153, please refer to FIG. 1 at the same time), and the graphene heat dissipating structure of the first embodiment is compared with the comparative example of the heat dissipating structure without graphene. The low temperature distribution block is obviously wider, that is, the overall temperature of the graphene heat dissipating structure of the embodiment 1 is lower, and thus the heat dissipation capability of the graphene heat dissipating structure of the embodiment 1 is significantly better than that of the comparative example. Does not have the heat dissipation structure of graphene.

It can be seen from the above that, by using the graphene layer 30, the graphene heat dissipating structure of the invention has a good heat dissipating effect, so that it can effectively discharge outward when the heat energy is generated, thereby reducing the overall temperature of the heat dissipating structure, thereby avoiding The thermal runaway and collapse effects of power amplifiers facilitate the application of power amplifiers in both limited and high frequency environments.

The above is only the preferred embodiment of the present invention, and the scope of the invention is not limited thereto, that is, the simple equivalent changes and modifications made by the scope of the invention and the description of the invention are All remain within the scope of the invention patent. In addition, any of the objects or advantages or features of the present invention are not required to be achieved by any embodiment or application of the invention. In addition, the abstract sections and headings are only used to assist in the search of patent documents and are not intended to limit the scope of the invention.

10‧‧‧Upper collector heterojunction transistor

11‧‧‧Substrate

111‧‧‧Upper surface

112‧‧‧ lower surface

113‧‧‧ hole wall

114‧‧‧Perforation

12‧‧‧ times emitter

121‧‧‧Seal section

13‧‧‧ emitter

14‧‧‧Insulation

151‧‧‧graded base

152‧‧‧graded layer

153‧‧‧non-uniform doped collector

153A‧‧‧First doped layer

153B‧‧‧Second doped layer

154‧‧‧ Coverage

155‧‧‧ Collector electrode

16‧‧‧Space layer

20‧‧‧ Collector wiring layer

30‧‧‧graphene layer

D, 2D, G‧‧‧ characteristic peak

1 is a side cross-sectional view of a graphene heat dissipating structure of the present invention; FIG. 2 is a Raman spectrum diagram of a graphene layer of a graphene heat dissipating structure according to Embodiment 1 of the present invention; FIG. 3 is an embodiment of the present invention. 1 is an optical micrograph of a graphene layer of a graphene heat dissipating structure; FIG. 4A is a temperature distribution diagram of thermal characteristics analysis of a graphene heat dissipating structure of Embodiment 1 of the present invention; and FIG. 4B is a comparative example of the present invention. Temperature profile for thermal analysis without the heat dissipation profile of graphene.

Claims (8)

A graphene heat dissipating structure for a power amplifier chip, comprising: an upper collector type heterojunction transistor, comprising: a substrate comprising: an upper surface; a lower surface opposite to the upper surface; And a hole wall connected between the upper surface and the lower surface, the hole wall defining a perforation; a primary emitter superposed on the upper surface and having a mouth segment, the sealing segment closing the perforation An emitter is stacked on the emitter; an insulating layer is stacked on the emitter; a plurality of stacked structures, the stacks are spaced apart from the insulating layer and the positions correspond to the through holes Each stacked structure includes: a graded base stacked on the emitter; a graded layer superposed on the graded base; a non-uniformly doped collector stacked on the graded layer and including a first doped layer stacked on the graded layer; and a second doped layer stacked on the first doped layer, and the doping concentration of the second doped layer is lower than a doping concentration of the first doped layer; and a cap layer, Provided on the second doped layer, wherein a space layer is disposed between the emitter, the insulating layer, and the gradual base of each stacked structure; and a collector electrode is stacked on the cover layer; a graphene layer covering the lower surface, the pore wall and the sealing segment. The graphene heat dissipation package for a power amplifier chip according to claim 1, wherein the substrate, the graded base and the collector comprise gallium arsenide, the emitter comprises indium gallium phosphide, and the collector electrode comprises Indium gallium arsenide. The graphene heat dissipating structure for a power amplifier chip according to claim 2, wherein the indium contained in the emitter is 45% to 55% based on indium and gallium contained in the emitter. A graphene heat dissipating structure for a power amplifier wafer according to claim 1, wherein the insulating layer comprises hafnium oxide. The graphene heat dissipating structure for a power amplifier chip according to claim 1, further comprising a collector wiring layer, wherein the collector wiring is laminated on each of the stacked structures and the insulating layer. A graphene heat dissipation package for a power amplifier wafer according to claim 5, wherein the collector wiring layer comprises gold. The graphene heat dissipating structure for a power amplifier chip according to claim 1, wherein the upper collector heterojunction transistor is of an NPN type, and the characteristic contact resistance of the gradual base is 1×10 ^-7 Ω. -cm ² to 3 x 10 ^-6 Ω-cm ² . The graphene heat dissipating structure for a power amplifier chip according to claim 1, wherein the upper collector heterojunction transistor is of a PNP type, and the characteristic contact resistance of the graded base is 1×10 ^-7 Ω. -cm ² to 5 x 10 ^-7 Ω-cm ² .