TWI649749B - Method for obtaining optimal operating condition of resistive random access memory - Google Patents

Abstract

The present invention provides a method for finding the optimal operating conditions of a resistive random access memory (RRAM), comprising: taking an RRAM wafer, and performing a molding operation and initial weight on the RRAM wafer according to the first operating condition. The RRAM wafer is divided into a plurality of blocks; the foregoing blocks are individually set based on a plurality of operating voltages; the error bit values in each block are obtained; and the error bit values in each block are as described above. The operating voltage produces an operating characteristic curve associated with the RRAM wafer, wherein the operating characteristic curve has the lowest error bit value and the operating voltage interval; and when the lowest error bit value meets the first condition and the operating voltage interval meets the second condition, determining the foregoing The first operating condition is the optimum operating conditions for the RRAM wafer.

Description

Method for finding the optimal operating conditions of resistive random access memory

The present invention relates to a method for finding the optimal operating conditions of a memory, and in particular to a forming operation condition and an initial reset operation for finding a resistive random access memory (RRAM). Conditional method.

The RRAM is a non-volatile memory in which the RRAM cells each include an upper electrode plate, a lower electrode plate, and a dielectric material layer sandwiched between the upper and lower electrode plates. The layer of dielectric material is typically insulative, and by applying a suitable voltage to the upper electrode plate to form a memory cell, a conductive path through the layer of dielectric material can be formed in the layer of dielectric material (commonly referred to as It is a conductive filament (CF). Once the conductive filament is formed, it can be reset by applying an appropriate voltage on the upper electrode plate (ie, the conductive wire is broken or broken, resulting in a high resistance state on the RRAM cell (high resistance). State, HRS).

Thereafter, the RRAM cell can be set up by applying an appropriate voltage to the upper electrode plate (i.e., the conductive filament is reformed, resulting in a low resistance state (LRS) on the RRAM cell). The RRAM resistance state (LRS or HRS) can be controlled by repeated set operations and reset operations. The LRS and HRS can be used to indicate a digital signal of "0" or "1" to provide associated memory functions.

In the prior art, since the process of the RRAM and the materials used are changing with each passing day, how to find the proper operating conditions quickly and effectively has become a very important issue in the RRAM development process. If poor operating conditions are used, it is likely to cause factors related to the material misjudgment during the test, which will affect the development time and performance of the RRAM. For RRAMs produced by different processes and materials, since the molding operation and the initial reset operation are the key steps in determining the conductive wire pattern, it is possible to find out the proper molding operation and initial reset. The operating voltage range will facilitate the formation of a preferred conductive filament to provide a good conductive path.

In view of this, the embodiment of the present invention provides a method for finding the optimal operating condition of the resistive random access memory, which can draw a corresponding operation of the RRAM wafer after undergoing a molding operation and an initial voltage operation according to a specific mechanism. The characteristic curve is operated and it is determined whether the above-described molding operation and initial voltage operation are the optimum operating conditions of the RRAM wafer.

The present invention provides a method for finding the optimal operating conditions of a resistive random access memory, comprising: obtaining a first resistive random access memory chip, and randomly storing the first resistive memory according to a first operating condition Taking a memory wafer for performing a first molding operation and a first initial reset operation; dividing the first resistive random access memory wafer into a plurality of first blocks; and the first block based on the plurality of operating voltages Performing a setting operation individually; obtaining a first error bit value in each first block; generating a correlation with the first resistive random access according to the first error bit value in each first block and the foregoing operating voltage a first operational characteristic of the memory chip, wherein the first operational characteristic has a first lowest error bit value and a first operational voltage interval; and when the first lowest error bit value meets a first condition and When an operating voltage interval meets a second condition, the first operating condition is determined to be a first optimal operating condition of the first resistive random access memory chip.

Based on the above, the method of the embodiment of the present invention can perform different setting operations on different blocks on the RRAM wafer based on a plurality of different operating voltages after performing the molding operation and the initial reset operation on the RRAM wafer. After that, the error bit value on each block can be counted and the operating characteristic curve of the RRAM chip can be drawn, and based on whether the operating characteristic curve meets the first condition and the second condition, the RRAM wafer is initially subjected to the molding operation and the initial weight. Whether the operating conditions of the operation are appropriate.

The above described features and advantages of the invention will be apparent from the following description.

Referring to FIG. 1, if the RRAM memory cell is subjected to an excessively low molding voltage during the molding operation, the formed conductive wire is made too thin and thus easily broken. On the other hand, if the RRAM memory cell is subjected to an excessively heavy forming voltage in the molding operation, the formed conductive wire will be made too thick, thereby causing too many conductive paths and increasing the difficulty in control. Therefore, if a more ideal molding operation condition (for example, a molding voltage) can be found, the formed conductive yarn can be made to have a better circumference, thereby providing a better conductive path.

Referring to FIG. 2, in general, the initial reset operation on the RRAM memory cell will determine the performance of the RRAM memory cell to switch back to the resistance state (ie, switching from HRS to LRS or from LRS to HRS). ).

As shown in FIG. 2, if the RRAM memory cell is subjected to an excessive initial reset voltage during the initial reset operation, a short and narrow gap 21 will appear between the reset conductive wire and the upper electrode plate. In this case, if the RRAM memory cell is set to switch to LRS, it is likely that the RRAM memory cell has an over-set state.

Conversely, if the RRAM memory cell is subjected to an excessive initial reset voltage during the initial reset operation, a long and wide gap 22 will occur between the reset conductive filament and the upper electrode plate. In this case, even if the RRAM memory cell is set, it may be difficult to smoothly switch the RRAM memory cell to the LRS, that is, the set under-set state occurs. Therefore, if a better initial reset operating condition (for example, an initial reset voltage) can be found, the gap between the formed conductive wire and the upper electrode plate can be better, thereby facilitating subsequent operations. Resistance state switching operation.

In view of this, the present invention proposes a method for finding the optimum operating conditions of an RRAM, which can be used to find the optimum forming voltage and the optimum initial reset voltage that are most suitable for the RRAM wafer, and thus the individual memory cells of the RRAM wafer. Formed into an ideal conductive filament pattern.

Referring to FIG. 3 and FIG. 4, first, in step S310, the first RRAM wafer 40 can be obtained, and the first RRAM wafer 40 is subjected to a molding operation and an initial reset operation according to the first operating condition. In this embodiment, the first RRAM wafer 40 may include a plurality of RRAM memory cells, and the foregoing first operating conditions include, for example, a first molding voltage and a first initial reset voltage. After the forming operation and the initial reset operation of the first RRAM wafer 40, the respective RRAM memory cells on the first RRAM wafer 40 should have formed one of the conductive filament patterns as shown in FIG.

Thereafter, in step S320, the first RRAM wafer 40 can be divided into a plurality of blocks 401a, 401b, ..., and 401p. In this embodiment, the first RRAM wafer 40 can be divided into, for example, 16 blocks 401a, 401b, ..., and 401p having the same size, but in other embodiments, the first RRAM wafer 40 can also be designed by the designer. It is required to be divided into NxM (N, M are positive integers) blocks of the same size, as long as each block can reflect the wafer characteristics of the first RRAM wafer 40, but the present invention is not limited thereto. The blocks 401a, 401b, ..., and 401p may individually include A memory cell pages, and each memory cell page may include B RRAM memory cells, that is, the blocks 401a, 401b, ..., and 401p may individually include AxB RRAM memory cells.

Next, in step S330, the setting operations can be individually performed on the blocks 401a, 401b, ..., and 401p based on the plurality of operating voltages. In the present embodiment, the aforementioned operating voltage refers to a setting operation and a reset operation, and is, for example, a gate voltage VG corresponding to each of the blocks 401a, 401b, ..., and 401p, that is, applied to each of the blocks 401a, 401b, ...and the word line voltage of the RRAM memory cell in 401p, but is not limited thereto.

As shown in FIG. 4, the gate voltage VG of the present embodiment can be first applied to the block 401a with an initial value a to perform a setting operation on the block 401a, so that the RRAM memory cell in the block 401a can be disabled once. Value transition (ie, HRS switches to LRS). Then, the gate voltage VG can be incremented to a+d based on the step value d, and then applied to the block 401b to perform the setting operation on the block 401b, so that the RRAM memory cell in the block 401b can be performed once. Sexual resistance. Thereafter, the gate voltage VG can be incremented again to a+2d based on the step value d, and then applied to the block 401c to perform a setting operation on the block 401c, so that the RRAM memory cell in the block 401c can be performed. One-time resistance change. In various embodiments, the values of a, d can be implemented using any real number depending on the needs of the designer.

Similarly, the blocks 410d to 401p can be applied with corresponding gate voltages VG according to the above teachings to make the RRAM memory cells in the blocks 410d to 401p perform a one-time resistance transition.

In step S340, the error bit value (which may be characterized as a fail bit count (FBC)) in each of the blocks 401a to 401p may be obtained. In this embodiment, each of the RRAM cells in each of the blocks 401a to 401p will be converted into LRS and generate a memory cell current after undergoing the setting operation, and the memory cell current of one of the RRAM memory cells in a certain block. When less than a current threshold is measured, the error bit value of the corresponding block can be accumulated.

For example, if the memory cell current of the Z1 RRAM memory cells is measured to be less than the current threshold after the setting operation 401a, the error bit value of the block 401a can be determined as Z1. Similarly, after the block operation 401b undergoes the setting operation, if Z2 memory cells having a memory cell current smaller than the current threshold value appear, the error bit value of the block 401b can be determined as Z2. The error bit values of the other blocks 401c to 401p can be derived from the above teachings, and the details thereof will not be described herein.

After the error bit values of the blocks 401a to 401p are obtained, in step S350, the operation characteristic curve 403 associated with the first RRAM wafer 40 may be generated according to the error bit value in each of the blocks 401a to 401p and the aforementioned operating voltage. .

Specifically, as shown in FIG. 4, the operational characteristic curve 403 of the first RRAM wafer 40 is, for example, a curve of the gate voltage VG versus the error bit value (which is characterized by FBC), each of which is drawn in a circle Each of them corresponds to one of the blocks 401a to 401p, and can be used to indicate the error bit value of the corresponding block after the different gate voltages VG are applied to perform the setting operation. For example, the data point 402a may indicate an error bit value of the block 401a (which is for example applied with a gate voltage VG of value a), and the measured error bit value on the block 401a may be, for example, slightly larger than K value (K is a positive number). Similarly, data point 402b may indicate the error bit value of block 401b (which is for example gated with a value of a+d), and data point 402c may indicate block 401c (which is for example given a value of The error bit value of the gate voltage VG of a+2d.

After the error bit values measured in the remaining blocks 401d through 401p are labeled with data points 402d through 402p in accordance with the teachings above, the data points 402a through 402p can be connected to form an operational characteristic 403 of the first RRAM wafer 40. .

As shown in FIG. 4, the operational characteristic 403 of the first RRAM wafer 40 has the lowest error bit value X and the operating voltage interval VR. In a different embodiment, the lowest error bit value X is, for example, the minimum of the measured error bit values in each block. Taking FIG. 4 as an example, the lowest error bit value X (which is between K/10 ³ and K/10 ⁴ ) corresponds to the block 401f, that is, in the blocks 401a to 401p, in the block 401f. The measured error bit value is the lowest.

In addition, as can be seen from FIG. 4, the operational characteristic curve 403 of the first RRAM wafer 40 has a U-shaped section 403a having a first end point (corresponding to the data point 402d) and a second end point (corresponding to the data point 402j). The first endpoint corresponds to a first operating voltage (eg, a+3d) and the second endpoint corresponds to a second operating voltage (eg, a+9d). In this case, the interval between the first operating voltage and the second operating voltage may be defined as the operating voltage interval VR of the operating characteristic curve 403, and the width of the operating voltage interval VR is, for example, 6d (ie, (a+9d) )-(a+3d)) but is not limited to this.

In the present embodiment, the difference between the error bit values of adjacent data points in the operational characteristic curve 403 can be calculated. When the difference between the first data point of the operation characteristic curve 403 and the error bit value of the next data point becomes significantly larger, the first data point can be regarded as the first end point of the operation characteristic curve 403. (For example, data point 402d). On the other hand, when the difference between the second data point of the operation characteristic curve 403 and the error bit value of the next data point becomes significantly smaller, the second data point can be regarded as the operation characteristic curve 403. Two endpoints (eg, data point 402j).

Further, in the operation characteristic curve 403 of FIG. 4, the area on the left side of the material point 402d may be referred to as a set-out area, and the area on the right side of the material point 402j may be referred to as an over-set area. For the designer of the first RRAM wafer 40, the preferred operating characteristic curve should have at least the following two characteristics: (1) the minimum error bit value X corresponds to a smaller gate voltage VG; and (2) the operating voltage The width of the interval VR is moderate.

Regarding point (1), it represents that the less than full area is set to be narrow (ie, the gate voltage VG corresponding to the lowest error bit value X is small), so that the first RRAM wafer 40 after undergoing the molding operation and the initial reset operation is performed. It can be set to LRS more easily in the future. Regarding point (2), if the width of the operating voltage interval VR is too small, it means that the conductive wires formed in the respective RRAM memory cells of the first RRAM wafer 40 after undergoing the molding operation and the initial reset operation may be too fine, and thus It is easy to have the problem of complementary switching (CS) in the subsequent resistance switching operation, that is, the measured cell current does not increase and decrease after switching to LRS (ie, the resistance does not fall and rise) . On the other hand, if the width of the operating voltage interval VR is too large, it means that the conductive wires formed in the respective RRAM memory cells of the first RRAM wafer 40 after undergoing the molding operation and the initial reset operation may be too thick, so that The problem mentioned in the related description of Figure 2.

In other words, by the operational characteristic curve 403 drawn by the one-time setting operation performed on each of the blocks 401a to 401p of the first RRAM wafer 40, it can be seen whether the molding operation and the initial reset operation previously experienced by the first RRAM wafer 40 can be A preferred conductive filament is formed in each of the RRAM memory cells. That is, the operational characteristic 403 can be used to assist in examining whether the first operating condition is sufficiently desirable, that is, whether the operational characteristic 403 has the previously mentioned (1), (2) point characteristics.

In an embodiment of the present invention, it is determined whether the first operating condition is sufficiently desirable by the step S360 mentioned in the following description.

Specifically, in step S360, when the lowest error bit value X meets the first condition and the operating voltage interval VR meets the second condition, the first operating condition may be determined as the first optimal operating condition of the first RRAM wafer 40. .

Wherein, in an embodiment, when the lowest error bit value X is smaller than a preset ratio value of the total number of RRAM memory cells in the first RRAM wafer 40, it may be determined that the lowest error bit value X meets the foregoing first condition, and A condition can be considered to correspond to the previously mentioned point (1) characteristic. That is, when the lowest error bit value X satisfies the first condition, it can be determined that the operation characteristic curve 403 has the characteristic of the above point (1).

In an embodiment, the preset ratio value is 20%, that is, when the lowest error bit value X is less than 20% of the total number of RRAM memory cells in the first RRAM wafer 40, the lowest error bit value X can be determined. Meet the first condition described above. In another embodiment, the aforementioned preset ratio value is 10%. In a preferred embodiment, the aforementioned preset ratio is 5%.

In another embodiment, when the width of the operating voltage interval VR is greater than a predetermined voltage value, it may be determined that the operating voltage interval VR meets the foregoing second condition, and the second condition may be regarded as corresponding to the previously mentioned (2) Point characteristics. That is, when the operation voltage section VR satisfies the second condition described above, it can be determined that the operation characteristic curve 403 has the characteristic of the above point (2).

In an embodiment, the preset voltage value is 0.3V, that is, when the width of the operating voltage interval VR is greater than 0.3V, it can be determined that the operating voltage interval VR meets the foregoing second condition. In a preferred embodiment, the aforementioned preset voltage value is 0.6V.

In detail, when the lowest error bit value X and the operation voltage interval VR of the operation characteristic curve 403 meet the first condition and the second condition, respectively, that is, the first operation condition adopted in step S310 can make the first RRAM available. Each of the RRAM memory cells in the wafer 40, after undergoing a forming operation and an initial reset operation, forms a conductive filament having a preferred aspect (such as the one shown in the middle of FIG. 2). Therefore, the aforementioned first operating condition can be defined as the optimum operating condition of the first RRAM wafer 40.

In this case, when the designer wants to perform the molding operation and the initial reset operation on the other RRAM wafers of the same process as the first RRAM wafer 40, the first operating conditions can be directly applied to the RRAM wafers. The molding voltage and the first initial reset voltage are used to form a preferred conductive filament (such as the one shown in the middle of FIG. 2) in each of the RRAM cells of the RRAM wafer.

It can be seen from the above that the method proposed by the embodiment of the present invention can quickly and effectively find appropriate operating conditions for performing a molding operation and an initial reset operation on the RRAM wafer, thereby enabling each RRAM memory cell in the RRAM wafer to undergo a molding operation and After the initial reset operation, a conductive wire having a preferred aspect is formed accordingly, thereby facilitating subsequent resistance state switching operations.

In addition, in other embodiments, when the lowest error bit value X of the operation characteristic curve 403 does not meet the first condition or the operation voltage interval VR does not meet the second condition, the first and the first operation condition may be used to The second RRAM wafer of the same process as the RRAM wafer performs the method shown in FIG.

Specifically, the second RRAM wafer may be subjected to a molding operation and an initial reset operation according to the second operating condition, and the second operating condition includes, for example, a second molding voltage and a second initial reset voltage. Thereafter, the second RRAM wafer can be divided into a plurality of blocks, and the blocks of the second RRAM wafer are individually set based on the above operating voltage. Next, the error bit values for each block in the second RRAM wafer can be taken and the operational characteristic associated with the second RRAM wafer can be plotted in accordance with the teachings of the previous embodiments. Similar to the operational characteristic 403, the operational characteristic of the second RRAM wafer will also have the lowest error bit value and the operating voltage interval.

When the lowest error bit value and the operating voltage interval corresponding to the second RRAM chip meet the first condition and the second condition, the second operating condition is determined to be the second optimal operating condition of the second RRAM wafer.

In other words, if the first operating condition does not allow the RRAM cells of the first RRAM wafer 40 to form a conductive filament having a preferred aspect, the method of the present invention can be based on a second operating condition that is different from the first operating condition. The two RRAM wafers are subjected to a molding operation and an initial reset operation, and the operational characteristics of the second RRAM wafer are drawn in accordance with the previous teachings. If the operating characteristic curve of the second RRAM wafer has the previously mentioned point (1), (2) characteristics, that is, the second operating condition employed allows the RRAM memory cells in the second RRAM wafer to undergo a molding operation. After the initial reset operation, a conductive wire having a preferred aspect is formed (such as the one shown in the middle of FIG. 2). Therefore, the aforementioned second operating condition can be defined as the optimum operating condition of the second RRAM wafer.

In this case, when the designer wants to perform a molding operation and an initial reset operation on other RRAM wafers of the same process as the second RRAM wafer, the second operating condition can be directly applied to apply the second molding to the RRAM wafers. The voltage and the second initial reset voltage are used to form a preferred conductive filament (e.g., the pattern shown in the middle of FIG. 2) in each of the RRAM cells of the RRAM wafer.

Conversely, if the operating characteristic curve of the second RRAM wafer still does not have the (1) point and/or the (2) point characteristic, the embodiment of the present invention can continue to use other operating conditions to perform RRAM wafers of other processes of the same process. The above teachings are performed until an operating condition is obtained in which the plotted operating characteristic curve has the characteristics of points (1) and (2).

Referring to FIG. 5, in the present embodiment, it is assumed that the operational characteristic curves 501, 502, and 503 are different RRAM wafers are drawn based on the teachings in the previous embodiments after undergoing different molding voltages and initial reset voltages.

In FIG. 5, although the operating characteristic curve 501 has a narrower set-out area (i.e., a steeper slope), its over-set area is wider, so that its corresponding initial reset voltage may be too light. In other words, after the RRAM wafer corresponding to the operation characteristic 501 undergoes the molding operation and the initial reset operation, the formed conductive filament structure is too loose, so that it is easy to be disconnected after undergoing the setting operation, and a diffusion path is easily generated. Causes the resistance to fall and rise. That is, since the selected initial reset voltage is too low, the RRAM wafer corresponding to the operation characteristic curve 501 is caused to have poor high temperature data retention (HTDR) and durability.

On the other hand, since the operating characteristic curve 503 has a wider set of underfilled areas, its corresponding initial reset voltage may be excessive. In other words, after the RRAM wafer corresponding to the operating characteristic 503 undergoes the forming operation and the initial resetting operation, the gap between the conductive wire structure and the upper electrode plate formed is too large, so that the resistance value cannot be well connected after undergoing the setting operation due to the conductive wire. The upper electrode plate cannot be reliably switched to the LRS. That is, since the selected initial reset voltage is too heavy, the RRAM wafer corresponding to the operating characteristic curve 503 will also have a poor HTDR.

In contrast, the RRAM wafer corresponding to the operating characteristic curve 502 undergoes a molding operation and an initial reset operation which are obviously superior to the other two, so that the corresponding molding voltage and the initial reset voltage can be regarded as optimal operating conditions, and The molding operation and the initial reset operation are performed on other RRAM wafers of the same process.

In other embodiments, the method of the embodiment of the present invention may separately draw and select operating characteristic curves for a plurality of RRAM wafers of the same process (or a plurality of small RRAM wafers separated by a large RRAM chip). An operating characteristic curve having the characteristics of points (1) and (2). Moreover, if there are a plurality of operating characteristic curves having the characteristics of points (1) and (2) at the same time, the method of the present invention can further compare the operating characteristic curves to find a better operating characteristic curve therefrom, and Find the best operating conditions accordingly.

Referring to FIG. 6, in the present embodiment, it is assumed that the operating characteristic curves 601, 602, 603, and 604 are different RRAM wafers, after undergoing different forming voltages and initial reset voltages, based on the teachings in the previous embodiments. to make.

In FIG. 6, it is assumed that only the lowest error bit value and the operating voltage interval of the operating characteristic curve 602 meet the first condition and the second condition, respectively, and the forming voltage and the initial reset voltage corresponding to the operating characteristic curve 602 can be determined as each RRAM. Optimal operating conditions for the wafer.

However, if the lowest error bit value and the operating voltage interval of the operating characteristic curve 601 also meet the first condition and the second condition, respectively, the lowest error bit value of the operating characteristic curve 601 and the lowest of the operating characteristic curve 602 can be continued. The error bit values are compared.

For example, it can be determined whether the lowest error bit value of the operational characteristic 601 is lower than the lowest error bit value of the operational characteristic 602. As can be seen from FIG. 6, the lowest error bit value of the operating characteristic curve 601 is lower than the lowest error bit value of the operating characteristic curve 602, so that the forming voltage and the initial reset voltage corresponding to the operating characteristic curve 601 can be determined to be the highest of each RRAM chip. Good operating conditions.

In other embodiments, if the lowest error bit value of the operating characteristic curve 601 is higher than the lowest error bit value of the operating characteristic curve 602, the forming voltage and the initial reset voltage corresponding to the operating characteristic curve 602 can be determined as each RRAM. Optimal operating conditions for the wafer.

In other embodiments, if the lowest error bit value of the operation characteristic curve 601 is equal to the lowest error bit value of the operation characteristic curve 602, it may be determined whether the voltage operation interval of the operation characteristic curve 601 is greater than the voltage of the operation characteristic curve 602. Operating interval. If so, it is determined that the molding voltage corresponding to the operating characteristic curve 601 and the initial reset voltage are optimal operating conditions, and conversely, the forming voltage and the initial reset voltage corresponding to the operating characteristic curve 602 are determined as optimal operating conditions for the respective RRAM wafers.

In summary, the method of the embodiment of the present invention can perform different setting operations on different blocks on the RRAM wafer based on a plurality of different operating voltages after performing the molding operation and the initial reset operation on the RRAM wafer. After that, the error bit value on each block can be counted and the operating characteristic curve of the RRAM wafer can be drawn, and based on the operation characteristic curve, it is judged whether the operating condition of the RRAM wafer initial molding operation and the initial reset operation is appropriate. If the lowest error bit value of the operation characteristic curve and the operation voltage interval meet the first condition and the second condition, respectively, it is determined that the operation condition corresponding to the molding operation and the initial reset operation is the optimal operating condition of the RRAM wafer.

In addition, the embodiment of the present invention can also draw an operation characteristic curve corresponding to a plurality of RRAMs after undergoing different molding operations and initial reset operations, and find an optimal operation characteristic curve therefrom, and then use the corresponding molding operation and The operating conditions corresponding to the initial reset operation are the best operating conditions for the RRAM wafer.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

21, 22 ‧ ‧ gap

40‧‧‧First RRAM Wafer

401a, 401b, ..., 401p‧‧‧ blocks

402a, 402b, ..., 402p‧‧‧ data points

403, 501~503, 601~604‧‧‧ operating characteristic curve

403a‧‧‧U-shaped section

VR‧‧‧Operating voltage range

VG‧‧‧ gate voltage

X‧‧‧ Lowest error bit value

S310~S360‧‧‧Steps

BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a view showing a conductive filament pattern formed under various molding voltage conditions according to an embodiment of the present invention. 2 is a diagram of a conductive filament pattern caused by various initial reset voltage conditions in accordance with an embodiment of the present invention. 3 is a flow chart of a method for finding an optimal operating condition of an RRAM according to an embodiment of the invention. 4 is a schematic diagram of finding an operational characteristic curve for an RRAM wafer according to an embodiment of the invention. FIG. 5 is a schematic diagram of a plurality of operational characteristic curves according to an embodiment of the invention. FIG. 6 is a schematic diagram of a plurality of operating characteristic curves according to another embodiment of the invention.

Claims (12)

A method for finding an optimal operating condition of a resistive random access memory, comprising: obtaining a first resistive random access memory chip, and performing the first resistive random access memory according to a first operating condition The first wafer forming operation and a first initial reset operation; dividing the first resistive random access memory wafer into a plurality of first blocks; and the first blocks based on the plurality of operating voltages Performing a setting operation individually; obtaining a first error bit value in each of the first blocks; generating, according to the first error bit value in each of the first blocks, the operating voltages associated with the first a first operational characteristic of the resistive random access memory chip, wherein the first operational characteristic has a first lowest error bit value and a first operational voltage interval; and when the first lowest error bit value When the first condition is met and the first operating voltage interval meets a second condition, the first operating condition is determined to be a first optimal operating condition of the first resistive random access memory chip. The method of claim 1, wherein each of the first blocks comprises a plurality of memory cells, each of which converts to a low resistance state and generates a memory current after undergoing the setting operation, wherein Obtaining the first error bit value in each of the first blocks includes: measuring the memory cell current of each of the memory cells, and determining whether the memory cell current is lower than a current threshold; and when the memory cell When the current is lower than the current threshold, the corresponding first error bit value of the first block is accumulated. The method of claim 1, wherein the operating voltages are a plurality of gate voltages corresponding to the first resistive random access memory chip. The method of claim 1, wherein the first resistive random access memory chip comprises a plurality of memory cells, and when the first lowest error bit value is less than a total of the total number of memory cells When the scale value is set, it is determined that the first lowest error bit value conforms to the first condition. The method of claim 4, wherein the preset ratio is 20%. The method of claim 1, wherein the first operational characteristic curve comprises a U-shaped segment having a first end point and a second end point, the first end point corresponding to And at a first operating voltage, the second end point corresponds to a second operating voltage, and the interval between the first operating voltage and the second operating voltage is the first operating voltage interval. The method of claim 1, wherein when the width of the first operating voltage interval is greater than a predetermined voltage value, determining that the first operating voltage interval meets the second condition. The method of claim 7, wherein the preset voltage value is 0.3V. The method of claim 1, further comprising: obtaining a second resistive random access memory chip, and performing a second resistive random access memory chip according to a second operating condition a second forming operation and a second initial reset operation, wherein the second resistive random access memory chip has the same process as the first resistive random access memory chip; the second resistive random access memory The body wafer is divided into a plurality of second blocks; the setting operation is performed on the second blocks individually based on the operating voltages; and a second error bit value in each of the second blocks is obtained; The second erroneous bit value in the second block and the operating voltages are associated with a second operational characteristic of the second resistive random access memory chip, wherein the second operational characteristic has a second a minimum error bit value and a second operating voltage interval; and determining that the second operating condition is when the second lowest error bit value meets the first condition and the second operating voltage interval meets the second condition A second optimal operating condition of the second resistive random access memory chip. The method of claim 9, further comprising: determining whether the first lowest error bit value is less than the second lowest error bit value; if yes, determining that the first operating condition is the first resistive random An optimal operating condition for accessing the memory chip and the second resistive random access memory chip. The method of claim 9, wherein when the first lowest error bit value is equal to the second lowest error bit value, the method further comprises: determining whether the first operating voltage interval is greater than the second operating voltage The interval; if yes, determining that the first operating condition is an optimal operating condition of the first resistive random access memory chip and the second resistive random access memory chip. The method of claim 1, wherein when the first lowest error bit value does not meet the first condition or the first operating voltage interval does not meet the second condition, the method further comprises: obtaining a second a resistive random access memory chip, and performing a second molding operation and a second initial reset operation on the second resistive random access memory chip according to a second operating condition, wherein the second resistive random Accessing the memory chip is the same as the process of the first resistive random access memory chip; dividing the second resistive random access memory chip into a plurality of second blocks; and based on the operating voltages The second block performs the setting operation individually; obtaining a second error bit value in each of the second blocks; generating an association according to the second error bit value in each of the second blocks and the operating voltages a second operational characteristic of the second resistive random access memory chip, wherein the second operational characteristic has a second lowest error bit value and a second operating voltage interval; and when the second lowest When the error bit value meets the first condition and the second operation voltage interval meets the second condition, determining that the second operating condition is a second optimal operating condition of the second resistive random access memory chip.