TWI649749B - Method for obtaining optimal operating condition of resistive random access memory - Google Patents
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Abstract
本發明提供一種找出電阻式隨機存取記憶體(resistive random access memory,RRAM)的最佳操作條件的方法,包括:取得RRAM晶片,並依據第一操作條件對RRAM晶片進行成型操作及初始重置操作;將RRAM晶片區分為多個區塊;基於多個操作電壓對前述區塊個別進行設定操作;取得各區塊中的錯誤位元值;依據各區塊中的錯誤位元值及前述操作電壓產生關聯於RRAM晶片的操作特性曲線,其中操作特性曲線具有最低錯誤位元值及操作電壓區間;以及當最低錯誤位元值符合第一條件且操作電壓區間符合第二條件時,判定前述第一操作條件為RRAM晶片的最佳操作條件。The present invention provides a method for finding the optimal operating conditions of a resistive random access memory (RRAM), comprising: taking an RRAM wafer, and performing a molding operation and initial weight on the RRAM wafer according to the first operating condition. The RRAM wafer is divided into a plurality of blocks; the foregoing blocks are individually set based on a plurality of operating voltages; the error bit values in each block are obtained; and the error bit values in each block are as described above. The operating voltage produces an operating characteristic curve associated with the RRAM wafer, wherein the operating characteristic curve has the lowest error bit value and the operating voltage interval; and when the lowest error bit value meets the first condition and the operating voltage interval meets the second condition, determining the foregoing The first operating condition is the optimum operating conditions for the RRAM wafer.
Description
本發明是有關於一種找出記憶體的最佳操作條件的方法,且特別是有關於一種找出電阻式隨機存取記憶體(resistive random access memory,RRAM)的成型操作條件及初始重置操作條件的方法。The present invention relates to a method for finding the optimal operating conditions of a memory, and in particular to a forming operation condition and an initial reset operation for finding a resistive random access memory (RRAM). Conditional method.
RRAM是一種非揮發性記憶體,其中的RRAM單元各自包括上電極板、下電極板、及夾在上、下電極板之間的介電材料層。介電材料層通常是絕緣的,而透過在上電極板上施加合適電壓以對記憶胞進行成型(forming)操作,可在介電材料層中形成穿過介電材料層的導電路徑(通常稱為導電絲(conductive filament,CF))。導電絲一旦形成,便可透過在上電極板上施加適當的電壓對其進行重置(reset)操作(即,令導電絲斷開或破裂,導致在RRAM單元上出現高阻值狀態(high resistance state,HRS)。The RRAM is a non-volatile memory in which the RRAM cells each include an upper electrode plate, a lower electrode plate, and a dielectric material layer sandwiched between the upper and lower electrode plates. The layer of dielectric material is typically insulative, and by applying a suitable voltage to the upper electrode plate to form a memory cell, a conductive path through the layer of dielectric material can be formed in the layer of dielectric material (commonly referred to as It is a conductive filament (CF). Once the conductive filament is formed, it can be reset by applying an appropriate voltage on the upper electrode plate (ie, the conductive wire is broken or broken, resulting in a high resistance state on the RRAM cell (high resistance). State, HRS).
之後,可再透過在上電極板上施加適當的電壓對RRAM單元進行設定(set)操作(即,重新形成導電絲,導致在RRAM單元上出現低阻值狀態(low resistance state,LRS))。透過反覆的設定操作及重置操作,可控制RRAM的阻值狀態(LRS或HRS),LRS和HRS可用於指示“0”或“1”的數位信號,從而提供相關的記憶體功能。Thereafter, the RRAM cell can be set up by applying an appropriate voltage to the upper electrode plate (i.e., the conductive filament is reformed, resulting in a low resistance state (LRS) on the RRAM cell). The RRAM resistance state (LRS or HRS) can be controlled by repeated set operations and reset operations. The LRS and HRS can be used to indicate a digital signal of "0" or "1" to provide associated memory functions.
在現有技術中,由於RRAM的製程及所使用的材料日新月異,因此如何快速而有效地找出適當的操作條件已是RRAM開發過程中相當重要的一項議題。若採用了不佳的操作條件,很可能造成在測試的過程中誤判材料的相關因素,進而影響RRAM的開發時程及效能。對於不同製程及材料所產出的RRAM而言,由於成型操作及初始重置(initial reset)操作是決定導電絲態樣的關鍵步驟,因此,若能具體找出適當的成型操作及初始重置操作的電壓範圍,將有利於形成較佳的導電絲,從而提供良好的導電路徑。In the prior art, since the process of the RRAM and the materials used are changing with each passing day, how to find the proper operating conditions quickly and effectively has become a very important issue in the RRAM development process. If poor operating conditions are used, it is likely to cause factors related to the material misjudgment during the test, which will affect the development time and performance of the RRAM. For RRAMs produced by different processes and materials, since the molding operation and the initial reset operation are the key steps in determining the conductive wire pattern, it is possible to find out the proper molding operation and initial reset. The operating voltage range will facilitate the formation of a preferred conductive filament to provide a good conductive path.
有鑑於此,本發明實施例提出一種找出電阻式隨機存取記憶體的最佳操作條件的方法,其可依特定的機制繪製出RRAM晶片在經歷某成型操作及初始電壓操作後所對應的操作特性曲線,並據以判定上述成型操作及初始電壓操作是否為RRAM晶片的最佳操作條件。In view of this, the embodiment of the present invention provides a method for finding the optimal operating condition of the resistive random access memory, which can draw a corresponding operation of the RRAM wafer after undergoing a molding operation and an initial voltage operation according to a specific mechanism. The characteristic curve is operated and it is determined whether the above-described molding operation and initial voltage operation are the optimum operating conditions of the RRAM wafer.
本發明提供一種找出電阻式隨機存取記憶體的最佳操作條件的方法,包括:取得一第一電阻式隨機存取記憶體晶片,並依據一第一操作條件對第一電阻式隨機存取記憶體晶片進行一第一成型操作及一第一初始重置操作;將第一電阻式隨機存取記憶體晶片區分為多個第一區塊;基於多個操作電壓對前述第一區塊個別進行一設定操作;取得各第一區塊中的一第一錯誤位元值;依據各第一區塊中的第一錯誤位元值及前述操作電壓產生關聯於第一電阻式隨機存取記憶體晶片的一第一操作特性曲線,其中第一操作特性曲線具有一第一最低錯誤位元值及一第一操作電壓區間;以及當第一最低錯誤位元值符合一第一條件且第一操作電壓區間符合一第二條件時,判定第一操作條件為第一電阻式隨機存取記憶體晶片的一第一最佳操作條件。The present invention provides a method for finding the optimal operating conditions of a resistive random access memory, comprising: obtaining a first resistive random access memory chip, and randomly storing the first resistive memory according to a first operating condition Taking a memory wafer for performing a first molding operation and a first initial reset operation; dividing the first resistive random access memory wafer into a plurality of first blocks; and the first block based on the plurality of operating voltages Performing a setting operation individually; obtaining a first error bit value in each first block; generating a correlation with the first resistive random access according to the first error bit value in each first block and the foregoing operating voltage a first operational characteristic of the memory chip, wherein the first operational characteristic has a first lowest error bit value and a first operational voltage interval; and when the first lowest error bit value meets a first condition and When an operating voltage interval meets a second condition, the first operating condition is determined to be a first optimal operating condition of the first resistive random access memory chip.
基於上述,本發明實施例的方法可在對RRAM晶片進行成型操作及初始重置操作之後,基於多個不同的操作電壓對此RRAM晶片上的不同區塊進行不同的設定操作。之後,可統計各區塊上的錯誤位元值並繪製出此RRAM晶片的操作特性曲線,並基於操作特性曲線是否符合第一條件及第二條件來判斷此RRAM晶片當初進行成型操作及初始重置操作的操作條件是否恰當。Based on the above, the method of the embodiment of the present invention can perform different setting operations on different blocks on the RRAM wafer based on a plurality of different operating voltages after performing the molding operation and the initial reset operation on the RRAM wafer. After that, the error bit value on each block can be counted and the operating characteristic curve of the RRAM chip can be drawn, and based on whether the operating characteristic curve meets the first condition and the second condition, the RRAM wafer is initially subjected to the molding operation and the initial weight. Whether the operating conditions of the operation are appropriate.
為讓本發明的上述特徵和優點能更明顯易懂,下文特舉實施例,並配合所附圖式作詳細說明如下。The above described features and advantages of the invention will be apparent from the following description.
請參照圖1,若在成型操作中對RRAM記憶胞施以過輕的成型電壓,將使得所形成的導電絲過細,因而容易被斷開。另一方面,若在成型操作中對RRAM記憶胞施以過重的成型電壓,將使得所形成的導電絲過粗,進而造成導電路徑過多,增加控制上的難度。因此,若能找出較為理想的成型操作條件(例如,成型電壓),將可使得所形成的導電絲具有較佳的圍度,從而提供較佳的導電路徑。Referring to FIG. 1, if the RRAM memory cell is subjected to an excessively low molding voltage during the molding operation, the formed conductive wire is made too thin and thus easily broken. On the other hand, if the RRAM memory cell is subjected to an excessively heavy forming voltage in the molding operation, the formed conductive wire will be made too thick, thereby causing too many conductive paths and increasing the difficulty in control. Therefore, if a more ideal molding operation condition (for example, a molding voltage) can be found, the formed conductive yarn can be made to have a better circumference, thereby providing a better conductive path.
請參照圖2,一般而言,對RRAM記憶胞所進行的初始重置操作將會決定此RRAM記憶胞往後切換阻值狀態的表現(即,從HRS切換至LRS或是從LRS切換為HRS)。Referring to FIG. 2, in general, the initial reset operation on the RRAM memory cell will determine the performance of the RRAM memory cell to switch back to the resistance state (ie, switching from HRS to LRS or from LRS to HRS). ).
如圖2所示,若在初始重置操作中對RRAM記憶胞施以過輕的初始重置電壓,將使得重置後的導電絲與上電極板之間出現較短且窄的間隙21。在此情況下,若對RRAM記憶胞進行設定操作以將其切換為LRS,則很可能使RRAM記憶胞出現過設定(over-set)狀態。As shown in FIG. 2, if the RRAM memory cell is subjected to an excessive initial reset voltage during the initial reset operation, a short and narrow gap 21 will appear between the reset conductive wire and the upper electrode plate. In this case, if the RRAM memory cell is set to switch to LRS, it is likely that the RRAM memory cell has an over-set state.
相反地,若在初始重置操作中對RRAM記憶胞施以過重初始重置電壓,將使得重置後的導電絲與上電極板之間出現較長且寬的間隙22。在此情況下,即便對RRAM記憶胞進行設定操作也可能難以順利地RRAM記憶胞切換為LRS,亦即出現了設定未滿(under-set)狀態。因此,若能找出較為理想的初始重置操作條件(例如,初始重置電壓),將可使得所形成的導電絲與上電極板之間的間隙具有較佳的態樣,從而利於進行後續的阻值狀態切換操作。Conversely, if the RRAM memory cell is subjected to an excessive initial reset voltage during the initial reset operation, a long and wide gap 22 will occur between the reset conductive filament and the upper electrode plate. In this case, even if the RRAM memory cell is set, it may be difficult to smoothly switch the RRAM memory cell to the LRS, that is, the set under-set state occurs. Therefore, if a better initial reset operating condition (for example, an initial reset voltage) can be found, the gap between the formed conductive wire and the upper electrode plate can be better, thereby facilitating subsequent operations. Resistance state switching operation.
有鑑於此,本發明提出一種找出RRAM的最佳操作條件的方法,其可用於找出最適於進行RRAM晶片的最佳成型電壓及最佳初始重置電壓,進而在RRAM晶片的各個記憶胞成形成理想的導電絲態樣。In view of this, the present invention proposes a method for finding the optimum operating conditions of an RRAM, which can be used to find the optimum forming voltage and the optimum initial reset voltage that are most suitable for the RRAM wafer, and thus the individual memory cells of the RRAM wafer. Formed into an ideal conductive filament pattern.
請參照圖3及圖4,首先,在步驟S310中,可取得第一RRAM晶片40,並依據第一操作條件對第一RRAM晶片40進行成型操作及初始重置操作。在本實施例中,第一RRAM晶片40上可包括多個RRAM記憶胞,而前述第一操作條件例如包括第一成型電壓及第一初始重置電壓。在對第一RRAM晶片40進行成型操作及初始重置操作之後,第一RRAM晶片40上的各個RRAM記憶胞應已相應地形成如圖2所示的其中一種導電絲態樣。Referring to FIG. 3 and FIG. 4, first, in step S310, the first RRAM wafer 40 can be obtained, and the first RRAM wafer 40 is subjected to a molding operation and an initial reset operation according to the first operating condition. In this embodiment, the first RRAM wafer 40 may include a plurality of RRAM memory cells, and the foregoing first operating conditions include, for example, a first molding voltage and a first initial reset voltage. After the forming operation and the initial reset operation of the first RRAM wafer 40, the respective RRAM memory cells on the first RRAM wafer 40 should have formed one of the conductive filament patterns as shown in FIG.
之後,在步驟S320中,可將第一RRAM晶片40區分為多個區塊401a、401b、…及401p。在本實施例中,第一RRAM晶片40例如可被區分為具有相同大小的16個區塊401a、401b、…及401p,但在其他實施例中,第一RRAM晶片40亦可依設計者的需求而被區分為NxM(N、M皆為正整數)個相同大小的區塊,只要各區塊可反映出第一RRAM晶片40的晶片特性即可,但本發明可不限於此。區塊401a、401b、…及401p可個別包括A條記憶胞頁面,各記憶胞頁面可包括B個RRAM記憶胞,亦即區塊401a、401b、…及401p可個別包括AxB個RRAM記憶胞。Thereafter, in step S320, the first RRAM wafer 40 can be divided into a plurality of blocks 401a, 401b, ..., and 401p. In this embodiment, the first RRAM wafer 40 can be divided into, for example, 16 blocks 401a, 401b, ..., and 401p having the same size, but in other embodiments, the first RRAM wafer 40 can also be designed by the designer. It is required to be divided into NxM (N, M are positive integers) blocks of the same size, as long as each block can reflect the wafer characteristics of the first RRAM wafer 40, but the present invention is not limited thereto. The blocks 401a, 401b, ..., and 401p may individually include A memory cell pages, and each memory cell page may include B RRAM memory cells, that is, the blocks 401a, 401b, ..., and 401p may individually include AxB RRAM memory cells.
接著,在步驟S330中,可基於多個操作電壓對區塊401a、401b、…及401p個別進行設定操作。在本實施例中,前述操作電壓是指設定操作及重置操作,並且例如是對應於各區塊401a、401b、…及401p的閘極電壓VG,亦即施加於各區塊401a、401b、…及401p中的RRAM記憶胞的字元線(word line)電壓,但可不限於此。Next, in step S330, the setting operations can be individually performed on the blocks 401a, 401b, ..., and 401p based on the plurality of operating voltages. In the present embodiment, the aforementioned operating voltage refers to a setting operation and a reset operation, and is, for example, a gate voltage VG corresponding to each of the blocks 401a, 401b, ..., and 401p, that is, applied to each of the blocks 401a, 401b, ...and the word line voltage of the RRAM memory cell in 401p, but is not limited thereto.
如圖4所示,本實施例的閘極電壓VG例如可先以初始值a施加於區塊401a以對區塊401a進行設定操作,使得區塊401a中的RRAM記憶胞可進行一次性的阻值轉態(即,HRS切換至LRS)。接著,可基於步進值d將閘極電壓VG增量為a+d,並接續將其施加於區塊401b以對區塊401b進行設定操作,使得區塊401b中的RRAM記憶胞可進行一次性的阻值轉態。之後,可再次基於步進值d將閘極電壓VG增量為a+2d,並接續將其施加於區塊401c以對區塊401c進行設定操作,使得區塊401c中的RRAM記憶胞可進行一次性的阻值轉態。在不同的實施例中,a、d的值可依設計者的需求而採用任意實數來實現。As shown in FIG. 4, the gate voltage VG of the present embodiment can be first applied to the block 401a with an initial value a to perform a setting operation on the block 401a, so that the RRAM memory cell in the block 401a can be disabled once. Value transition (ie, HRS switches to LRS). Then, the gate voltage VG can be incremented to a+d based on the step value d, and then applied to the block 401b to perform the setting operation on the block 401b, so that the RRAM memory cell in the block 401b can be performed once. Sexual resistance. Thereafter, the gate voltage VG can be incremented again to a+2d based on the step value d, and then applied to the block 401c to perform a setting operation on the block 401c, so that the RRAM memory cell in the block 401c can be performed. One-time resistance change. In various embodiments, the values of a, d can be implemented using any real number depending on the needs of the designer.
相似地,區塊410d至401p皆可依上述教示而被施以相應的閘極電壓VG,以令區塊410d至401p中的RRAM記憶胞進行一次性的阻值轉態。Similarly, the blocks 410d to 401p can be applied with corresponding gate voltages VG according to the above teachings to make the RRAM memory cells in the blocks 410d to 401p perform a one-time resistance transition.
在步驟S340中,可取得各區塊401a至401p中的錯誤位元值(其可表徵為錯誤位元數(fail bit count,FBC))。在本實施例中,各區塊401a至401p中的各個RRAM記憶胞在經歷設定操作之後將轉換為LRS並產生記憶胞電流,而當某一個區塊中的某一個RRAM記憶胞的記憶胞電流被測量到小於一電流門限值時,可累加對應的區塊的錯誤位元值。In step S340, the error bit value (which may be characterized as a fail bit count (FBC)) in each of the blocks 401a to 401p may be obtained. In this embodiment, each of the RRAM cells in each of the blocks 401a to 401p will be converted into LRS and generate a memory cell current after undergoing the setting operation, and the memory cell current of one of the RRAM memory cells in a certain block. When less than a current threshold is measured, the error bit value of the corresponding block can be accumulated.
舉例而言,假設區塊401a在經歷設定操作之後,其中的Z1個RRAM記憶胞的記憶胞電流被測量到小於上述電流門限值,則區塊401a的錯誤位元值即可判定為Z1。同理,在區塊401b經歷設定操作之後,若出現了Z2個記憶胞電流小於上述電流門限值的RRAM記憶胞,則區塊401b的錯誤位元值即可判定為Z2。其他區塊401c至401p的錯誤位元值皆可依上述教示而推得,在此不再贅述其細節。For example, if the memory cell current of the Z1 RRAM memory cells is measured to be less than the current threshold after the setting operation 401a, the error bit value of the block 401a can be determined as Z1. Similarly, after the block operation 401b undergoes the setting operation, if Z2 memory cells having a memory cell current smaller than the current threshold value appear, the error bit value of the block 401b can be determined as Z2. The error bit values of the other blocks 401c to 401p can be derived from the above teachings, and the details thereof will not be described herein.
在取得區塊401a至401p的錯誤位元值之後,在步驟S350中,可依據各區塊401a至401p中的錯誤位元值及前述操作電壓產生關聯於第一RRAM晶片40的操作特性曲線403。After the error bit values of the blocks 401a to 401p are obtained, in step S350, the operation characteristic curve 403 associated with the first RRAM wafer 40 may be generated according to the error bit value in each of the blocks 401a to 401p and the aforementioned operating voltage. .
具體而言,如圖4所示,第一RRAM晶片40的操作特性曲線403例如是閘極電壓VG對錯誤位元值(其以FBC表徵)的曲線,其中的每個資料點(以圓圈繪示)皆對應於區塊401a至401p的其中之一,並可用於標示相應區塊在被施加不同閘極電壓VG以進行設定操作之後的錯誤位元值。舉例而言,資料點402a可標示區塊401a(其例如被施以數值為a的閘極電壓VG)的錯誤位元值,而區塊401a上所測得的錯誤位元值例如可略大於K值(K為某正數)。相似地,資料點402b可標示區塊401b(其例如被施以數值為a+d的閘極電壓VG)的錯誤位元值,資料點402c可標示區塊401c(其例如被施以數值為a+2d的閘極電壓VG)的錯誤位元值。Specifically, as shown in FIG. 4, the operational characteristic curve 403 of the first RRAM wafer 40 is, for example, a curve of the gate voltage VG versus the error bit value (which is characterized by FBC), each of which is drawn in a circle Each of them corresponds to one of the blocks 401a to 401p, and can be used to indicate the error bit value of the corresponding block after the different gate voltages VG are applied to perform the setting operation. For example, the data point 402a may indicate an error bit value of the block 401a (which is for example applied with a gate voltage VG of value a), and the measured error bit value on the block 401a may be, for example, slightly larger than K value (K is a positive number). Similarly, data point 402b may indicate the error bit value of block 401b (which is for example gated with a value of a+d), and data point 402c may indicate block 401c (which is for example given a value of The error bit value of the gate voltage VG of a+2d.
在依據上述教示將其餘區塊401d至401p中所測得的錯誤位元值以資料點402d至402p予以標示後,資料點402a至402p可經連接而形成第一RRAM晶片40的操作特性曲線403。After the error bit values measured in the remaining blocks 401d through 401p are labeled with data points 402d through 402p in accordance with the teachings above, the data points 402a through 402p can be connected to form an operational characteristic 403 of the first RRAM wafer 40. .
如圖4所示,第一RRAM晶片40的操作特性曲線403具有最低錯誤位元值X及操作電壓區間VR。在不同的實施例中,最低錯誤位元值X例如是各區塊中所測得的錯誤位元值的最小值。以圖4為例,最低錯誤位元值X(其介於K/10 3及K/10 4之間)係對應於區塊401f,亦即在區塊401a至401p中,區塊401f中所測得的錯誤位元值為最低。 As shown in FIG. 4, the operational characteristic 403 of the first RRAM wafer 40 has the lowest error bit value X and the operating voltage interval VR. In a different embodiment, the lowest error bit value X is, for example, the minimum of the measured error bit values in each block. Taking FIG. 4 as an example, the lowest error bit value X (which is between K/10 3 and K/10 4 ) corresponds to the block 401f, that is, in the blocks 401a to 401p, in the block 401f. The measured error bit value is the lowest.
此外,由圖4可知,第一RRAM晶片40的操作特性曲線403具有U形區段403a,其具有第一端點(對應於資料點402d)及第二端點(對應於資料點402j),而第一端點對應於第一操作電壓(例如是a+3d),第二端點對應於第二操作電壓(例如是a+9d)。在此情況下,且第一操作電壓及第二操作電壓之間的區間可定義為操作特性曲線403的操作電壓區間VR,而此操作電壓區間VR的寬度例如是6d(即,(a+9d)-(a+3d))但可不限於此。In addition, as can be seen from FIG. 4, the operational characteristic curve 403 of the first RRAM wafer 40 has a U-shaped section 403a having a first end point (corresponding to the data point 402d) and a second end point (corresponding to the data point 402j). The first endpoint corresponds to a first operating voltage (eg, a+3d) and the second endpoint corresponds to a second operating voltage (eg, a+9d). In this case, the interval between the first operating voltage and the second operating voltage may be defined as the operating voltage interval VR of the operating characteristic curve 403, and the width of the operating voltage interval VR is, for example, 6d (ie, (a+9d) )-(a+3d)) but is not limited to this.
在本實施例中,可計算操作特性曲線403中相鄰資料點的錯誤位元值之間的差。當操作特性曲線403中的一第一資料點與其次一資料點的錯誤位元值之間的差明顯變大時,即可將前述第一資料點視為操作特性曲線403的第一端點(例如,資料點402d)。另一方面,當操作特性曲線403中的一第二資料點與其次一資料點的錯誤位元值之間的差明顯變小時,即可將前述第二資料點視為操作特性曲線403的第二端點(例如,資料點402j)。In the present embodiment, the difference between the error bit values of adjacent data points in the operational characteristic curve 403 can be calculated. When the difference between the first data point of the operation characteristic curve 403 and the error bit value of the next data point becomes significantly larger, the first data point can be regarded as the first end point of the operation characteristic curve 403. (For example, data point 402d). On the other hand, when the difference between the second data point of the operation characteristic curve 403 and the error bit value of the next data point becomes significantly smaller, the second data point can be regarded as the operation characteristic curve 403. Two endpoints (eg, data point 402j).
進一步而言,在圖4的操作特性曲線403中,資料點402d左側的區域可稱為設定未滿區域,而資料點402j右側的區域可稱為過設定區域。對於第一RRAM晶片40的設計者而言,較佳的操作特性曲線應至少具有以下兩點特性:(1)最低錯誤位元值X對應的閘極電壓VG較小;及(2)操作電壓區間VR的寬度適中。Further, in the operation characteristic curve 403 of FIG. 4, the area on the left side of the material point 402d may be referred to as a set-out area, and the area on the right side of the material point 402j may be referred to as an over-set area. For the designer of the first RRAM wafer 40, the preferred operating characteristic curve should have at least the following two characteristics: (1) the minimum error bit value X corresponds to a smaller gate voltage VG; and (2) the operating voltage The width of the interval VR is moderate.
關於第(1)點,其代表設定未滿區域較窄(即最低錯誤位元值X對應的閘極電壓VG較小),使得在經歷成型操作及初始重置操作後的第一RRAM晶片40在往後能夠較經易地被設定為LRS。關於第(2)點,若操作電壓區間VR的寬度過小,即代表在經歷成型操作及初始重置操作後的第一RRAM晶片40的各RRAM記憶胞中所形成的導電絲可能會過細,進而容易在之後的阻值切換操作中出現互補式切換(complementary switching,CS)的問題,亦即在切換為LRS之後所測得的記憶胞電流不增反降(即,阻值不降反升)。另一方面,若操作電壓區間VR的寬度過大,即代表在經歷成型操作及初始重置操作後的第一RRAM晶片40的各RRAM記憶胞中所形成的導電絲可能會過粗,從而可能出現圖2相關說明中提及的問題。Regarding point (1), it represents that the less than full area is set to be narrow (ie, the gate voltage VG corresponding to the lowest error bit value X is small), so that the first RRAM wafer 40 after undergoing the molding operation and the initial reset operation is performed. It can be set to LRS more easily in the future. Regarding point (2), if the width of the operating voltage interval VR is too small, it means that the conductive wires formed in the respective RRAM memory cells of the first RRAM wafer 40 after undergoing the molding operation and the initial reset operation may be too fine, and thus It is easy to have the problem of complementary switching (CS) in the subsequent resistance switching operation, that is, the measured cell current does not increase and decrease after switching to LRS (ie, the resistance does not fall and rise) . On the other hand, if the width of the operating voltage interval VR is too large, it means that the conductive wires formed in the respective RRAM memory cells of the first RRAM wafer 40 after undergoing the molding operation and the initial reset operation may be too thick, so that The problem mentioned in the related description of Figure 2.
換言之,透過對第一RRAM晶片40的各區塊401a至401p進行的一次性設定操作所繪製的操作特性曲線403,可看出第一RRAM晶片40先前經歷的成型操作及初始重置操作是否能夠在各RRAM記憶胞中形成較佳態樣的導電絲。亦即,操作特性曲線403可用於協助檢視第一操作條件是否足夠理想,也就是操作特性曲線403是否具有先前提及的第(1)、(2)點特性。In other words, by the operational characteristic curve 403 drawn by the one-time setting operation performed on each of the blocks 401a to 401p of the first RRAM wafer 40, it can be seen whether the molding operation and the initial reset operation previously experienced by the first RRAM wafer 40 can be A preferred conductive filament is formed in each of the RRAM memory cells. That is, the operational characteristic 403 can be used to assist in examining whether the first operating condition is sufficiently desirable, that is, whether the operational characteristic 403 has the previously mentioned (1), (2) point characteristics.
在本發明的實施例中,可藉由以下說明提及的步驟S360來判定第一操作條件是否足夠理想。In an embodiment of the present invention, it is determined whether the first operating condition is sufficiently desirable by the step S360 mentioned in the following description.
具體而言,在步驟S360中,當最低錯誤位元值X符合第一條件且操作電壓區間VR符合第二條件時,可判定第一操作條件為第一RRAM晶片40的第一最佳操作條件。Specifically, in step S360, when the lowest error bit value X meets the first condition and the operating voltage interval VR meets the second condition, the first operating condition may be determined as the first optimal operating condition of the first RRAM wafer 40. .
其中,在一實施例中,當最低錯誤位元值X小於第一RRAM晶片40中RRAM記憶胞的總數的預設比例值時,可判定最低錯誤位元值X符合前述第一條件,而第一條件可視為對應於先前提及的第(1)點特性。亦即,當最低錯誤位元值X符合第一條件時,可判定操作特性曲線403具備上述第(1)點的特性。Wherein, in an embodiment, when the lowest error bit value X is smaller than a preset ratio value of the total number of RRAM memory cells in the first RRAM wafer 40, it may be determined that the lowest error bit value X meets the foregoing first condition, and A condition can be considered to correspond to the previously mentioned point (1) characteristic. That is, when the lowest error bit value X satisfies the first condition, it can be determined that the operation characteristic curve 403 has the characteristic of the above point (1).
在一實施例中,前述預設比例值為20%,亦即當最低錯誤位元值X小於第一RRAM晶片40中RRAM記憶胞的總數的20%時,即可判定最低錯誤位元值X符合前述第一條件。在另一實施例中,前述預設比例值為10%。在一較佳實施例中,前述預設比例值為5%。In an embodiment, the preset ratio value is 20%, that is, when the lowest error bit value X is less than 20% of the total number of RRAM memory cells in the first RRAM wafer 40, the lowest error bit value X can be determined. Meet the first condition described above. In another embodiment, the aforementioned preset ratio value is 10%. In a preferred embodiment, the aforementioned preset ratio is 5%.
在另一實施例中,當操作電壓區間VR的寬度大於一預設電壓值時,可判定操作電壓區間VR符合前述第二條件,而第二條件可視為對應於先前提及的第(2)點特性。亦即,當操作電壓區間VR符合前述第二條件時,可判定操作特性曲線403具備上述第(2)點的特性。In another embodiment, when the width of the operating voltage interval VR is greater than a predetermined voltage value, it may be determined that the operating voltage interval VR meets the foregoing second condition, and the second condition may be regarded as corresponding to the previously mentioned (2) Point characteristics. That is, when the operation voltage section VR satisfies the second condition described above, it can be determined that the operation characteristic curve 403 has the characteristic of the above point (2).
在一實施例中,前述預設電壓值為0.3V,亦即當操作電壓區間VR的寬度大於0.3V時,可判定操作電壓區間VR符合前述第二條件。在一較佳實施例中,前述預設電壓值為0.6V。In an embodiment, the preset voltage value is 0.3V, that is, when the width of the operating voltage interval VR is greater than 0.3V, it can be determined that the operating voltage interval VR meets the foregoing second condition. In a preferred embodiment, the aforementioned preset voltage value is 0.6V.
詳細而言,當操作特性曲線403的最低錯誤位元值X及操作電壓區間VR分別符合第一條件及第二條件時,即代表在步驟S310中所採用的第一操作條件可讓第一RRAM晶片40中的各RRAM記憶胞在經歷成型操作及初始重置操作後,形成具較佳態樣的導電絲(例如圖2中間所示的態樣)。因此,即可將前述第一操作條件定義為第一RRAM晶片40的最佳操作條件。In detail, when the lowest error bit value X and the operation voltage interval VR of the operation characteristic curve 403 meet the first condition and the second condition, respectively, that is, the first operation condition adopted in step S310 can make the first RRAM available. Each of the RRAM memory cells in the wafer 40, after undergoing a forming operation and an initial reset operation, forms a conductive filament having a preferred aspect (such as the one shown in the middle of FIG. 2). Therefore, the aforementioned first operating condition can be defined as the optimum operating condition of the first RRAM wafer 40.
在此情況下,當設計者欲對與第一RRAM晶片40相同製程的其他RRAM晶片進行成型操作及初始重置操作時,即可直接採用上述第一操作條件來對這些RRAM晶片施以第一成型電壓及第一初始重置電壓,以在這些RRAM晶片的各個RRAM記憶胞中形成具較佳態樣的導電絲(例如圖2中間所示的態樣)。In this case, when the designer wants to perform the molding operation and the initial reset operation on the other RRAM wafers of the same process as the first RRAM wafer 40, the first operating conditions can be directly applied to the RRAM wafers. The molding voltage and the first initial reset voltage are used to form a preferred conductive filament (such as the one shown in the middle of FIG. 2) in each of the RRAM cells of the RRAM wafer.
由上可知,本發明實施例提出的方法可快速而有效地找出對RRAM晶片進行成型操作及初始重置操作的適當操作條件,因而能夠讓RRAM晶片中的各RRAM記憶胞在經歷成型操作及初始重置操作之後,相應地形成具較佳態樣的導電絲,從而利於進行後續的阻值狀態切換操作。It can be seen from the above that the method proposed by the embodiment of the present invention can quickly and effectively find appropriate operating conditions for performing a molding operation and an initial reset operation on the RRAM wafer, thereby enabling each RRAM memory cell in the RRAM wafer to undergo a molding operation and After the initial reset operation, a conductive wire having a preferred aspect is formed accordingly, thereby facilitating subsequent resistance state switching operations.
此外,在其他實施例中,當操作特性曲線403的最低錯誤位元值X不符合第一條件或操作電壓區間VR不符合第二條件時,可接續地基於第二操作條件來對與第一RRAM晶片相同製程的第二RRAM晶片進行圖3所示的方法。In addition, in other embodiments, when the lowest error bit value X of the operation characteristic curve 403 does not meet the first condition or the operation voltage interval VR does not meet the second condition, the first and the first operation condition may be used to The second RRAM wafer of the same process as the RRAM wafer performs the method shown in FIG.
具體而言,可依據第二操作條件對第二RRAM晶片進行成型操作及初始重置操作,而前述第二操作條件例如包括第二成型電壓及第二初始重置電壓。之後,可將第二RRAM晶片區分為多個區塊,並基於上述操作電壓對第二RRAM晶片的區塊個別進行設定操作。接著,可取得第二RRAM晶片中各區塊的錯誤位元值,並依據先前實施例的教示繪製關聯於第二RRAM晶片的操作特性曲線。相似於操作特性曲線403,第二RRAM晶片的操作特性曲線亦將具有最低錯誤位元值及操作電壓區間。Specifically, the second RRAM wafer may be subjected to a molding operation and an initial reset operation according to the second operating condition, and the second operating condition includes, for example, a second molding voltage and a second initial reset voltage. Thereafter, the second RRAM wafer can be divided into a plurality of blocks, and the blocks of the second RRAM wafer are individually set based on the above operating voltage. Next, the error bit values for each block in the second RRAM wafer can be taken and the operational characteristic associated with the second RRAM wafer can be plotted in accordance with the teachings of the previous embodiments. Similar to the operational characteristic 403, the operational characteristic of the second RRAM wafer will also have the lowest error bit value and the operating voltage interval.
當第二RRAM晶片對應的最低錯誤位元值及操作電壓區間別符合上述的第一條件及第二條件時,即可判定前述第二操作條件為第二RRAM晶片的第二最佳操作條件。When the lowest error bit value and the operating voltage interval corresponding to the second RRAM chip meet the first condition and the second condition, the second operating condition is determined to be the second optimal operating condition of the second RRAM wafer.
換言之,若第一操作條件無法令第一RRAM晶片40的各RRAM記憶胞形成具較佳態樣的導電絲,本發明的方法可基於相異於第一操作條件的第二操作條件來對第二RRAM晶片進行成型操作及初始重置操作,並可接續依據前先的教示而繪製第二RRAM晶片的操作特性曲線。若第二RRAM晶片的操作特性曲線具有先前提及的第(1)、(2)點特性,即代表所採用的第二操作條件可讓第二RRAM晶片中的各RRAM記憶胞在經歷成型操作及初始重置操作後,形成具較佳態樣的導電絲(例如圖2中間所示的態樣)。因此,即可將前述第二操作條件定義為第二RRAM晶片的最佳操作條件。In other words, if the first operating condition does not allow the RRAM cells of the first RRAM wafer 40 to form a conductive filament having a preferred aspect, the method of the present invention can be based on a second operating condition that is different from the first operating condition. The two RRAM wafers are subjected to a molding operation and an initial reset operation, and the operational characteristics of the second RRAM wafer are drawn in accordance with the previous teachings. If the operating characteristic curve of the second RRAM wafer has the previously mentioned point (1), (2) characteristics, that is, the second operating condition employed allows the RRAM memory cells in the second RRAM wafer to undergo a molding operation. After the initial reset operation, a conductive wire having a preferred aspect is formed (such as the one shown in the middle of FIG. 2). Therefore, the aforementioned second operating condition can be defined as the optimum operating condition of the second RRAM wafer.
在此情況下,當設計者欲對與第二RRAM晶片相同製程的其他RRAM晶片進行成型操作及初始重置操作時,即可直接採用上述第二操作條件來對這些RRAM晶片施以第二成型電壓及第二初始重置電壓,以在這些RRAM晶片的各個RRAM記憶胞中形成具較佳態樣的導電絲(例如圖2中間所示的態樣)。In this case, when the designer wants to perform a molding operation and an initial reset operation on other RRAM wafers of the same process as the second RRAM wafer, the second operating condition can be directly applied to apply the second molding to the RRAM wafers. The voltage and the second initial reset voltage are used to form a preferred conductive filament (e.g., the pattern shown in the middle of FIG. 2) in each of the RRAM cells of the RRAM wafer.
相反地,若第二RRAM晶片的操作特性曲線仍不具有第(1)點及/或第(2)點特性,則本發明實施例可接續採用其他操作條件來對其他相同製程的RRAM晶片進行以上教示的操作,直至找到可令所繪製的操作特性曲線具有第(1)、(2)點特性的操作條件為止。Conversely, if the operating characteristic curve of the second RRAM wafer still does not have the (1) point and/or the (2) point characteristic, the embodiment of the present invention can continue to use other operating conditions to perform RRAM wafers of other processes of the same process. The above teachings are performed until an operating condition is obtained in which the plotted operating characteristic curve has the characteristics of points (1) and (2).
請參照圖5,在本實施例中,假設操作特性曲線501、502、503係不同的RRAM晶片在經歷不同的成型電壓及初始重置電壓後,基於先前實施例中的教示所繪製而成。Referring to FIG. 5, in the present embodiment, it is assumed that the operational characteristic curves 501, 502, and 503 are different RRAM wafers are drawn based on the teachings in the previous embodiments after undergoing different molding voltages and initial reset voltages.
在圖5中,雖然操作特性曲線501具有較窄的設定未滿區域(即,較陡的斜率),但由於其過設定區域較寬,因而代表其對應的初始重置電壓可能過輕。換言之,操作特性曲線501對應的RRAM晶片在經歷成型操作及初始重置操作之後,所形成的導電絲結構過於鬆散,使得在經歷設定操作之後容易斷開,也容易產生擴散路徑(diffusion path),造成阻值不降反升的情形。也就是說,由於所選擇的初始重置電壓過低,將造成操作特性曲線501對應的RRAM晶片具有不佳的高溫資料保存(high temperature data retention,HTDR)及耐久性。In FIG. 5, although the operating characteristic curve 501 has a narrower set-out area (i.e., a steeper slope), its over-set area is wider, so that its corresponding initial reset voltage may be too light. In other words, after the RRAM wafer corresponding to the operation characteristic 501 undergoes the molding operation and the initial reset operation, the formed conductive filament structure is too loose, so that it is easy to be disconnected after undergoing the setting operation, and a diffusion path is easily generated. Causes the resistance to fall and rise. That is, since the selected initial reset voltage is too low, the RRAM wafer corresponding to the operation characteristic curve 501 is caused to have poor high temperature data retention (HTDR) and durability.
另一方面,由於操作特性曲線503具有較寬的設定未滿區域,因而代表其對應的初始重置電壓可能過重。換言之,操作特性曲線503對應的RRAM晶片在經歷成型操作及初始重置操作之後,所形成的導電絲結構與上電極板的間隙過大,使得阻值在經歷設定操作之後因導電絲無法良好地連接上電極板,因而無法確實地切換為LRS。也就是說,由於所選擇的初始重置電壓過重,將造成操作特性曲線503對應的RRAM晶片同樣具有不佳的HTDR。On the other hand, since the operating characteristic curve 503 has a wider set of underfilled areas, its corresponding initial reset voltage may be excessive. In other words, after the RRAM wafer corresponding to the operating characteristic 503 undergoes the forming operation and the initial resetting operation, the gap between the conductive wire structure and the upper electrode plate formed is too large, so that the resistance value cannot be well connected after undergoing the setting operation due to the conductive wire. The upper electrode plate cannot be reliably switched to the LRS. That is, since the selected initial reset voltage is too heavy, the RRAM wafer corresponding to the operating characteristic curve 503 will also have a poor HTDR.
相較之下,操作特性曲線502對應的RRAM晶片所經歷成型操作及初始重置操作顯然優於另外二者,因此可將對應的成型電壓及初始重置電壓視為最佳操作條件,並可據以對相同製程的其他RRAM晶片進行成型操作及初始重置操作。In contrast, the RRAM wafer corresponding to the operating characteristic curve 502 undergoes a molding operation and an initial reset operation which are obviously superior to the other two, so that the corresponding molding voltage and the initial reset voltage can be regarded as optimal operating conditions, and The molding operation and the initial reset operation are performed on other RRAM wafers of the same process.
在其他實施例中,本發明實施例的方法還可一次對多個相同製程的RRAM晶片(或是一個大RRAM晶片所區隔出的多個小RRAM晶片)個別繪製操作特性曲線,並從中選出具備第(1)、(2)點特性的操作特性曲線。並且,若同時存在多個具備第(1)、(2)點特性的操作特性曲線,本發明的方法還可進一步將這些操作特性曲線進行比較,以從中找出較佳的操作特性曲線,並相應地找出最佳的操作條件。In other embodiments, the method of the embodiment of the present invention may separately draw and select operating characteristic curves for a plurality of RRAM wafers of the same process (or a plurality of small RRAM wafers separated by a large RRAM chip). An operating characteristic curve having the characteristics of points (1) and (2). Moreover, if there are a plurality of operating characteristic curves having the characteristics of points (1) and (2) at the same time, the method of the present invention can further compare the operating characteristic curves to find a better operating characteristic curve therefrom, and Find the best operating conditions accordingly.
請參照圖6,在本實施例中,假設操作特性曲線601、602、603、604係不同的RRAM晶片在經歷不同的成型電壓及初始重置電壓後,基於先前實施例中的教示所繪製而成。Referring to FIG. 6, in the present embodiment, it is assumed that the operating characteristic curves 601, 602, 603, and 604 are different RRAM wafers, after undergoing different forming voltages and initial reset voltages, based on the teachings in the previous embodiments. to make.
在圖6中,假設只有操作特性曲線602的最低錯誤位元值及操作電壓區間分別符合第一條件及第二條件,則可判定操作特性曲線602對應的成型電壓及初始重置電壓為各RRAM晶片的最佳操作條件。In FIG. 6, it is assumed that only the lowest error bit value and the operating voltage interval of the operating characteristic curve 602 meet the first condition and the second condition, respectively, and the forming voltage and the initial reset voltage corresponding to the operating characteristic curve 602 can be determined as each RRAM. Optimal operating conditions for the wafer.
然而,若操作特性曲線601的最低錯誤位元值及操作電壓區間亦分別符合第一條件及第二條件的話,則可接續將操作特性曲線601的最低錯誤位元值及操作特性曲線602的最低錯誤位元值進行比較。However, if the lowest error bit value and the operating voltage interval of the operating characteristic curve 601 also meet the first condition and the second condition, respectively, the lowest error bit value of the operating characteristic curve 601 and the lowest of the operating characteristic curve 602 can be continued. The error bit values are compared.
舉例而言,可判斷操作特性曲線601的最低錯誤位元值是否低於操作特性曲線602的最低錯誤位元值。由圖6可知,操作特性曲線601的最低錯誤位元值低於操作特性曲線602的最低錯誤位元值,因而可判定操作特性曲線601對應的成型電壓及初始重置電壓為各RRAM晶片的最佳操作條件。For example, it can be determined whether the lowest error bit value of the operational characteristic 601 is lower than the lowest error bit value of the operational characteristic 602. As can be seen from FIG. 6, the lowest error bit value of the operating characteristic curve 601 is lower than the lowest error bit value of the operating characteristic curve 602, so that the forming voltage and the initial reset voltage corresponding to the operating characteristic curve 601 can be determined to be the highest of each RRAM chip. Good operating conditions.
在其他實施例中,若操作特性曲線601的最低錯誤位元值高於操作特性曲線602的最低錯誤位元值時,則可判定操作特性曲線602對應的成型電壓及初始重置電壓為各RRAM晶片的最佳操作條件。In other embodiments, if the lowest error bit value of the operating characteristic curve 601 is higher than the lowest error bit value of the operating characteristic curve 602, the forming voltage and the initial reset voltage corresponding to the operating characteristic curve 602 can be determined as each RRAM. Optimal operating conditions for the wafer.
在其他實施例中,若操作特性曲線601的最低錯誤位元值等於於操作特性曲線602的最低錯誤位元值,則可接續判定操作特性曲線601的電壓操作區間是否大於操作特性曲線602的電壓操作區間。若是,則判定操作特性曲線601對應的成型電壓及初始重置電壓為最佳的操作條件,反之則判定操作特性曲線602對應的成型電壓及初始重置電壓為各RRAM晶片的最佳操作條件。In other embodiments, if the lowest error bit value of the operation characteristic curve 601 is equal to the lowest error bit value of the operation characteristic curve 602, it may be determined whether the voltage operation interval of the operation characteristic curve 601 is greater than the voltage of the operation characteristic curve 602. Operating interval. If so, it is determined that the molding voltage corresponding to the operating characteristic curve 601 and the initial reset voltage are optimal operating conditions, and conversely, the forming voltage and the initial reset voltage corresponding to the operating characteristic curve 602 are determined as optimal operating conditions for the respective RRAM wafers.
綜上所述,本發明實施例的方法可在對RRAM晶片進行成型操作及初始重置操作之後,基於多個不同的操作電壓對此RRAM晶片上的不同區塊進行不同的設定操作。之後,可統計各區塊上的錯誤位元值並繪製出此RRAM晶片的操作特性曲線,並基於操作特性曲線來判斷此RRAM晶片當初進行成型操作及初始重置操作的操作條件是否恰當。若操作特性曲線的最低錯誤位元值及操作電壓區間分別符合第一條件及第二條件,則判定上述成型操作及初始重置操作對應的操作條件為RRAM晶片的最佳操作條件。In summary, the method of the embodiment of the present invention can perform different setting operations on different blocks on the RRAM wafer based on a plurality of different operating voltages after performing the molding operation and the initial reset operation on the RRAM wafer. After that, the error bit value on each block can be counted and the operating characteristic curve of the RRAM wafer can be drawn, and based on the operation characteristic curve, it is judged whether the operating condition of the RRAM wafer initial molding operation and the initial reset operation is appropriate. If the lowest error bit value of the operation characteristic curve and the operation voltage interval meet the first condition and the second condition, respectively, it is determined that the operation condition corresponding to the molding operation and the initial reset operation is the optimal operating condition of the RRAM wafer.
此外,本發明實施例亦可一次繪製多個RRAM在經歷不同成型操作及初始重置操作後所對應的操作特性曲線,並從中找出最佳的操作特性曲線,進而以其對應的成型操作及初始重置操作對應的操作條件作為RRAM晶片的最佳操作條件。In addition, the embodiment of the present invention can also draw an operation characteristic curve corresponding to a plurality of RRAMs after undergoing different molding operations and initial reset operations, and find an optimal operation characteristic curve therefrom, and then use the corresponding molding operation and The operating conditions corresponding to the initial reset operation are the best operating conditions for the RRAM wafer.
雖然本發明已以實施例揭露如上,然其並非用以限定本發明,任何所屬技術領域中具有通常知識者,在不脫離本發明的精神和範圍內,當可作些許的更動與潤飾,故本發明的保護範圍當視後附的申請專利範圍所界定者為準。Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.
21、22‧‧‧間隙21, 22 ‧ ‧ gap
40‧‧‧第一RRAM晶片 40‧‧‧First RRAM Wafer
401a、401b、…、401p‧‧‧區塊 401a, 401b, ..., 401p‧‧‧ blocks
402a、402b、…、402p‧‧‧資料點 402a, 402b, ..., 402p‧‧‧ data points
403、501~503、601~604‧‧‧操作特性曲線 403, 501~503, 601~604‧‧‧ operating characteristic curve
403a‧‧‧U形區段 403a‧‧‧U-shaped section
VR‧‧‧操作電壓區間 VR‧‧‧Operating voltage range
VG‧‧‧閘極電壓 VG‧‧‧ gate voltage
X‧‧‧最低錯誤位元值 X‧‧‧ Lowest error bit value
S310~S360‧‧‧步驟 S310~S360‧‧‧Steps
圖1是本發明之一實施例的在各種成型電壓條件下所形成的導電絲態樣。 圖2是本發明之一實施例的在各種初始重置電壓條件下所造成的導電絲態樣。 圖3是依據本發明之一實施例繪示的找出RRAM的最佳操作條件的方法流程圖。 圖4是依據本發明之一實施例繪示的為RRAM晶片找出操作特性曲線的示意圖。 圖5是依據本發明之一實施例繪示的多條操作特性曲線示意圖。 圖6是依據本發明另一實施例繪示的多條操作特性曲線示意圖。BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a view showing a conductive filament pattern formed under various molding voltage conditions according to an embodiment of the present invention. 2 is a diagram of a conductive filament pattern caused by various initial reset voltage conditions in accordance with an embodiment of the present invention. 3 is a flow chart of a method for finding an optimal operating condition of an RRAM according to an embodiment of the invention. 4 is a schematic diagram of finding an operational characteristic curve for an RRAM wafer according to an embodiment of the invention. FIG. 5 is a schematic diagram of a plurality of operational characteristic curves according to an embodiment of the invention. FIG. 6 is a schematic diagram of a plurality of operating characteristic curves according to another embodiment of the invention.
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