CN111223508B - Memory storage device and resistive memory element forming method thereof - Google Patents
Memory storage device and resistive memory element forming method thereof Download PDFInfo
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- CN111223508B CN111223508B CN201811427146.9A CN201811427146A CN111223508B CN 111223508 B CN111223508 B CN 111223508B CN 201811427146 A CN201811427146 A CN 201811427146A CN 111223508 B CN111223508 B CN 111223508B
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- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
Abstract
The invention provides a memory storage device and a forming method of a resistance type memory element thereof. A test forming voltage is applied to the redundant resistive memory element, and a corresponding test current is read. And determining the forming voltage applied to the main memory cell block according to the test forming voltage, the test current, the forming current-voltage characteristic data and the target forming current.
Description
Technical Field
The present invention relates to a memory device, and more particularly, to a resistive memory device and a method for forming a resistive memory element thereof.
Background
In recent years, Resistive Memory, such as Resistive Random Access Memory (RRAM), has been developed very rapidly, and is currently the most attractive future Memory structure. Resistive memory devices are well suited for the next generation of non-volatile memory devices due to their low power consumption, high speed operation, high density, and potential advantages compatible with Complementary Metal Oxide Semiconductor (CMOS) process technologies. For reliability testing and commercialization, the High Temperature Data Retention (HTDR) of resistive memory elements has a decisive influence. In the prior art, there is still considerable effort to improve high temperature data retention or to make adjustments to the process, algorithms, or electrical parameters.
RRAM is a nonvolatile memory in which RRAM cells each include an upper electrode plate, a lower electrode plate, and a dielectric material layer sandwiched between the upper and lower electrode plates. The layer of dielectric material is typically insulating, and conductive paths (commonly referred to as Conductive Filaments (CF)) can be formed in the layer of dielectric material through the memory cell by applying a suitable voltage across the upper electrode plate to perform a forming operation (forming operation) on the memory cell.
After the conductive wires are formed, they are reset by applying a suitable voltage to the upper electrode plate, so that the conductive wires are disconnected, resulting in a High Resistance State (HRS) in the RRAM cell. Thereafter, the set operation (set operation) may be performed on the RRAM cell by applying an appropriate voltage to the upper electrode plate, and the conductive wire may be reformed, resulting in a Low Resistance State (LRS) on the RRAM cell. The resistance state (LRS or HRS) of the RRAM can be controlled by repeated set and reset operations, and the LRS and HRS can be used to indicate a "0" or "1" digital signal, thereby providing related memory functions.
In the prior art, as the manufacturing process and the materials used in RRAM are gradually changed, how to quickly and efficiently find out the proper operating conditions has become an important issue in the RRAM development process. If poor operating conditions are adopted, the related factors of materials are likely to be misjudged in the testing process, and further the development time and the efficiency of the RRAM are affected. Since the forming operation is a critical step in determining the manner of the conductive filament, finding a suitable voltage range for the forming operation is beneficial to forming a better conductive filament, thereby providing a good conductive path.
Disclosure of Invention
The invention provides a memory storage device and a forming method of a resistance type memory element thereof, which can optimize the forming voltage of a conductive wire of each crystal grain (die) so as to obtain the optimal High Temperature Data Retention (HTDR).
The memory storage device comprises a memory cell array and a memory control circuit. The memory cell array includes a main memory cell block and a redundancy memory cell block. The main memory cell block includes a plurality of resistive memory elements arranged in an array. The redundant memory cell block includes a plurality of redundant resistive memory elements arranged in an array. The memory control circuit is coupled with the memory cell array, applies a test forming voltage to at least one redundant resistance type memory element, reads a corresponding test current, and determines the forming voltage applied to the main memory cell block according to the test forming voltage, the test current, the forming current-voltage characteristic data and the target forming current.
In an embodiment of the invention, the memory control circuit includes a forming control circuit, a forming voltage generator and a forming current sensing circuit. The forming voltage generator is coupled with the forming control circuit and the memory array and is controlled by the forming control circuit to generate a test forming voltage and a forming voltage. The forming current sensing circuit is coupled with the forming control circuit and the memory array, reads the test current to generate a test current signal to the forming control circuit, and the forming control circuit determines a forming voltage according to the test forming voltage, the test current signal, the forming current voltage characteristic data and the target forming current and controls the forming voltage generator to apply the forming voltage to the main memory cell block.
The invention also provides a resistive memory element forming method of the memory storage device, the memory storage device comprises a memory array, the memory cell array comprises a main memory cell block and a redundant memory cell block, and the resistive memory element forming method comprises the following steps. A test forming voltage is applied to at least one redundant resistive memory element, and a corresponding test current is read. And determining the forming voltage applied to the main memory cell block according to the test forming voltage, the test current, the forming current-voltage characteristic data and the target forming current. A shaping voltage is applied to the main memory cell block.
Based on the above, the embodiment of the invention applies the test forming voltage to at least one redundant resistive memory element, reads the corresponding test current, and then determines the forming voltage applied to the main memory cell block according to the test forming voltage, the test current, the forming current-voltage characteristic data and the target forming current. Thus, the forming voltage used for forming the conductive wire for each crystal grain can be optimized to obtain the optimal high-temperature data holding capacity.
In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.
Drawings
FIG. 1 is a schematic diagram of a memory storage device according to an embodiment of the invention;
FIG. 2 is a schematic diagram of a memory storage device according to another embodiment of the invention;
FIG. 3 is a flow chart of a method for forming a resistive memory element of a memory storage device according to an embodiment of the invention.
The reference numbers illustrate:
102: memory control circuit
104: memory cell array
106: main memory cell block
108: redundant memory cell block
202: molding control circuit
204: shaping voltage generator
206: profiled current sensing circuit
S302 to S306: step (ii) of
Detailed Description
In the following, a number of embodiments are presented to illustrate the invention, however, the invention is not limited to the illustrated embodiments. Suitable combinations between the embodiments are also allowed. The term "coupled" as used throughout this specification, including the claims, may refer to any direct or indirect connection means. For example, if a first device couples to a second device, that should be construed that the first device may be directly connected to the second device or the first device may be indirectly connected to the second device through some other device or connection means. Furthermore, the term "signal" may refer to at least one current, voltage, charge, temperature, data, electromagnetic wave, or any other signal or signals.
FIG. 1 is a schematic diagram of a memory storage device according to an embodiment of the invention. The memory storage device of the present embodiment includes a memory control circuit 102 and a memory cell array 104. The memory cell array 104 is coupled to the memory control circuit 102. The memory cell array 104 includes a main memory cell block 106 and a redundant memory cell block 108, and the memory storage device may be, for example, a Resistive Random Access Memory (RRAM) device. The main memory cell block 106 includes a plurality of resistive memory elements (not shown) arranged in an array, and the redundant memory cell block 108 includes a plurality of redundant resistive memory elements (not shown) arranged in an array.
The memory control circuit 102 may perform a forming process (shaping process) on the resistive memory elements in the main memory cell block 106 and the redundancy memory cell block 108. The forming process refers to a process of initializing the resistive memory element. In this process, the electrodes at the two ends of the resistive memory element are continuously biased to generate an applied electric field to the dielectric layer. When the applied electric field exceeds a critical value, the dielectric layer will generate dielectric breakdown phenomenon to generate conductive wires, so as to change from a High Resistance State (HRS) to a Low Resistance State (LRS). Such breakdown is not permanent and the resistance of the dielectric layer can still be changed depending on the subsequently applied voltage.
Further, when the memory control circuit 102 of the present embodiment performs the forming process, a test forming voltage is applied to the redundant resistive memory element in the redundant memory cell block 108, a corresponding test current is read from the bit line, and a forming voltage applied to the resistive memory element in the main memory cell block 106 is determined according to the test forming voltage, the test current, the forming current-voltage characteristic data, and the target forming current. In detail, the memory control circuit 102 of the present embodiment may have a forming current voltage characteristic data set according to a target forming current required to be achieved by the main memory cell block 106, for indicating a test forming voltage, a relationship between the test current and the forming voltage. The forming current-voltage characteristic data may include a forming current-voltage characteristic curve or a forming current-voltage characteristic look-up table, wherein the forming current-voltage characteristic curve, the forming current-voltage characteristic look-up table and the target forming current may be different depending on the manufacturing process or circuit design of the memory storage device, but have similar characteristics for memory storage devices having the same manufacturing process and circuit design.
In some embodiments, the forming voltage may be determined using a forming current-voltage characteristic. For example, the forming current-voltage characteristic curve may be a straight line having a predetermined slope, in the embodiment, the predetermined slope may be 17, and the optimal target forming current for forming the conductive filament may be 31 μ a, but not limited thereto. When the memory control circuit 102 applies a test forming voltage of 1.9V to the redundant resistive memory elements in the redundant memory cell block 108, if the read test current is 25 μ a, the forming voltage applied to the main memory cell block 106 will be equal to 1.9+ (31-25)/17-2.253V. By analogy, if the read test current is 27 μ a, the shaping voltage applied to the main memory cell block 106 will be equal to 1.9+ (31-27)/17-2.135V. The test forming voltage and the forming voltage may include a gate voltage and a drain voltage, and the present embodiment is described by calculating the gate voltage, and the drain voltage may also be optimized in the same manner, which is not described herein again.
In other embodiments, the forming voltage may be determined by using a look-up table. For example, table 1 is an embodiment of a profiling current-voltage characteristic look-up table, which indicates the required applied profiling voltage for the main memory cell block 106 to reach the target profiling current according to the test profiling voltage applied to the redundant memory element and the read test current.
TABLE 1
As shown in table 1, the memory control circuit 102 may apply a fixed test forming voltage to the redundant resistive memory element, and then determine the forming voltage of the main memory cell block 106 according to the test current read from the redundant resistive memory element, so that the forming voltage does not need to be calculated according to the forming current-voltage characteristic curve as in the above embodiments, and the operation resources can be saved. For example, when the test current is 24 μ A, the table lookup can directly find that the corresponding forming voltage is 2.31V.
In some embodiments, to ensure the accuracy of the test current, the memory control circuit 102 calculates the test current for estimating the forming voltage according to the test current values read from the plurality of redundant resistive memory elements, for example, a median current value of the plurality of redundant resistive memory elements may be used as the test current for estimating the forming voltage, or an average value of the test currents of the plurality of redundant resistive memory elements may be used as the test current for estimating the forming voltage.
As described above, the memory storage device of the present embodiment can perform the molding process on the redundant memory cell block 108 to estimate the voltage value of the molding voltage applied to the main memory cell block 106, so as to optimize the formation of the conductive wire, improve the high temperature data retention capability of the memory storage device, and increase the reliability of the memory storage device. In addition, by using the conductive wire forming process of the present embodiment, the forming voltage used for forming the conductive wire for each die can be optimized, so as to improve the problem of conductive wire defects caused by inter-die variation (die-to-die variation) or wafer-to-wafer variation (wafer-to-wafer variation).
It should be noted that, in some embodiments, after applying the forming voltage to the main memory cell block 106, the memory control circuit 102 may determine whether the corresponding forming current has reached the target forming current, and if the corresponding forming current has not reached the target forming current, the memory control circuit 102 may further apply the forming voltage to the main memory cell block 106 until the forming current reaches the target forming current.
FIG. 2 is a schematic diagram of a memory storage device according to another embodiment of the invention. Further, the memory control circuit 102 of the embodiment of fig. 1 may include a shaping control circuit 202, a shaping voltage generator 204, and a shaping current sensing circuit 206, wherein the shaping voltage generator 204 is coupled to the shaping control circuit 202 and the memory cell array 104, and the shaping current sensing circuit 206 is coupled to the shaping control circuit 202 and the memory cell array 104. Wherein the forming control circuit 202 can control the forming voltage generator 204 to generate the test forming voltage to the redundant memory cell block in the memory cell array 104. The forming current sensing circuit 206 can read the test current corresponding to the test forming voltage to generate a test current signal, and transmit the test current signal to the forming control circuit 202. The forming control circuit 202 determines a forming voltage according to the test forming voltage, the test current signal, the forming current-voltage characteristic data, and the target forming current, and controls the forming voltage generator to apply the forming voltage to the main memory cell block 106. The detailed implementation of the forming control circuit 202 for determining the forming voltage is the same as the above embodiments, and therefore, the detailed description thereof is omitted.
FIG. 3 is a flow chart of a method for forming resistive memory elements of a memory device according to an embodiment of the invention. In the above embodiments, the method for forming a resistive memory element of a memory storage device may include at least the following steps. First, a test forming voltage is applied to at least one redundant resistive memory element, and a corresponding test current is read (step S302), wherein the test forming voltage includes a gate voltage and a drain voltage. Next, the forming voltage applied to the main memory cell block is determined according to the test forming voltage, the test current, the forming current-voltage characteristic data and the target forming current (step S304), wherein the forming current-voltage characteristic data may include, for example, a forming current-voltage characteristic curve or a forming current-voltage characteristic look-up table, the forming current-voltage characteristic curve may be, for example, a straight line having a predetermined slope, and the forming current-voltage characteristic look-up table may indicate that the target forming current is reached, and the test forming voltage and the forming voltage corresponding to the test current are determined. In addition, the test current may be, for example, a median current value of the plurality of redundant resistive memory elements as the test current for estimating the forming voltage, or an average value of the test currents of the plurality of redundant resistive memory elements as the test current for estimating the forming voltage. Finally, the estimated forming voltage is applied to the resistive memory element of the main memory cell block (step S306).
In summary, the embodiments of the invention perform the forming process on the redundant memory cell block to estimate the voltage value of the forming voltage applied to the main memory cell block, so as to optimize the formation of the conductive wire, improve the high temperature data retention capability of the memory storage device, and increase the reliability of the memory storage device. In addition, the conductive wire forming process of the above embodiment optimizes the forming voltage used for forming the conductive wire for each crystal grain, so as to effectively solve the problem of conductive wire defects caused by inter-crystal grain variation or inter-wafer variation.
Although the present invention has been described with reference to the above embodiments, it should be understood that various changes and modifications can be made therein by those skilled in the art without departing from the spirit and scope of the invention.
Claims (11)
1. A memory storage device, comprising:
an array of memory cells, comprising:
a main memory cell block including a plurality of resistive memory elements arranged in an array; and
a redundancy memory cell block including a plurality of redundancy resistive memory elements arranged in an array; and
and a memory control circuit coupled to the memory cell array for applying a test forming voltage to at least one redundant resistive memory element, reading a corresponding test current, and determining a forming voltage applied to the main memory cell block according to the test forming voltage, the test current, forming current-voltage characteristic data, and a target forming current.
2. The memory storage device of claim 1, wherein the memory control circuitry comprises:
a molding control circuit;
a forming voltage generator coupled to the forming control circuit and the memory cell array and controlled by the forming control circuit to generate the test forming voltage and the forming voltage; and
and the forming control circuit determines the forming voltage according to the test forming voltage, the test current signal, the forming current voltage characteristic data and the target forming current and controls the forming voltage generator to apply the forming voltage to the main memory cell block.
3. The memory storage device of claim 1 or 2, wherein the molding current-voltage characteristic data comprises a molding current-voltage characteristic curve or a molding current-voltage characteristic look-up table indicating the molding voltage corresponding to the test molding voltage and the test current signal to achieve the target molding current.
4. The memory storage device of claim 3, wherein the profiled current-voltage characteristic is a straight line having a preset slope.
5. The memory storage device of claim 1, wherein the test shaping voltage comprises a gate voltage and a drain voltage.
6. The memory storage device of claim 1, wherein the memory control circuit further determines the forming voltage applied to the main memory cell block according to a median current value of a test current corresponding to the at least one redundant resistive memory element.
7. A resistive memory element shaping method of a memory storage device, the memory storage device comprising a memory cell array comprising a main memory cell block and a redundant memory cell block, the resistive memory element shaping method comprising:
applying a test forming voltage to at least one redundant resistive memory element and reading a corresponding test current;
determining a forming voltage applied to the main memory cell block according to the test forming voltage, the test current, forming current-voltage characteristic data and a target forming current; and
applying the shaping voltage to the main memory cell block.
8. The method of claim 7, wherein the forming current-voltage characteristic data comprises a forming current-voltage characteristic curve or a forming current-voltage characteristic look-up table indicating a forming voltage corresponding to the test forming voltage and the test current signal to achieve the target forming current.
9. The method according to claim 8, wherein the forming current-voltage characteristic curve is a straight line having a predetermined slope.
10. The method according to claim 7, wherein the test forming voltage comprises a gate voltage and a drain voltage.
11. The resistive memory element forming method of claim 7, comprising:
determining the forming voltage applied to the main memory cell block according to a median current value of the test current corresponding to the at least one redundant resistive memory element.
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