<title lang="zh">具有適應性環路頻寬調整機制的時鐘資料恢復電路及利用其之通信裝置</title><technical-field><p>本發明係關於一種具時鐘資料恢復電路，特別是關於一種具有適應性環路頻寬調整機制的時鐘資料恢復電路。</p></technical-field><background-art><p>請參照圖1，其繪示一習知應用於高速串列資料通信之時鐘資料恢復電路之方塊圖。如圖1所示，該時鐘資料恢復電路具有一二進制相位偵測器11、一比例增益單元12、一積分器13、一加法器14及一壓控振盪器15。</p><p>於操作時，該時鐘資料恢復電路會依一資料信號RX_DATA，其載有一微小振幅的時鐘信號，以產生一回復時鐘信號RCLK，其中回復時鐘信號RCLK係與該微小振幅的時鐘信號具有相同的頻率。另外，資料信號RX_DATA的翻轉率(單位時間內的邏輯位準翻轉次數)會決定該時鐘資料恢復電路的更新頻率而影響到該時鐘資料恢復電路的環路頻寬，而該時鐘資料恢復電路的環路頻寬則直接決定了該時鐘資料恢復電路的雜訊容忍度。</p><p><img he="51" wi="427" img-format="jpg" id="i0003" img-content="drawing" orientation="portrait" inline="no" file="TWI648954B_D0001.tif" />另外，一般的二進位時鐘資料恢復電路的開環傳輸函數可表示如下：
</p><p><p>其中，
<img he="21" wi="33" img-format="jpg" id="i0005" img-content="drawing" orientation="portrait" inline="no" file="TWI648954B_D0002.tif" />代表一時鐘資料恢復電路的開環傳輸函數，
<img he="15" wi="12" img-format="jpg" id="i0005" img-content="drawing" orientation="portrait" inline="no" file="TWI648954B_D0003.tif" />代表一複數頻率(complex frequency)，
<img he="25" wi="25" img-format="jpg" id="i0005" img-content="drawing" orientation="portrait" inline="no" file="TWI648954B_D0004.tif" />代表一輸入資料的翻轉率，
<img he="25" wi="28" img-format="jpg" id="i0005" img-content="drawing" orientation="portrait" inline="no" file="TWI648954B_D0005.tif" />代表輸入資料雜訊的標準差，
<img he="24" wi="21" img-format="jpg" id="i0005" img-content="drawing" orientation="portrait" inline="no" file="TWI648954B_D0006.tif" />代表該時鐘資料恢復電路的一比例增益，
<img he="24" wi="20" img-format="jpg" id="i0005" img-content="drawing" orientation="portrait" inline="no" file="TWI648954B_D0007.tif" />代表該時鐘資料恢復電路的一積分路徑時間常數，
<img he="25" wi="21" img-format="jpg" id="i0005" img-content="drawing" orientation="portrait" inline="no" file="TWI648954B_D0008.tif" />代表該時鐘資料恢復電路的一環路更新周期，
<img he="24" wi="23" img-format="jpg" id="i0005" img-content="drawing" orientation="portrait" inline="no" file="TWI648954B_D0009.tif" />代表該時鐘資料恢復電路的一環路延遲時間周期，且其中輸入資料的翻轉率
<img he="25" wi="25" img-format="jpg" id="i0005" img-content="drawing" orientation="portrait" inline="no" file="TWI648954B_D0004.tif" />的大小直接決定了該時鐘資料恢復電路的一環路頻寬。請參照圖2，其繪示一習知二進位時鐘資料恢復電路的一實測結果。如圖2所示，在輸入資料的翻轉率α的數值越小的情形下，該習知二進位時鐘資料恢復電路的環路頻寬就越窄。
</p><p>為使環路頻寬維持固定，現有的解決方法包括：（1）以人為的方式調整一環路濾波器增益，以改變環路頻寬；以及（2）通過板級晶片測試獲得一環路頻寬，從而指導晶片內環路頻寬調節。</p><p>然而，方法(1)帶有盲目性，另外在應用環境改變時有不能自主調節的缺點；而方法(2)在大批量應用時其所需的測試工作量相當大。</p><p>為解決前述問題，本領域亟需一新穎的時鐘資料恢復電路。</p></background-art><disclosure><p>本發明之一目的在於揭露一種具有適應性環路頻寬調整機制的時鐘資料恢復電路，其可由一輸入資料信號獲得一回復時鐘信號及一回復資料信號，及依該回復時鐘信號及該回復資料信號獲得該回復資料信號的翻轉率。</p><p>本發明之另一目的在於揭露一種具有適應性環路頻寬調整機制的時鐘資料恢復電路，其可自動依一回復資料信號的翻轉率自我調節一環路頻寬，以使該環路頻寬維持固定。</p><p>本發明之另一目的在於揭露一種具有適應性環路頻寬調整機制的時鐘資料恢復電路，其可依一環路增益控制模組提高一時鐘資料的雜訊容忍性。</p><p>本發明之又一目的在於揭露一種具有適應性環路頻寬調整機制的時鐘資料恢復電路，其可在一次頻寬調節作業結束後關閉一環路增益控制模組以節省功耗。</p><p>為達前述目的，一種具有適應性環路頻寬調整機制的時鐘資料恢復電路乃被提出，其具有：</p><p>一時鐘資料恢復單元，係用以依一增益控制信號控制一環路頻寬以依一資料信號產生一回復時鐘信號；以及</p><p>一環路增益控制模組，係用以依該回復時鐘信號及該資料信號產生一回復資料信號，及依該回復資料信號之一翻轉率決定該增益控制信號的數值，以使該環路頻寬維持固定。</p><p>為達前述目的，另一種具有適應性環路頻寬調整機制的時鐘資料恢復電路乃被提出，其具有：</p><p>一相位偵測器，具有一資料信號輸入端、一時鐘信號輸入端及一相位偵測輸出端，該資料信號輸入端係用以接收一資料信號，該時鐘信號輸入端係用以接收一回復時鐘信號，且該相位偵測輸出端係用以提供一相位差輸出信號；</p><p>一環路濾波器，具有一濾波輸入端、一增益控制端及一濾波輸出端，且其內具一低通濾波電路，其中，該濾波輸入端係與該相位偵測輸出端耦接以接收該相位差輸出信號，該增益控制端係用以與一增益控制信號耦接以決定該低通濾波電路之一增益值，且該濾波輸出端係與該低通濾波電路之一輸出端耦接以提供一控制電壓信號；</p><p>一振盪單元，具有一控制電壓輸入端及一時鐘信號輸出端，該控制電壓輸入端係與該控制電壓信號耦接，該時鐘信號輸出端係用以提供該回復時鐘信號，其中該回復時鐘信號之一頻率係由該控制電壓信號之一電壓值決定；以及</p><p>一環路增益控制模組，其具有：</p><p>一第一正反器，具有一第一資料信號輸入端、一第一時鐘信號輸入端及一第一輸出端，該第一資料信號輸入端係用以接收該資料信號，該第一時鐘信號輸入端係用以接收該回復時鐘信號，且該第一輸出端係用以提供一回復資料信號之一目前邏輯電位；</p><p>一第二正反器，具有一第二資料信號輸入端、一第二時鐘信號輸入端及一第二輸出端，該第二資料信號輸入端係用以接收該回復資料信號，該第二時鐘信號輸入端係用以接收該回復時鐘信號，且該第二輸出端係用以提供該回復資料信號之一先前邏輯電位；</p><p>一互斥或邏輯單元，具有二輸入端以分別與該第一輸出端及該第二輸出端耦接，及一輸出端以提供一資料翻轉指示信號；</p><p>一第一計數器，具有一第一計數觸發端及一第一計數輸出端，該第一計數觸發端係與該回復時鐘信號耦接，且該第一計數輸出端係用以輸出一第一計數值；</p><p>一第二計數器，具有一第二計數觸發端及一第二計數輸出端，該第二計數觸發端係與該資料翻轉指示信號耦接，且該第二計數輸出端係用以輸出一第二計數值；以及</p><p>一翻轉率運算模組，具有二輸入端以分別與該第一計數輸出端及該第二計數輸出端耦接，及一輸出端以提供該增益控制信號，其中該翻轉率運算模組係依該第二計數值和該第一計數值的比值進行一轉換運算以決定該增益控制信號之一數值，以使該環路頻寬維持固定。</p><p>在一實施例中，該環路濾波器係一數位濾波器或一類比濾波器。</p><p>在一實施例中，該振盪單元係一壓控振盪器或一數位至相位轉換器。</p><p>在一實施例中，該轉換運算包含一線性轉換函數或一對照表。</p><p>為達前述目的，本發明進一步提出一種通信裝置，其具有如前述之具有適應性環路頻寬調整機制的時鐘資料恢復電路。</p><p>為使 貴審查委員能進一步瞭解本發明之結構、特徵及其目的，茲附以圖式及較佳具體實施例之詳細說明如後。</p></disclosure><mode-for-invention><p>請參照圖3，其繪示本發明之具有適應性環路頻寬調整機制的時鐘資料恢復電路之一實施例方塊圖。</p><p>如圖3所示，該時鐘資料恢復電路包括一相位偵測器100、一環路濾波器110、一振盪單元120及一環路增益控制模組130。</p><p>相位偵測器100係一二進制相位偵測器，且其係以二種電位狀態分別代表一相位領先狀態和一相位落後狀態。相位偵測器100具有一資料信號輸入端、一時鐘信號輸入端及一相位偵測輸出端，該資料信號輸入端係用以接收一資料信號RX_DATA，該時鐘信號輸入端係用以接收一回復時鐘信號RCLK，且該相位偵測輸出端係用以提供一相位差輸出信號PD。</p><p>環路濾波器110係一數位濾波器或一類比濾波器，其具有一濾波輸入端、一增益控制端及一濾波輸出端，且其內具一低通濾波電路，其中，該濾波輸入端係與該相位偵測輸出端耦接以接收該相位差輸出信號PD，該增益控制端係用以與一增益控制信號GAIN_CNTL耦接以決定該低通濾波電路之一增益值，且該濾波輸出端係與該低通濾波電路之一輸出端耦接以提供一控制電壓信號V
<sub>C</sub>。
</p><p>振盪單元120係一壓控振盪器或一數位至相位轉換器，其具有一控制電壓輸入端及一時鐘信號輸出端，該控制電壓輸入端係與該控制電壓信號V
<sub>C</sub>耦接，該時鐘信號輸出端係用以提供該回復時鐘信號RCLK，其中該回復時鐘信號RCLK之一頻率係由該控制電壓信號V
<sub>C</sub>之一電壓值決定。
</p><p>環路增益控制模組130具有一第一正反器131、一第二正反器132、一互斥或邏輯單元133、一第一計數器134、一第二計數器135及一翻轉率運算模組136。</p><p>第一正反器131具有一第一資料信號輸入端、一第一時鐘信號輸入端及一第一輸出端，該第一資料信號輸入端係用以接收該資料信號RX_DATA，該第一時鐘信號輸入端係用以接收該回復時鐘信號RCLK，且該第一輸出端係用以提供一回復資料信號D
<sub>n</sub>。
</p><p>第二正反器132具有一第二資料信號輸入端、一第二時鐘信號輸入端及一第二輸出端，該第二資料信號輸入端係用以接收該回復資料信號D
<sub>n</sub>，該第二時鐘信號輸入端係用以接收該回復時鐘信號RCLK，且該第二輸出端係用以提供一先前回復資料信號D
<sub>n-1</sub>，也就是說，所述先前回復資料信號D
<sub>n-1</sub>和該回復資料信號D
<sub>n</sub>之間有著該回復時鐘信號RCLK的一個時鐘周期的相位差。
</p><p>互斥或邏輯單元133具有二輸入端以分別與該第一輸出端及該第二輸出端耦接，及一輸出端以提供一資料翻轉指示信號D
<sub>R</sub>。
</p><p>第一計數器134具有一第一計數觸發端及一第一計數輸出端，該第一計數觸發端係與該回復時鐘信號RCLK耦接，且該第一計數輸出端係用以輸出一第一計數值CNT1。</p><p>第二計數器135具有一第二計數觸發端及一第二計數輸出端，該第二計數觸發端係與該資料翻轉指示信號D
<sub>R</sub>耦接，且該第二計數輸出端係用以輸出一第二計數值CNT2。
</p><p>翻轉率運算模組136具有二輸入端以分別與該第一計數輸出端及該第二計數輸出端耦接，及一輸出端以提供該增益控制信號GAIN_CNTL，其中該翻轉率運算模組係依該第二計數值CNT2和該第一計數值CNT1的比值進行一轉換運算以決定該增益控制信號之一數值，以使該環路頻寬維持固定。該轉換運算可包含一線性轉換函數或一對照表。</p><p>於操作時，互斥或邏輯單元133會對該回復資料信號D
<sub>n</sub>及所述先前回復資料信號D
<sub>n-1</sub>進行一互斥或運算，以在該回復資料信號D
<sub>n</sub>和所述先前回復資料信號D
<sub>n-1</sub>的邏輯電位相異(一為邏輯1，另一為邏輯0)時使該資料翻轉指示信號D
<sub>R</sub>產生邏輯1以代表一次翻轉；第一計數器134所產生的第一計數值CNT1代表一單位時間；第二計數器135所產生的第二計數值CNT2代表一翻轉次數；翻轉率運算模組136係依該翻轉次數和該單位時間的比值產生一翻轉率，並對該翻轉率進行一轉換運算以產生該增益控制信號GAIN_CNTL之一數值，從而使該時鐘資料恢復電路的環路頻寬維持固定。
</p><p>請參照圖4，其繪示本發明之具有適應性環路頻寬調整機制的時鐘資料恢復電路之一實測結果，如圖4所示，在各種不同資料翻轉率的條件下，本發明之具有適應性環路頻寬調整機制的時鐘資料恢復電路均能使環路頻寬維持固定。</p><p>另外，環路增益控制模組130可在完成一次頻寬調節作業結束後停止工作，或每間隔一段時間執行一次頻寬調節作業，以節省電路的功耗。</p><p>另外，依本發明所能獲致的技術效果，本發明的具有適應性環路頻寬調整機制的時鐘資料恢復電路乃可應用於V-by-one(一種平板顯示器的信號傳輸接口標準)高速串列資料通信、HDMI（high definition multimedia interface；高畫質多媒體介面）資料通信、EDP (embedded display port；嵌入式顯示埠) 資料通信、PCIE（peripheral component interconnect-express快速型周邊部件互連）資料通信及USB（universal serial bus；通用序列匯流排）資料通信等領域的通信裝置中。</p><p>藉由前述所揭露的設計，本發明乃可提供以下優點：</p><p>1.本發明之具有適應性環路頻寬調整機制的時鐘資料恢復電路可由一輸入資料信號獲得一回復時鐘信號及一回復資料信號，及依該回復時鐘信號及該回復資料信號獲得該回復資料信號的翻轉率。</p><p>2.本發明之具有適應性環路頻寬調整機制的時鐘資料恢復電路可自動依一回復資料信號的翻轉率自我調節一環路頻寬，以使該環路頻寬維持固定。</p><p>3.本發明之具有適應性環路頻寬調整機制的時鐘資料恢復電路可依一環路增益控制模組提高一時鐘資料的雜訊容忍性。</p><p>4.本發明之具有適應性環路頻寬調整機制的時鐘資料恢復電路可在一次頻寬調節作業結束後關閉一環路增益控制模組以節省功耗。</p><p>本案所揭示者，乃較佳實施例，舉凡局部之變更或修飾而源於本案之技術思想而為熟習該項技藝之人所易於推知者，俱不脫本案之專利權範疇。</p><p>綜上所陳，本案無論就目的、手段與功效，在在顯示其迥異於習知之技術特徵，且其首先發明合於實用，亦在在符合發明之專利要件，懇請 貴審查委員明察，並祈早日賜予專利，俾嘉惠社會，實感德便。</p></mode-for-invention><description-of-drawings><description-of-element><p>11‧‧‧二進制相位偵測器</p><p>12‧‧‧比例增益單元</p><p>13‧‧‧積分器</p><p>14‧‧‧加法器</p><p>15‧‧‧壓控振盪器</p><p>100‧‧‧第一相位偵測器</p><p>110‧‧‧環路濾波器</p><p>120‧‧‧振盪單元</p><p>130‧‧‧環路增益控制模組</p><p>131‧‧‧第一正反器</p><p>132‧‧‧第二正反器</p><p>133‧‧‧互斥或邏輯單元</p><p>134‧‧‧第一計數器</p><p>135‧‧‧第二計數器</p><p>136‧‧‧翻轉率運算模組</p></description-of-element><p>圖1繪示一習知應用於高速串列資料通信之時鐘資料恢復電路之方塊圖。 圖2繪示一習知二進位時鐘資料恢復電路的一實測結果。 圖3繪示本發明之具有適應性環路頻寬調整機制的時鐘資料恢復電路之一實施例方塊圖。 圖4繪示本發明之具有適應性環路頻寬調整機制的時鐘資料恢復電路之一實測結果。</p></description-of-drawings><bio-deposit /><sequence-list-text /><title lang="zh">Clock data recovery circuit with adaptive loop bandwidth adjustment mechanism and communication device using the same</title><technical-field><p>The present invention relates to a clock data recovery circuit In particular, it relates to a clock data recovery circuit with an adaptive loop bandwidth adjustment mechanism. </p></technical-field><background-art><p> Referring to FIG. 1, a block diagram of a conventional clock data recovery circuit for high-speed serial data communication is shown. As shown in FIG. 1, the clock data recovery circuit has a binary phase detector 11, a proportional gain unit 12, an integrator 13, an adder 14, and a voltage controlled oscillator 15. </p><p> In operation, the clock data recovery circuit according to a data signal RX_DATA, which carries a clock signal of a small amplitude to generate a return clock signal RCLK, wherein the clock signal RCLK is restored with the small amplitude The clock signals have the same frequency. In addition, the inversion rate of the data signal RX_DATA (the number of logic level inversions per unit time) determines the update frequency of the clock data recovery circuit and affects the loop bandwidth of the clock data recovery circuit, and the clock data recovery circuit The loop bandwidth directly determines the noise tolerance of the clock data recovery circuit. </p><p><img he="51" wi="427" img-format="jpg" id="i0003" img-content="drawing" orientation="portrait" inline="no" file= "TWI648954B_D0001.tif" /> In addition, the open-loop transfer function of the general binary clock data recovery circuit can be expressed as follows:
</p><p><p>where,
<img he="21" wi="33" img-format="jpg" id="i0005" img-content="drawing" orientation="portrait" inline="no" file="TWI648954B_D0002.tif" /> An open loop transfer function representing a clock data recovery circuit,
<img he="15" wi="12" img-format="jpg" id="i0005" img-content="drawing" orientation="portrait" inline="no" file="TWI648954B_D0003.tif" /> Represents a complex frequency,
<img he="25" wi="25" img-format="jpg" id="i0005" img-content="drawing" orientation="portrait" inline="no" file="TWI648954B_D0004.tif" /> Represents the flip rate of an input data,
<img he="25" wi="28" img-format="jpg" id="i0005" img-content="drawing" orientation="portrait" inline="no" file="TWI648954B_D0005.tif" /> Represents the standard deviation of the input data noise,
<img he="24" wi="21" img-format="jpg" id="i0005" img-content="drawing" orientation="portrait" inline="no" file="TWI648954B_D0006.tif" /> Representing a proportional gain of the clock data recovery circuit,
<img he="24" wi="20" img-format="jpg" id="i0005" img-content="drawing" orientation="portrait" inline="no" file="TWI648954B_D0007.tif" /> An integral path time constant representing the clock data recovery circuit,
<img he="25" wi="21" img-format="jpg" id="i0005" img-content="drawing" orientation="portrait" inline="no" file="TWI648954B_D0008.tif" /> Representing a loop update cycle of the clock data recovery circuit,
<img he="24" wi="23" img-format="jpg" id="i0005" img-content="drawing" orientation="portrait" inline="no" file="TWI648954B_D0009.tif" /> Representing a loop delay time period of the clock data recovery circuit, and the flip rate of the input data
<img he="25" wi="25" img-format="jpg" id="i0005" img-content="drawing" orientation="portrait" inline="no" file="TWI648954B_D0004.tif" /> The size directly determines the loop bandwidth of the clock data recovery circuit. Please refer to FIG. 2, which shows a measured result of a conventional binary clock data recovery circuit. As shown in FIG. 2, in the case where the value of the inversion rate α of the input data is smaller, the loop bandwidth of the conventional binary clock data recovery circuit is narrower.
</p><p>In order to maintain the loop bandwidth fixed, existing solutions include: (1) artificially adjusting the loop filter gain to change the loop bandwidth; and (2) passing the board level The wafer test obtains a loop bandwidth to guide the loop bandwidth adjustment within the wafer. </p><p>However, method (1) is blind, and there is a disadvantage that it cannot be adjusted autonomously when the application environment changes; and method (2) requires a considerable amount of test work in high-volume applications. . </p><p> In order to solve the aforementioned problems, there is a need in the art for a novel clock data recovery circuit. </p></background-art><disclosure><p> One of the objects of the present invention is to disclose a clock data recovery circuit with an adaptive loop bandwidth adjustment mechanism, which can obtain a reply clock signal from an input data signal. And returning a data signal, and obtaining a turnover rate of the reply data signal according to the reply clock signal and the reply data signal. </p><p> Another object of the present invention is to disclose a clock data recovery circuit with an adaptive loop bandwidth adjustment mechanism, which can automatically adjust a loop bandwidth according to a flip rate of a reply data signal, Keep the loop bandwidth constant. Another object of the present invention is to disclose a clock data recovery circuit with an adaptive loop bandwidth adjustment mechanism, which can improve the noise tolerance of a clock data according to a loop gain control module. </p><p> A further object of the present invention is to disclose a clock data recovery circuit with an adaptive loop bandwidth adjustment mechanism, which can close a loop gain control module after the end of the primary bandwidth adjustment operation to save Power consumption. </p><p>To achieve the foregoing purpose, a clock data recovery circuit with an adaptive loop bandwidth adjustment mechanism is proposed, which has:</p><p>a clock data recovery unit, which is used for Controlling a loop bandwidth according to a gain control signal to generate a return clock signal according to a data signal; and </p><p> a loop gain control module for generating a signal according to the reply clock signal and the data signal The data signal is replied, and the value of the gain control signal is determined according to a flip rate of the reply data signal, so that the loop bandwidth is maintained constant. </p><p>For the foregoing purposes, another clock data recovery circuit with an adaptive loop bandwidth adjustment mechanism is proposed, which has: </p><p>a phase detector with one a data signal input end, a clock signal input end and a phase detection output end, wherein the data signal input end is configured to receive a data signal, the clock signal input end is configured to receive a return clock signal, and the phase detection The output end is configured to provide a phase difference output signal; </p><p> a loop filter having a filter input end, a gain control end and a filter output end, and having a low pass filter circuit therein The filter input end is coupled to the phase detection output end to receive the phase difference output signal, and the gain control end is coupled to a gain control signal to determine a gain value of the low pass filter circuit. And the filter output end is coupled to an output end of the low pass filter circuit to provide a control voltage signal; </p><p> an oscillating unit having a control voltage input end and a clock signal output end, Control voltage input terminal and the control power The voltage signal is coupled to provide the return clock signal, wherein a frequency of the return clock signal is determined by a voltage value of the control voltage signal; and </p><p> a loop gain a control module, comprising: </p><p> a first flip-flop having a first data signal input end, a first clock signal input end and a first output end, the first data signal input The end is configured to receive the data signal, the first clock signal input end is configured to receive the reply clock signal, and the first output end is configured to provide a current logic potential of a reply data signal;</p>< a second data signal input terminal, a second clock signal input end and a second output end, wherein the second data signal input end is configured to receive the reply data signal, the first The second clock signal input end is configured to receive the reply clock signal, and the second output end is configured to provide a previous logic potential of the reply data signal; </p><p>a mutually exclusive or logic unit having two Input end to the first output and the second The output end is coupled to the output end to provide a data flip indication signal;</p><p> a first counter having a first count trigger end and a first count output end, the first count trigger end The first counter output is configured to output a first count value; </p><p> a second counter having a second count trigger and a second count The output end, the second counting trigger end is coupled to the data flip indication signal, and the second count output end is configured to output a second count value; and </p><p> a flip rate calculation module a second input end coupled to the first count output end and the second count output end, and an output end to provide the gain control signal, wherein the flip rate calculation module is based on the second count value and The ratio of the first count value is subjected to a conversion operation to determine a value of the gain control signal such that the loop bandwidth remains fixed. </p><p> In one embodiment, the loop filter is a digital filter or an analog filter. </p><p> In one embodiment, the oscillating unit is a voltage controlled oscillator or a digital to phase converter. </p><p> In one embodiment, the conversion operation includes a linear conversion function or a look-up table. For the foregoing purposes, the present invention further provides a communication apparatus having a clock data recovery circuit having an adaptive loop bandwidth adjustment mechanism as described above. The structure, features, and objects of the present invention will become more apparent from the following detailed description. </p></disclosure><mode-for-invention><p> Referring to FIG. 3, a block diagram of an embodiment of a clock data recovery circuit with an adaptive loop bandwidth adjustment mechanism of the present invention is shown. </p><p> As shown in FIG. 3, the clock data recovery circuit includes a phase detector 100, a loop filter 110, an oscillating unit 120, and a loop gain control module 130. </p><p>The phase detector 100 is a binary phase detector, and it represents a phase leading state and a phase backward state in two potential states. The phase detector 100 has a data signal input end, a clock signal input end and a phase detection output end. The data signal input end is configured to receive a data signal RX_DATA, and the clock signal input end is configured to receive a reply. The clock signal RCLK is used to provide a phase difference output signal PD. </p><p>The loop filter 110 is a digital filter or an analog filter having a filter input terminal, a gain control terminal and a filter output terminal, and has a low pass filter circuit therein. The filter input terminal is coupled to the phase detection output terminal to receive the phase difference output signal PD, and the gain control terminal is coupled to a gain control signal GAIN_CNTL to determine a gain of the low pass filter circuit. a value, and the filter output is coupled to an output of the low pass filter circuit to provide a control voltage signal V
<sub>C</sub>.
</p><p> The oscillating unit 120 is a voltage controlled oscillator or a digital to phase converter having a control voltage input terminal and a clock signal output terminal, and the control voltage input terminal and the control voltage signal V
The <sub>C</sub> is coupled, the clock signal output end is configured to provide the return clock signal RCLK, wherein a frequency of the return clock signal RCLK is controlled by the control voltage signal V
The voltage value of one of <sub>C</sub> is determined.
</p><p>The loop gain control module 130 has a first flip-flop 131, a second flip-flop 132, a mutually exclusive or logic unit 133, a first counter 134, and a second counter 135. And a flip rate calculation module 136. </p><p> The first flip-flop 131 has a first data signal input end, a first clock signal input end and a first output end, and the first data signal input end is configured to receive the data signal RX_DATA, the first clock signal input end is configured to receive the reply clock signal RCLK, and the first output end is configured to provide a reply data signal D
<sub>n</sub>.
</p><p> The second flip-flop 132 has a second data signal input terminal, a second clock signal input terminal and a second output terminal, and the second data signal input terminal is configured to receive the reply data. Signal D
<sub>n</sub>, the second clock signal input end is configured to receive the reply clock signal RCLK, and the second output end is configured to provide a previous reply data signal D
<sub>n-1</sub>, that is, the previous reply data signal D
<sub>n-1</sub> and the reply data signal D
There is a phase difference of one clock period of the reply clock signal RCLK between <sub>n</sub>.
</p><p>The mutual exclusion or logic unit 133 has two inputs for coupling with the first output and the second output, and an output for providing a data flip indication signal D.
<sub>R</sub>.
</p><p> The first counter 134 has a first counting trigger end and a first counting output end, the first counting trigger end is coupled to the reply clock signal RCLK, and the first counting output end is It is used to output a first count value CNT1. </p><p>The second counter 135 has a second counting trigger terminal and a second counting output terminal, and the second counting trigger terminal and the data inversion indicating signal D
The <sub>R</sub> is coupled, and the second counting output is configured to output a second count value CNT2.
</p><p>The flip rate calculation module 136 has two input ends respectively coupled to the first count output end and the second count output end, and an output end to provide the gain control signal GAIN_CNTL, wherein The flip rate calculation module performs a conversion operation according to the ratio of the second count value CNT2 and the first count value CNT1 to determine a value of the gain control signal so that the loop bandwidth remains fixed. The conversion operation can include a linear conversion function or a look-up table. </p><p>In operation, the mutex or logic unit 133 will respond to the data signal D
<sub>n</sub> and the previous reply data signal D
<sub>n-1</sub> performs a mutual exclusion operation on the reply data signal D
<sub>n</sub> and the previous reply data signal D
When the logical potential of <sub>n-1</sub> is different (one is logic 1 and the other is logic 0), the data is inverted to indicate signal D.
<sub>R</sub> generates a logic 1 to represent a flip; the first counter value CNT1 generated by the first counter 134 represents a unit time; the second counter value CNT2 generated by the second counter 135 represents a number of flips; The flip rate calculation module 136 generates a flip rate according to the ratio of the number of flips and the unit time, and performs a conversion operation on the flip rate to generate a value of the gain control signal GAIN_CNTL, so that the clock data recovery circuit The loop bandwidth remains fixed.
</p><p>Please refer to FIG. 4, which shows the measured result of the clock data recovery circuit with the adaptive loop bandwidth adjustment mechanism of the present invention, as shown in FIG. 4, at various data inversion rates. Under the condition, the clock data recovery circuit with the adaptive loop bandwidth adjustment mechanism of the present invention can maintain the loop bandwidth constant. </p><p> In addition, the loop gain control module 130 can stop working after completion of a bandwidth adjustment operation, or perform a bandwidth adjustment operation every interval to save power consumption of the circuit. </p><p> In addition, according to the technical effects that can be obtained by the present invention, the clock data recovery circuit with the adaptive loop bandwidth adjustment mechanism of the present invention can be applied to V-by-one (a flat panel display). Signal transmission interface standard) High-speed serial data communication, HDMI (high definition multimedia interface) data communication, EDP (embedded display port) data communication, PCIE (peripheral component interconnect-express fast type) Peripheral components are interconnected in communication devices such as data communication and USB (universal serial bus) data communication. </p><p>The present invention provides the following advantages by the foregoing disclosed design:</p><p>1. The clock data recovery circuit of the present invention having an adaptive loop bandwidth adjustment mechanism can be An input data signal obtains a reply clock signal and a reply data signal, and obtains a flip rate of the reply data signal according to the reply clock signal and the reply data signal. </p><p>2. The clock data recovery circuit with the adaptive loop bandwidth adjustment mechanism of the present invention can automatically adjust the loop bandwidth according to the flip rate of the data signal to make the loop bandwidth. Maintain fixed. </p><p>3. The clock data recovery circuit with adaptive loop bandwidth adjustment mechanism of the present invention can improve the noise tolerance of a clock data according to a loop gain control module. </p><p>4. The clock data recovery circuit with the adaptive loop bandwidth adjustment mechanism of the present invention can close the loop gain control module after the end of the primary bandwidth adjustment operation to save power consumption. </p><p>The person disclosed in the present case is a preferred embodiment. Anyone who has changed or modified locally and originated from the technical idea of the case and is easily acquainted by those who are familiar with the skill, does not deviate from the patent of the case. The scope of rights. </p><p>In summary, the case, regardless of its purpose, means and efficacy, is showing its technical characteristics that are different from the conventional ones, and its first invention is practical and practical, and it is also in compliance with the patent requirements of the invention. Your review board member is inspected and prayed for an early patent. </p></mode-for-invention><description-of-drawings><description-of-element><p>11‧‧‧Binary Phase Detector</p><p>12‧‧ Gain unit</p><p>13‧‧Integrator</p><p>14‧‧ Adder</p><p>15‧‧‧Variable-controlled oscillator</p><p> 100‧‧‧First Phase Detector</p><p>110‧‧‧Circuit Filter</p><p>120‧‧‧Oscillator Unit</p><p>130‧‧‧ Ring Road Gain Control Module</p><p>131‧‧‧First Front and Back Counter</p><p>132‧‧‧Secondary Forward and Reverser</p><p>133‧‧‧Exclusive Or logical unit</p><p>134‧‧‧first counter</p><p>135‧‧‧second counter</p><p>136‧‧‧flip rate computing module</p ></description-of-element> <p> FIG. 1 is a block diagram showing a conventional clock data recovery circuit applied to high-speed serial data communication. FIG. 2 illustrates a measured result of a conventional binary clock data recovery circuit. 3 is a block diagram showing an embodiment of a clock data recovery circuit of the present invention having an adaptive loop bandwidth adjustment mechanism. FIG. 4 is a diagram showing measured results of a clock data recovery circuit with an adaptive loop bandwidth adjustment mechanism according to the present invention. </p></description-of-drawings><bio-deposit /><sequence-list-text />