TWI648634B - Memory management method, memory storage device and memory control circuit unit - Google Patents

Abstract

An exemplary embodiment of the present invention provides a memory management method, including: receiving a plurality of instructions from a host system; counting a latest idle time corresponding to the instruction and a past average instruction receiving time interval; if the latest idle time is greater than the first threshold The value and the past average command receiving time interval is greater than the second threshold, dynamically switching the operating mode of the memory storage device from the first operating mode to the second operating mode. Thereby, the power consumption of the memory storage device can be reduced, and the memory storage device can be prevented from switching too frequently between different operating modes.

Description

Memory management method, memory storage device, and memory control circuit unit

The invention relates to a memory management method, a memory storage device and a memory control circuit unit.

Digital cameras, mobile phones and MP3 players have grown very rapidly in recent years, and the demand for storage media has increased rapidly. Because the rewritable non-volatile memory module (for example, flash memory) has the characteristics of non-volatile data, power saving, small size, and no mechanical structure, it is very suitable. It is built into various portable multimedia devices exemplified above.

In general, the memory storage device may be pre-set with a fixed threshold value to determine whether to enter the idle mode or the power saving mode. When the memory storage device has not received an instruction from the host system for a long time such that its idle time exceeds the threshold, the memory storage device enters the idle mode or the power saving mode to save power consumption. In addition, when entering the idle mode, the memory storage device usually uses the idle time to write the data in the buffer memory into the rewritable non-volatile memory module. However, if the memory storage device enters the idle mode or the power saving mode too frequently, the read/write frequency of the rewritable non-volatile memory module may be greatly increased, and the rewritable non-volatile memory mode may be shortened. The service life of the group.

An exemplary embodiment of the present invention provides a memory management method, a memory storage device, and a memory control circuit unit, which can determine whether to switch the working mode according to two different meaning parameters, and extend the rewritable non-volatile memory module. The service life.

An exemplary embodiment of the present invention provides a memory management method for a memory storage device including a counting circuit, a working mode controller, and a rewritable non-volatile memory module, the memory management method including: Receiving, by the host system, a plurality of instructions; counting, by the counting circuit, a latest idle time corresponding to the instruction and a past average instruction receiving time interval corresponding to the instruction; if the latest idle time is greater than the first threshold and The past average command receiving time interval is greater than a second threshold value, and the working mode controller dynamically switches the working mode of the memory storage device from the first working mode to the second working mode; and if the latest idle state The time is not greater than the first threshold or the past average command receiving time interval is not greater than the second threshold, and the operating mode of the memory storage device is maintained by the operating mode controller a first mode of operation, wherein the memory storage device operates in the first mode of operation and consumes more power than the memory Device operates in the second operating mode the power consumption is saved.

In an exemplary embodiment of the present invention, the step of counting, by the counting circuit, the past average instruction receiving time interval of the instruction comprises: counting a first past instruction receiving time interval and a second past instruction receiving time interval; A weighted average of the first past instruction reception time interval and the second past instruction reception time interval is calculated to obtain the past average instruction reception time interval.

In an exemplary embodiment of the present invention, the step of calculating the weighted average of the first past instruction receiving time interval and the second past instruction receiving time interval comprises: determining a first past instruction receiving time a first weight value of the interval and a second weight value corresponding to the second past instruction receiving time interval; and according to the first weight value, the second weight value, the first past instruction receiving time interval, and The second past instruction receives a time interval to calculate the weighted average.

In an exemplary embodiment of the present invention, the first past instruction receiving time interval refers to a receiving time interval between a first instruction in the instruction and a previous instruction in the first instruction, and the second past instruction The receiving time interval is a receiving time interval between the second instruction in the instruction and the previous instruction in the second instruction, and determining the first weight value corresponding to the first past instruction receiving time interval and corresponding The step of receiving the second weight value of the second past instruction receiving time interval includes: determining the first weight value and the second weight value according to a receiving order of the first instruction and the second instruction .

In an exemplary embodiment of the present invention, the step of determining the first weight value and the second weight value according to the receiving order of the first instruction and the second instruction includes: responding to the Receiving a time point of an instruction earlier than a receiving time point of the second instruction, determining the first weight value as a first value and determining the second weight value as a second value greater than the first value .

In an exemplary embodiment of the present invention, the weighted average is calculated according to the first weight value, the second weight value, the first past instruction receiving time interval, and the second past instruction receiving time interval. The steps include: calculating the weighted average according to the following equation:

Where REF represents the past average instruction reception time interval, V[k] represents the kth weight value, ΔT[k] represents the kth past instruction reception time interval, and k and N are both positive integers.

In an exemplary embodiment of the present invention, the second working mode includes an interrupt mode, and the memory management method further includes: switching to the interrupt mode in response to the working mode of the memory storage device Sending a sequence of write instructions to instruct storage of data temporarily stored in the buffer memory into the rewritable non-volatile memory module; and emptying the buffer memory.

Another exemplary embodiment of the present invention provides a memory storage device including a connection interface unit, a rewritable non-volatile memory module, and a memory control circuit unit. The connection interface unit is configured to be coupled to a host system. The memory control circuit unit is coupled to the connection interface unit and the rewritable non-volatile memory module, wherein the memory control circuit unit is configured to receive a plurality of instructions from the host system, wherein The memory control circuit unit is further configured to count a latest idle time corresponding to the instruction and a past average instruction reception time interval corresponding to the instruction, wherein the latest idle time is greater than the first threshold and the past The average command receiving time interval is greater than the second threshold, and the memory control circuit unit is further configured to dynamically switch the working mode of the memory storage device from the first working mode to the second working mode, wherein the latest The idle control time is not greater than the first threshold or the past average command reception interval is not greater than the second threshold, and the memory control circuit unit is further configured to use the working mode of the memory storage device Maintaining in the first working mode, wherein the memory storage device operates in the first operating mode and consumes more power than the recording Device operates in the second operating mode the power consumption of the storage body.

In an exemplary embodiment of the present invention, the operation of the memory control circuit unit to count the past average instruction receiving time interval of the instruction comprises: counting a first past instruction receiving time interval and a second past instruction receiving time interval And calculating a weighted average of the first past instruction reception time interval and the second past instruction reception time interval to obtain the past average instruction reception time interval.

In an exemplary embodiment of the present invention, the operation of the memory control circuit unit to calculate the weighted average of the first past instruction receiving time interval and the second past instruction receiving time interval includes: determining a corresponding a first weight value of the first past instruction receiving time interval and a second weight value corresponding to the second past instruction receiving time interval; and according to the first weight value, the second weight value, the first The past instruction reception time interval and the second past instruction reception time interval are used to calculate the weighted average.

In an exemplary embodiment of the present invention, the first past instruction receiving time interval refers to a receiving time interval between a first instruction in the instruction and a previous instruction in the first instruction, and the second past instruction The receiving time interval refers to a receiving time interval of a second instruction in the instruction and a previous instruction of the second instruction, and the memory control circuit unit determines a location corresponding to the first past instruction receiving time interval The operation of the first weight value and the second weight value corresponding to the second past instruction receiving time interval includes: determining the first weight value according to the receiving order of the first instruction and the second instruction And the second weight value.

In an exemplary embodiment of the present invention, the memory control circuit unit determines an operation of the first weight value and the second weight value according to the receiving order of the first instruction and the second instruction. The method includes: determining, according to a receiving time point of the first instruction, a receiving time point of the second instruction, determining the first weight value as a first value, and determining the second weight value to be greater than the The second value of the first value.

In an exemplary embodiment of the present invention, the memory control circuit unit is configured to receive, according to the first weight value, the second weight value, the first past instruction receiving time interval, and the second past instruction receiving time. The operation of calculating the weighted average by the interval includes calculating the weighted average according to the following equation:

Where REF represents the past average instruction reception time interval, V[k] represents the kth weight value, ΔT[k] represents the kth past instruction reception time interval, and k and N are both positive integers.

In an exemplary embodiment of the present invention, the second working mode includes an interrupt mode, and the memory control circuit unit is further configured to switch to the interrupt in response to the operating mode of the memory storage device a mode of transmitting a write command sequence to indicate that the data temporarily stored in the buffer memory is stored in the rewritable non-volatile memory module, wherein the memory control circuit unit is further configured to clear the buffer memory body.

Another exemplary embodiment of the present invention provides a memory control circuit unit for controlling a memory storage device, wherein the memory storage device includes a rewritable non-volatile memory module, wherein the memory control The circuit unit includes a host interface, a memory interface, a counting circuit, a working mode controller, and a memory management circuit. The host interface is configured to be coupled to a host system. The memory interface is coupled to the rewritable non-volatile memory module. The memory management circuit is coupled to the host interface, the memory interface, the counting circuit, and the working mode controller, wherein the memory management circuit is configured to receive a plurality of instructions from the host system The counting circuit is configured to count a latest idle time corresponding to the instruction and a past average instruction receiving time interval corresponding to the instruction, wherein the latest idle time is greater than a first threshold and the past average instruction The receiving time interval is greater than a second threshold value, and the working mode controller is configured to dynamically switch the working mode of the memory storage device from the first working mode to the second working mode, wherein if the latest idle time is not greater than The first threshold value or the past average command receiving time interval is not greater than the second threshold value, and the working mode controller is further configured to maintain the working mode of the memory storage device at the first Working mode, wherein the memory storage device operates in the first working mode and consumes more power than the memory storage device operates The second mode of power consumption.

In an exemplary embodiment of the present invention, the counting circuit counting the past average instruction receiving time interval of the instruction comprises: counting a first past instruction receiving time interval and a second past instruction receiving time interval; and calculating And a weighted average of the first past instruction reception time interval and the second past instruction reception time interval to obtain the past average instruction reception time interval.

In an exemplary embodiment of the present invention, the calculating, by the counting circuit, calculating the weighted average of the first past instruction receiving time interval and the second past instruction receiving time interval includes: determining, corresponding to the first a first weight value of the past instruction receiving time interval and a second weight value corresponding to the second past instruction receiving time interval; and according to the first weight value, the second weight value, the first past instruction The weighted average is calculated by receiving the time interval and the second past instruction receiving time interval.

In an exemplary embodiment of the present invention, the first past instruction receiving time interval refers to a receiving time interval between a first instruction in the instruction and a previous instruction in the first instruction, and the second past instruction The receiving time interval refers to a receiving time interval of the second instruction in the instruction and the previous instruction of the second instruction, and the counting circuit determines the first time corresponding to the first past instruction receiving time interval The operation of the weight value and the second weight value corresponding to the second past instruction receiving time interval includes: determining the first weight value according to the receiving order of the first instruction and the second instruction, and the The second weight value.

In an exemplary embodiment of the present invention, the determining, by the counting circuit, the determining the first weight value and the second weight value according to the receiving order of the first instruction and the second instruction comprises: responding Determining the first weight value as a first value and determining the second weight value to be greater than the first value, before a receiving time point of the first instruction is earlier than a receiving time point of the second instruction The second value.

In an exemplary embodiment of the present invention, the counting circuit calculates, according to the first weight value, the second weight value, the first past instruction receiving time interval, and the second past instruction receiving time interval. The weighted average operation includes calculating the weighted average according to the following equation:

Where REF represents the past average instruction reception time interval, V[k] represents the kth weight value, ΔT[k] represents the kth past instruction reception time interval, and k and N are both positive integers.

In an exemplary embodiment of the present invention, the second working mode includes an interrupt mode, and the memory management circuit is further configured to switch to the interrupt mode in response to the operating mode of the memory storage device. And sending a sequence of write instructions to indicate that the data temporarily stored in the buffer memory is stored in the rewritable non-volatile memory module, wherein the memory management circuit is further configured to clear the buffer memory.

Based on the above, the present invention is further based on whether the latest idle time is greater than the first threshold as a condition for determining whether to switch the operating mode of the memory storage device, and further based on whether the past average command receiving time interval is greater than the second threshold value. Switch the working mode for double confirmation. Thereby, the timing of switching the working mode, the switching frequency of the working mode can be reduced more accurately, and the service life of the rewritable non-volatile memory module can be prolonged.

The above described features and advantages of the invention will be apparent from the following description.

In general, a memory storage device (also referred to as a memory storage system) includes a rewritable non-volatile memory module and a controller (also referred to as a control circuit). Typically, the memory storage device is used with a host system to enable the host system to write data to or read data from the memory storage device.

FIG. 1 is a schematic diagram of a host system, a memory storage device, and an input/output (I/O) device according to an exemplary embodiment of the invention. FIG. 2 is a schematic diagram of a host system, a memory storage device, and an I/O device according to another exemplary embodiment of the present invention.

Referring to FIG. 1 and FIG. 2, the host system 11 generally includes a processor 111, a random access memory (RAM) 112, a read only memory (ROM) 113, and a data transmission interface 114. The processor 111, the random access memory 112, the read-only memory 113, and the data transmission interface 114 are all coupled to the system bus 110.

In the exemplary embodiment, the host system 11 is coupled to the memory storage device 10 through the data transmission interface 114. For example, the host system 11 can store data to or from the memory storage device 10 via the data transfer interface 114. In addition, the host system 11 is coupled to the I/O device 12 through the system bus bar 110. For example, host system 11 can transmit output signals to or receive input signals from I/O device 12 via system bus 110.

In the present exemplary embodiment, the processor 111, the random access memory 112, the read-only memory 113, and the data transfer interface 114 may be disposed on the motherboard 20 of the host system 11. The number of data transmission interfaces 114 may be one or more. The motherboard 20 can be coupled to the memory storage device 10 via a data transmission interface 114 via a wired or wireless connection. The memory storage device 10 can be, for example, a flash drive 201, a memory card 202, a solid state drive (SSD) 203, or a wireless memory storage device 204. The wireless memory storage device 204 can be, for example, a Near Field Communication (NFC) memory storage device, a wireless fax (WiFi) memory storage device, a Bluetooth memory storage device, or a low power Bluetooth memory. A memory storage device based on various wireless communication technologies, such as a storage device (for example, iBeacon). In addition, the motherboard 20 can also be coupled to the Global Positioning System (GPS) module 205, the network interface card 206, the wireless transmission device 207, the keyboard 208, the screen 209, the speaker 210, etc. through the system bus bar 110. I/O device. For example, in an exemplary embodiment, the motherboard 20 can access the wireless memory storage device 204 via the wireless transmission device 207.

In an exemplary embodiment, the host system referred to is any system that can substantially cooperate with a memory storage device to store data. Although in the above exemplary embodiment, the host system is illustrated by a computer system, FIG. 3 is a schematic diagram of the host system and the memory storage device according to another exemplary embodiment of the present invention. Referring to FIG. 3, in another exemplary embodiment, the host system 31 can also be a digital camera, a video camera, a communication device, an audio player, a video player, or a tablet computer, and the memory storage device 30 can be used for Various non-volatile memory storage devices such as a Secure Digital (SD) card 32, a Compact Flash (CF) card 33, or an embedded storage device 34 are used. The embedded storage device 34 includes an embedded multimedia card (eMMC) 341 and/or an embedded multi-chip package (eMCP) storage device 342, and the like, directly coupling the memory module to the memory module. An embedded storage device on the base of the host system.

FIG. 4 is a schematic block diagram of a memory storage device according to an exemplary embodiment of the invention.

Referring to FIG. 4, the memory storage device 10 includes a connection interface unit 402, a memory control circuit unit 404, and a rewritable non-volatile memory module 406.

The connection interface unit 402 is configured to couple the memory storage device 10 to the host system 11 . In the present exemplary embodiment, the connection interface unit 402 is compatible with the Serial Advanced Technology Attachment (SATA) standard. However, it must be understood that the present invention is not limited thereto, and the connection interface unit 402 may also be a Parallel Advanced Technology Attachment (PATA) standard, Institute of Electrical and Electronic Engineers (IEEE) 1394. Standard, high-speed Peripheral Component Interconnect Express (PCI Express) standard, Universal Serial Bus (USB) standard, SD interface standard, Ultra High Speed-I (UHS-I) interface Standard, Ultra High Speed II (UHS-II) interface standard, Memory Stick (MS) interface standard, MCP interface standard, MMC interface standard, eMMC interface standard, universal flash memory (Universal) Flash Storage, UFS) interface standard, eMCP interface standard, CF interface standard, Integrated Device Electronics (IDE) standard or other suitable standards. The connection interface unit 402 can be packaged in a wafer with the memory control circuit unit 404, or the connection interface unit 402 can be disposed outside a wafer including the memory control circuit unit 404.

The memory control circuit unit 404 is configured to execute a plurality of logic gates or control commands implemented in a hard type or a firmware type and perform data in the rewritable non-volatile memory module 406 according to an instruction of the host system 11. Write, read, and erase operations.

The rewritable non-volatile memory module 406 is coupled to the memory control circuit unit 404 and is used to store data written by the host system 11. The rewritable non-volatile memory module 406 can be a single-level memory cell (SLC) NAND-type flash memory module (ie, one memory cell can store one bit of flash memory) Module), Multi Level Cell (MLC) NAND flash memory module (ie, a flash memory module that can store 2 bits in a memory cell), and complex memory cells ( Triple Level Cell, TLC) NAND flash memory module (ie, a flash memory module that can store 3 bits in a memory cell), other flash memory modules, or other memory with the same characteristics Body module.

Each of the memory cells of the rewritable non-volatile memory module 406 stores one or more bits in response to a change in voltage (hereinafter also referred to as a threshold voltage). Specifically, there is a charge trapping layer between the control gate and the channel of each memory cell. By applying a write voltage to the control gate, the amount of electrons in the charge trapping layer can be changed, thereby changing the threshold voltage of the memory cell. This operation of changing the threshold voltage of the memory cell is also referred to as "writing data to the memory cell" or "programming memory cell". As the threshold voltage changes, each of the memory cells of the rewritable non-volatile memory module 406 has a plurality of storage states. By applying the read voltage, it can be determined which storage state a memory cell belongs to, thereby obtaining one or more bits stored by the memory cell.

In the present exemplary embodiment, the memory cells of the rewritable non-volatile memory module 406 constitute a plurality of physical stylized units, and the physical stylized units constitute a plurality of physical erasing units. Specifically, the memory cells on the same word line form one or more entity stylized units. If each memory cell can store more than 2 bits, the entity stylized units on the same word line can be classified into at least a lower entity stylized unit and an upper physical stylized unit. For example, a Least Significant Bit (LSB) of a memory cell belongs to a lower entity stylized unit, and a Most Significant Bit (MSB) of a memory cell belongs to an upper entity stylized unit. In general, in MLC NAND flash memory, the write speed of the lower stylized unit will be greater than the write speed of the upper stylized unit, and / or the reliability of the lower stylized unit is higher than the upper The reliability of the entity stylized unit.

In this exemplary embodiment, the physical stylized unit is the smallest unit that is stylized. That is, the entity stylized unit is the smallest unit that writes data. For example, an entity stylized unit is a physical page or a sector. If the entity stylized unit is a physical page, then the entity stylized units typically include a data bit area and a redundancy bit field. The data bit area contains a plurality of physical fans for storing user data, and the redundant bit area is used for storing system data (for example, management data such as error correction codes). In this exemplary embodiment, the data bit area includes 32 physical fans, and one physical fan has a size of 512 bytes (byte, B). However, in other exemplary embodiments, the data bit area may also contain 8, 16, or a greater or lesser number of solid fans, and the size of each of the physical fans may also be larger or smaller. On the other hand, the physical erase unit is the smallest unit of erase. That is, each physical erase unit contains one of the smallest number of erased memory cells. For example, the physical erase unit is a physical block.

FIG. 5 is a schematic block diagram of a memory control circuit unit according to an exemplary embodiment of the invention.

Referring to FIG. 5, the memory control circuit unit 404 includes a memory management circuit 502, a host interface 504, a memory interface 506, a counting circuit 507, an operating mode controller 509, and a buffer memory 510.

The memory management circuit 502 is used to control the overall operation of the memory control circuit unit 404. Specifically, the memory management circuit 502 has a plurality of control commands, and when the memory storage device 10 operates, such control commands are executed to perform operations such as writing, reading, and erasing of data. The operation of the memory management circuit 502 will be described below, which is equivalent to the operation of the memory control circuit unit 404.

In the present exemplary embodiment, the control instructions of the memory management circuit 502 are implemented in a firmware version. For example, the memory management circuit 502 has a microprocessor unit (not shown) and a read-only memory (not shown), and such control instructions are programmed into the read-only memory. When the memory storage device 10 is in operation, such control commands are executed by the microprocessor unit to perform operations such as writing, reading, and erasing data.

In another exemplary embodiment, the control command of the memory management circuit 502 can also be stored in a specific area of the rewritable non-volatile memory module 406 (for example, the memory module is dedicated to storing system data). In the system area). In addition, the memory management circuit 502 has a microprocessor unit (not shown), a read-only memory (not shown), and a random access memory (not shown). In particular, the read-only memory has a boot code, and when the memory control circuit unit 404 is enabled, the microprocessor unit first executes the boot code to store the rewritable non-volatile memory. The control commands in the body module 406 are loaded into the random access memory of the memory management circuit 502. After that, the microprocessor unit will run these control commands to perform data writing, reading and erasing operations.

In addition, in another exemplary embodiment, the control command of the memory management circuit 502 can also be implemented in a hardware format. For example, the memory management circuit 502 includes a microcontroller, a memory cell management circuit, a memory write circuit, a memory read circuit, a memory erase circuit, and a data processing circuit. The memory cell management circuit, the memory write circuit, the memory read circuit, the memory erase circuit and the data processing circuit are coupled to the microcontroller. The memory cell management circuit is used to manage the memory cells of the rewritable non-volatile memory module 406 or a group thereof. The memory write circuit is used to issue a write command sequence to the rewritable non-volatile memory module 406 to write data into the rewritable non-volatile memory module 406. The memory read circuit is configured to issue a read command sequence to the rewritable non-volatile memory module 406 to read data from the rewritable non-volatile memory module 406. The memory erase circuit is used to issue an erase command sequence to the rewritable non-volatile memory module 406 to erase data from the rewritable non-volatile memory module 406. The data processing circuit is configured to process data to be written to the rewritable non-volatile memory module 406 and data read from the rewritable non-volatile memory module 406. The write command sequence, the read command sequence, and the erase command sequence may each include one or more code codes or instruction codes and are used to instruct the rewritable non-volatile memory module 406 to perform corresponding writes and reads. Take the erase and other operations. In an exemplary embodiment, the memory management circuit 502 can also provide other types of instruction sequences to the rewritable non-volatile memory module 406 to indicate that the corresponding operations are performed.

The host interface 504 is coupled to the memory management circuit 502 and is configured to receive and identify instructions and data transmitted by the host system 11. That is to say, the instructions and data transmitted by the host system 11 are transmitted to the memory management circuit 502 through the host interface 504. In the present exemplary embodiment, host interface 504 is compatible with the SATA standard. However, it must be understood that the present invention is not limited thereto, and the host interface 504 may be compatible with the PATA standard, the IEEE 1394 standard, the PCI Express standard, the USB standard, the SD standard, the UHS-I standard, the UHS-II standard, and the MS standard. , MMC standard, eMMC standard, UFS standard, CF standard, IDE standard or other suitable data transmission standard.

The memory interface 506 is coupled to the memory management circuit 502 and is used to access the rewritable non-volatile memory module 406. That is, the data to be written to the rewritable non-volatile memory module 406 is converted to a format acceptable to the rewritable non-volatile memory module 406 via the memory interface 506. Specifically, if the memory management circuit 502 is to access the rewritable non-volatile memory module 406, the memory interface 506 will transmit a corresponding sequence of instructions. For example, the sequences of instructions may include a sequence of write instructions indicating write data, a sequence of read instructions indicating read data, a sequence of erase instructions indicating erased material, and instructions for indicating various memory operations (eg, changing read The corresponding instruction sequence that takes the voltage level or performs a garbage collection operation, etc.). These sequences of instructions are generated, for example, by the memory management circuit 502 and transmitted to the rewritable non-volatile memory module 406 via the memory interface 506. These sequences of instructions may include one or more signals or data on the bus. These signals or materials may include instruction codes or code. For example, in the read command sequence, information such as the read identification code, the memory address, and the like are included.

The counting circuit 507 is coupled to the memory management circuit 502. The counting circuit 50 is configured to count the reception time interval of any two instructions based on the point in time at which each instruction is received from the host system 11. For example, if an instruction is received at time point T1 and another instruction is received at another time point T2, the reception time interval ΔT of the two instructions may be regarded as T1-T2.

In the present exemplary embodiment, after receiving a plurality of instructions from the host system 11, the counting circuit 507 can also count the latest idle time corresponding to the instructions and the past average instruction receive time interval corresponding to the instructions. It should be noted that the latest idle time corresponding to these instructions refers to the idle time elapsed after the latest receipt of an instruction. During this idle time, no new commands from the host system 11 are received. The past average instruction receiving time interval corresponding to the instructions refers to an average value, a weighted average value or a median value of a plurality of receiving time intervals of the received plurality of instructions in the past period of time, and the like, as long as It is reflected in the approximate average value of multiple receiving time intervals in the past period of time.

The counting circuit 507 may include various logic circuit elements that can provide a counting function, such as a counter, a sampling circuit, a clock circuit, and/or a flip-flop. Those having ordinary knowledge in the art should know how to The counting circuit 507 is implemented by using such logic circuit elements, and will not be described herein. In an exemplary embodiment, the counting circuit 507 may further include processing circuits having logic operations and/or data processing functions, such as a microprocessor, a microcontroller, and/or an embedded controller, which are not limited in the present invention. In addition, in another exemplary embodiment, the counting circuit 507 may also be disposed in the memory management circuit 502 or implemented as a software or firmware and executed by the memory management circuit 502, which is not limited in the present invention.

The working mode controller 509 is coupled to the memory management circuit 502 and the counting circuit 507. The operation mode controller 509 can judge whether or not to switch the operation mode of the memory storage device 10 based on the counting result of the counting circuit 507. It is assumed that the current working mode of the memory storage device 10 is a certain working mode (also referred to as a first working mode). According to the counting result of the counting circuit 507, if the operating mode controller 509 determines that the operating mode of the memory storage device 10 is to be switched, the operating mode controller 509 can transmit a trigger signal (or an interrupt signal) to the memory management circuit 502. The memory management circuit 502 can instruct to switch the operating mode of the memory storage device 10 from the first working mode to another working mode (also referred to as the second working mode) according to the trigger signal (or interrupt signal). However, if the operating mode controller 509 does not transmit the trigger signal (or interrupt signal) to the memory management circuit 502, the memory management circuit 502 can maintain the operating mode of the memory storage device 10 in the first working mode or from the current The second working mode is switched to the first working mode.

In an exemplary embodiment, the operational mode controller 509 stores a first threshold value and a second threshold value. In an exemplary embodiment, the second threshold value is greater than the first threshold value. For example, the difference between the first threshold and the second threshold may be a preset value or may be dynamically determined. In addition, in another exemplary embodiment, the second threshold may also be less than or equal to the first threshold, which is not limited by the present invention. According to the counting result of the counting circuit 507, the working mode controller 509 determines whether the latest idle time corresponding to the received plurality of instructions is greater than the first threshold value and determines whether the past average command receiving time interval corresponding to the instructions is greater than the first Two thresholds. If the latest idle time corresponding to the instructions is greater than the first threshold and the past average command receiving time interval corresponding to the instructions is greater than the second threshold, the working mode controller 509 determines that the memory storage device 10 is to be switched. The mode, for example, switches the mode of operation of the memory storage device 10 from the first mode of operation to the second mode of operation. However, if the latest idle time corresponding to the instructions is not greater than the first threshold and/or the past average command reception interval corresponding to the instructions is not greater than the second threshold, the operational mode controller 509 determines that the memory will be remembered. The mode of operation of the body storage device 10 is maintained in the first mode of operation.

In an exemplary embodiment, the first mode of operation refers to a normal mode of operation. In the normal mode of operation, the memory storage device 10 can perform all scheduled tasks normally. Each scheduling job may be a work that is indicated by instructions from the host system 11, such as accessing rewritable non-volatile memory for writing or reading data, or any arrangement by the memory management circuit 502. jobs.

In an exemplary embodiment, the power consumption of the memory storage device 10 operating in the first mode of operation may be higher than the power consumption of the memory storage device 10 operating in the second mode of operation. In an exemplary embodiment, the workload of the memory storage device 10 operating in the first mode of operation may be higher than the amount of operation of the memory storage device 10 in the second mode of operation. In an exemplary embodiment, the amount of operation of the memory storage device 10 in the first mode of operation may be higher than the amount of operation of the memory storage device 10 in the second mode of operation. It should be noted that the aforementioned power consumption, workload and calculation amount are measured by the power consumption, workload and calculation amount in a unit time.

In an exemplary embodiment, the second mode of operation includes a suspend mode, an idle mode, or a power saving mode. In the interrupt mode (eg, in response to the operating mode of the memory storage device 10 being switched to the interrupt mode), the memory management circuit 502 sends a sequence of write commands to indicate that the data temporarily stored in the buffer memory 510 is stored to The non-volatile memory module 406 is rewound for long-term storage. After the data temporarily stored in the buffer memory 510 is completely copied to the rewritable non-volatile memory module 406, the memory management circuit 502 can empty the buffer memory 510 to release additional storage in the buffer memory 510. space. In the idle mode (eg, in response to the operating mode of the memory storage device 10 being switched to the idle mode), the memory management circuit 502 can enter an idle state and/or can perform certain preset tasks. In the power saving mode (eg, in response to the operating mode of the memory storage device 10 being switched to the power saving mode), the memory management circuit 502 can enter a power saving state to reduce partial system performance, such as reducing the memory storage device 10 Operating voltage and / or operating frequency. In an exemplary embodiment, the second mode of operation may also include at least some characteristics of the foregoing interrupt mode, idle mode, and power saving mode, depending on practical requirements. In addition, in an exemplary embodiment, the first working mode refers to all working modes except the second working mode, and the power consumption of the memory storage device 10 in the first working mode is higher than that of the memory storage device 10 . The power consumption for operating in the second mode of operation is sufficient.

In an exemplary embodiment, if the current mode of operation of the memory storage device 10 is the second mode of operation, the operating mode controller 509 may indicate that the memory storage device 10 is to be received when the latest command from the host system 11 is received. The working mode is switched back to the first working mode. In the first mode of operation, the memory management circuit 502 can perform operations such as data reading, data writing, or data deletion (or erasure) indicated by the latest instruction.

In an exemplary embodiment, the working mode controller 509 may include a control circuit having logic operations and/or control functions, such as a microprocessor, a microcontroller, and/or an embedded controller, which are not limited in the present invention. In addition, in an exemplary embodiment, the working mode controller 509 may also be implemented in the memory management circuit 502 or implemented as a software or firmware and executed by the memory management circuit 502, which is not limited in the present invention.

The buffer memory 510 is coupled to the memory management circuit 502 and used to temporarily store data and instructions from the host system 11 or data from the rewritable non-volatile memory module 406.

In an exemplary embodiment, the memory control circuit unit 404 further includes an error checking and correction circuit 508 and a power management circuit 512.

The error checking and correction circuit 508 is coupled to the memory management circuit 502 and is used to perform error checking and correcting operations to ensure the correctness of the data. Specifically, when the memory management circuit 502 receives a write command from the host system 11, the error check and correction circuit 508 generates a corresponding error correcting code (ECC) for the data corresponding to the write command. And/or error detecting code (EDC), and the memory management circuit 502 writes the data corresponding to the write command and the corresponding error correction code and/or error check code to the rewritable non-volatile In the memory module 406. Thereafter, when the memory management circuit 502 reads the data from the rewritable non-volatile memory module 406, the error correction code and/or the error check code corresponding to the data are simultaneously read, and the error check and correction circuit 508 An error check and correction operation is performed on the read data based on the error correction code and/or the error check code.

The power management circuit 512 is coupled to the memory management circuit 502 and is used to control the power of the memory storage device 10.

FIG. 6 is a schematic diagram of managing a rewritable non-volatile memory module according to an exemplary embodiment of the invention.

Referring to FIG. 6, the memory management circuit 502 logically groups the physical units 610(0)-610(B) of the rewritable non-volatile memory module 406 into the storage area 601 and the replacement area 602. The physical units 610(0)-610(A) in the storage area 601 are used to store data, and the physical units 610(A+1)~610(B) in the replacement area 602 are used to replace the storage area 601. Damaged physical unit. For example, if a material read from a physical unit contains too many errors and cannot be corrected, the physical unit is considered to be a damaged physical unit. It should be noted that if there is no physical erasing unit available in the replacement area 602, the memory management circuit 502 may declare the entire memory storage device 10 as a write protect state, and the data cannot be written again. .

In the present exemplary embodiment, each physical unit refers to a physical erasing unit. However, in another exemplary embodiment, an entity unit may also refer to a physical address, an entity stylized unit, or a plurality of consecutive or non-contiguous physical addresses. The memory management circuit 502 configures the logic units 612(0)-612(C) to map the physical units 610(0)-610(A) in the storage area 601. In the present exemplary embodiment, each logical unit refers to a logical address. However, in another exemplary embodiment, a logical unit may also refer to a logical stylized unit, a logical erase unit, or a plurality of consecutive or discontinuous logical addresses. Moreover, each of logic units 612(0)-612(C) can be mapped to one or more physical units.

The memory management circuit 502 records the mapping relationship between the logical unit and the physical unit (also referred to as a logical-physical address mapping relationship) in at least one logical-physical address mapping table. When the host system 11 wants to read data from the memory storage device 10 or write data to the memory storage device 10, the memory management circuit 502 can execute the memory storage device 10 according to the logical-physical address mapping table. Data access operation.

FIG. 7 is a schematic diagram of a threshold voltage distribution of a memory cell according to an exemplary embodiment of the invention.

Referring to FIG. 7, when receiving a write command from the host system 11, the memory management circuit 502 sends a write according to the data written by the write command and the write address (eg, a logical unit). The sequence of instructions is to instruct the rewritable non-volatile memory module 406 to program the corresponding memory cells to store the data. Taking SLC NAND type flash memory as an example, the threshold voltage distribution of the programmed memory cell may include states 701 and 702. State 701 corresponds to the number of memory cells of the memory cell in which the first bit value is stored, and state 702 corresponds to the number of memory cells of the memory cell in which the second bit value is stored. In the present exemplary embodiment, the first bit value is 1 and the second bit value is 0. Alternatively, in another exemplary embodiment, the first bit value is zero and the second bit value is one.

Upon receiving a read command from the host system 11, the memory management circuit 502 sends a read command sequence to instruct the rewritable non-volatile memory module 406 to read data from such memory cells. For example, based on the received sequence of read commands, the rewritable non-volatile memory module 406 can use the read voltage level Vread to read data from such memory cells. For example, after the read voltage level Vread is applied to the corresponding memory cell, if the threshold voltage of a certain memory cell is less than the read voltage level Vread, the memory management circuit 502 reads the first bit value. (for example, 1) bit data; or, if the threshold voltage of a certain memory cell is greater than the read voltage level Vread, the memory management circuit 502 reads the bit having the second bit value (for example, 0). Metadata.

It should be noted that as the total number of bits stored in each memory cell is different, the total number of states included in the threshold voltage distribution of the memory cell may also be different. For example, in the exemplary embodiment of FIG. 7, each memory cell stores one bit, and therefore, the threshold voltage distribution of the memory cell includes two states. However, in other exemplary embodiments, if one memory cell can store two bits (for example, MLC NAND type flash memory), the threshold voltage distribution of the memory cells in the rewritable non-volatile memory module 406 Can contain four states. Alternatively, if a memory cell can store three bits (eg, TLC NAND type flash memory), the threshold voltage distribution of the memory cells in the rewritable non-volatile memory module 406 can include eight states.

FIG. 8 is a schematic diagram showing the latest idle time and the receiving time interval of multiple instructions according to an exemplary embodiment of the invention.

Referring to FIG. 8, it is assumed that the memory management circuit 502 sequentially receives the instructions CMD(0)~CMD(N) from the host system 11, where N is an integer and the instruction CMD(N) is the latest received instruction. There is a receiving time interval ΔT[0] between the time point when the command CMD(0) is received and the time point when the command CMD(1) is received, and the time point when the command CMD(1) is received and the time point when the command CMD(2) is received. There is a reception time interval ΔT[1], and so on, a time interval of receiving the command CMD(N-1) and a time point of receiving the command CMD(N) have a reception time interval ΔT[N-1]. The reception time intervals ΔT[0]~ΔT[N-1] may be different or at least partially identical.

In an exemplary embodiment, each of the receive time intervals ΔT[0]~ΔT[N-1] is also referred to as a past command reception time interval, and ΔT[N] is the latest idle time. No instruction from the host system 11 is received during each of the reception time intervals ΔT[0]~ΔT[N-1]. In addition, the latest idle time ΔT[N] is the idle time of the next instruction CMD(N+1) that has not been received after receiving the last instruction CMD(N).

The counting circuit 507 can count the reception time intervals ΔT[0] to ΔT[N-1] according to the time points at which the commands CMD(0) to CMD(N) are received and can count the latest idle time ΔT[N]. In an exemplary embodiment, the counting circuit 507 can calculate a weighted average of the receiving time intervals ΔT[0]~ΔT[N-1] to obtain a past average instruction receiving time interval corresponding to the commands CMD(0)~CMD(N). .

In an exemplary embodiment, the counting circuit 507 can configure a weight value for each of the reception time intervals ΔT[0]~ΔT[N-1]. For example, the counting circuit 507 can configure a weight value V[k] for the reception time interval ΔT[k], where k is an integer between 0 and N-1. For example, the weight value V[0] corresponds to the reception time interval ΔT[0], and the weight value V[1] corresponds to the reception time interval ΔT[1], and so on, and the weight value V[N-1] corresponds to reception. Time interval ΔT[N-1]. The weight values V[0]~V[N-1] may be different from each other or at least partially identical.

The counting circuit 507 can calculate the receiving time interval ΔT[0]~ΔT[N-1 according to the receiving time interval ΔT[0]~ΔT[N-1] and the corresponding weight value V[0]~V[N-1]. The weighted average of ]. For example, the counting circuit 507 can calculate a weighted average of the reception time intervals ΔT[0] to ΔT[N-1] according to the following equation (1.1).

(1.1)

In equation (1.1), REF represents the past average instruction reception time interval corresponding to the instructions CMD(0)~CMD(N). Taking FIG. 8 as an example, assuming that 30 instructions have been sequentially received (ie, N=29), the past average instruction reception time interval corresponding to the 30 instructions can be calculated according to equation (1.1). It should be noted that, in an exemplary embodiment, the calculation of the past average instruction reception time interval corresponding to the instructions CMD(0)~CMD(N) is independent of the latest idle time ΔT[N], as shown in equation (1.1). .

In an exemplary embodiment, equation (1.1) may also be adjusted, such as adding other variables or adjusting at least some of the logical operation elements to meet practical requirements, as long as multiple instructions can be calculated (roughly) reflected in the past period of time. The value of the average value of the receiving time interval can be used. In addition, in another exemplary embodiment, the counting circuit 507 can also input the receiving time interval ΔT[0]~ΔT[N-1] and the corresponding weight value V[0]~V[N-1] to a search. The table also takes the output of this lookup table as the past average instruction reception time interval corresponding to the instructions CMD(0)~CMD(N).

In an exemplary embodiment of FIG. 8, instructions CMD(0)~CMD(N) are received sequentially. That is, the instruction CMD(0) is first received, then the instruction CMD(1) is received, then the instruction CMD(2) is received, and so on, the instruction CMD(N) is finally received. In an exemplary embodiment, the weight values V[0]~V[N-1] may be determined according to the order of reception of the instructions CMD(0)~CMD(N).

In an exemplary embodiment, in response to a reception time point of an instruction (also referred to as a first instruction) being earlier than a reception time point of another instruction (also referred to as a second instruction), the counting circuit 507 may correspond to the The weight value of an instruction (also referred to as a first weight value) is determined to be a certain value (also referred to as a first value) and the weight value corresponding to the second instruction (also referred to as a second weight value) is determined to be greater than Another value of a value (also known as a second value). In other words, if the reception time point of the command CMD(k) is earlier, the weight value V[k] corresponding to the reception time interval ΔT[k] can be determined to be a smaller value. Alternatively, if the reception time point of the command CMD(k) is later, the weight value V[k] corresponding to the reception time interval ΔT[k] is larger. Taking Figure 8 as an example, the command CMD(2) is received later than the command CMD(0), so the determined weight value V[1] will be greater than the determined weight value V[0]; similarly, the command CMD ( N) is received later than the command CMD (2), so the determined weight value V[N-1] will be greater than the determined weight value V[1]. From another point of view, in an exemplary embodiment, the weight value V[k] may be determined according to the ranking position of the corresponding instruction CMD[k] in the entire instruction queue CMD(0)~CMD(N).

In the exemplary embodiment of FIG. 8, if the operating mode controller 509 determines that the latest idle time ΔT[N] is greater than the first threshold and corresponds to the past average command receiving time interval of the commands CMD(0)~CMD(N) (eg, If REF) in equation (1.1) is greater than the second threshold, the operational mode controller 509 can instruct the memory management circuit 502 to switch the operational mode of the memory storage device 10 from the first operational mode to the second operational mode. However, if the latest idle time ΔT[N] is not greater than the first threshold value, and/or the past average command reception time interval corresponding to the command CMD(0)~CMD(N) is not greater than the second threshold value, the operation mode control The device 509 can instruct the memory management circuit 502 to maintain the operating mode of the memory storage device 10 in the first mode of operation. In other words, if the latest idle time ΔT[N] is not greater than the first threshold value and/or the past average command reception time interval corresponding to the commands CMD(0)~CMD(N) is not greater than the second threshold value, the operational mode controller 509 may not instruct to switch the operating mode of the memory storage device 10 from the first operating mode to the second operating mode.

It should be noted that the latest idle time ΔT[N] in the exemplary embodiment of FIG. 8 is counted from the time point when the latest instruction CMD(N) is received until the next instruction CMD (N) from the host system 11 is received. +1) so far. In other words, before the next instruction CMD(N+1) is received, if the latest idle time ΔT[N] is greater than the first threshold and the past average instruction reception interval corresponding to the instructions CMD(0)~CMD(N) is greater than The second threshold value, the operating mode controller 509 can instruct to switch the operating mode of the memory storage device 10 from the first operating mode to the second operating mode. If the next command CMD(N+1) is received before the latest idle time ΔT[N] is greater than the first threshold, the operational mode controller 509 determines that the latest idle time ΔT[N] is not greater than the first threshold.

In an exemplary embodiment of FIG. 8, after switching the operating mode of the memory storage device 10 to the second operating mode, if the next command CMD(N+1) is received, the working mode controller 509 may indicate that The mode of operation of the memory storage device 10 is switched from the second mode of operation back to the first mode of operation to perform the operation indicated by the instruction CMD(N+1).

FIG. 9 is a flowchart of a memory management method according to an exemplary embodiment of the invention.

Referring to FIG. 9, in step S901, a plurality of instructions are received from the host system. In step S902, the latest idle time corresponding to the instruction and the past average instruction reception time interval corresponding to the instruction are counted. In step S903, it is determined whether the latest idle time corresponding to the instruction is greater than the first threshold and the past average instruction reception time interval corresponding to the instruction is greater than the second threshold. If the latest idle time corresponding to the instruction is greater than the first threshold and the past average command reception time interval corresponding to the instruction is greater than the second threshold, in step S904, the operating mode of the memory storage device is from the first The working mode is switched to the second working mode. If the latest idle time corresponding to the instruction is not greater than the first threshold and/or the past average command reception interval corresponding to the instruction is not greater than the second threshold, the memory storage device is operated in step S905. The mode is maintained in the first mode of operation.

However, the steps in FIG. 9 have been described in detail above, and will not be described again here. It should be noted that the steps in FIG. 9 can be implemented as multiple code codes or circuits, and the present invention is not limited. In addition, the method of FIG. 9 may be used in combination with the above exemplary embodiments, or may be used alone, and the present invention is not limited thereto.

In summary, the present invention further determines the time interval of receiving the memory storage device based on whether the latest idle time that has not received the next command is greater than the first threshold value. Whether it is greater than the second threshold value to double check whether to switch the working mode. Thereby, the timing of switching the working mode, the switching frequency of the working mode can be reduced more accurately, and the service life of the rewritable non-volatile memory module can be prolonged.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

10, 30‧‧‧ memory storage device

11, 31‧‧‧ host system

110‧‧‧System Bus

111‧‧‧ Processor

112‧‧‧ Random access memory

113‧‧‧Read-only memory

114‧‧‧Data transmission interface

12‧‧‧Input/Output (I/O) devices

20‧‧‧ motherboard

201‧‧‧USB flash drive

202‧‧‧ memory card

203‧‧‧ Solid State Drive

204‧‧‧Wireless memory storage device

205‧‧‧Global Positioning System Module

206‧‧‧Network Interface Card

207‧‧‧Wireless transmission

208‧‧‧ keyboard

209‧‧‧ screen

210‧‧‧ Horn

32‧‧‧SD card

33‧‧‧CF card

34‧‧‧ embedded storage device

341‧‧‧Embedded multimedia card

342‧‧‧Embedded multi-chip package storage device

402‧‧‧Connection interface unit

404‧‧‧Memory Control Circuit Unit

406‧‧‧Reusable non-volatile memory module

502‧‧‧Memory Management Circuit

504‧‧‧Host interface

506‧‧‧ memory interface

507‧‧‧counting circuit

508‧‧‧Error checking and correction circuit

509‧‧‧Work mode controller

510‧‧‧ Buffer memory

512‧‧‧Power Management Circuit

601‧‧‧ storage area

602‧‧‧Replacement area

610(0)~610(B)‧‧‧ entity unit

612(0)~612(C)‧‧‧ Logical unit

701, 702‧‧‧ Status

CMD(0)~CMD(N+1)‧‧‧ directive

ΔT[0]~ΔT[N-1]‧‧‧ Reception interval

ΔT[N]‧‧‧ latest idle time

S901‧‧‧Steps (receive multiple instructions)

S902‧‧‧ steps (counting the latest idle time corresponding to the instruction and the past average instruction reception time interval corresponding to the instruction)

S903‧‧‧Steps (whether the latest idle time is greater than the first threshold and the past average command reception interval is greater than the second threshold)

S904‧‧‧Step (switching the working mode of the memory storage device from the first working mode to the second working mode)

S905‧‧‧Step (maintaining the working mode of the memory storage device in the first working mode)

FIG. 1 is a schematic diagram of a host system, a memory storage device, and an input/output (I/O) device according to an exemplary embodiment of the invention. FIG. 2 is a schematic diagram of a host system, a memory storage device, and an I/O device according to another exemplary embodiment of the present invention. FIG. 3 is a schematic diagram of a host system and a memory storage device according to another exemplary embodiment of the invention. FIG. 4 is a schematic block diagram of a memory storage device according to an exemplary embodiment of the invention. FIG. 5 is a schematic block diagram of a memory control circuit unit according to an exemplary embodiment of the invention. FIG. 6 is a schematic diagram of managing a rewritable non-volatile memory module according to an exemplary embodiment of the invention. FIG. 7 is a schematic diagram of a threshold voltage distribution of a memory cell according to an exemplary embodiment of the invention. FIG. 8 is a schematic diagram showing the latest idle time and the receiving time interval of multiple instructions according to an exemplary embodiment of the invention. FIG. 9 is a flowchart of a memory management method according to an exemplary embodiment of the invention.

Claims (21)

A memory management method for a memory storage device including a counting circuit, a working mode controller and a rewritable non-volatile memory module, the memory management method comprising: receiving more from a host system An instruction: counting, by the counting circuit, a latest idle time corresponding to the instructions and a past average instruction receiving time interval corresponding to the instructions; if the latest idle time is greater than a first threshold and the past average command receiving The time interval is greater than a second threshold value, and the working mode controller dynamically switches an operating mode of the memory storage device from a first operating mode to a second operating mode; and if the latest idle time is not greater than the The first threshold value or the past average command receiving time interval is not greater than the second threshold value, and the working mode controller maintains the working mode of the memory storage device in the first working mode, wherein the memory storage device A power consumption operation in the first working mode is higher than the memory storage device operating in the second working mode A power consumption. The memory management method of claim 1, wherein the step of counting, by the counting circuit, the past average instruction receiving time interval of the instructions comprises: counting a first past instruction receiving time interval and a second The past instruction receiving time interval; and calculating a weighted average of the first past instruction receiving time interval and the second past instruction receiving time interval to obtain the past average instruction receiving time interval. The memory management method of claim 2, wherein the calculating the weighted average of the first past instruction reception time interval and the second past instruction reception time interval comprises: determining to correspond to the first past instruction a first weight value of the receiving time interval and a second weight value corresponding to the second past instruction receiving time interval; and according to the first weight value, the second weight value, the first past instruction receiving time interval, and The second past instruction receives the time interval to calculate the weighted average. The memory management method of claim 3, wherein the first past instruction receiving time interval is a receiving time interval between a first instruction of the instructions and a previous instruction of the first instruction, The second past instruction receiving time interval is a receiving time interval between a second instruction of the some instruction and the previous instruction of the second instruction, and determining the first corresponding to the first past instruction receiving time interval The step of the weight value and the second weight value corresponding to the second past instruction receiving time interval comprises: determining the first weight value and the second weight value according to a first instruction and a receiving order of the second instruction. The memory management method of claim 4, wherein the determining the first weight value and the second weight value according to the receiving order of the first instruction and the second instruction comprises: responding to the a receiving time point of an instruction is earlier than a receiving time point of the second instruction, determining the first weight value as a first value and determining the second weight value as a second value greater than the first value . The memory management method of claim 3, wherein the weighting is calculated according to the first weight value, the second weight value, the first past instruction receiving time interval, and the second past instruction receiving time interval. The averaging steps include: Calculating the weighted average according to the following equation: Where REF represents the past average command reception time interval, V[k] represents the kth weight value, ΔT[k] represents the kth past instruction reception time interval, and k and N are both positive integers. The memory management method of claim 1, wherein the second working mode comprises an interrupt mode, and the memory management method further comprises: switching to the operating mode in response to the memory storage device In the interrupt mode, a write command sequence is sent to indicate that the data temporarily stored in a buffer memory is stored in the rewritable non-volatile memory module; and the buffer memory is emptied. A memory storage device includes: a connection interface unit for coupling to a host system; a rewritable non-volatile memory module; and a memory control circuit unit coupled to the connection interface unit and The rewritable non-volatile memory module, wherein the memory control circuit unit is configured to receive a plurality of instructions from the host system, wherein the memory control circuit unit is further configured to count an latest idle corresponding to the instructions a time interval and a past average command receiving time interval corresponding to the instructions, wherein the memory control circuit unit is further if the latest idle time is greater than a first threshold and the past average command receiving time interval is greater than a second threshold And dynamically switching the working mode of the memory storage device from a first working mode to a second working mode, wherein if the latest idle time is not greater than the first threshold or the past average command receiving time interval is not More than the second threshold, the memory control circuit unit is further configured to maintain the working mode of the memory storage device. In the first working mode, a power consumption of the memory storage device operating in the first working mode is higher than a power consumption of the memory storage device operating in the second working mode. The memory storage device of claim 8, wherein the memory control circuit unit counts the past average instruction receiving time interval of the instructions comprises: counting a first past instruction receiving time interval and a a second past instruction receiving time interval; and calculating a weighted average of the first past instruction receiving time interval and the second past instruction receiving time interval to obtain the past average instruction receiving time interval. The memory storage device of claim 9, wherein the memory control circuit unit calculates the weighted average of the first past instruction reception time interval and the second past instruction reception time interval comprises: determining a correspondence And a second weight value corresponding to the second past instruction receiving time interval; and the first weight value, the second weight value, the first The past instruction reception time interval and the second past instruction reception time interval are used to calculate the weighted average. The memory storage device of claim 10, wherein the first past instruction receiving time interval is a receiving time interval between a first instruction of the instructions and a previous instruction of the first instruction, The second past instruction receiving time interval is a receiving time interval between a second instruction of the instructions and the previous instruction of the second instruction, and the memory control circuit unit determines to receive the first past instruction corresponding to the first instruction. The operation of the first weight value of the time interval and the second weight value corresponding to the second past instruction receiving time interval includes: determining the first weight value according to a first instruction and a receiving order of the second instruction The second weight value. The memory storage device of claim 11, wherein the memory control circuit unit determines the operation of the first weight value and the second weight value according to the receiving order of the first instruction and the second instruction. The method includes: determining, according to a receiving time point of the first instruction, a receiving time point earlier than the second instruction, determining the first weight value as a first value and determining the second weight value to be greater than the first A second value of the value. The memory storage device of claim 10, wherein the memory control circuit unit receives according to the first weight value, the second weight value, the first past instruction receiving time interval, and the second past instruction The time interval to calculate the weighted average includes: Calculating the weighted average according to the following equation: Where REF represents the past average command reception time interval, V[k] represents the kth weight value, ΔT[k] represents the kth past instruction reception time interval, and k and N are both positive integers. The memory storage device of claim 8, wherein the second operating mode comprises an interrupt mode, and the memory control circuit unit is further configured to switch to the operating mode of the memory storage device to be In the interrupt mode, a write command sequence is sent to indicate that the data temporarily stored in a buffer memory is stored in the rewritable non-volatile memory module, wherein the memory control circuit unit is further used to clear the buffer. Memory. A memory control circuit unit for controlling a memory storage device, wherein the memory storage device comprises a rewritable non-volatile memory module, wherein the memory control circuit unit comprises: a host interface for Coupling to a host system; a memory interface for coupling to the rewritable non-volatile memory module; a counting circuit; a working mode controller; a memory management circuit coupled to the host The interface, the memory interface, the counting circuit, and the operating mode controller, wherein the memory management circuit is configured to receive a plurality of instructions from the host system, wherein the counting circuit is configured to count a latest idle corresponding to the instructions a time interval and a past average command receiving time interval corresponding to the instructions, wherein the working mode controller is used to dynamically if the latest idle time is greater than a first threshold and the past average command receiving time interval is greater than a second threshold Switching an operating mode of the memory storage device from a first operating mode to a second operating mode, wherein The latest idle time is not greater than the first threshold or the past average command receiving interval is not greater than the second threshold, and the working mode controller is further configured to maintain the working mode of the memory storage device at the first The working mode, wherein a power consumption of the memory storage device operating in the first working mode is higher than a power consumption of the memory storage device operating in the second working mode. The memory control circuit unit of claim 15, wherein the counting circuit counts the past average instruction receiving time interval of the instructions comprises: counting a first past instruction receiving time interval and a second The past instruction receiving time interval; and calculating a weighted average of the first past instruction receiving time interval and the second past instruction receiving time interval to obtain the past average instruction receiving time interval. The memory control circuit unit of claim 16, wherein the counting circuit calculates the weighted average of the first past instruction receiving time interval and the second past instruction receiving time interval comprises: determining corresponding to the a first weight value of the first past instruction receiving time interval and a second weight value corresponding to the second past instruction receiving time interval; and according to the first weight value, the second weight value, the first past instruction The weighted average is calculated by the reception time interval and the second past instruction reception time interval. The memory control circuit unit of claim 17, wherein the first past instruction receiving time interval is a receiving time interval between a first instruction of the instructions and a previous instruction of the first instruction. The second past instruction receiving time interval refers to a receiving time interval of a second instruction of the instructions and the previous instruction of the second instruction, and the counting circuit determines a receiving time interval corresponding to the first past instruction. The operation of the first weight value and the second weight value corresponding to the second past instruction receiving time interval includes: determining the first weight value and the first according to a first instruction and a receiving order of the second instruction Two weight values. The memory control circuit unit of claim 18, wherein the determining, by the counting circuit, the first weight value and the second weight value according to the receiving order of the first instruction and the second instruction comprises: Responding to a receiving time point of the first instruction being earlier than a receiving time point of the second instruction, determining the first weight value as a first value and determining the second weight value as being greater than the first value A second value. The memory control circuit unit of claim 17, wherein the counting circuit is based on the first weight value, the second weight value, the first past instruction receiving time interval, and the second past instruction receiving time interval. The operation to calculate the weighted average includes: Calculating the weighted average according to the following equation: Where REF represents the past average command reception time interval, V[k] represents the kth weight value, ΔT[k] represents the kth past instruction reception time interval, and k and N are both positive integers. The memory control circuit unit of claim 15, wherein the second operating mode comprises an interrupt mode, and the memory management circuit is further configured to switch to the operating mode of the memory storage device to be In the interrupt mode, a write command sequence is sent to indicate that the data temporarily stored in a buffer memory is stored in the rewritable non-volatile memory module, wherein the memory management circuit is further used to clear the buffer memory. body.