TWI646796B - Current flattening circuit, current compensation circuit and associated control method - Google Patents

Abstract

The invention provides a current flattening circuit, a current compensation circuit and a related control method thereof. The current flattening circuit is electrically connected to a core node, and the current flattening circuit includes a reference voltage regulator and a current compensation circuit. The reference voltage regulator generates a reference voltage in which the reference voltage is constant. The current compensation circuit is electrically connected to the core node and the reference voltage regulator. The current compensation circuit generates a compensation current based on a voltage difference between the reference voltage and a core voltage corresponding to the core node.

Description

Current flattening circuit, current compensation circuit and related control method

The invention relates to a current flattening circuit, a current compensation circuit and a related control method thereof, and particularly relates to a current flattening circuit, a current compensation circuit and a related control thereof, which can avoid power consumption of a core circuit being used for analysis. method.

Semiconductors are widely used in many current electronic products, and security issues are becoming an important issue in designing embedded systems.

Please refer to FIG. 1 , which is a schematic diagram of the operation of the core circuit by adding an ammeter between the voltage source and the wafer. The power pin of wafer 10 receives a supply voltage (Vsrc) from a voltage source. The wafer 10 may include a core circuit 15 in which the core circuit 15 executes the sequence of instructions and may be leaked by the current detection result of the ammeter 11.

Because the power consumed by the core circuit 15 will follow the core circuit 15 The operation varies, and the supply current Ivdd flowing through the core circuit 15 may carry information related to the operation being performed and the material being processed. Therefore, a differential power analysis (DPA) technique has been developed which analyzes the operations performed by the core circuit 15 in accordance with the instantaneous power consumption of the core circuit 15. Therefore, there is an urgent need to develop a related art that can protect the operation of the core circuit 15 from being analyzed.

The disclosure relates to a current flattening circuit, a current compensation circuit and a related control method therefor.

According to a first aspect of the present disclosure, a current leveling circuit is proposed. The current flattening circuit is electrically connected to a core node and includes: a reference voltage regulator and a current compensation circuit. The reference voltage regulator generates a reference voltage, wherein the reference voltage is constant. The current compensation circuit is electrically connected to the core node and the reference voltage regulator, and generates a compensation current according to a voltage difference between the reference voltage and a core voltage corresponding to the core node.

According to a second aspect of the present disclosure, a current compensation circuit is provided. The current compensation circuit is electrically connected to a core node, wherein the current compensation circuit comprises: a voltage matching circuit and a first current circuit. The voltage matching circuit receives a reference voltage and a core voltage corresponding to the core node, wherein an output signal of the voltage matching circuit changes according to a voltage difference between the reference voltage and the core voltage. The first current circuit is electrically connected to the core node and the voltage matching circuit, wherein the first current circuit generates a compensation current.

According to a third aspect of the present disclosure, a control method applied to a current leveling circuit is proposed. The control method includes the steps of: generating a reference voltage; and generating a compensation current according to the reference voltage and a voltage difference between a core voltage corresponding to the core node. Wherein the reference voltage is constant and the compensation current is part of the supply current.

In order to better understand the above and other aspects of the present invention, the preferred embodiments are described below, and in conjunction with the drawings, the detailed description is as follows:

10‧‧‧ wafer

11, 22‧‧‧ galvanometer

15, 25‧‧‧ core circuits

21‧‧‧ Current Flattening Circuit

23‧‧‧Power pin

40‧‧‧ Current Balance Circuit

30, 30a, 30c‧‧‧reference voltage regulator

50, 51, 53‧‧‧ current compensation circuit

60‧‧‧ Current sensing circuit

20‧‧‧System Circuit

S41, S42, S43, S44, S45, S47, S49, S471, S472, S473, S474, S477, S479‧‧

32a, 32c‧‧‧ Constant voltage source

301a, 301c‧‧‧ voltage supply circuit

303a, 303c‧‧‧voltage to current circuit

305a, 305c‧‧‧ current conduction circuit

309a, 309c‧‧‧current to voltage circuit

306a‧‧‧First current mirror

306b‧‧‧second current mirror

50a, 51a, 53a‧‧‧ voltage matching circuit

50b, 51b, 42b‧‧‧ first current circuit

50c, 51c, 53c‧‧‧ second current circuit

Figure 1 is a schematic diagram showing the operation of the core circuit through an ammeter added between the voltage source and the wafer.

Figure 2 is a schematic diagram showing the system circuit including a current flattening circuit and a core circuit.

Figure 3 is a flow diagram illustrating how the operation of the current flattening circuit maintains the core voltage consistent.

Figure 4 is a schematic diagram of one embodiment of a reference voltage regulator.

Figure 5 is a schematic diagram of another embodiment of a reference voltage regulator.

Figure 6, which is a schematic diagram of the inner block of the current compensation circuit.

Figure 7 is a flow chart showing the operation of the current compensation circuit.

Figure 8, which is a schematic diagram of one embodiment of a current compensation circuit.

Figure 9, which is a schematic diagram of another embodiment of a current compensation circuit.

The present disclosure proposes a current flattening circuit and a current compensation circuit Road, and the control methods associated with it. The use of the current compensation circuit enables the current variation measured by the ammeter to remain relatively stable.

In this document, the voltages on nodes and nodes are denoted by the same symbol for convenience of explanation. For example, the ground voltage and the ground voltage node are represented as "Gnd".

Please refer to FIG. 2, which illustrates a schematic diagram of a system circuit including a current flattening circuit and a core circuit. The system circuit 20 includes a core circuit 25 and a current flattening circuit 21, and the power pin 23 of the system circuit 20 is electrically coupled to a voltage source that supplies a supply voltage (Vsrc). The galvanometer 22 is connected in series with the power pin 23 and is used to measure the supply current (Ivdd) flowing through the power pin 23, thereby taking the operation of the core circuit 25.

The current flattening circuit 21 is electrically connected between the power pin 23 and the core circuit 25. A node to which the current flattening circuit 21 is connected to the power pin 23 is defined as a supply voltage node (Nvdd), and a node connected to the core circuit 25 and the current flattening circuit 21 is defined as a core node (Ncore). Among them, the voltage level of the core node (Ncore) is defined as the core voltage (Vcore). Furthermore, the core current (Icore) represents the current flowing from the core node (Ncore) to the core circuit 25, and the core current (Icore) changes with the operation of the core circuit 25. The system circuit 20 can be a system-on-chip (SOC) or a system-on-package (SOP), so the core current (Icore) cannot be detected but is detected. Measure the supply current (Ivdd). Accordingly, the present disclosure proposes a plurality of embodiments capable of suppressing fluctuations in supply current (Ivdd).

According to one embodiment of the present disclosure, the current flattening circuit 21 includes a current sensing circuit 60 and a current balancing circuit 40. The current sensing circuit 60 is electrically coupled to a supply voltage node (Nvdd) and a core node (Ncore). The current sensing circuit 60 can be a sensing resistor Rs, and the current flowing through the current sensing circuit 60 is defined as a sensing current (Is). The current balancing circuit 40 is electrically coupled to a core node (Ncore).

According to the concept of the present disclosure, it is desirable to keep the current value of the sense current (Is) consistent, and the sense current (Is) does remain consistent most of the time. The sense current (Is) flowing through the current sensing circuit 60 is divided into two parts at the core node (Ncore), one being the core current (Icore) and the other being the compensation current (Icmp). Therefore, the sense current (Is) is equivalent to the sum of (Icore) and the compensation current (Icmp). Based on this summing relationship, the compensation current (Icmp) and the core current (Icore) are negatively correlated with each other and the fluctuation of the sensing current (Is) can be eliminated.

The supply current (Ivdd) flowing through the power pin 23 is divided into two at the supply voltage node (Nvdd), that is, the sense current (Is) and the auxiliary current (Iadd). The auxiliary current (Iadd) does not necessarily occur. When the auxiliary current (Iadd) is generated, the supply current (Ivdd) is equivalent to the sum of the sense current (Is) and the auxiliary current (Iadd). Otherwise, the supply current (Ivdd) is equivalent to the sense current (Is). In general, the auxiliary current (Iadd) is relatively smaller than the sense current (Is).

The current balancing circuit 40 further includes a reference voltage regulator 30 and a current compensation circuit 50 that are electrically connected to each other. The reference voltage regulator 30 supplies a reference voltage (Vref) to the current compensation circuit 50, and the voltage level of the reference voltage (Vref) is designed to be constant.

In theory, the core voltage (Vcore) can be equal to a multiple of the reference voltage (Vref). For convenience of explanation, it is assumed here that the core voltage (Vcore) is equal to the reference voltage (Vref). The current balancing circuit 40 dynamically generates a compensation current (Icmp) and an auxiliary current (Iadd) based on the core voltage (Vcore) and the reference voltage (Vref). Once there is a voltage difference between the reference voltage (Vref) and the core voltage (Vcore), the compensation current (Icmp) will change and the voltage difference can be reduced.

As the core current (Icore) increases, the sense current (Is) increases, which in turn increases the voltage drop across the sense resistor (Rs) and reduces the core voltage (Vcore). In this case, the reference voltage (Vref) will be greater than the core voltage (Vcore), and the voltage difference between the reference voltage (Vref) and the core voltage (Vcore) will cause a change in the compensation current (Icmp). That is, the compensation current (Icmp) will begin to decrease. As the compensation current (Icmp) decreases, the core voltage (Vcore) will increase. Thereafter, the core voltage (Vcore) will continue to increase until the core voltage (Vcore) is equal to the reference voltage (Vref). Accordingly, the core voltage (Vcore) can be maintained substantially equal to the reference voltage (Vref).

As a result, since the level of the core voltage (Vcore) is substantially equal to the reference voltage (Vref), the voltage drop across the sense resistor (Rs) (ie, (Vdd-Vcore)) can be maintained. According to Ohm's law, the sense current (Is) flowing through the sense resistor (Rs) can be calculated from (Vdd-Vcore)/Rs. Since the resistance values of the supply voltage (Vdd), the core voltage (Vcore), and the sense group (Rs) are all consistent, the fluctuation of the sense current (Is) can be slowed down.

See Figure 3, which is a flow chart illustrating how the operation of the current flattening circuit keeps the core voltage consistent. First, assume current flattening circuit 21 It is in an equilibrium state with the core circuit 25. When the current flattening circuit 21 and the core circuit 25 are in an equilibrium state, the core voltage (Vcore) is equal to the reference voltage (Vref), and the sensing current (Is) flowing to the core voltage (Vcore) remains the same (step S41). The current sensing circuit 60 provides a portion of the sense current (Is) as a core current (Icore) and supplies a core current (Icore) to the core circuit 25 (step S42).

The reference voltage regulator 30 continuously generates a reference voltage (Vref) (step S43). At the same time, the current sensing circuit 60 detects the sensing current (Is) according to the detection result of the core voltage (Vocre), and the current sensing circuit 60 outputs the detected core voltage (Vcore) to the current compensation. Circuit 50 (step S44). After receiving the core voltage (Vcore) from the current sensing circuit 60, the current compensation circuit 50 determines whether the core voltage (Vcore) is changed (step S45). If the result of the determination in step S45 is negative, step S41 is repeatedly executed.

If the result of the determination in step S45 is affirmative, the current compensation circuit 50 adjusts the compensation current (Icmp), wherein the compensation current (Icmp) which is another part of the sensing current (Is) follows the core voltage (Vcore) and the reference voltage (Vref). A voltage difference between them is generated (step S47). Thereafter, the core voltage (Vcore) will be changed based on the adjustment of the compensation current (Icmp) (step S49). Thereafter, the entire operation flow will be repeated.

As mentioned earlier, the sense current (Is) can be divided into two parts, the core current (Icore) and the compensation current (Icmp). When the core current (Icore) changes with the operation of the core circuit 25, the compensation current (Icmp) is adjusted in a reverse manner.

Different embodiments of the reference voltage regulator and current compensation circuit are separately described below. The following reference voltage regulator and current compensation circuit can be arbitrarily selected and For use with.

Please refer to FIG. 4, which is a schematic diagram of one embodiment of a reference voltage regulator. The reference voltage regulator 30a receives a constant voltage (Vbg) from the constant voltage source 32a and generates a reference voltage (Vref) to the reference voltage node. For example, constant voltage source 32a can be, but is not limited to, a bandgap voltage circuit and is used to generate a bandgap voltage having a small temperature coefficient. In FIG. 4, the reference voltage regulator 30a includes a voltage supply circuit 301a, a voltage-to-current circuit 303a, a current conduction circuit 305a, and a current-to-voltage circuit 309c.

The voltage supply circuit 301a includes source operational amplifiers (OPs). The inverting input terminal (-) of the source operational amplifier (OPs) receives a constant voltage (Vbg) from the constant voltage source 32a. The non-inverting input terminal (+) of the source operational amplifier (OPs) is electrically coupled to the voltage to current circuit 303a. The voltage levels of the non-inverting input terminal (+) and the inverting input terminal (-) are equal to each other, and the non-inverting input input terminal (+) of the source operational amplifier (Ops) will have a quasi-constant voltage (Vbg' ) is transmitted to the voltage to current circuit 303a. The output terminal of the source operational amplifier (Ops) is electrically coupled to current conducting circuit 305a. The source operational amplifier (Ops) amplifies the voltage difference between the constant voltage (Vbg) and the quasi-constant voltage (Vbg') to produce an output signal. The constant voltage (Vbg) and the quasi-constant voltage (Vbg') are substantially equal to each other (Vbg = Vbg').

The voltage-to-current circuit 303a includes a first resistor (R1), and the voltage-to-current circuit 303 is electrically connected to the voltage supply circuit 301 and a ground node (Gnd). As shown in the formula (1), the source current (Isrc) can be determined by the constant voltage (Vbg) and the first resistance (R1).

Is=Vbg’/R1=Vbg/R1....................................(1)

The current conducting circuit 305a of Fig. 4 includes a PMOS transistor (P). The gate of the PMOS transistor (P) is electrically connected to the output terminal of the voltage supply circuit 301a. The source of the PMOS transistor (P) is electrically connected to the current to voltage circuit 309a. The drain of the PMOS transistor (P) is electrically connected to the voltage-to-current circuit 303a.

The current to voltage circuit 309a includes a second resistor (R2). As shown in FIG. 4, the second resistor (R2) is electrically connected to the supply voltage node (Vdd), and the reference current (Iref) flows through the second resistor (R2). According to the reference current (Iref), the voltage drop ΔV R2 across the second resistor _R2 can be expressed as equation (2).

ΔV _R2 =Iref*R2=Vdd-Vref..............................(2)

The PMOS transistor (P) is controlled by the output signal (Vops) of the source operational amplifier (OPs). When the PMOS transistor (P) is turned on, the conduction current (Icon) flows through the PMOS transistor (P). As shown in Figure 4, the conduction current (Icon), the reference current (Iref) and the source current (Isrc) together form a current path. Therefore, the current values of the conduction current (Icon), the source current (Isrc), and the reference current (Iref) are equal to each other, that is, Icon=Is=Iref.

Since the source current (Isrc) and the reference current (Iref) are equal to each other, the reference current (Iref) of the equation (2) can be replaced with the source current (Isrc). Therefore, the formula (2) can be further derived into the formula (3).

Vref=Vdd-Iref*R2=Vdd-Is*R2=Vdd-(Vbg*R2)/R1..........................................(3)

According to equation (3), the reference voltage (Vref) can be supplied from the voltage (Vdd), constant Constant voltage (Vbg), voltage to current circuit 303a (first resistor R1), and current to voltage circuit 309a (second resistor R2), and supply voltage (Vdd), constant voltage (Vbg), first resistor R1 And the value of the second resistor R2 is known both when designing and producing the voltage reference regulator 30a.

Please refer to FIG. 5, which is a schematic diagram of another embodiment of a reference voltage regulator. The reference voltage regulator 30c receives a constant voltage (Vbg) from the constant voltage source 32c and generates a reference voltage (Vref) to a current compensation circuit (not shown). In Fig. 5, the reference voltage regulator 30c includes a voltage supply circuit 301c, a voltage-to-current circuit 303c, a current conduction circuit 305c, and a current-to-voltage circuit 309c. The current conducting circuit 305c further includes a first current mirror 306a and a second current mirror 306b.

The connection relationship and operation mode of the source operational amplifier 301c and the voltage-to-current circuit 303c are similar to those of FIG. 4, and details thereof will not be described in detail herein. Therefore, the source current (Isrc) of Fig. 5 can also be derived from equation (1).

The first current mirror 306a includes a first PMOS transistor (P1) and a second PMOS transistor (P2). The gates of the first PMOS transistor (P1) and the second PMOS transistor (P2) are electrically connected to the output terminal of the voltage supply circuit 301c. The sources of the first PMOS transistor (P1) and the second PMOS transistor (P2) are both electrically connected to the supply voltage node (Vdd). The drain of the first PMOS transistor (P1) is electrically connected to the voltage-to-current circuit 303c, and the drain of the second PMOS transistor (P2) is electrically connected to the second current mirror 306b.

As shown in FIG. 5, the first PMOS transistor (P1) and the first resistor (R1) together form a first current path, and the first mirror input current (Iin1) and the source power The stream (Isrc) flows through the first current path. Therefore, the current value of the first mirror input current (Iin1) is equal to the current value of the source current (Isrc). The first mirrored input current (Iin1) flows through the first PMOS transistor (P1), and the first mirrored output current (Iout1) flows through the second PMOS transistor (P2). Based on the current mirror architecture, the first mirrored input current (Iin1) is equal to the first mirrored output current (Iout1).

The second current mirror 306b includes a first NMOS transistor (N1) and a second NMOS transistor (N2). The gate of the first NMOS transistor (N1) and the gate of the second NMOS transistor (N2) are electrically connected to the output terminal of the first current mirror 306a. The sources of the first NMOS transistor (N1) and the second NMOS transistor (N2) are electrically connected to the ground node (Gnd). The drain of the first NMOS transistor (N1) is electrically connected to the output terminal of the first current mirror 306a, and the drain of the second NMOS transistor (N2) is electrically connected to the current-turning voltage circuit 309c.

As shown in FIG. 5, the second PMOS transistor (P2) and the first NMOS transistor (N1) together form a second current path, and the first mirror output (Iout1) and the second mirror input current (Iin2) are both current. Through the second current path. Therefore, the current values of the first mirror output (Iout1) and the second mirror input current (Iin2) are equal to each other. The second mirrored input current (Iin2) flows through the first NMOS transistor (N1), and the second mirrored output current (Iout2) flows through the second NMOS transistor (N2). According to the architecture of the current mirror, the second mirrored input current (Iin2) is equal to the second mirrored output current (Iout2).

The current to voltage circuit 309c includes a second resistor (R2). The current-to-voltage circuit 309a of FIG. 4 and the current-to-voltage circuit 309c of FIG. 5 are both connected between the supply voltage node (Vdd) and the current compensation circuit, and the operation modes of the current-to-voltage circuits 309a, 309c are similar to each other. Since the connection relationship and position of the second resistor (R2) in Figs. 4 and 5 are similar, the voltage drop ΔV _R2 across the second resistor (R2) of Fig. 5 can also be calculated by applying equation (2).

As shown in FIG. 5, the second resistor (R2) and the second NMOS transistor (N2) together form a third current path, wherein both the reference current Iref and the second mirror output current (Iout2) flow through the third current path. Therefore, the current values of the reference current Iref and the second mirror output current (Iout2) are equal to each other. According to the foregoing description, the source current (Isrc), the first mirror input current (Iin1), the first mirror output current (Iout1), the second mirror input current (Iin2), the second mirror output current (Iout2), and The reference currents (Iref) are assumed to be equal to each other. That is, Isrc=Iinl=Iout=Iin2=Iout2=Iref.

However, the relationship between the reference voltage (Vref) and the constant voltage (Vbg) can be freely defined without limitation. Therefore, source current (Isrc), first image input current (Iin1), first image output current (Iout1), second image input current (Iin2), second image output current (Iout2), and reference current (Iref) The current transfer ratio may not be equal to "1".

Therefore, the design of the first current mirror 306a and the second current mirror 306b is relatively flexible, and the current conversion ratio between the input currents (Iin1 and Iin2) and the output currents (Iout1 and Iout2) is not necessarily equal to "1". Incidentally, the first image input current (Iin1), the first image output current (Iout1), the second image input current (Iin2), the second image output current (Iout2), and the reference current (Iref) may be source currents ( A multiple of Isrc). Or, the current value of the reference current (Iref) and the current of the source current (Isrc) The value is proportional. The design changes regarding the current conversion ratio can be arbitrarily substituted or changed by those having ordinary knowledge in the technical field to which the present invention pertains, and will not be described in detail herein.

Since the source current (Isrc) and the reference current (Iref) are equal to each other, the equation (3) can be applied to the reference voltage (Vref) of FIG. Since the supply voltage (Vdd), the constant voltage (Vbg), the voltage-to-current circuit 303c (the first resistor R1), and the current-to-voltage circuit 309a (the second resistor R2) are both designed and manufactured by the voltage reference adjuster 30c, It is determined that the reference voltage (Vref) provided by the reference voltage regulator 30c will remain unchanged.

According to the above embodiment, the current conducting circuits 305a, 305c in the reference voltage regulators 30a, 30c can be used to bridge the voltage to current circuits 303a, 303c and the current to voltage circuits 309a, 309c. The current conducting circuits 305a, 305c transmit the preset current values of the source current (Isrc) to the current converting voltage circuits t 309a, 309c, thereby allowing the current converting voltage circuits 309a, 309c to use the preset current values as the reference currents (Iref). Current value.

In other words, the design of the voltage to current circuits 303a, 303c will determine the current value of the source current (Isrc). The current value of the source current (Isrc) is supplied to the current conducting circuits 305a, 305c, and the current value of the conduction current (Icon) is determined accordingly. Through the bridging of the current conducting circuits 305a, 305c, the source current (Isrc) is always equal to the reference current (Iref), and the current values of these currents can be maintained at a constant preset value. Accordingly, the current to voltage circuit 309c can continuously supply a constant voltage (ie, a reference voltage (Vref)) to the current compensation circuit.

As shown in Figures 4 and 5, the current-to-voltage circuits 309a, 309c are both It is disposed between the supply voltage node (Vdd) and the reference voltage node having the reference voltage (Vref) to improve the power supply rejection ratio (PSRR) of the reference voltage regulators 30a, 30c.

Since the reference current (Iref) is equal to the source current (Isrc), the reference current (Iref) remains relatively stable when the supply voltage (Vdd) interferes, that is, Iref=Is=Vbg/R1. Incidentally, the reference voltage (Vref) may change as the supply voltage (Vdd) changes. When the reference voltage (Vref) changes simultaneously with the supply voltage (Vdd), the core voltage (Vcore) determined by the reference voltage (Vref) also changes with the supply voltage (Vdd). Since the second resistor (R2) is connected between the supply voltage node (Vdd) and the reference voltage node (Vref), the source current (Isrc) is less likely to be disturbed by the supply voltage (Vdd).

According to an embodiment of the present disclosure, the reference voltage regulator 30 continues to receive a constant voltage (Vbg) and accordingly provides a reference voltage (Vref) to the current compensation circuit 50. The current compensation circuit 50 reuses the reference voltage (Vref) as a basis for comparison of the core voltage (Vcore). Based on the comparison of the reference voltage (Vref) with the core voltage (Vcore), the current compensation circuit 50 will dynamically adjust the generation of the compensation current (Icmp). The operation of the current compensation circuit 50 will be described below.

Please refer to Fig. 6, which is a schematic diagram of the inner block of the current compensation circuit. The current compensation circuit 50 includes a voltage matching circuit 50a and a first current circuit 50b. Further, the current compensation circuit 50 may further include a second current circuit 50c. The first current circuit 50b and the second current circuit 50c may be turned on or off by the first switch (sw1) and the second switch (sw2), respectively.

The voltage matching circuit 50a is electrically connected to the core node (Ncore), and the first current circuit 50b is electrically connected to the core node (Ncore) through the conduction of the first switch (sw1). The second current circuit 50c is electrically connected to the supply voltage node (Nvdd) by conduction of the second switch (sw2). Unlike the first current circuit 50b, the voltage matching circuit 50a does not conduct current from the core node (Ncore) to the ground node (Gnd), and the voltage matching circuit 50a senses only the core voltage (Vcore). That is, no current is conducted from the core node (Ncore) to the voltage matching circuit 50a.

The first switch (sw1) and the second switch (sw2) may be selectively turned on or off by a core circuit (not shown), and the first switch (sw1) and the second switch (sw2) may be implemented by using a MOS transistor. . In practical applications, the control signals for controlling the switching states of the first switch (sw1) and the second switch (sw2) are independent of each other, and the two switches (sw1 and sw2) can be turned on simultaneously or separately. The two control signals used to control the corresponding switches can be either a random sequence control signal or a control signal that is maintained at a high level. For ease of explanation, this article assumes that the two switches are simultaneously turned on.

The voltage matching circuit 50a receives the reference voltage (Vref) from the reference voltage regulator 30 and receives the core voltage (Vcore) from the core node (Ncore). The output signal of the voltage matching circuit 50a (Vopm) is used to control the first current circuit 50b and the second current circuit 50c, and the output signal of the voltage matching circuit 50a (Vopm) is based on the reference voltage (Vref) and the core voltage (Vcore). The voltage difference between them is generated. Herein, the voltages that the voltage matching circuit 50a draws from the reference voltage regulator 30 and the core node (Ncore), that is, the reference voltage (Vref) and the core voltage (Vcore), are respectively represented in a voltage form. In practical applications, the signal provided by the reference voltage regulator 30 and the core node (Ncore) can also be represented by current.

According to the output signal (Vopm) of the voltage matching circuit 50a, the first current circuit 50b and the second current circuit 50c generate a compensation current (Icmp) and an auxiliary current (Iadd), respectively. The auxiliary current (Iadd) is proportional to the compensation current (Icmp). The compensation current (Icmp) auxiliary current (Iadd) increases as the core current (Icore) decreases, and vice versa.

The supply current (Ivdd) is divided into auxiliary current (Iadd) and sensing current (Is) at the supply voltage node (Nvdd), wherein the sensing current (Is) is further divided into compensation currents at the core node (Ncore) (Icmp). ) with the core current (Icore) two parts. According to an embodiment of the present disclosure, the sense current (Is) is larger than the auxiliary current (Iadd), and the sense current (Is) is a major portion of the supply current (Ivdd).

Table 1 lists the currents defined in Figures 2 and 6, with changes at two time points (first time point t1 and second time point t2).

The first column of Table 1 shows the change in core current (Icore). The core currents at the first time point (t1) and the second time point (t2) are represented as Icore(t1) and Icore(t2), respectively. The amount of change in core current (ΔIcore) between two time points can be calculated from the core current (Icore) at the first time point (t1) and the second time point (t2), that is, ΔIcore=Icore (t2)-Icore(t1).

The second column of Table 1 is the variation of the compensation current (Icmp). The compensation currents at the first time point (t1) and the second time point (t2) are denoted as Icmp(t1) and Icmp(t2), respectively. The amount of change in the compensation current (ΔIcmp) between the two time points can be calculated from the compensation current (Icmp) at the first time point (t1) and the second time point (t2), that is, ΔIcmp=Icmp( T2) - Icmp (t1).

The third column of Table 1 is the change in the sense current (Is). The sense currents at the first time point (t1) and the second time point (t2) are represented as Is(t1) and Is(t2), respectively. The amount of change in the sense current (ΔIs) between the two time points can be based on the first time point (t1) and the second time The sense current (Is) at the time point (t2) is calculated, that is, ΔIs = Is(t2) - Is(t1).

As previously mentioned, the sense current (Is) is equal to the sum of the core current (Icore) and the compensation current (Icmp), ie, Is = Icore + Icmp. Therefore, ΔIs=Is(t2)−Is(t1) can be rewritten as equation (4).

△Is=Is(t2)-Is(t1)=[Icore(t2)+Icmp(t2)]-[Icore(t1)+Icmp(t1)]=[Icore(t2)-Icore(t1)]+[ Icmp(t2)+Icmp(t1)]=△Icore+△Icmp................................................(4)

Ideally, the sum of the equations (4) will remain at "0". In practical applications, the summation result of equation (4) may not be equal to "0" due to some extreme cases, and the summation result of equation (4) may be positive or negative. These extremes can occur when the core current (Icore) increases significantly or significantly at a brief instant.

When the core current (Icore) increases significantly at a brief instant, the speed at which the compensation current (Icmp) decreases cannot keep up with the increase in the core current (Icore) because the compensation current (Icmp) decreases at a slower rate. Incidentally, the summation result of equation (4) is a positive value, which means that the sense current (Is) may increase when the core current (Icore) increases significantly at a brief moment.

When the core current (Icore) is significantly reduced at a short instant, the speed at which the compensation current (Icmp) increases cannot keep up with the speed at which the core current (Icore) decreases because the compensation current (Icmp) increases at a slower rate. Associated with the sum of formula (4) The result is a negative value, which means that the sense current (Is) may decrease when the core current (Icore) is significantly reduced at a brief instant.

In other words, in an extreme case, the change in the sense current (Is) may be positively correlated with the change in the core current (Icore). To further reduce the correlation between the sense current (Is) and the core current (Icore) in such extreme cases, the present disclosure further provides for providing a second current of the auxiliary current (Iadd) when the second switch (sw2) is turned on. Circuit 50c, wherein. The generation of the auxiliary current (Iadd) can be adjusted, and the auxiliary current (Iadd) is smaller than the compensation current (Icmp).

The fourth column of Table 1 shows the change in the auxiliary current (Iadd). The auxiliary currents at the first time point (t1) and the second time point (t2) are represented as Iadd(t1) and Iadd(t2), respectively. The amount of change (ΔIadd) of the auxiliary current between the two time points can be calculated from the auxiliary current (Iadd) at the first time point (t1) and the second time point (t2), that is, ΔIadd=Iadd (t2)-Iadd(t1). According to the embodiment of the present disclosure, the amount of auxiliary current change (ΔIadd) between the two time points is smaller than the amount of change (ΔIcmp) of the compensation current between the two time points, that is, ΔIadd<ΔIcmp.

The fifth column of Table 1 shows the change in supply current (Ivdd). The supply currents at the first time point (t1) and the second time point (t2) are represented as Ivdd(t1) and Ivdd(t2), respectively. The amount of change (ΔIvdd) of the supply current between the two time points can be calculated from the supply current (Ivdd) at the first time point (t1) and the second time point Ivdd(t2), that is, ΔIvdd=Ivdd (t2) - Ivdd (t1). Since the supply current (Ivdd) is equivalent to the sum of the sense current (Is) and the auxiliary current (Iadd) (ie, Ivdd=Is+Iadd), ΔIvdd=Ivdd(t2)-Ivdd(t1) can be rewritten. For the formula (5).

ΔIvdd=Ivdd(t2)-Ivdd(t1)=[Is(t2)+Iadd(t2)]-[Is(t1)+Iadd(t1)]=[Is(t2)-Is(t1)]+[ Iadd(t2)-Iadd(t1)]=△Is+△Iadd.................................................(5)

According to the equation (5), the amount of change (ΔIvdd) of the supply current (Ivdd) flowing through the power pin 23 depends on the amount of change in the sense current (ΔIs) and the amount of change in the assist current (ΔIadd). According to the formula (4), the formula (5) can be further rewritten to the formula (6).

ΔIvdd=ΔIs+ΔIadd=(ΔIcore+ΔIcmp)+ΔIadd....................................(6)

According to equation (6), the amount of change in supply current (ΔIvdd) includes three parts, the amount of change in core current (ΔIcore), the amount of change in compensation current (ΔIcmp), and the amount of change in auxiliary current (ΔIadd). ). According to the equation (6), when the core current changes (generating ΔIcore), the amount of change in the compensation current (ΔIcmp) and the amount of change in the auxiliary current (ΔIadd) can be used to adjust and reduce the amount of change in the supply current (ΔIvdd). ), that is, ΔIvdd≒0. Since both the compensation current (Icmp) and the auxiliary current (Iadd) are negatively correlated with the core current (Icore), the fluctuation of the supply current (Ivdd) can be suppressed.

In short, the compensation current (Icmp) generated by the first current circuit 50b can be regarded as providing the first stage of the ripple suppression function, and the auxiliary current (Iadd) generated by the second current circuit 50c can be regarded as providing the second stage of the fluctuation. Suppress function. Furthermore, the first switch (sw1) and the second switch (sw2) can be controlled independently of each other. The number is selectively turned on or off, which in turn makes the supply current (Ivdd) measured by the ammeter 22 more difficult to predict.

When the first switch (sw1) is turned on, the first current circuit 50b will generate a compensation current (Icmp), where the sense current (Is) includes a core current (Icore) and a compensation current (Icmp). When the second switch (sw2) is turned on, the second current circuit 50c generates an auxiliary current (Iadd), at which time the supply current (Ivdd) will include the sense current (Is) and the auxiliary current (Iadd).

Among these currents, the sense current (Is) is more consistent than the core current (Icore), and the supply current (Ivdd) is mainly the sense current (Is) and can be matched with the auxiliary current (Iadd). Make a slight adjustment. Compared with the sense current (Is), the auxiliary current (Idd) can alleviate the fluctuation of the supply current (Ivdd) in the transient response. As shown in FIG. 2, the ammeter 22 measures the supply current (Ivdd) instead of the core current (Icore). According to the concept of the present disclosure, the supply current (Ivdd) is more consistent than the core current (Icore), and therefore, the measurement of the supply current (Ivdd) by the ammeter 22 does not reveal the operation of the core circuit 25.

Please refer to FIG. 7, which is a flow chart illustrating the operation of the current compensation circuit. First, the voltage matching circuit 50a receives the core voltage (Vcore) (step S471) and the reference voltage (Vref), respectively (step S472). Thereafter, the voltage matching circuit 50a generates an output signal (Vopm) based on the voltage difference between the reference voltage (Vref) and the core voltage (Vcore) (step S473). Steps S471, S472 and S473, which are selected by the broken line, represent the operation of the voltage matching circuit 50a.

The first current circuit 50b is based on the output signal of the voltage matching circuit 50a The compensation current (Icmp) is generated and adjusted by the number (Vopm) (step S474). The change in the compensation current (Icmp) affects the core voltage (Vcore). Incidentally, the core voltage (Vcore) changes and approaches the reference voltage (Vref) (step S477). When the second switch (sw2) is turned on, the second current circuit 50c generates an auxiliary current (Iadd) (step S479). The operation shown in Figure 7 continues until the core voltage (Vcore) is equal to the reference voltage (Vref).

Please refer to Fig. 8, which is a schematic diagram of one embodiment of a current compensation circuit. The current compensation circuit 51 includes a voltage matching circuit 51a, a first current circuit 51b, and a second current circuit 51c.

The voltage matching circuit 51a includes a matching operational amplifier (OPm'). The matched operational amplifier (OPm') has an inverting input terminal (-), a non-inverting input terminal (+), and an output terminal. The inverting input terminal (-) of the matching operational amplifier (OPm') receives the reference voltage (Vref) from the reference voltage regulator 30, and the non-inverting input terminal (+) of the matching operational amplifier (OPm') is electrically coupled to The core node (Ncore) and the first current circuit 51b. The output terminal of the matching operational amplifier 51a is electrically connected to the first current circuit 51b and the second current circuit 51c.

The first current circuit 51b includes a compensation transistor (Mb1') (e.g., a third NMOS transistor); the second current circuit 51c includes an auxiliary transistor (Mb2') (e.g., a fourth NMOS transistor). When designing the circuit, the size of the auxiliary transistor (Mb2') will generally be smaller than that of the compensation transistor (Mb1'). Based on the dimensional relationship between the transistors, the auxiliary current (Iadd') flowing through the auxiliary transistor (Mb2') is smaller than the compensation current (Icmp') flowing through the compensation transistor (Mb1'). Make up The compensating crystal (Mb1') is electrically coupled to the control terminal of the auxiliary operating transistor (Mb2') to the output terminal of the matching operational amplifier (OPm'). Therefore, the conduction of the compensation transistor (Mb1') and the auxiliary transistor (Mb2') is determined by the output signal (Vopm') of the matching operational amplifier (OPm').

When the output signal (Vopm') of the matching operational amplifier (OPm') is greater than the threshold voltage of the compensation transistor (Mb1') and the auxiliary transistor (Mb2'), the compensation transistor (Mb1') and the auxiliary transistor (Mb2) ') will turn on, and thus generate compensation current (Icmp') and auxiliary current (Iadd). The compensation current (Icmp') flows from the core node (Ncore) to the ground node (Gnd) via the compensation transistor (Mb1'), and the auxiliary current (Iadd') flows from the supply voltage node (Nvdd) via the auxiliary transistor (Mb2') To the ground node (Gnd).

If the size of the auxiliary transistor (Mb2') is smaller than the size of the compensation transistor (Mb1'), the conduction speed of the auxiliary transistor (Mb2) is faster than the conduction speed of the compensation transistor (Mb1). In other words, the auxiliary current (Iadd') is generated faster than the compensation current (Icmp').

Figure 9, which is a schematic diagram of another embodiment of a current compensation circuit. The current compensation circuit 53 includes a voltage matching circuit 53a, a first current circuit 53b, and a second current circuit 53c.

The voltage matching circuit 53a includes a matching operational amplifier (OPm"). The matched operational amplifier (OPm" has a non-inverting input terminal (+) that receives a reference voltage (Vref) from the reference voltage regulator 30, and is electrically connected to the core node ( Ncore) and an inverting input terminal (-) of the first current circuit 53b, and electrically connected to the first current circuit 53b And an output terminal of the second current circuit 53c.

The first current circuit 53b includes a compensation transistor (Mb1") (for example, a third PMOS transistor); the second current circuit 53c includes an auxiliary transistor (Mb2'') (for example, a fourth PMOS transistor). The size of (Mb2") is usually smaller than the size of the compensation transistor (Mb1"). Depending on the size relationship of the transistor, the auxiliary current (Iadd" flowing through the auxiliary transistor (Mb2") is smaller than that flowing through the compensation transistor (Mb1) ") compensation current (Icmp"). The compensation transistor (Mb1") and the control terminal of the auxiliary transistor (Mb2" are electrically connected to the output terminal of the matching operational amplifier (OPm").

When there is a voltage difference between the core voltage (Vcore) and the reference voltage (Vref), the output signal (Vopm) of the matched operational amplifier (OPm" is greater than that of the compensation transistor (Mb1) and the auxiliary transistor (Mb2). When the voltage is limited, the compensation transistor (Mb1") and the auxiliary transistor (Mb2") will be turned on, and the compensation current (Icmp') and the auxiliary current (Iadd" will be generated respectively. The compensation current (Icmp) is from the core node. (Ncore) flows to the ground node (Gnd) via the compensation transistor (Mb1", and the auxiliary current (Iadd" flows from the supply voltage node (Vdd) to the ground node (Gnd) via the auxiliary transistor (Mb2"). The size of the auxiliary transistor (Mb2") is smaller than the size of the compensation transistor (Mb1"), and the conduction speed of the auxiliary transistor (Mb2") is faster than the conduction speed of the compensation transistor (Mb1"). The current (Iadd'') is generated faster than the compensation current (Icmp).

The current flattening circuit proposed by the present disclosure includes a current sensing circuit, a current compensation circuit, and a reference voltage regulator. Reference voltage regulator provides reference voltage (Vref) to the current compensation circuit. As the core current (Icore) flowing to the core circuit changes, the compensation current (Icmp) generated by the current compensation circuit also changes. In general, the current compensation current (Icmp) maintains the reference voltage (Vref) equal to the core voltage (Vcore). The sense current (Is) flowing through the current sensing circuit can be kept consistent. As mentioned earlier, after the auxiliary current (Iadd) is included, the supply current (Ivdd) is more consistent.

In conclusion, the present invention has been disclosed in the above preferred embodiments, and is not intended to limit the present invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

Claims (9)

A current flattening circuit for compensating a core current, electrically connected to a core node, comprising: a reference voltage regulator, which generates a reference voltage, wherein the reference voltage is constant; and a current compensation circuit electrically connected to the core And a reference voltage regulator that generates a compensation current according to a voltage difference between the reference voltage and a core voltage corresponding to the core node; and a current sensing circuit at a supply voltage node and the A sense current is conducted between the core nodes, wherein the current sense circuit adjusts the core voltage as the sense current changes, and the sense current is equal to a sum of the core current and the compensation current. The current leveling circuit of claim 1, wherein the reference voltage regulator comprises: a voltage supply circuit that receives a constant voltage; and a voltage-to-current circuit electrically coupled to the voltage supply circuit. Generating a source current according to the constant voltage; a current-to-voltage circuit receiving a supply voltage and generating the reference voltage according to the supply voltage and a reference current, wherein the current value of the reference current and the source current The current value is proportional; and a current conducting circuit is electrically connected to the voltage providing circuit, the voltage converting current circuit and the current converting voltage circuit, wherein the current conducting circuit is based on the source The reference current is supplied by the flow. The current leveling circuit of claim 1, wherein the current compensation circuit comprises: a voltage matching circuit that receives the reference voltage and the core voltage, wherein an output signal of the voltage matching circuit follows The reference voltage is changed by a voltage difference between the core voltage; and a first current circuit electrically connected to the core node and the voltage matching circuit, wherein the first current circuit generates the compensation current. A current compensation circuit for compensating a core current is electrically connected to a core node, wherein the current compensation circuit comprises: a voltage matching circuit that receives a reference voltage and a core voltage corresponding to the core node, wherein the voltage An output signal of the matching circuit changes with a voltage difference between the reference voltage and the core voltage; and a first current circuit electrically connected to the core node and the voltage matching circuit, wherein the first current circuit is A compensation current is generated, wherein the compensation current tends to be stable when the core voltage is equal to the reference voltage. The current leveling circuit of claim 1, or the current compensation circuit of claim 4, wherein the current compensation circuit compensates the core current, and the core current and the compensation current are consistent. The current leveling circuit of the invention of claim 1, wherein the current compensation circuit further comprises: a second current circuit electrically connected to the voltage matching circuit, The electricity The output signal of the voltage matching circuit generates an auxiliary current, wherein the auxiliary current is proportional to the compensation current. The current flattening circuit or current compensation circuit of claim 6, wherein the second current circuit randomly turns on or off the auxiliary current according to a control signal. The current flattening circuit of claim 1, or the current compensation circuit of the fourth aspect, wherein the voltage matching circuit comprises a matching operational amplifier, wherein a first input terminal of the matching operational amplifier Receiving the reference voltage from a reference voltage regulator; a second input terminal of the matched operational amplifier is electrically connected to the core node and the first current circuit; and an output terminal of the matched operational amplifier is electrically connected In the first current circuit. A control method for electrically connecting to a current flattening circuit of a core node, wherein the control method comprises the steps of: generating a reference voltage, wherein the reference voltage is constant; according to the reference voltage and the core node Generating a compensation current corresponding to a voltage difference between one of the core voltages, wherein the compensation current is part of a supply current, and the core voltage is adjusted as a sense current changes; and at a supply voltage node The sense current is conducted between the core node and the sense current is equal to a sum of a core current and the compensation current.