CN108415498B

CN108415498B - Current flattening circuit, current compensation circuit and related control method thereof

Info

Publication number: CN108415498B
Application number: CN201710073424.4A
Authority: CN
Inventors: 洪俊雄; 杨尚辑
Original assignee: Macronix International Co Ltd
Current assignee: Macronix International Co Ltd
Priority date: 2017-02-10
Filing date: 2017-02-10
Publication date: 2020-05-19
Anticipated expiration: 2037-02-10
Also published as: CN108415498A

Abstract

The invention discloses a current flattening circuit, a current compensation circuit and a related control method thereof. The current flattening circuit is electrically connected to a core node and comprises a reference voltage regulator and a current compensation circuit. The reference voltage regulator generates a reference voltage, wherein the reference voltage is constant. The current compensation circuit is electrically connected to the core node and the reference voltage regulator. The current compensation circuit generates a compensation current according to a voltage difference between the reference voltage and a core voltage corresponding to the core node.

Description

Current flattening circuit, current compensation circuit and related control method thereof

Technical Field

The present invention relates to a current flattening circuit, a current compensation circuit and a control method thereof, and more particularly, to a current flattening circuit, a current compensation circuit and a control method thereof capable of preventing power consumption of a core circuit from being analyzed.

Background

Semiconductors are widely used in many current electronic products, and security issues are becoming an important issue in designing embedded systems.

Referring to fig. 1, a schematic diagram of detecting the operation of a core circuit by a current meter added between a voltage source and a chip is shown. The power pin of the chip 10 receives a supply voltage (Vsrc) from a voltage source. The chip 10 may include a core circuit 15, wherein the sequence of instructions executed by the core circuit 15 may be leaked by the current detection result of the current meter 11.

Since the power consumed by the core circuit 15 varies with the operation of the core circuit 15, and the supply current Ivdd flowing through the core circuit 15 may carry information related to the operation performed and the data being processed. Therefore, a Differential Power Analysis (DPA) technique has been developed, which analyzes the operation of the core circuit 15 according to the instantaneous power consumption of the core circuit 15. Therefore, it is highly desirable to develop a related art capable of protecting the operation of the core circuit 15 from being analyzed.

Disclosure of Invention

The present disclosure relates to a current planarization circuit, a current compensation circuit and a control method thereof.

According to a first aspect of the present disclosure, a current planarization circuit is provided. The current flattening circuit is electrically connected to a core node and comprises: a reference voltage regulator and a current compensation circuit. The reference voltage regulator generates a reference voltage, wherein the reference voltage is constant. The current compensation circuit is electrically connected to the core node and the reference voltage regulator, and generates a compensation current according to a voltage difference between the reference voltage and a core voltage corresponding to the core node.

According to a second aspect of the present disclosure, a current compensation circuit is provided. The current compensation circuit is electrically connected to a core node, wherein the current compensation circuit comprises: a voltage matching circuit and a first current circuit. The voltage matching circuit receives a reference voltage and a core voltage corresponding to the core node, wherein an output signal of the voltage matching circuit changes with a voltage difference between the reference voltage and the core voltage. The first current circuit is electrically connected to the core node and the voltage matching circuit, wherein the first current circuit generates a compensation current.

According to a third aspect of the present disclosure, a control method for a current planarization circuit is provided. The control method comprises the following steps: generating a reference voltage; and generating a compensation current according to a voltage difference between the reference voltage and a core voltage corresponding to the core node. Wherein the reference voltage is constant and the compensation current is a fraction of the supply current.

In order to better understand the above and other aspects of the present invention, the following detailed description of the preferred embodiments is made with reference to the accompanying drawings, in which:

drawings

FIG. 1 is a schematic diagram of the operation of the core circuit detected by the current meter between the voltage source and the chip.

FIG. 2 illustrates a system circuit including a current flattening circuit and a core circuit.

FIG. 3 is a flow chart illustrating how the operation of the current flattening circuit keeps the core voltage consistent.

FIG. 4 is a schematic diagram of one embodiment of a reference voltage regulator.

FIG. 5 is a schematic diagram of another embodiment of a reference voltage regulator.

FIG. 6 is a schematic diagram of an internal block of the current compensation circuit.

Fig. 7 is a flow chart illustrating the operation of the current compensation circuit.

FIG. 8 is a schematic diagram of one embodiment of a current compensation circuit.

FIG. 9 is a schematic diagram of another embodiment of a current compensation circuit.

[ notation ] to show

Chip 10

amperemeters

11, 22

Core circuit

15, 25 current flattening circuit 21

Power pin 23 current balancing circuit 40

Reference voltage regulator

30, 30a,30c

Current compensation circuit

50, 51, 53 current sensing circuit 60

System circuit 20

Steps S41, S42, S43, S44, S45, S47, S49, S471, S472, S473, S474, S477, S479

Constant voltage sources

32a, 32c

Voltage supply circuits

301a, 301c voltage-to-

current circuits

303a,303c

Current conduction circuits

305a,305c current to

voltage conversion circuits

309a,309c

First current mirror 306a and second current mirror 306b

Voltage matching circuits

50a, 51a, 53a

First

current circuits

50b, 51b, 42b

Second

current circuits

50c, 51c, 53c

Detailed Description

The present disclosure provides a current planarization circuit, a current compensation circuit, and a control method thereof. The use of the current compensation circuit can keep the current variation (devision) measured by the current meter relatively stable.

Herein, for convenience of description, the node and the voltage on the node are denoted by the same symbol. For example, the ground voltage and ground voltage node is denoted as "Gnd".

Referring to fig. 2, a schematic diagram of a system circuit including a current flattening circuit and a core circuit is illustrated. The system circuit 20 includes a core circuit 25 and a current flattening circuit 21, and the power pin 23 of the system circuit 20 is electrically connected to a voltage source providing a supply voltage (Vsrc). The current meter 22 is connected in series with the power pin 23 and is used for measuring the supply current (Ivdd) flowing through the power pin 23, thereby capturing the operation of the core circuit 25.

The current flattening circuit 21 is electrically connected between the power pin 23 and the core circuit 25. The node where the current flattening circuit 21 is connected to the power pin 23 is defined herein as the supply voltage node (Nvdd), and the node connected to the core circuit 25 and the current flattening circuit 21 is defined as the core node (Ncore). Therein, the voltage level of the core node (Ncore) is defined as the core voltage (Vcore). Further, core current (Icore) represents the current flowing from the core node (Ncore) to the core circuitry 25, and the core current (Icore) varies with the operation of the core circuitry 25. The system circuit 20 may be a system-on-chip (SOC) or a system-on-package (SOP), so the core current (Icore) cannot be detected but the supply current (Ivdd) is detected. Accordingly, the present disclosure provides embodiments that suppress supply current (Ivdd) fluctuations.

According to an embodiment of the present disclosure, the current flattening circuit 21 includes a current sensing circuit 60 and a current balancing circuit 40. The current sense circuit 60 is electrically connected to the supply voltage node (Nvdd) and the core node (Ncore). The current sensing circuit 60 may be a sense resistor Rs, and the current flowing through the current sensing circuit 60 Is defined as a sense current (Is). The current balancing circuit 40 is electrically connected to the core node (Ncore).

In accordance with the present disclosure, it Is desirable to have the sensing current (Is) consistent in current value, and the sensing current (Is) Is consistent in most cases. The sense current (Is) flowing through current sense circuit 60 Is split into two portions at the core node (Ncore), one core current (Icore) and one compensation current (Icmp). Therefore, the sensing current (Is) Is equivalent to the sum of (Icore) and the compensation current (Icmp). Based on this summation relationship, the compensation current (Icmp) and the core current (Icore) are inversely related to each other and fluctuations in the sense current (Is) can be eliminated.

The supply current (Ivdd) flowing through the power pin 23 Is divided into two at the supply voltage node (Nvdd), i.e., the sense current (Is) and the auxiliary current (Iadd). The auxiliary current (Iadd) does not necessarily occur. When the auxiliary current (Iadd) Is generated, the supply current (Ivdd) Is equivalent to the sum of the sense current (Is) and the auxiliary current (Iadd). Otherwise, the supply current (Ivdd) Is equivalent to the sense current (Is). Generally, the auxiliary current (Iadd) Is relatively smaller than the sense current (Is).

The current balancing circuit 40 further includes a reference voltage regulator 30 and a current compensation circuit 50 electrically connected to each other. The reference voltage regulator 30 provides a reference voltage (Vref) to the current compensation circuit 50, and the voltage level of the reference voltage (Vref) is designed to be constant.

In theory, the core voltage (Vcore) may be equal to a multiple of the reference voltage (Vref). For ease of illustration, it is assumed herein that the core voltage (Vcore) is equal to the reference voltage (Vref). The current balancing circuit 40 dynamically generates the compensation current (Icmp) and the auxiliary current (Iadd) based on the core voltage (Vcore) and the reference voltage (Vref). Once a voltage difference exists between the reference voltage (Vref) and the core voltage (Vcore), the compensation current (Icmp) varies and the voltage difference can be reduced.

As the core current (Icore) increases, the sense current (Is) increases, which in turn increases the voltage drop across the sense resistor (Rs) and decreases the core voltage (Vcore). In this case, the reference voltage (Vref) will be greater than the core voltage (Vcore), and the voltage difference between the reference voltage (Vref) and the core voltage (Vcore) will cause the compensation current (Icmp) to vary. That is, the compensation current (Icmp) will begin to decrease. As the compensation current (Icmp) decreases, the core voltage (Vcore) will increase. Thereafter, the core voltage (Vcore) will continue to increase until the core voltage (Vcore) equals the reference voltage (Vref). Accordingly, the core voltage (Vcore) may be maintained substantially equal to the reference voltage (Vref).

In turn, the voltage drop across the sense resistor (Rs), i.e., (Vdd-Vcore), may be maintained consistent because the level of the core voltage (Vcore) is substantially equal to the reference voltage (Vref). The sense current (Is) through the sense resistor (Rs) can be calculated from (Vdd-Vcore)/Rs according to ohm's Law. Because the resistance values of the supply voltage (Vdd), core voltage (Vcore), and sense resistor (Rs) are all maintained consistent, the fluctuations in the sense current (Is) can be mitigated.

FIG. 3 is a flow chart illustrating how the operation of the current flattening circuit keeps the core voltage consistent. First, assume that the current flattening circuit 21 and the core circuit 25 are in a balanced state. When the current flattening circuit 21 and the core circuit 25 are in an equilibrium state, the core voltage (Vcore) Is equal to the reference voltage (Vref), and the sense current (Is) flowing to the core voltage (Vcore) Is kept uniform (step S41). The current sensing circuit 60 provides a portion of the sensing current (Is) as the core current (Icore) and supplies the core current (Icore) to the core circuit 25 (step S42).

The reference voltage regulator 30 continuously generates the reference voltage (Vref) (step S43). Meanwhile, the current sensing circuit 60 detects the sensing current (Is) according to the detection result of the core voltage (Vocre), and the current sensing circuit 60 outputs the detected core voltage (Vcore) to the current compensation circuit 50 (step S44). Upon receiving the core voltage (Vcore) from the current sensing circuit 60, the current compensation circuit 50 determines whether the core voltage (Vcore) changes (step S45). If the determination result of step S45 is negative, step S41 is repeatedly executed.

If the determination result of step S45 Is positive, the current compensation circuit 50 adjusts the compensation current (Icmp), wherein the compensation current (Icmp) as another part of the sensing current (Is) Is generated according to the voltage difference between the core voltage (Vcore) and the reference voltage (Vref) (step S47). Thereafter, the core voltage (Vcore) will change based on the adjustment of the compensation current (Icmp) (step S49). Thereafter, the entire operation flow is repeatedly executed.

As previously described, the sense current (Is) may be divided into two portions, the core current (Icore) and the compensation current (Icmp). The compensation current (Icmp) is adjusted in an inverse manner as the core current (Icore) varies with operation of the core circuitry 25.

Different embodiments of the reference voltage regulator and the current compensation circuit are described below. The reference voltage regulator and the current compensation circuit described below can be arbitrarily selected and used in combination.

Referring to fig. 4, a schematic diagram of an embodiment of a reference voltage regulator is shown. The reference voltage regulator 30a receives a constant voltage (Vbg) from a constant voltage source 32a and generates a reference voltage (Vref) to a reference voltage node. For example, the constant voltage source 32a may be, but is not limited to, a bandgap voltage (bandgap voltage) circuit and is used to generate a bandgap voltage having a small temperature coefficient (temperature coefficient). In fig. 4, the reference voltage regulator 30a includes a voltage providing circuit 301a, a voltage to current circuit 303a, a current conducting circuit 305a, and a current to voltage circuit 309 c.

The voltage supply circuit 301a includes source operational amplifiers (OPs). The inverting input terminal (-) of the source operational amplifier (OPs) receives a constant voltage (Vbg) from the constant voltage source 32 a. The non-inverting input terminal (+) of the source operational amplifiers (OPs) is electrically connected to the voltage-to-current circuit 303 a. The voltage levels of the non-inverting input terminal (+) and the inverting input terminal (-) are equal to each other, and the non-inverting input terminal (+) of the source operational amplifier (Ops) transmits a quasi-constant voltage (Vbg') to the voltage-to-current circuit 303 a. The output terminals of the source operational amplifiers (OPs) are electrically connected to the current conducting circuit 305 a. The source operational amplifiers (OPs) amplify a voltage difference between the constant voltage (Vbg) and the quasi-constant voltage (Vbg') to generate output signals. The constant voltage (Vbg) and the quasi-constant voltage (Vbg ') are substantially equal to each other (Vbg ═ Vbg').

The voltage-to-current circuit 303a includes a first resistor (R1), and the voltage-to-current circuit 303 is electrically connected to the voltage supply circuit 301 and the ground node (Gnd). As shown in equation (1), the source current (Isrc) may be determined by a constant voltage (Vbg) and a first resistor (R1).

Is Vbg'/R1 Vbg/R1 … … … … … … … … … … … … … … formula (1)

The current conduction circuit 305a of fig. 4 includes a PMOS transistor (P). The gate of the PMOS transistor (P) is electrically connected to the output terminal of the voltage supply circuit 301 a. The source of the PMOS transistor (P) is electrically connected to the current-to-voltage circuit 309 a. The drain of the PMOS transistor (P) is electrically connected to the voltage-to-current circuit 303 a.

The current-to-voltage circuit 309a includes a second resistor (R2).As shown in fig. 4, the second resistor (R2) is electrically connected to the supply voltage node (Vdd), and the reference current (Iref) flows through the second resistor (R2). The voltage drop Δ V across the second resistor R2 according to the reference current (Iref)_R2Can be represented by formula (2).

ΔV_R2Iref R2 Vdd-Vref … … … … … … … … … … … … formula (2)

The PMOS transistor (P) is controlled by the output signal (Vops) of the source operational amplifier (OPs). When the PMOS transistor (P) is turned on, a conduction current (Icon) flows through the PMOS transistor (P). As shown in fig. 4, the conduction current (Icon), the reference current (Iref), and the source current (Isrc) together form a current path. Therefore, the conduction current (Icon), the source current (Isrc), and the reference current (Iref) have the same current value, i.e., Icon ═ Is ═ Iref.

The reference current (Iref) of equation (2) may be replaced with the source current (Isrc) due to the source current (Isrc) and the reference current (Iref) being equal to each other. Therefore, the formula (2) can be further derived as the formula (3).

Vref＝Vdd-Iref*R2＝Vdd-Is*R2

Vdd- (Vbg R2)/R1 … … … … … … … … … … … … … … … … formula (3)

According to equation (3), the reference voltage (Vref) can be derived from the supply voltage (Vdd), the constant voltage (Vbg), the voltage-to-current circuit 303a (the first resistor R1), and the current-to-voltage circuit 309a (the second resistor R2), and the values of the supply voltage (Vdd), the constant voltage (Vbg), the first resistor R1, and the second resistor R2 are known in the design and production of the voltage reference regulator 30 a.

Referring to fig. 5, a schematic diagram of another embodiment of a reference voltage regulator is shown. The reference voltage regulator 30c receives a constant voltage (Vbg) from the constant voltage source 32c and generates a reference voltage (Vref) to a current compensation circuit (not shown). In fig. 5, the reference voltage regulator 30c includes a voltage providing circuit 301c, a voltage to current circuit 303c, a current conducting circuit 305c, and a current to voltage circuit 309 c. The current conducting circuit 305c further includes a first current mirror 306a and a second current mirror 306 b.

The source operational amplifier 301c and the voltage-to-current circuit 303c are connected in a manner similar to that of fig. 4, and the details thereof are not described herein. Therefore, the source current (Isrc) of fig. 5 can be derived from equation (1) as well.

The first current mirror 306a includes a first PMOS transistor (P1) and a second PMOS transistor (P2). The gates of the first PMOS transistor (P1) and the second PMOS transistor (P2) are electrically connected to the output terminal of the voltage supply circuit 301 c. The sources of the first PMOS transistor (P1) and the second PMOS transistor (P2) are electrically connected to the supply voltage node (Vdd). The drain of the first PMOS transistor (P1) is electrically connected to the voltage-to-current circuit 303c, and the drain of the second PMOS transistor (P2) is electrically connected to the second current mirror 306 b.

As shown in fig. 5, the first PMOS transistor (P1) and the first resistor (R1) form a first current path, and both the first mirror input current (Iin1) and the source current (Isrc) flow through the first current path. Therefore, the current value of the first mirrored input current (Iin1) is equal to the current value of the source current (Isrc). The first mirror input current (Iin1) flows through the first PMOS transistor (P1), and the first mirror output current (Iout1) flows through the second PMOS transistor (P2). Based on the architecture of the current mirror, the first mirrored input current (Iin1) is equal to the first mirrored output current (Iout 1).

The second current mirror 306b includes a first NMOS transistor (N1) and a second NMOS transistor (N2). The gate of the first NMOS transistor (N1) and the gate of the second NMOS transistor (N2) are electrically connected to the output terminal of the first current mirror 306 a. The sources of the first NMOS transistor (N1) and the second NMOS transistor (N2) are electrically connected to the ground node (Gnd). The drain of the first NMOS transistor (N1) is electrically connected to the output terminal of the first current mirror 306a, and the drain of the second NMOS transistor (N2) is electrically connected to the current-to-voltage circuit 309 c.

As shown in fig. 5, the second PMOS transistor (P2) and the first NMOS transistor (N1) form a second current path, and the first mirror output (Iout1) and the second mirror input current (Iin2) both flow through the second current path. Therefore, the current values of the first mirror output (Iout1) and the second mirror input current (Iin2) are equal to each other. The second mirrored input current (Iin2) flows through the first NMOS transistor (N1), and the second mirrored output current (Iout2) flows through the second NMOS transistor (N2). According to the architecture of the current mirror, the second mirrored input current (Iin2) is equal to the second mirrored output current (Iout 2).

The current-to-voltage circuit 309c includes a second resistor (R2). The current-to-voltage circuit 309a of fig. 4 and the current-to-voltage circuit 309c of fig. 5 are connected between the supply voltage node (Vdd) and the current compensation circuit, and the current-to-

voltage circuits

309a,309c operate in a similar manner. Since the connection relationship and the position of the second resistor (R2) in fig. 4 and 5 are similar, the voltage drop Δ VR2 across the second resistor (R2) in fig. 5 can also be calculated by applying equation (2).

As shown in fig. 5, the second resistor (R2) and the second NMOS transistor (N2) form a third current path, wherein the reference current Iref and the second mirror output current (Iout2) both flow through the third current path. Therefore, the reference current Iref and the second mirror output current (Iout2) have the same current value. From the foregoing description, the source current (Isrc), the first mirror input current (Iin1), the first mirror output current (Iout1), the second mirror input current (Iin2), the second mirror output current (Iout2), and the reference current (Iref) are assumed to be equal to each other. That is, Isrc is Iin1, Iout is Iin2, Iout2, Iref.

However, the relationship between the reference voltage (Vref) and the constant voltage (Vbg) can be freely defined without limitation. Therefore, the current transfer ratio (currenttransfer ratio) between the source current (Isrc), the first mirror input current (Iin1), the first mirror output current (Iout1), the second mirror input current (Iin2), the second mirror output current (Iout2), and the reference current (Iref) may not be equal to "1".

Therefore, the first current mirror 306a and the second current mirror 306b are designed to be quite flexible, and the current conversion ratio between the input current (Iin1 and Iin2) and the output current (Iout1 and Iout2) is not necessarily equal to "1". In conjunction, the first mirrored input current (Iin1), the first mirrored output current (Iout1), the second mirrored input current (Iin2), the second mirrored output current (Iout2), and the reference current (Iref) may be a multiple of the source current (Isrc). Alternatively, the current value of the reference current (Iref) is proportional to the current value of the source current (Isrc). The design change of the current conversion ratio can be arbitrarily replaced or changed by a person having ordinary skill in the art, and is not described in detail herein.

Since the source current (Isrc) and the reference current (Iref) are equal to each other, equation (3) can be applied to the reference voltage (Vref) of fig. 5. Since the supply voltage (Vdd), the constant voltage (Vbg), the voltage-to-current circuit 303c (the first resistor R1) and the current-to-voltage circuit 309a (the second resistor R2) are determined when the voltage reference regulator 30c is designed and manufactured, the reference voltage (Vref) provided by the reference regulator 30c will remain unchanged.

According to the above embodiments, the

current conducting circuits

305a,305c in the

reference voltage regulators

30a,30c may be used to bridge the voltage-to-

current circuits

303a,303c and the current-to-

voltage circuits

309a,309 c. The

current conducting circuits

305a,305c transmit a predetermined current value of the source current (Isrc) to the current-to-voltage circuits t 309a,309c, so that the current-to-

voltage circuits

309a,309c use the predetermined current value as the current value of the reference current (Iref).

In other words, the design of the voltage-to-

current circuits

303a,303c will determine the value of the source current (Isrc). The current value of the source current (Isrc) is provided to the

current conducting circuits

305a,305c, and the current value of the conducting current (Icon) is determined accordingly. Through the bridging of the

current conducting circuits

305a,305c, the source current (Isrc) is always equal to the reference current (Iref), and the current values of these currents can be maintained at a constant default value. Accordingly, the current-to-voltage circuit 309c may continuously provide a constant voltage (i.e., a reference voltage (Vref)) to the current compensation circuit.

As shown in fig. 4 and 5, the current-to-

voltage circuits

309a and 309c are both disposed between the supply voltage node (Vdd) and the reference voltage node having the reference voltage (Vref) for improving the Power Supply Rejection Ratio (PSRR) of the

reference voltage regulators

30a and 30 c.

Because the reference current (Iref) Is equal to the source current (Isrc), the reference current (Iref) remains relatively stable when the supply voltage (Vdd) Is disturbed, i.e., Iref Is Vbg/R1. In conjunction, the reference voltage (Vref) may vary with variations in the supply voltage (Vdd). When the reference voltage (Vref) and the supply voltage (Vdd) are changed at the same time, the core voltage (Vcore) determined by the reference voltage (Vref) is also changed according to the change of the supply voltage (Vdd). Because the second resistor (R2) is connected between the supply voltage node (Vdd) and the reference voltage node (Vref), the source current (Isrc) is less disturbed by the supply voltage (Vdd).

According to an embodiment of the present disclosure, the reference voltage regulator 30 continuously receives the constant voltage (Vbg) and provides the reference voltage (Vref) to the current compensation circuit 50 accordingly. The current compensation circuit 50 reuses the reference voltage (Vref) as the comparison basis for the core voltage (Vcore). Based on the comparison of the reference voltage (Vref) and the core voltage (Vcore), the current compensation circuit 50 will dynamically adjust the generation of the compensation current (Icmp). The operation of the current compensation circuit 50 is explained below.

Fig. 6 is a schematic diagram of an internal block of the current compensation circuit. The current compensation circuit 50 includes a voltage matching circuit 50a and a first current circuit 50 b. In addition, the current compensation circuit 50 may further include a second current circuit 50 c. The first current circuit 50b and the second current circuit 50c can be turned on or off by the first switch (sw1) and the second switch (sw2), respectively.

The voltage matching circuit 50a is electrically connected to the core node (Ncore), and the first current circuit 50b is electrically connected to the core node (Ncore) through conduction of the first switch (sw 1). The second current circuit 50c is electrically connected to the supply voltage node (Nvdd) by the conduction of the second switch (sw 2). Unlike the first current circuit 50b, the voltage matching circuit 50a does not conduct current from the core node (Ncore) to the ground node (Gnd), and the voltage matching circuit 50a only senses the core voltage (Vcore). That is, no current is conducted from the core node (Ncore) to the voltage matching circuit 50 a.

The first switch (sw1) and the second switch (sw2) can be selectively turned on or off by a core circuit (not shown), and the first switch (sw1) and the second switch (sw2) can be implemented by MOS transistors. In practical applications, the control signals for controlling the switch states of the first switch (sw1) and the second switch (sw2) are independent of each other, and the two switches (sw1 and sw2) can be turned on simultaneously or separately. Both control signals for controlling the corresponding switches may be random sequence (randomsequence) control signals or one control signal maintained at a high level. For ease of explanation, the case where both switches are on at the same time is assumed herein.

The voltage matching circuit 50a receives a reference voltage (Vref) from the reference voltage regulator 30 and a core voltage (Vcore) from a core node (Ncore). The output signal of the voltage matching circuit 50a (Vopm) is used to control the first current circuit 50b and the second current circuit 50c, and the output signal of the voltage matching circuit 50a (Vopm) is generated according to the voltage difference between the reference voltage (Vref) and the core voltage (Vcore). Herein, the signals extracted by the voltage matching circuit 50a from the reference voltage regulator 30 and the core node (Ncore), i.e., the reference voltage (Vref) and the core voltage (Vcore), respectively, are represented in voltage form. In practice, the signals provided by the reference voltage regulator 30 and the core node (Ncore) may also be represented as currents.

According to the output signal (Vopm) of the voltage matching circuit 50a, the first current circuit 50b and the second current circuit 50c generate the compensation current (Icmp) and the auxiliary current (Iadd), respectively. The auxiliary current (Iadd) is proportional to the compensation current (Icmp). The compensation current (Icmp) assist current (Iadd) increases when the core current (Icore) decreases and vice versa.

The supply current (Ivdd) Is divided into an auxiliary current (Iadd) and a sense current (Is) at a supply voltage node (Nvdd), wherein the sense current (Is) Is further divided into a compensation current (Icmp) and a core current (Icore) at a core node (Ncore). According to an embodiment of the present disclosure, the sense current (Is) Is larger than the auxiliary current (Iadd), and the sense current (Is) Is a major portion of the supply current (Iadd).

Table 1 lists the changes in the currents defined in fig. 2 and fig. 6 at two time points (the first time point t1 and the second time point t 2).

TABLE 1

The first column of table 1 is the change in core current (Icore). The core currents at the first time point (t1) and the second time point (t2) are denoted as Icore (t1) and Icore (t2), respectively. The change amount (Δ Icore) of the core current between the two timings may be calculated from the core current (Icore) at the first timing (t1) and the second timing (t2), that is, Δ Icore (t2) -Icore (t 1).

The second column of table 1 is the variation of the compensation current (Icmp). The compensation currents at the first time (t1) and the second time (t2) are denoted as Icmp (t1) and Icmp (t2), respectively. The amount of change in the compensation current (Δ Icmp) between the two timings can be calculated from the compensation current (Icmp) at the first timing (t1) and the second timing (t2), that is, Δ Icmp ═ Icmp (t2) -Icmp (t 1).

The third column of table 1 Is the change in the sense current (Is). The sensing currents at the first time point (t1) and the second time point (t2) are denoted as Is (t1) and Is (t2), respectively. The variation (Δ Is) of the sensing current between the two time points can be calculated according to the sensing current (Is) at the first time point (t1) and the second time point (t2), i.e., Δ Is ═ Is (t2) -Is (t 1).

As described above, the sense current (Is) Is equal to the sum of the core current (Icore) and the compensation current (Icmp), i.e., Is Icore + Icmp. Therefore, Δ Is ═ Is (t2) -Is (t1) can be rewritten as formula (4).

ΔIs＝Is(t2)-Is(t1)

＝[Icore(t2)+Icmp(t2)]-[Icore(t1)+Icmp(t1)]

＝[Icore(t2)-Icore(t1)]+[Icmp(t2)+Icmp(t1)]

Δ Icore + Δ Icmp … … … … … … … … … … … … … … … … … formula (4)

Ideally, the sum of equation (4) remains "0". In practical applications, the summation result of equation (4) may not equal "0" due to some extreme cases, and the summation result of equation (4) may be a positive value or a negative value. These extremes may occur when the core current (Icore) significantly increases or decreases at brief instants.

When the core current (Icore) increases significantly in a brief instant, the speed of the compensation current (Icmp) decrease cannot keep up with the speed of the core current (Icore) increase because the compensation current (Icmp) decreases at a slower speed. In conjunction, the summation of equation (4) Is a positive value, which means that the sense current (Is) may increase when the core current (Icore) significantly increases at a brief instant.

When the core current (Icore) is significantly reduced at a brief instant, the compensation current (Icmp) does not increase as fast as the core current (Icore) because the compensation current (Icmp) increases at a slower rate. In conjunction, the summation of equation (4) Is a negative value, which means that the sense current (Is) may decrease when the core current (Icore) decreases significantly for a brief moment.

In other words, in extreme cases, the change in sense current (Is) may appear positively correlated to the change in core current (Icore). To further reduce the correlation between the sense current (Is) and the core current (Icore) under such extreme conditions, the present disclosure further provides a second current circuit 50c that provides an auxiliary current (Iadd) when the second switch (sw2) Is turned on, wherein. The generation of the auxiliary current (Iadd) is adjustable, and the auxiliary current (Iadd) is smaller than the compensation current (Icmp).

The fourth column of table 1 is the change in auxiliary current (Iadd). The auxiliary currents at the first time point (t1) and the second time point (t2) are denoted as Iadd (t1) and Iadd (t2), respectively. The amount of change in the auxiliary current (Δ Iadd) between the two times can be calculated from the auxiliary current (Iadd) at the first time (t1) and the second time (t2), i.e., Δ Iadd ═ Iadd (t2) -Iadd (t 1). According to an embodiment of the present disclosure, the change amount of the auxiliary current (Δ Iadd) between the two time points is smaller than the change amount of the compensation current (Δ Icmp) between the two time points, i.e., Δ Iadd < Δ Icmp.

The fifth column of Table 1 is the change in supply current (Ivdd). The supply currents at the first time point (t1) and the second time point (t2) are denoted as Ivdd (t1) and Ivdd (t2), respectively. The amount of change in the supply current (Δ Ivdd) between these two points in time can be calculated from the supply current (Ivdd) at the first point in time (t1) and the second point in time Ivdd (t2), i.e., Δ Ivdd ═ Ivdd (t2) -Ivdd (t 1). Since the supply current (Ivdd) Is equivalent to the sum of the sense current (Is) and the auxiliary current (Iadd) (i.e., Ivdd ═ Is + Iadd)), Δ Ivdd ═ Ivdd (t2) -Ivdd (t1) can be rewritten as equation (5).

ΔIvdd＝Ivdd(t2)-Ivdd(t1)

＝[Is(t2)+Iadd(t2)]-[Is(t1)+Iadd(t1)]

＝[Is(t2)-Is(t1)]+[Iadd(t2)-Iadd(t1)]

Δ Is + Δ Iadd … … … … … … … … … … … … … … … … … … equation (5)

According to equation (5), the change amount (Δ Ivdd) of the supply current (Ivdd) flowing through the power pin 23 depends on the change amount (Δ Is) of the sensing current and the change amount (Δ Iadd) of the auxiliary current. According to the formula (4), the formula (5) can be further rewritten as the formula (6).

ΔIvdd＝ΔIs+ΔIadd

(Δ Icore + Δ Icmp) + Δ Iadd … … … … … … … … … … … … … … formula (6)

According to equation (6), the change amount of the supply current (Δ Ivdd) includes three components in total, the change amount of the core current (Δ Icore), the change amount of the compensation current (Δ Icmp), and the change amount of the assist current (Δ Iadd). According to equation (6), when the core current varies (Δ Icore is generated), the variation (Δ Icmp) of the compensation current and the variation (Δ Iadd) of the auxiliary current are used to adjust and reduce the variation (Δ Ivdd) of the supply current, i.e., Δ Ivdd ≈ 0. Because both the compensation current (Icmp) and the auxiliary current (Iadd) are inversely related to the core current (Icore), fluctuations in the supply current (Ivdd) may be suppressed.

In short, the compensation current (Icmp) generated by the first current circuit 50b may be considered to provide a ripple suppression function for the first stage, and the auxiliary current (Iadd) generated by the second current circuit 50c may be considered to provide a ripple suppression function for the second stage. Furthermore, the first switch (sw1) and the second switch (sw2) can be selectively turned on or off according to independent control signals, so that the supply current (Ivdd) measured by the current meter 22 is more difficult to predict.

When the first switch (sw1) Is turned on, the first current circuit 50b generates the compensation current (Icmp), and the sensing current (Is) includes the core current (Icore) and the compensation current (Icmp). When the second switch (sw2) Is turned on, the second current circuit 50c generates the auxiliary current (Iadd), and the supply current (Iadd) includes the sensing current (Is) and the auxiliary current (Iadd).

Among these currents, the sense current (Is) has a higher uniformity than the core current (Icore), and the main portion of the supply current (Ivdd) Is the sense current (Is) and can be slightly adjusted with the auxiliary current (Iadd). The auxiliary current (Idd) enables fluctuations in the supply current (Ivdd) in transient response to be mitigated compared to the sense current (Is). As shown in FIG. 2, current meter 22 measures the supply current (Ivdd) rather than the core current (Icore). In accordance with the present disclosure, the supply current (Ivdd) is more consistent than the core current (Icore), and thus, the measurement of the supply current (Ivdd) by current meter 22 does not reveal the operation of core circuit 25.

Referring to fig. 7, a flow chart illustrating the operation of the current compensation circuit is shown. First, the voltage matching circuit 50a receives the core voltage (Vcore) (step S471) and the reference voltage (Vref), respectively (step S472). Thereafter, the voltage matching circuit 50a generates an output signal (Vopm) according to a voltage difference between the reference voltage (Vref) and the core voltage (Vcore) (step S473). Steps S471, S472, and S473 outlined by the dotted line represent the operation of the voltage matching circuit 50 a.

The first current circuit 50b generates and adjusts the compensation current (Icmp) according to the output signal (Vopm) of the voltage matching circuit 50a (step S474). Changes in the compensation current (Icmp) affect the core voltage (Vcore). In conjunction, the core voltage (Vcore) varies and approaches the reference voltage (Vref) (step S477). When the second switch (sw2) is turned on, the second current circuit 50c generates the auxiliary current (Iadd) (step S479). The process flow shown in FIG. 7 continues until the core voltage (Vcore) is equal to the reference voltage (Vref).

Fig. 8 is a schematic diagram of an embodiment of a current compensation circuit. The current compensation circuit 51 includes a voltage matching circuit 51a, a first current circuit 51b and a second current circuit 51 c.

The voltage matching circuit 51a includes a matching operational amplifier (OPm'). The matched operational amplifier (OPm') has an inverting input terminal (-), a non-inverting input terminal (+) and an output terminal. The inverting input terminal (-) of the matching operational amplifier (OPm ') receives the reference voltage (Vref) from the reference voltage regulator 30, and the non-inverting input terminal (+) of the matching operational amplifier (OPm') is electrically connected to the core node (Ncore) and the first current circuit 51 b. The output terminals of the matching operational amplifier 51a are electrically connected to the first current circuit 51b and the second current circuit 51 c.

The first current circuit 51b includes a compensation transistor (Mb 1') (e.g., a third NMOS transistor); the second current circuit 51c includes an auxiliary transistor (Mb 2') (e.g., a fourth NMOS transistor). The size of the auxiliary transistor (Mb2 ') will typically be smaller than the size of the compensation transistor (Mb 1') when designing the circuit. Based on the size relationship between the transistors, the auxiliary current (Iadd ') flowing through the auxiliary transistor (Mb 2') may be smaller than the compensation current (Icmp ') flowing through the compensation transistor (Mb 1'). The compensation transistor (Mb1 ') and the control terminal of the auxiliary transistor (Mb2 ') are electrically connected in common to the output terminal of the matched operational amplifier (OPm '). Therefore, the conduction of the compensation transistor (Mb1 ') and the auxiliary transistor (Mb 2') is determined by the output signal (Vopm ') of the matched operational amplifier (OPm').

When the output signal (Vopm ') of the matched operational amplifier (OPm ') is greater than the threshold voltages of the compensation transistor (Mb1 ') and the auxiliary transistor (Mb2 '), the compensation transistor (Mb1 ') and the auxiliary transistor (Mb2 ') will be turned on and thus generate the compensation current (Icmp ') and the auxiliary current (Iadd). The compensation current (Icmp ') flows from the core node (Ncore) to the ground node (Gnd) via the compensation transistor (Mb 1'), and the auxiliary current (Iadd ') flows from the supply voltage node (Nvdd) to the ground node (Gnd) via the auxiliary transistor (Mb 2').

If the size of the auxiliary transistor (Mb2 ') is smaller than the size of the compensation transistor (Mb 1'), the auxiliary transistor (Mb2) has a higher conduction speed than the compensation transistor (Mb 1). In other words, the auxiliary current (Iadd ') is generated faster than the compensation current (Icmp').

FIG. 9 is a schematic diagram of another embodiment of a current compensation circuit. The current compensation circuit 53 includes a voltage matching circuit 53a, a first current circuit 53b, and a second current circuit 53 c.

The voltage matching circuit 53a includes a matching operational amplifier (OPm "). The matching operational amplifier (OPm ") has a non-inverting input terminal (+), which receives the reference voltage (Vref) from the reference voltage regulator 30, an inverting input terminal (-) that is electrically connected to the core node (Ncore) and the first current circuit 53b, and an output terminal that is electrically connected to the first current circuit 53b and the second current circuit 53 c.

The first current circuit 53b includes a compensation transistor (Mb1 ") (e.g., a third PMOS transistor); the second current circuit 53c includes an auxiliary transistor (Mb2 ") (e.g., a fourth PMOS transistor). The size of the auxiliary transistor (Mb2 ") is typically smaller than the size of the compensation transistor (Mb 1"). Depending on the size of the transistors, the auxiliary current (Iadd ") flowing through the auxiliary transistor (Mb 2") may be less than the compensation current (Icmp ") flowing through the compensation transistor (Mb 1"). The control terminals of the compensation transistor (Mb1 ') and the auxiliary transistor (Mb2 ') are electrically connected in common to the output terminal of the matched operational amplifier (OPm ').

When a voltage difference exists between the core voltage (Vcore) and the reference voltage (Vref), causing the output signal (Vopm ") of the matched operational amplifier (OPm") to be greater than the threshold voltages of the compensation transistor (Mb1 ") and the auxiliary transistor (Mb 2"), the compensation transistor (Mb1 ") and the auxiliary transistor (Mb 2") will thus be turned on and generate the compensation current (Icmp') and the auxiliary current (Iadd "), respectively. The compensation current (Icmp ") flows from the core node (Ncore) to the ground node (Gnd) via the compensation transistor (Mb 1"), and the auxiliary current (Iadd ") flows from the supply voltage node (Vdd) to the ground node (Gnd) via the auxiliary transistor (Mb 2"). If the size of the auxiliary transistor (Mb2 ") is smaller than the size of the compensation transistor (Mb 1"), the auxiliary transistor (Mb2 ") will turn on faster than the compensation transistor (Mb 1"). That is, the auxiliary current (Iadd ") is generated faster than the compensation current (Icmp").

The current flattening circuit provided by the present disclosure includes a current sensing circuit, a current compensation circuit, and a reference voltage regulator. The reference voltage regulator provides a reference voltage (Vref) to the current compensation circuit. As the core current (Icore) flowing to the core circuit varies, the compensation current (Icmp) generated by the current compensation circuit also varies. In general, the current compensation current (Icmp) may maintain the reference voltage (Vref) equal to the core voltage (Vcore). In conjunction, the sense current (Is) flowing through the current sensing circuit may be maintained uniform. As previously described, the uniformity of the supply current (Iadd) is higher after the auxiliary current (Iadd) is taken in.

While the invention has been described with reference to the preferred embodiments, it is to be understood that the invention is not limited thereto. Those skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the protection scope of the present invention should be determined by the scope of the appended claims.

Claims

1. A current flattening circuit electrically connected to a core node, comprising:

a reference voltage regulator that generates a reference voltage, wherein the reference voltage is constant; and

a current compensation circuit, electrically connected to the core node and the reference voltage regulator, for generating a compensation current according to a voltage difference between the reference voltage and a core voltage corresponding to the core node;

wherein the reference voltage regulator comprises:

a voltage supply circuit, which receives a constant voltage;

a voltage-to-current circuit, electrically connected to the voltage supply circuit, for generating a source current according to the constant voltage;

a current-to-voltage circuit for receiving a supply voltage and generating the reference voltage according to the supply voltage and a reference current, wherein a current value of the reference current is proportional to a current value of the source current; and

a current conducting circuit electrically connected to the voltage providing circuit, the voltage-to-current circuit and the current-to-voltage circuit, wherein the current conducting circuit provides the reference current according to the source current;

the reference voltage regulator continuously receives a constant voltage and provides the reference voltage to the current compensation circuit according to the constant voltage, the current compensation circuit utilizes the reference voltage as a comparison basis of a core voltage, and the current compensation circuit dynamically adjusts the generation of the compensation current based on a comparison result of the reference voltage and the core voltage.

2. The current flattening circuit of claim 1, which compensates for a core current, wherein the current flattening circuit further comprises:

a current sensing circuit that conducts a sense current between a supply voltage node and the core node, wherein the current sensing circuit adjusts the core voltage as the sense current changes, and the sense current is equal to the sum of the core current and the offset current.

3. The current flattening circuit of claim 1, wherein the current compensation circuit comprises:

a voltage matching circuit receiving the reference voltage and the core voltage, wherein an output signal of the voltage matching circuit varies with a voltage difference between the reference voltage and the core voltage; and

a first current circuit electrically connected to the core node and the voltage matching circuit, wherein the first current circuit generates the compensation current.

4. A current compensation circuit electrically connected to a core node, wherein the current compensation circuit comprises:

a voltage matching circuit receiving a reference voltage and a core voltage corresponding to the core node, wherein an output signal of the voltage matching circuit varies with a voltage difference between the reference voltage and the core voltage; and

a first current circuit electrically connected to the core node and the voltage matching circuit, wherein the first current circuit generates a compensation current, wherein the compensation current tends to be stable when the core voltage is equal to the reference voltage;

the reference voltage is continuously received by a reference voltage regulator and is provided to the current compensation circuit according to the constant voltage, the current compensation circuit utilizes the reference voltage as a comparison basis of the core voltage, and the current compensation circuit dynamically regulates the generation of the compensation current based on the comparison result of the reference voltage and the core voltage;

the reference voltage regulator includes:

a voltage supply circuit, which receives a constant voltage;

a current conducting circuit electrically connected to the voltage providing circuit, the voltage-to-current circuit and the current-to-voltage circuit, wherein the current conducting circuit provides the reference current according to the source current.

5. The current flattening circuit of claim 1 or the current compensation circuit of claim 4 wherein the current compensation circuit compensates for a core current and the sum of the core current and the compensation current remains the same.

6. The current flattening circuit of claim 1 or the current compensation circuit of claim 4, wherein the current compensation circuit further comprises:

a second current circuit electrically connected to the voltage matching circuit for generating an auxiliary current according to the output signal of the voltage matching circuit,

wherein the auxiliary current is proportional to the compensation current.

7. The current flattening circuit or the current compensation circuit of claim 6, wherein the second current circuit randomly turns on or off the auxiliary current according to a control signal.

8. The current flattening circuit of claim 1 or the current compensation circuit of claim 5, wherein the voltage matching circuit includes a matched operational amplifier, wherein,

a first input terminal of the matched operational amplifier receiving the reference voltage from a reference voltage regulator;

a second input terminal of the matched operational amplifier is electrically connected to the core node and the first current circuit; and

an output terminal of the matching operational amplifier is electrically connected to the first current circuit.

9. A control method applied to the current flattening circuit of any one of claims 1 to 3, wherein the control method comprises the following steps:

generating a reference voltage, wherein the reference voltage is constant; and

a compensation current is generated based on a voltage difference between the reference voltage and a core voltage corresponding to the core node, wherein the compensation current is a portion of a supply current.