TWI646664B - Semiconductor structure and method for manufacturing the same - Google Patents

Abstract

A semiconductor structure includes a substrate, a secondary dummy structure, a sub-array structure, a three-dimensional array memory cell, a first conductive structure, and a second conductive structure. The substrate includes a dummy area and an array area, and the array area is adjacent to the dummy area. The secondary dummy structure is disposed on the dummy region and separated from each other by a plurality of first trenches, and the first trench extends in the first direction. The sub-array structure is disposed on the substrate and separated from each other by a plurality of second trenches, and the second trench extends in the second direction. These memory cells include a plurality of memory cell groups that are respectively disposed in the sub-array structure. The first conductive structure and the second conductive structure are respectively disposed in the first trench and the second trench. Each of the first conductive structures extends along the first direction. Each of the second electrically conductive structures extends along the second direction. The first direction is different from the second direction.

Description

Semiconductor structure and method of manufacturing same

The present disclosure relates to a semiconductor structure and a method of fabricating the same. The present disclosure relates in particular to a semiconductor structure including a memory cell and a method of fabricating the same.

In order to reduce the volume, reduce the weight, increase the power density, and improve the portability, a three-dimensional (3-D) semiconductor structure has been developed. Furthermore, components and spaces in semiconductor devices are continuously reduced. This can cause some problems. For example, in the fabrication of a 3-D memory device, a stack having a high aspect ratio may be formed for the construction of memory cells and/or other components. Such a stack may bend or collapse due to its high aspect ratio. Therefore, it is still desirable to have various improvements to the semiconductor structure and its method of fabrication.

The present disclosure relates to semiconductor structures and methods of fabricating the same, and more particularly to semiconductor structures including memory cells and methods of fabricating the same.

In accordance with some embodiments, a semiconductor structure includes a substrate, a secondary dummy structure, a sub-array structure, a three-dimensional array memory cell, a first conductive structure, and a second conductive structure. The substrate includes a dummy area and an array area, and the array area is adjacent to the dummy area. The secondary dummy structure is disposed on the dummy area and separated from each other by the plurality of first grooves, A groove extends in the first direction. The sub-array structure is disposed on the array region and separated from each other by a plurality of second trenches, and the second trench extends in the second direction. These memory cells include a plurality of memory cell groups that are respectively disposed in the sub-array structure. The first conductive structure and the second conductive structure are respectively disposed in the first trench and the second trench. Each of the first conductive structures extends along the first direction. Each of the second electrically conductive structures extends along the second direction. The first direction is different from the second direction.

According to some embodiments, a method of fabricating a semiconductor structure includes the following steps. First, a starting structure is provided. The starting structure includes a substrate and a preliminary array structure formed on the substrate. The substrate includes a dummy region and an array region. The preliminary array structure includes a plurality of active structures stacked and passed through the stack. Each of these active structures includes a channel layer and a memory layer formed between the channel layer and the stack. Next, a plurality of first trenches extending along the first direction are formed at the first predetermined trench locations in the preliminary array structure, and the preliminary array structures located on the dummy regions are separated into a plurality of secondary dummy structures. Forming a plurality of second trenches extending along the second direction in the second predetermined trench location in the preliminary array structure separates the plurality of sub-array structures in the preliminary array structure on the array region. Then, a plurality of first conductive structures and a plurality of second conductive structures are respectively formed in the first trench and the second trench. Each of the first conductive structures extends along a first direction, and each of the second conductive structures extends along a second direction, the first direction being different from the second direction.

In order to better understand the above and other aspects of the present invention, the following detailed description of the embodiments and the accompanying drawings

102‧‧‧Substrate

104‧‧‧ buried layer

108, 208‧‧‧ Stacking

110‧‧‧ Conductive layer

112‧‧‧High dielectric constant dielectric layer

114‧‧‧ Conductive core layer

116‧‧‧Insulation

118, 218‧‧‧ hard mask layer

120, 120a, 120b‧‧‧ active structure

122‧‧‧Channel layer

124‧‧‧ memory layer

126‧‧‧Insulation materials

128‧‧‧Electrical pads

130‧‧‧ memory cells

132‧‧‧Interlayer dielectric layer

140a‧‧‧ dummy structure

140b‧‧‧ array structure

154‧‧‧conductive central part

156‧‧‧Insulation lining

158‧‧‧Flexible wire

171‧‧‧ first trench

172‧‧‧Second trench

181‧‧‧First conductive structure

182‧‧‧Second conductive structure

210‧‧‧ Sacrifice layer

212‧‧‧High dielectric constant dielectric layer

216‧‧‧Insulation

232‧‧‧Interlayer dielectric layer

242‧‧‧Photoresist layer

251‧‧‧First predetermined groove position

252‧‧‧second predetermined groove position

254‧‧‧conductive central part

256‧‧‧Insulation lining

271‧‧‧ first opening

272‧‧‧ second opening

1811‧‧‧ Conductive filling section

1812‧‧‧High dielectric constant dielectric layer

1821‧‧‧conductive central part

1822‧‧‧Insulation lining

Aa‧‧‧Dummy area

Ab‧‧‧Array area

1A-1C illustrate a semiconductor structure in accordance with an embodiment.

2A-9C illustrate a method of fabricating a semiconductor structure in accordance with an embodiment.

Various embodiments will be described in more detail below in conjunction with the drawings. The drawings are for illustrative purposes only and are not intended to be limiting. For the sake of clarity, the components may not be shown in actual scale. In addition, some elements and/or component symbols may be omitted from the drawings. It is contemplated that elements and features of one embodiment can be advantageously included in another embodiment without further elaboration.

A semiconductor structure according to an embodiment includes a substrate, a secondary dummy structure, a sub-array structure, a three-dimensional array memory cell, a first conductive structure, and a second conductive structure. The substrate includes a dummy area and an array area, and the array area is adjacent to the dummy area. The secondary dummy structure is disposed on the dummy region and separated from each other by a plurality of first trenches, and the first trench extends in the first direction. The sub-array structure is disposed on the substrate and separated from each other by a plurality of second trenches, and the second trench extends in the second direction. These memory cells include a plurality of memory cell groups that are respectively disposed in the sub-array structure. The first conductive structure and the second conductive structure are respectively disposed in the first trench and the second trench. Each of the first conductive structures extends along the first direction. Each of the second electrically conductive structures extends along the second direction. The first direction is different from the second direction.

Please refer to FIGS. 1A-1C for a semiconductor structure. In the drawings, for ease of understanding, the semiconductor structure is depicted as a 3-D vertical pass. The NAND memory structure.

The semiconductor structure includes a substrate 102. Substrate 102 can include structures and elements, and the like formed therein and/or thereon. For example, substrate 102 can include a buried layer 104 disposed thereon. The substrate 102 includes a dummy area Aa and an array area Ab. The dummy area Aa is adjacent to the array area Ab.

The semiconductor structure includes a plurality of sub-fiction structures 140a and a plurality of sub-array structures 140b. The secondary dummy structure 140a is disposed on the dummy area Aa of the substrate 102. The sub-array structure 140b is disposed on the array region Ab of the substrate 102. These secondary dummy structures 140a are separated from each other by a plurality of first trenches 171. Each of the first trenches 171 extends in the first direction. These sub-array structures 140b are separated from one another by a plurality of second trenches 172. Each of the second grooves 172 extends in the second direction. The first direction is different from the second direction.

In a comparative example in which the extending direction of the trench having no dummy region or a dummy region but the dummy region is the same as the extending direction of the trench of the array region, the stress toward the array region may cause the array after performing a thermal process. The structure of the area is bent. In the present application, since the first trench 171 extends in a direction different from the extending direction of the second trench 172, the stress toward the array region Ab can be disabled by the first trench 171 after performing a thermal process. The release and balance in the area Aa can avoid the stress accumulated between the dummy area Aa and the array area Ab, and the stress can affect the physical structure of the semiconductor structure, and can solve the bending problem of the structure on the array area ( For example, the bending of the common source line).

In this embodiment, the first direction may be perpendicular to the second direction, for example The first direction may be the X-axis direction in the drawing, and the second direction may be the Y-axis direction in the drawing. In other embodiments, the first direction may not be perpendicular to the second direction. FIGS. 1A to 1C exemplarily show a portion of the dummy area Aa and the array area Ab, and more sub-dummy structures 140a and more sub-array structures 140b may be disposed on the substrate 102.

In this embodiment, each of the first trenches 171 and the second trenches 172 has a strip structure. In other embodiments, each of the first trenches 171 and the second trenches 172 may have other kinds of shapes.

According to some embodiments, the semiconductor structure can include a stack 108 and one or more active structures 120 that pass through the stack 108. The active structure 120 includes a first active structure 120a and a second active structure 120b. The first active structure 120a and the second active structure 120b are respectively disposed on the dummy area Aa and the array area Ab. Although FIG. 1B illustrates an example in which each memory cell group includes two active structures 120 (ie, the first active structure 120a and the second active structure 120b), the embodiment is not limited thereto. The stack 108 includes a plurality of conductive layers 110 and a plurality of insulating layers 116 that are alternately stacked. In some embodiments, each conductive layer 110 includes two high-k dielectric layers 112 and a conductive core layer 114 disposed therebetween, as shown in FIGS. 1B-1C. In such an example, the conductive core layer 114 can be formed from a metallic material. The two high-k dielectric layers 112 may be connected to each other. In some other embodiments, each conductive layer 110 can be comprised of a single layer. In such an example, the conductive core layer 114 can be formed of doped polysilicon. In some embodiments, the stack 108 further includes a hard mask layer 118 disposed on the conductive layer 110 and the insulating layer 116. According to some embodiments, Each active structure 120 can be formed in a columnar configuration. In such an example, each active structure 120 can include a channel layer 122 and a memory layer 124 disposed between the channel layer 122 and the stack 108. In some embodiments, each active structure 120 further includes an insulating material 126 that fills the space formed by the channel layer 122. In some embodiments, each array structure 140 further includes one or more conductive pads 128 coupled to one or more active structures 120, respectively. In some embodiments, each array structure 140b further includes an interlevel dielectric layer 132 disposed on the stack 108. According to some embodiments, the sub-array structure 140b can have a high aspect ratio.

The semiconductor structure includes a plurality of first conductive structures 181 and a plurality of second conductive structures 182. The first conductive structure 181 and the second conductive structure 182 are disposed in the first trench 171 and the second trench 172, respectively. Each of the first conductive structures 181 extends along a first direction (X direction in the drawing). Each of the second conductive structures 182 extends along a second direction (Y direction in the drawing). Each of the first conductive structures 181 includes a conductive fill portion 1811 and a high-k dielectric layer 1812 surrounding the conductive fill portion 1811. Each of the second conductive structures 182 includes a conductive central portion 1821 and an insulating liner 1822 surrounding the conductive central portion 1821.

The semiconductor structure includes a three-dimensional array of a plurality of memory cells 130. These memory cells 130 include a plurality of memory cell groups (not indicated in the figures) that are respectively disposed in the sub-array structure 140b. More specifically, the memory cells 130 of the memory cell group disposed in each of the sub-array structures 140b can be defined by the intersection between the conductive layer 110 of the stack 108 and the one or more active structures 120. . Conductive layer 110 of stack 108 of sub-array structures 140b, in accordance with some embodiments Configurable for word lines, the conductive pads 128 of the sub-array structure 140b can be configured for bit lines, and the conductive central portion 1821 can be configured for common source lines.

According to some embodiments, the distribution and number of active structures 120 are different in the dummy area Aa and the array area Ab. The first active structure 120a may have a first density in the dummy area Aa, and the second active structure 120b may have a second density in the array area Ab. The first density can be less than the second density.

A method of fabricating a semiconductor structure in accordance with an embodiment will now be described. It includes the following steps. First, a starting structure is provided. The starting structure includes a substrate and a preliminary array structure formed on the substrate. The substrate includes a dummy area and an array area. The preliminary array structure includes a plurality of active structures stacked and passed through the stack. Each of these active structures includes a channel layer and a memory layer formed between the channel layer and the stack. Next, a plurality of first trenches extending along the first direction are formed at the first predetermined trench locations in the preliminary array structure, and the preliminary array structures located on the dummy regions are separated into a plurality of secondary dummy structures. Forming a plurality of second trenches extending along the second direction in the second predetermined trench location in the preliminary array structure separates the plurality of sub-array structures in the preliminary array structure on the array region. Then, a plurality of first conductive structures and a plurality of second conductive structures are respectively formed in the first trench and the second trench. Each of the first conductive structures extends along a first direction, and each of the second conductive structures extends along a second direction, the first direction being different from the second direction.

Please refer to Figures 2A-9C, which show such a method. For ease of understanding, this method is illustrated as using a process using a sacrificial layer to form The semiconductor structure shown in Figures 1A-1C, wherein the sacrificial layer will be replaced by a conductive layer in a subsequent step. The drawings indicated by "B" and "C" are cross-sectional views taken from the B-B line and the C-C line in the pattern indicated by "A".

As shown in Figures 2A-2B, a substrate 102 is provided. The substrate 102 can include a dummy area Aa and an array area Ab. The array area Ab is adjacent to the dummy area Aa. Substrate 102 can include structures and elements, and the like formed therein and/or thereon. For example, substrate 102 can include a buried layer 104 disposed thereon as shown in FIG. 2B. The buried layer 104 may be formed of an oxide. A stack 208 is formed on the substrate 102. Stack 208 includes a plurality of sacrificial layers 210 and a plurality of insulating layers 216 that are alternately stacked. The sacrificial layer 210 may be formed of tantalum nitride (SiN). The insulating layer 216 may be formed of an oxide. In some embodiments, as shown in FIGS. 2A-2B, the stack 208 further includes a hard mask layer 218 formed on the sacrificial layer 210 and the insulating layer 216 for compensating for film stress and avoiding stack collapse or bending.

As shown in Figures 3A-3B, a plurality of active structures 120 are formed through stack 208. The active structure 120 includes a first active structure 120a and a second active structure 120b respectively disposed in the dummy area Aa and the array area Ab. More specifically, in some embodiments, a plurality of holes can be formed through the stack 208. A plurality of memory layers 124 can be formed correspondingly on the sidewalls of the holes. The memory layer 124 may have a multilayer structure such as ONO (Oxide/Nitride/Oxide) or ONONO (Oxide/Nitride/Oxide/Nitride/Oxide) or the like. A plurality of channel layers 122 may be formed on the memory layer 124 correspondingly. A channel layer 122 can also be formed on the bottom of the hole. Channel layer 122 may be formed of polysilicon. An insulating material 126 can be filled into the hole In the remaining space. In some embodiments, a plurality of conductive pads 128 are formed on the insulating material 126 in the holes. The conductive pads 128 are respectively coupled to the corresponding active structures 120, particularly the channel layers 122 of the active structures 120. An interlevel dielectric layer 232 can then be formed over the stack 208 and the active structure 120.

In this way, the "starting structure" is formed. The starting structure includes a substrate 102 and a preliminary array structure formed on the substrate 102, wherein the preliminary array structure includes a plurality of sub-fiction structures 140a and a plurality of sub-array structures 140b to be separated in a subsequent step. The preliminary array structure includes a stack 208 and a plurality of active structures 120 that pass through the stack 208. Each active structure 120 includes a channel layer 122 and a memory layer 124 formed between the channel layer 122 and the stack 208. In some embodiments, the preliminary array structure further includes a plurality of conductive pads 128 coupled to the active structures 120, respectively. In some embodiments, the preliminary array structure further includes an interlevel dielectric layer 232 formed on the stack 208.

As shown in FIGS. 4A-4B, a photoresist layer 242 is formed on the interlayer dielectric layer 232. Photoresist layer 242 includes openings for defining a first predetermined trench location 251 and a second predetermined trench location 252. The first predetermined trench location 251 corresponds to the first trench 171, and the first trench 171 is configured to separate the preliminary array structure on the dummy region Aa into a plurality of sub-fiction structures 140a. The second predetermined trench location 252 corresponds to the second trench 172, and the second trench 172 is configured to separate the preliminary array structure on the array region Ab into a plurality of sub-array structures 140b.

As shown in FIGS. 5A-5C, for example, by the etching process, a plurality of numbers are formed at the first predetermined trench position 251 and the second predetermined trench position 252, respectively. An opening 271 and a plurality of second openings 272. The first opening 271 and the second opening 272 expose the buried layer 104. Next, the photoresist layer 242 is removed.

As shown in FIGS. 6A-6C, the sacrificial layer 210 is removed through the first opening 271 and the second opening 272, for example, by an etching process using hot phosphoric acid (H ₃ PO ₄ ).

As shown in FIGS. 7A-7C, a plurality of high-k dielectric layers 212 are formed on the upper and lower sides of the insulating layer 216, in the first opening 271 and the second opening 272, and on the top of the interlayer dielectric layer 232. . For example, a high-k dielectric material can be formed in a conformal manner on the structures of FIGS. 6A to 6C, as shown in FIGS. 7A to 7C. The high dielectric constant dielectric material may be aluminum oxide (Al ₂ O ₃ ) or the like.

As shown in FIGS. 8A-8C, a conductive material is filled into the remaining portion of the space created by the removal of the sacrificial layer 210. The conductive material may be tungsten (W). As a result, the stack 108 as shown in Figs. 1A to 1C is formed. In addition, the unwanted portions of the high dielectric constant dielectric material are removed. That is, a portion of the high-k dielectric material that is positioned in the first opening 271 and on top of the interlayer dielectric layer 232 is removed. Next, a plurality of insulating liners 1822 are correspondingly formed in the second opening 272 using an insulating material. For example, the insulating material can be an oxide material.

As shown in FIGS. 9A to 9C, a conductive material is filled into the first opening 271 and the second opening 272. As a result, a conductive central portion 1821 is formed which is isolated by the insulating liner 1822 and the conductive layer 110. The conductive material may be tungsten (W). Thus, a first conductive structure 181 including a high-k dielectric layer 1812 and a conductive fill portion 1811, respectively, is formed in the first predetermined trench location 251. respectively A second conductive structure 182 including an insulating liner 1822 and a conductive central portion 1821 is formed in the second predetermined trench location 252. As such, each of the first conductive structures 181 extends along a first direction (eg, the X direction in the drawing), and each of the second conductive structures 182 extends along a second direction (eg, the Y direction in the drawing).

Thereafter, other processes typically used to fabricate semiconductor structures, such as the back end (BEOL) process, can be performed. For example, in the BEOL process, the word lines are defined using the conductive layer 110 disposed on the array area Ab, the bit lines are defined using the conductive pads 128 disposed on the array area Ab, and the common source lines are defined using the conductive central portion 1821. The memory cell 130 is defined by the intersection between the word line and the channel layer 122. During the BEOL, a contact may be formed over the array region Ab, and no contact may be formed over the dummy region Aa.

In the above method, since the first trench is formed in the dummy region, and the extending direction of the first trench is different from the extending direction of the second trench in the array region, the stress in the stack having a high aspect ratio can be borrowed Released by the first trench, less stress can affect the structure on the array area, thereby avoiding tilting of the stacks and preventing bending of the components. Furthermore, it is also possible to avoid the positional dislocation of the contacts formed in the BEOL process caused by the tilt of the stack. Although the foregoing examples describe the use of a 3-D vertical channel NAND memory structure and a method of using a sacrificial layer, the embodiment is not limited thereto. The concepts described herein can be applied to other manufacturing methods in which stacked semiconductor structures having a high aspect ratio are formed and semiconductor structures fabricated by these methods.

In summary, although the invention has been disclosed above by way of example, It is not intended to limit the invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

Claims (10)

A semiconductor structure includes: a substrate, wherein the substrate includes a dummy region and an array region, the array region is adjacent to the dummy region; a plurality of sub-dummy structures are disposed on the dummy region and are provided by the plurality of first trenches Separating from each other, each of the first trenches extends along a first direction; a plurality of sub-array structures are disposed on the array region and separated from each other by a plurality of second trenches, each of the second trenches being along a second direction extending; a plurality of memory cells comprising a three-dimensional array, wherein the memory cells comprise a plurality of memory cell groups respectively disposed in the sub-array structures; and a plurality of first conductive structures and a plurality of second conductive layers The structures are respectively disposed in the first trenches and the second trenches, wherein each of the first conductive structures extends along the first direction, and each of the second conductive structures extends along the second direction, the first One direction is different from the second direction. The semiconductor structure of claim 1, wherein the first direction is perpendicular to the second direction. The semiconductor structure of claim 1, further comprising: a plurality of first active structures disposed on the dummy area; and a plurality of second active structures disposed on the array area; wherein the first The active structure has a first density in the dummy region, the second active structures have a second density in the array region, and the first density is less than the second density. The semiconductor structure of claim 1, wherein each of the first conductive structures comprises a conductive filling portion and a high-k dielectric layer, the high-k dielectric layer surrounding the conductive filling portion. The semiconductor structure of claim 1, wherein each of the second conductive structures comprises a conductive central portion and an insulating layer surrounding the conductive central portion. The semiconductor structure of claim 1, wherein each of the sub-array structures comprises: a stack comprising a plurality of electrically conductive layers and a plurality of insulating layers alternately stacked; and one or more active structures, Passing through the stack, each of the one or more active structures includes: a channel layer; and a memory layer disposed between the channel layer and the stack; wherein each of the sub-array structures is disposed The memory cells of the memory cell group are defined by intersections between the conductive layers of the stack and the one or more active structures. The semiconductor structure of claim 6, wherein each of the conductive layers comprises two high-k dielectric layers and a conductive core layer disposed therebetween. The semiconductor structure of claim 6, wherein each of the sub-array structures further comprises: One or more conductive pads are respectively coupled to the one or more active structures. A method of fabricating a semiconductor structure, comprising: providing a starting structure, wherein the starting structure comprises a substrate and a preliminary array structure formed on the substrate, the substrate comprising a dummy region and an array region, the preliminary array structure comprising a plurality of active structures stacked and passed through the stack, each of the active structures including a channel layer and a memory layer formed between the channel layer and the stack; a plurality of the preliminary array structures The first predetermined trench position forms a plurality of first trenches extending along a first direction, and the preliminary array structure located on the dummy region is separated into a plurality of secondary dummy structures; and the plurality of first dummy structures in the preliminary array structure The two predetermined trench locations form a plurality of second trenches extending along a second direction to separate the preliminary array structure on the array region into a plurality of sub-array structures; and the first trenches and the plurality of trenches Forming a plurality of first conductive structures and a plurality of second conductive structures respectively in the second trench, wherein each of the first conductive structures extends along the first direction, each of the Two conductive structure extending along the second direction, different from the first direction to the second direction. The manufacturing method of claim 9, wherein the first direction is perpendicular to the second direction.