TWI642172B - Semiconductor device and method for manufacturing the same - Google Patents

Abstract

The present invention provides a semiconductor device capable of suppressing leakage current more than before.

The semiconductor device (22) includes a first carrier retention layer (48) disposed on the lower electrode (47) and contacting the lower electrode (47) at the first interface (49), and having one of the majority carriers And a second carrier retention layer (57) disposed on the first carrier retention layer (48) to divide a second interface (58) that forms a conduction path with respect to the first carrier retention layer (48), and Have the majority of the other carrier. The first interface (49) has a contour on the inner side of the outline of the first carrier-retaining layer (48) as viewed in a direction orthogonal to the surface of the substrate, and the second interface (58) in the plan view The outline of the layer (48) is more contoured on the inner side than the first carrier layer (48).

Description

Semiconductor device and method of manufacturing same

The present invention relates to a semiconductor device and a method of fabricating the same, and to a photoelectric conversion device, an electronic device, and the like using a semiconductor device.

A semiconductor device called a PIN type photodiode is generally known. The PIN type photodiode system forms a semiconductor layer on the lower electrode. The semiconductor layer includes, for example, an n+ layer, an i layer, and a p+ layer (both amorphous ruthenium layers) which are sequentially stacked from the lower electrode side. An n+ layer is formed entirely on the lower electrode. The i layer is overlapped on the n+ layer. An upper electrode is formed on the p+ layer. The p+ layer and the upper electrode have a profile on the inner side of the outline of the semiconductor layer. If light is irradiated, an electric charge is generated. Leakage current is suppressed by narrowing the upper p+ layer during processing. It is taught that even if the interface between the upper electrode and the p+ layer is reduced, if the p+ layer spreads over the entire surface of the i layer, leakage current cannot be sufficiently suppressed.

[Previous Technical Literature] [Patent Literature]

[Patent Document 1] Japanese Patent Laid-Open Publication No. 2011-77184

In the future, we expect a higher resolution of the image. The miniaturization of the photodiode is required for high resolution. For the photodiode, it corresponds to the micro layer of the semiconductor layer The effect of leakage current increases. Explore to further suppress leakage currents.

According to at least one aspect of the present invention, a semiconductor device capable of suppressing leakage current more than before can be provided.

(1) A semiconductor device comprising: a lower electrode disposed on a substrate; a first carrier retaining layer disposed on the lower electrode and contacting the lower portion at the first interface And an electrode having a majority carrier; and a second carrier retention layer disposed on the first carrier retention layer to divide a second interface forming a conduction path with respect to the first carrier retention layer and having a second interface a plurality of carriers; the first interface has a contour on the inner side of the contour of the first carrier-retaining layer in plan view as viewed in a direction orthogonal to a surface of the substrate, and in the plan view, the first The interface 2 has an outline on the inner side of the contour of the first carrier-preserving layer.

An electric field is enhanced between the lower electrode and the second carrier-preserving layer between the first interface and the second interface. Conversely, the electric field is weakened along the end face of the first carrier retaining layer. As a result, the leakage current is suppressed along the end faces of the first carrier-holding layer.

(2) Between the first interface and the distance a between the end of the first carrier-holding layer and the distance b between the second interface and the end of the first carrier-holding layer, b> The relationship between a is established. According to the verification by the inventors of the present invention, if the above relationship is established between the distances a and b, the leakage current is surely reduced.

(3) The difference between the distance b and the distance a may be greater than 1 μm and less than 3 μm. If the difference (b-a) between the distance b and the distance a is larger than 1 μm, the leakage current is surely reduced. On the other hand, if the difference (ba) between the distance b and the distance a is 3 μm or more, the second interface is too narrow with respect to the first interface, and the substantial current path is too narrow, and the first carrier retains the layer and the second carrier. The retaining layer is not fully functional.

(4) The semiconductor device may include an insulating film covering the lower electrode on the outer side of the first interface along the outline of the first interface, and on the lower electrode Supports one of the above-mentioned first carrier retention layers. When a semiconductor device is fabricated, an insulating film is formed on the lower electrode. The insulating film covers the surface of the lower electrode at a predetermined region of the first interface, but maintains the exposure of the predetermined region of the first interface. A first carrier retention layer is formed on the lower electrode and the insulating film. The insulating film separates the first carrier-preserving layer on the lower electrode. As described above, the first interface is formed between the first carrier retention layer and the lower electrode.

(5) The film thickness of the insulating film may be 300 nm or more from the surface of the lower electrode. When the film thickness of the insulating film is set in this manner, the insulating film can surely insulate between the lower electrode and the first carrier-preserving layer. The first interface can be reliably defined.

(6) The first carrier-preserving layer may have a length of 5 μm or more and 20 μm or less along the surface of the lower electrode. The semiconductor device can have sufficient sensitivity.

(7) The second interface may be divided between the first carrier retention layer and the second carrier retention layer. The movement of the carrier is realized between the first carrier retention layer and the second carrier retention layer. The semiconductor layer can be omitted as compared with the semiconductor device of the PIN structure.

(8) The semiconductor device may include a semiconductor layer formed on the first carrier-holding layer and in contact with the second carrier-holding layer at the second interface. The semiconductor layer functions as a supply source of the carrier with respect to the first carrier retention layer and the second carrier retention layer. Thus, the semiconductor layer can improve the sensitivity of the movement of the carrier. A semiconductor device of a so-called PIN structure can be formed.

(9) The semiconductor device can be assembled by being used in a photoelectric conversion device. In this case, the photoelectric conversion device may have a semiconductor device.

(10) The semiconductor device can be assembled by being used in an electronic device. In this case, the electronic device may have a semiconductor device. The electronic device can be exemplified by, for example, a living body authentication device.

(11) Another aspect of the present invention relates to a method of manufacturing a semiconductor device comprising the steps of: forming a lower electrode on a substrate; forming a first carrier retention layer on the lower electrode, the first carrier retaining The layer is expanded outward from the outline of the first interface of the lower electrode as viewed in a direction perpendicular to the surface of the substrate. a profile having a majority of carriers; and forming a second carrier retention layer on the first carrier retention layer, the second carrier retention layer division forming a conduction path with respect to the first carrier retention layer And having a second interface having a contour on the inner side of the contour of the first carrier-preserving layer, and having the other majority carrier.

The electric field between the lower electrode and the second carrier-preserving layer of the semiconductor device manufactured as described above is enhanced between the first interface and the second interface. Conversely, the electric field is weakened along the end face of the first carrier retaining layer. As a result, the leakage current is suppressed along the end faces of the first carrier-holding layer.

(12) A method of manufacturing a semiconductor device, comprising: exposing a predetermined region of the first interface to an upper surface of the first interface, and covering the lower electrode with an insulating film; and forming the lower electrode and the insulating layer A material film on which the first carrier retention layer is formed is laminated on the film; and the material is patterned by a predetermined pattern to form the first carrier retention layer. The insulating film separates the first carrier-preserving layer on the lower electrode. As described above, the first interface is formed between the first carrier retention layer and the lower electrode.

11‧‧‧Photoelectric conversion device

12‧‧‧Light detection components

13‧‧‧Component array (component area)

14‧‧‧ scan line

15‧‧‧Information line

16‧‧‧Scan line circuit

17‧‧‧Data line circuit

21‧‧‧Thin Film Transistor (TFT)

22‧‧‧Semiconductor device (photodiode)

22a‧‧‧Semiconductor device (photodiode)

22b‧‧‧Semiconductor device (photodiode)

23‧‧‧Source electrode

24‧‧‧汲electrode

25‧‧‧Constant potential line

26‧‧‧gate electrode

27‧‧‧Retaining capacitor

28‧‧‧Constant potential line

31‧‧‧Substrate

32‧‧‧Base insulating film

33‧‧‧Semiconductor film

34‧‧‧Insulation

36‧‧‧Channel forming area

37‧‧‧Source area

38‧‧‧Bungee area

39‧‧‧gate electrode

41‧‧‧1st interlayer insulating film

42‧‧‧ conductive film pattern

42a‧‧‧Source electrode

42b‧‧‧汲electrode

43‧‧‧Contact hole

44‧‧‧Contact hole

45‧‧‧Second interlayer insulating film

47‧‧‧lower electrode

48‧‧‧1st carrier layer (lower contact layer)

48a‧‧‧1st carrier layer (lower contact layer)

49‧‧‧1st interface

51‧‧‧Semiconductor layer

51a‧‧‧Semiconductor layer

52‧‧‧Insulation film

53‧‧ ‧ step surface

54‧‧‧ step surface

55‧‧‧3rd interlayer insulating film

56‧‧‧ openings

57‧‧‧2nd carrier layer (upper contact layer)

58‧‧‧2nd interface

61‧‧‧Upper electrode

62‧‧‧Contact hole

64‧‧‧Scheduled area

65‧‧‧material film

66‧‧‧Material film

67‧‧‧Resist film

71‧‧‧1st carrier layer (p-type semiconductor layer)

72‧‧‧1st interface

73‧‧ ‧ step surface

74‧‧‧2nd carrier layer (n-type semiconductor layer)

75‧‧‧2nd interface

77‧‧‧Electronic machines (living authentication devices)

78‧‧‧Microlens array

79‧‧‧Microlens

81‧‧‧Lighting substrate

82‧‧‧Substrate body

83‧‧‧Lighting layer

84‧‧‧1st electrode layer

85‧‧‧2nd electrode layer

86‧‧‧Lighting substrate

87‧‧‧Substrate body

88‧‧‧Lighting layer

89‧‧‧ openings

91‧‧‧Control Department

92‧‧‧Memory Department

93‧‧‧Output Department

A‧‧‧distance

B‧‧‧distance

C‧‧‧ film thickness

FG‧‧ fingers

Fig. 1 is a wiring diagram schematically showing an electrical configuration of a photoelectric conversion device according to an embodiment.

Fig. 2 is an equivalent circuit diagram of the photodetecting element.

Fig. 3 is a vertical sectional view schematically showing the structure of a photodetecting element of the first embodiment.

Fig. 4 is an enlarged vertical sectional view schematically showing the configuration of a photodiode.

Fig. 5 is a graph showing the relationship between the element diameter and the dark current.

Fig. 6 is a graph showing the spectral sensitivity characteristics.

Fig. 7 is a graph showing the relationship between the distance a between the first interface and the end faces of the lower contact layer and the dark current.

Figure 8 is a graph showing the relationship between the difference between the distance a and the distance b (b-a) and the dark current. table.

Fig. 9 is a graph showing the effect of reducing the first interface.

Fig. 10 is a graph showing the relationship between the film thickness and the dark current of the insulating film on the lower electrode.

Fig. 11 is a view schematically showing a method of manufacturing a photoelectric conversion device, and is a vertical sectional view showing an electrode formed on a lower portion of a substrate.

FIG. 12 is a view schematically showing a method of manufacturing a photoelectric conversion device, and is a vertical cross-sectional view schematically showing a step of forming an insulating film.

Fig. 13 is a view schematically showing a method of manufacturing a photoelectric conversion device, and is a vertical sectional view schematically showing a step of forming a lower contact layer and a semiconductor layer.

FIG. 14 is a view schematically showing a method of manufacturing a photoelectric conversion device, and is a vertical cross-sectional view schematically showing a step of forming a third interlayer insulating film.

Fig. 15 is a view schematically showing a method of manufacturing a photoelectric conversion device, and is a vertical sectional view schematically showing a step of forming an upper contact layer.

Fig. 16 is a view schematically showing a method of manufacturing a photoelectric conversion device, and is a vertical sectional view schematically showing a step of forming an upper electrode.

Fig. 17 is a vertical sectional view schematically showing the structure of a photodetecting element of a second embodiment.

Fig. 18 is a vertical sectional view schematically showing the structure of a photodetecting element of a third embodiment.

Fig. 19 is a conceptual diagram schematically showing the configuration of a living body authentication device as a specific example of an electronic device.

Hereinafter, an embodiment of the present invention will be described with reference to the accompanying drawings. Furthermore, the present embodiment described below does not unduly limit the content of the present invention described in the claims, and all the configurations described in the embodiment are not necessarily required. The solution of the invention.

(1) Composition of photoelectric conversion device

Fig. 1 is a view schematically showing an electrical configuration of a photoelectric conversion device 11 according to an embodiment of the present invention. The photoelectric conversion device 11 includes a plurality of photodetecting elements 12. The photodetecting elements 12 are arranged, for example, in an array to form an element array (element region) 13. Here, the photodetecting element 12 is arranged in accordance with a matrix pattern of a plurality of rows of a plurality of rows.

The photoelectric conversion device 11 includes a plurality of scanning lines 14 and a plurality of data lines 15. The scanning lines 14 extend in a direction parallel to each other. One scanning line 14 is assigned to one column of photodetecting elements 12. One scanning line 14 is commonly connected to one column of photodetecting elements 12. The scan lines 14 are commonly connected to the scan line circuit 16. The scan line circuit 16 sequentially ensures the conduction of the respective scan lines 14 based on the time axis. The data lines 15 extend in a direction parallel to each other. One data line 15 is assigned to one line of light detecting elements 12. One data line 15 is commonly connected to one line of light detecting elements 12. The data lines 15 are commonly connected to the data line circuit 17. The data line circuit 17 sequentially ensures the conduction of the respective data lines 15 based on the time axis. The electric power corresponding to the irradiation light is detected one by one for each of the photodetecting elements 12. Each of the photodetecting elements 12 corresponds to one pixel.

As shown in FIG. 2, each of the photodetecting elements 12 includes a thin film transistor (TFT) 21 as a switching element and a photodiode 22 as a photoelectric conversion element. The source electrode 23 of the TFT 21 is connected to the data line 15. One of the electrodes of the photodiode 22 is connected to the drain electrode 24 of the TFT 21. The other electrode of the photodiode 22 is connected to a constant potential line 25 arranged in parallel with the data line 15. A scan line 14 is connected to the gate electrode 26 of the TFT 21. When a voltage is applied from the scanning line 14 to the gate electrode 26, conduction is ensured between the source electrode 23 and the gate electrode 24. The photodiode 22 is configured as a PIN diode as follows. The photodiode 22 is a specific example of a semiconductor device that realizes photoelectric conversion.

The photodetecting element 12 is provided with a holding capacitor 27. One of the holding capacitors 27 is connected to the drain electrode 24 of the TFT 21, and the other electrode is connected to the constant potential line 28 arranged in parallel with the scanning line 14.

(2) Structure of Light Detecting Element of First Embodiment

As shown in FIG. 3, the photoelectric conversion device 11 is provided with a substrate 31. As the substrate 31, for example, a transparent glass substrate or an opaque tantalum substrate can be used. A base insulating film 32 is provided on the surface layer of the substrate 31. The base insulating film 32 covers one surface of the substrate 31. The base insulating film 32 may be formed of, for example, a hafnium oxide film (SiO ₂ ). A polysilicon semiconductor film 33 is formed on the substrate 31 on the islands of the photodetecting element 12 in an island shape. The semiconductor film 33 has a film thickness of, for example, about 50 nm. The semiconductor film 33 is covered by an insulating layer 34. The insulating layer 34 spreads over the entire surface of the base insulating film 32. The insulating layer 34 forms a gate insulating film on the semiconductor film 33. The insulating layer 34 is formed of an insulating material such as SiO ₂ . The insulating layer 34 has a film thickness of about 100 nm.

The semiconductor film 33 is divided into a source region 37 and a drain region 38 by the channel formation region 36. A gate electrode 39 is formed on the insulating layer 34 at a position opposite to the channel formation region 36. The gate electrode 39 is formed of a metal material such as molybdenum (Mo). The gate electrode 39 has a film thickness of about 500 nm. The first interlayer insulating film 41 is laminated on the insulating layer 34. The first interlayer insulating film 41 covers the gate electrode 39. The first interlayer insulating film 41 is formed of, for example, an insulating material called a hafnium oxide film. The first interlayer insulating film 41 has a film thickness of about 800 nm.

A conductive film pattern 42 is formed on the first interlayer insulating film 41. The conductive film pattern 42 individually includes a source electrode 42a and a drain electrode 42b. The conductive film pattern 42 is formed of a metal material such as Mo. The conductive film pattern 42 has a film thickness of about 500 nm. The conductive material of the source electrode 42a fills the contact hole 43 penetrating through the first interlayer insulating film 41 and the insulating layer 34. In this manner, the source electrode 42a is connected to the source region 37 of the semiconductor film 33. Similarly, the conductive material of the drain electrode 42b fills the contact hole 44 penetrating through the first interlayer insulating film 41 and the insulating layer 34. Thus, the drain electrode 42b is connected to the drain region 38 of the semiconductor film 33. The conductive film pattern 42 includes a data line 15 connected to the source electrode 42a.

A second interlayer insulating film 45 is laminated on the first interlayer insulating film 41. The second interlayer insulating film 45 is formed of, for example, a laminate of a planarizing film and a passivation film. As the planarizing film, for example, an insulating film called an acrylic resin having a film thickness of about 3 μm can be used, and for example, an insulating material called a tantalum nitride film (Si ₃ N ₄ ) having a film thickness of about 200 nm can be used. The second interlayer insulating film 45 covers the source electrode 42a, the drain electrode 42b, and the data line 15.

The photodiode 22 is disposed on the second interlayer insulating film 45. The photodiode 22 has a lower electrode 47. The lower electrode 47 is formed on the second interlayer insulating film 45. The lower electrode 47 is formed in a predetermined pattern in a plan view (hereinafter, simply referred to as "plan view") viewed from a direction orthogonal to the surface of the second interlayer insulating film 45. The lower electrode 47 may be formed of Al (aluminum), Mo (molybdenum), and other conductive materials.

A lower contact layer (first carrier retention layer) 48 is disposed on the lower electrode 47. The lower contact layer 48 covers the surface (upper surface) of the lower electrode 47 and contacts the lower electrode 47 at the first interface 49. The lower contact layer 48 is formed of, for example, an amorphous germanium. The film thickness of the lower contact layer 48 may be 10 nm to 200 nm. Here, the lower contact layer 48 forms an n+ layer. The lower contact layer 48 has electrons as a majority carrier. However, the lower contact layer 48 may be formed by a p+ layer instead of the n+ layer. The p+ layer contains holes as a majority carrier.

A semiconductor layer (i layer) 51 is formed on the lower contact layer 48. The semiconductor layer 51 is divided into a predetermined profile in plan view. Here, the outline of the semiconductor layer 51 is imitated as a circle. The outline of the semiconductor layer 51 overlaps the outline of the lower contact layer 48. The semiconductor layer 51 is formed of, for example, microcrystalline germanium. Therefore, along the interface between the semiconductor layer 51 and the lower contact layer 48, the end faces of the semiconductor layer 51 and the lower contact layer 48 are continuous in the same plane. The film thickness of the semiconductor layer 51 may be 400 nm to 1200 nm.

The insulating film 52 is disposed on the lower electrode 47 on the outer side of the first interface 49 along the outline of the first interface 49. The insulating film 52 covers the lower electrode 47 from the periphery of the lower electrode 47 toward the inner side of the periphery. The insulating film 52 divides the space on the lower electrode 47 into the inner side of the outline of the lower electrode 47. The lower contact layer 48 is disposed in the space. In this manner, the insulating film 52 is separated from the first interface 49 on the surface of the lower electrode 47. The first interface 49 has a profile on the inside of the lower contact layer 48 in plan view. The insulating film 52 may be formed of, for example, a tantalum nitride film or a hafnium oxide film. The film thickness of the insulating film 52 may be about 300 nm to 1000 nm.

The lower contact layer 48 covers the insulating film 52 on the lower electrode 47 on the outer side of the first interface 49. Thus, a step surface 53 is formed on the lower contact layer 48. Thus, since the semiconductor layer 51 is formed with a uniform film thickness on the contact layer 48 having the step surface 53, the surface of the semiconductor layer 51 reflects the step surface 53. A step surface 54 is similarly formed on the surface of the semiconductor layer 51.

A third interlayer insulating film 55 is laminated on the second interlayer insulating film 45. The third interlayer insulating film 55 covers the lower contact layer 48 and the semiconductor layer 51. The third interlayer insulating film 55 is formed of an insulating material called, for example, a hafnium oxide film or a tantalum nitride film. The film thickness of the third interlayer insulating film 55 may be, for example, 300 nm to 1000 nm. An opening 56 is formed in the third interlayer insulating film 55 on the semiconductor layer 51. The opening 56 is recessed inside the step surface 54 to divide the space contacting the surface of the flat semiconductor layer 51.

An upper contact layer (second carrier retention layer) 57 is laminated on the third interlayer insulating film 55. The upper contact layer 57 is formed of, for example, an amorphous germanium. The film thickness of the upper contact layer 57 may be 10 nm to 200 nm. The upper contact layer 57 enters the opening 56. The upper contact layer 57 is laminated on the surface of the semiconductor layer 51 in the opening 56. In this manner, the upper contact layer 57 divides the second interface 58 between the semiconductor layer 51 and the semiconductor layer 51. Between the second interface 58 and the first interface 49, the semiconductor layer 51 and the lower contact layer 48 form a conduction path for current. The second interface 58 has a contour on the inner side of the outline of the semiconductor layer 51 and the lower contact layer 48 in plan view. Here, the upper contact layer 57 forms a p+ layer. However, in the case where the p+ layer is used for the lower contact layer 48, the n+ layer is used for the upper contact layer 57.

The upper electrode 61 is formed on the upper contact layer 57. The upper electrode 61 is formed in a predetermined pattern in plan view. The upper electrode 61 may be formed of ITO (Indium Tin Oxide) or other transparent conductive material. The film thickness of the upper electrode 61 may be, for example, about 10 nm to 200 nm. The upper electrode 61 overlaps the upper contact layer 57 in the opening 56. The third interlayer insulating film 55 and the second interlayer insulating film 45 form a contact hole 62 to the drain electrode 42b. The upper electrode 61 extends into the contact hole 62. Thus, the upper electrode 61 is connected to the drain electrode 42b.

As shown in FIG. 4, the photodiode 22 is at a distance a between the first interface 49 and the end faces of the lower contact layer 48 and the semiconductor layer 51, and ends of the second interface 58 and the lower contact layer 48 and the semiconductor layer 51. The relationship between b>a is established between the distances b of the faces. At this time, the difference (b-a) between the distance b and the distance a is larger than 1 μm and smaller than 3 μm. Moreover, the film thickness c of the insulating film 52 measured from the surface of the lower electrode 47 is 300 nm or more. The lower contact layer 48 and the semiconductor layer 51 have a length of 5 μm or more and 20 μm or less along the surface of the lower electrode 47.

The photoelectric conversion device 11 is incident on the photodiode 22 in a state where a reverse bias voltage is applied to the photodiode 22 by the constant potential lines 25 and 28. Thereby, a photocurrent flows between the contact layer 57 as the p+ layer and the pn junction of the contact layer 48 as the n+ layer, and the corresponding charge is stored in the holding capacitor 27. The TFTs 21 are selected in accordance with each of the plurality of scanning lines 14, and the data lines 15 sequentially output, to the photodetecting elements 12, signals corresponding to the charges stored in the holding capacitors 27, one by one. In this way, the intensity of the light received by the respective photodetecting elements 12 can be detected separately.

Each of the photodetecting elements 12 has a contour on the inner side of the lower contact layer 48 and the semiconductor layer 51 in a plan view, and the second interface 58 is in the lower contact layer 48 and the semiconductor layer 51 in plan view. The contour has a contour on the inside. As described above, the first interface 49 and the second interface 58 are reduced in comparison with the horizontal cross sections of the lower contact layer 48 and the semiconductor layer 51. As a result, the conduction path of the current of the lower contact layer 48 and the semiconductor layer 51 becomes narrow. An electric field is increased between the lower electrode 47 and the upper contact layer 57 between the first interface 49 and the second interface 58. Conversely, along the lower contact layer 48 and the end faces of the semiconductor layer 51, the electric field is weakened. As a result, leakage current is suppressed along the end faces of the lower contact layer 48 and the semiconductor layer 51.

As described below, according to the verification by the inventors, the distance a between the first interface 49 and the end faces of the lower contact layer 48 and the semiconductor layer 51 in the photodiode 22, and the second interface 58 and the lower contact layer 48 are When the relationship b>a is established between the distances b between the end faces of the semiconductor layers 51, the leakage current is reduced. As described above, the lower contact layer 48 and the semiconductor layer 51 cover the insulating film 52. Step surfaces 53 and 54 are formed on the lower contact layer 48 and the semiconductor layer 51. The step difference causes an uneven growth of the film formation, and such uneven growth tends to form a path of leakage current. Therefore, if the relationship of b>a is established, the upper contact layer 57 can be prevented from having a step difference.

In particular, if the difference (b-a) between the distance b and the distance a is larger than 1 μm, the leakage current is surely reduced. On the other hand, when the difference (ba) between the distance b and the distance a is 3 μm or more, the second interface 58 is excessively reduced with respect to the first interface 49, and the substantial current path is too narrow, and the lower contact layer 48 and the upper contact layer 57 are 57. Unable to fully function. Further, since the film thickness of the lower contact layer 48 is 300 nm or more on the lower electrode 47, the insulating film 52 can surely insulate between the lower electrode 47 and the lower contact layer 48. The first interface 49 can be used reliably to narrow the conduction path of the current.

The lower contact layer 48 has a length of 5 μm or more and 20 μm or less along the surface of the lower electrode 47. That is, the first interface 49 has a length of 5 μm or more and 20 μm or less. If the length of the first interface 49 exceeds 20 μm, the insulating film 52 is not interposed, and the solid film can sufficiently contribute to the suppression of leakage current by the lower contact layer 48. When the length of the first interface 49 is 5 μm or less, the photodiode 22 cannot receive light with a sufficient amount of light. The sensitivity is reduced.

The semiconductor layer 51 functions as a supply source of carriers with respect to the lower contact layer 48 and the upper contact layer 57. Thus, the semiconductor layer 51 can improve the sensitivity of the movement of the carrier. A photodiode 22 of a so-called PIN structure can be formed.

(3) Verification

The inventors have verified the relationship between the size of the photodiode 22 and the dark current (leakage current). Here, the semiconductor layer 51 is formed in a circular shape in plan view. The thickness of the semiconductor layer 51 is 700 nm. The element diameter is from 10 μm to 500 μm. A 5V reverse bias voltage is applied to the photodiode 22. The inventors simultaneously verified the comparative example. In the comparative example, the lower contact layer was formed entirely on the lower electrode 47. Therefore, the first interface 49 of the lower electrode 47 and the lower contact layer 48 is defined to coincide with the outline of the semiconductor layer 51 with respect to the outline of the semiconductor layer 51. In the comparative example, the second interface 58 of the upper contact layer 57 and the semiconductor layer 51 is smaller than the outline of the semiconductor layer 51 in the same manner as the photodiode 22 of the present embodiment. As shown in FIG. 5, it was confirmed that the photodiode 22 of the present embodiment has a darker current as compared with the comparative example in an element diameter of 5.0 μm or more and 20.0 μm or less. It was found that the photodiode 22 of the present embodiment suppresses edge leakage as compared with the comparative example. The impact of electricity. Further, when the second interface 58 is reduced, the photoelectric conversion region cannot be determined by the diameter of the semiconductor layer 51. Therefore, the element diameter is determined by the spectral sensitivity characteristic shown in FIG. In this verification, the diameter of the element is expanded by 2.8 μm with respect to the diameter of the upper contact layer. In Fig. 6, the spectral sensitivity of the photodiode after the second interface 58 is narrowed is indicated by a solid line, and the photodiode of the first interface 49 and the second interface 58 is the same as that of the semiconductor layer 51 by a broken line. Sensitivity.

Next, the inventors measured the dark current while changing the distance a between the first interface 49 of the photodiode 22 and the end faces of the lower contact layer 48 and the semiconductor layer 51. As a result, as shown in FIG. 7, it was confirmed that the dark current was suppressed when the distance a was 1.0 μm or more. Further, in the verification, the distance b between the second interface 58 and the end faces of the lower contact layer 48 and the semiconductor layer 51 was fixed to 3 μm.

Next, the inventors verified the relationship between the difference (b-a) between the distance a and the distance b in the photodiode 22 and the dark current. As a result, as shown in FIG. 8, if the difference (b-a) exceeds 1 μm, the dark current decreases. Here, the distance a is maintained at 1.0 μm or more in any of the measurements.

Next, the inventors verified the effect of reducing the first interface 49. The inventors measured the dark current by changing the distance b while maintaining the distance a at 1.5 μm. The inventors determined the dark current in the comparative example. In the comparative example, the second interface 58 overlaps the outline of the semiconductor layer 51. That is, the distance a is maintained at "0 (zero)". As a result, as shown in FIG. 9, it was confirmed that when the distance b is 2.5 μm or more, the dark current is sharply reduced as compared with the comparative example.

Next, the inventors verified the effect of the film thickness of the insulating film 52. The inventors measured the dark current while changing the film thickness of the insulating film 52. The distance a was maintained at 1.5 μm and the distance b was maintained at 3.0 μm. As a result, as shown in FIG. 10, it was confirmed that the dark current was suppressed when the thickness of the insulating film 52 was 300 nm or more.

(4) Method of manufacturing photoelectric conversion device

Next, a method of manufacturing the photoelectric conversion device 11 will be described. The respective photoelectric conversion devices 11 are embedded one by one on the base plate. The base sheet is formed of the same material as the substrate 31. base The sheet material may be, for example, a glass substrate wafer or a tantalum wafer. Each of the photoelectric conversion devices 11 is cut from the base material.

When the photoelectric conversion device 11 is embedded, the TFTs 21 are formed one by one on each of the photodetecting elements 12 on the base plate according to the conventional forming method. When the TFT 21 is formed, the first interlayer insulating film 41 and the second interlayer insulating film 45 are entirely laminated on the base material. The second interlayer insulating film 45 is formed by planarizing the surface of the first interlayer insulating film 41 with an acrylic resin having a thickness of about 3 μm, and forming a nitride film having a thickness of about 200 nm by a CVD (Chemical Vapor Deposition) method. Decor film. Thereafter, a photodiode 22 is formed on each of the photodetecting elements 12 in association with each of the TFTs 21 on the second interlayer insulating film 45.

Next, a method of forming the photodiode 22 will be described in detail. As shown in FIG. 11, the lower electrode 47 is first formed on the second interlayer insulating film 45. For example, photolithography may be used in the formation. The lower electrode 47 is patterned into a pattern determined by a uniform film thickness of the conductive film. As the conductive film, for example, an aluminum film can be used. The same conductive film may be formed by, for example, a vapor deposition method or another method.

As shown in FIG. 12, the insulating film 52 is entirely laminated on the second interlayer insulating film 45. The insulating film 52 is formed of a tantalum nitride film or a hafnium oxide film. For example, a CVD method can be used for lamination. An insulating film 52 is formed on the lower electrode 47. The insulating film 52 is patterned by the determined pattern. The predetermined region 64 of the first interface 49 is divided by the lower electrode 47 in accordance with the patterning. The predetermined region 64 is surrounded by the insulating film 52. The surface (upper surface) of the lower electrode 47 is exposed at a predetermined area 64. In this manner, the insulating film 52 is covered from the periphery of the lower electrode 47 toward the inside.

Then, the lower contact layer 48 and the semiconductor layer 51 are formed on the lower electrode 47. When the lower contact layer 48 and the semiconductor layer 51 are formed, as shown in FIG. 13, the material film 65 of the lower contact layer 48 and the material film 66 of the semiconductor layer 51 are uniformly formed on the second interlayer insulating film 45. The material film 65 is formed of n + amorphous germanium, and the material film 66 is formed of microcrystalline germanium. The material films 65 and 66 may be continuously formed by a CVD method. The material films 65 and 66 are laminated on the lower electrode 47 and the insulating film 52. The material films 65, 66 cover a predetermined area 64 of the first interface 49. Due to the material film 65, 66 Since the film thickness is formed uniformly, the surfaces of the material films 65 and 66 reflect the surface shape of the insulating film 52. The material films 65 and 66 thus form the step faces 53 and 54 one by one for each of the photoelectric conversion devices 11. A resist film 67 is formed on the material film 66. The resist film 67 mimics the shapes of the semiconductor layer 51 and the lower contact layer 48. The lower contact layer 48 and the semiconductor layer 51 are patterned by the material films 65 and 66 by the determined pattern by the photolithography technique under the action of the resist film 67. In this manner, the lower contact layer 48 and the semiconductor layer 51 are formed. The insulating film 52 is separated from the lower electrode 47 by the lower contact layer 48. As described above, the first interface 49 is formed between the lower contact layer 48 and the lower electrode 47. The lower contact layer 48 and the semiconductor layer 51 have a profile that expands outward from the first interface 49 in plan view.

As shown in FIG. 14, the third interlayer insulating film 55 is uniformly formed on the second interlayer insulating film 45. The third interlayer insulating film 55 is formed of, for example, a hafnium oxide film or a tantalum nitride film. The CVD method is used for film formation. The insulating film 52, the semiconductor layer 51, and the lower contact layer 48 are buried in the third interlayer insulating film 55. An opening 56 is formed in the third interlayer insulating film 55 on the semiconductor layer 51. Thus, the surface (top surface) of the semiconductor layer 51 is exposed inside the step surface 54.

As shown in FIG. 15, an upper contact layer 57 is formed on the third interlayer insulating film 55. The upper contact layer 57 is uniformly formed. The upper contact layer 57 is formed of P+ amorphous germanium. The upper contact layer 57 may be formed by a CVD method. In the opening 56, the upper contact layer 57 covers the exposed surface of the semiconductor layer 51. On the semiconductor layer 51, the upper contact layer 57 is separated by the third interlayer insulating film 55. Thus, the second interface 58 is formed between the semiconductor layer 51 and the upper contact layer 57. The second interface 58 has a contour on the inner side of the outline of the semiconductor layer 51 and the lower contact layer 48 in plan view.

Then, as shown in FIG. 16, the upper electrode 61 is formed on the upper contact layer 57. The upper electrode 61 may be patterned by the same conductive film. The conductive film may be an ITO film. At the time of patterning, the conductive film or the upper contact layer 57 is removed by an etching process. Before the patterning of the upper electrode 61 and the upper contact layer 57, the exposed surface of the semiconductor layer 51 is covered by the third interlayer insulating film 55 and the upper contact layer 57. The end face of the semiconductor layer 51 is protected by the third interlayer insulating film 55.

(5) Structure of Light Detecting Element of Second Embodiment

Figure 17 is a view schematically showing a photodiode of a photoelectric conversion device according to a second embodiment; 22a. The photodiode 22a is formed by laminating a lower contact layer (first carrier retention layer) 48a on the lower electrode 47. The lower contact layer 48a extends to the outer side of the outline of the lower electrode 47 in plan view. The outline of the semiconductor layer 51a overlaps the outline of the lower contact layer 48a. The lower contact layer 48a is in contact with the lower electrode 47 at the first interface 49. The first interface 49 is disposed on the inner side of the lower contact layer 48a and the semiconductor layer 51a. The other configuration is the same as that of the above-described photodiode 22. The photodiode 22a is between the distance a between the first interface 49 and the end faces of the lower contact layer 48a and the semiconductor layer 51a, and the distance b between the second interface 58 and the end faces of the lower contact layer 48a and the semiconductor layer 51a. Similarly b>a and other relationships are established. Therefore, the photodiode 22a achieves the same operational effects as the above-described photodiode 22.

(6) Structure of Light Detecting Element of Third Embodiment

Fig. 18 is a view schematically showing a photodiode 22b of the photoelectric conversion device of the third embodiment. The photodiode 22b is provided with a p-type semiconductor layer (first carrier retention layer) 71 on the lower electrode 47. Similarly to the lower contact layer 48, the p-type semiconductor layer 71 is separated by the insulating film 52 on the lower electrode 47. In this manner, the p-type semiconductor layer 71 is in contact with the lower electrode 47 at the first interface 72. The first interface 72 has a profile on the inner side of the outline of the p-type semiconductor layer 71 in plan view. The p-type semiconductor layer 71 covers the insulating film 52 on the lower electrode 47 on the outer side of the first interface 72. Thus, a step surface 73 is formed on the p-type semiconductor layer 71. The third interlayer insulating film 55 covers the p-type semiconductor layer 71. As the p-type semiconductor layer 71, for example, a chalcopyrite-based light absorbing layer can be used.

An n-type semiconductor layer (second carrier-holding layer) 74 is disposed on the third interlayer insulating film 55. The n-type semiconductor layer 74 enters the opening 56. The n-type semiconductor layer 74 is laminated on the surface of the p-type semiconductor layer 71 in the opening 56. In this manner, the n-type semiconductor layer 74 divides the second interface 75 between the p-type semiconductor layer 71 and the p-type semiconductor layer 71. A p-type semiconductor layer 71 forms a conduction path for current between the second interface 75 and the first interface 72. The second interface 75 has a profile on the inner side of the outline of the p-type semiconductor layer 71 in plan view. The other structure is the same as that of the photodiode 22. The photodiode 22b is between the distance a between the end surface of the first interface 72 and the p-type semiconductor layer 71 and the distance b between the second interface 75 and the end surface of the p-type semiconductor layer 71, and is similar to b>a and Other relationships were established. Insulating film 52 The film thickness c described above is established. Therefore, the photodiode 22b achieves the same operational effects as the above-described photodiode 22. The movement of the carrier is realized between the p-type semiconductor layer 71 and the n-type semiconductor layer 74. The semiconductor layers 51, 51a can be omitted as compared with the photodiodes 22, 22a of the PIN structure.

(7) As a living body authentication device for an electronic device

As shown in FIG. 19, the photoelectric conversion device 11 can be incorporated in the living body authentication device 77 for use. The biometric authentication device 77 includes a microlens array 78. The microlens array 78 is formed of, for example, a matrix-arranged microlens 79. The light-emitting substrate 81 can be directed toward the microlens array 78. The light-emitting board 81 includes a light-emitting layer 83 formed on the surface of the board body 82. The light-emitting layer 83 is formed of, for example, an organic EL (Electroluminescence) material. The light-emitting layer 83 is sandwiched between the first electrode layer 84 and the second electrode layer 85. When a voltage is applied to the light-emitting layer 83 by the first electrode layer 84 and the second electrode layer 85, the light-emitting layer 83 emits light in the plane perpendicular direction.

The light-emitting board 81 is superposed on the light-shielding board 86. The light-shielding substrate 86 includes a light shielding layer 88 formed on the back surface of the substrate body 87. The light shielding layer 88 is formed of a light shielding material such as a metal film called a chromium film or an opaque resin film. The light shielding layer 88 forms an opening 89 corresponding to the optical path of the microlens 79. The light shielding substrate 86 is superposed on the photoelectric conversion device 11. Light collected by the microlens 79 is received by each of the light detecting elements 12.

The control unit 91 is connected to the light-emitting board 81 and the photoelectric conversion device 11. The control unit 91 controls the light emission of the light-emitting layer 83 and performs signal processing on the output of the light detecting element 12. When controlling the light emission, the control unit 91 controls the supply of voltage to the first electrode layer 84 and the second electrode layer 85 of the light-emitting board 81, for example. The self-luminous layer 83 illuminates the light to the finger FG. The light system is near infrared rays and has a wavelength of, for example, 750 to 3000 nm (preferably 800 to 900 nm). When the light reaches the inside of the finger FG, it is scattered, and a part of the light is directed toward the light detecting element 12 as reflected light. Each of the photodetecting elements 12 outputs an electrical signal corresponding to the intensity of the near-infrared light. An image of light is formed corresponding to the output of the array of light detecting elements 12. Since hemoglobin in the vein absorbs near-infrared light, a darker vein image can be drawn in the image. The control unit 91 uses a microprocessor called The operation processing circuit of the MPU (Microprocessor Unit) can be used.

The control unit 91 is connected to the storage unit 92 and the output unit 93. The memory unit 92 memorizes the vein image under the management of a specific identification code. The vein image is acquired by the photoelectric conversion device 11 and registered. Vein images vary from person to person. The memory portion 92 can use, for example, a non-volatile memory called a flash memory or a hard disk drive. At the time of biometric authentication, the control unit 91 compares the captured vein image with the registered vein image. If the vein image taken matches the registered vein image, the person's certification is achieved. The output signal of the end of authentication is output from the output unit 93. If the vein image taken does not match the registered vein image, the authentication is denied. The output signal of the poor authentication is output from the output unit 93. Such a living body authentication device 77 can be utilized for user management of the room management device, cash automatic teller machine (ATM), mobile phone, and smart phone, and the like.

Further, the present embodiment has been described in detail as described above, but it will be readily understood by those skilled in the art that various changes in the novel aspects and effects of the present invention can be made without departing from the scope of the invention. Therefore, such variations are all included in the scope of the present invention. For example, at least once in the specification or the drawings, the terms described in conjunction with the broader or synonymous terms may be replaced with any of the different terms in the specification or the drawings. In addition, the configuration and operation of the photoelectric conversion device 11, the photodetecting element 12, the switching element, the photoelectric conversion element, the biometric authentication device 77, and the electronic device are not limited to those described in the embodiment, and various changes can be made.

Claims (9)

A semiconductor device comprising: a lower electrode disposed on a substrate; a first carrier holding layer disposed on the lower electrode and contacting the lower electrode to divide a first electrode between the lower electrode and the lower electrode An interface having a plurality of majority carriers of a first type; a semiconductor layer disposed on the first carrier retention layer; and a second carrier retention layer disposed on the semiconductor layer and contacting the semiconductor layer Dividing a second interface between the semiconductor layer and the semiconductor layer, and having a plurality of carriers of a second type, wherein the conduction path is between the first interface and the second interface by the semiconductor layer The first carrier retains layer division; and the first interface has a contour on the inner side of the contour of the first carrier retention layer as viewed in a direction orthogonal to a surface of the substrate on which the lower electrode is disposed. In the above plan view, the second interface has a contour on the inner side of the contour of the first carrier-holding layer; and at least a part of the first interface is covered in the plan view The second interface is one part. The semiconductor device according to claim 1, wherein a distance a between the first interface and an end portion of the first carrier-holding layer and a distance b between the second interface and the end portion of the first carrier-holding layer are The relationship between b>a is established. The semiconductor device of claim 2, wherein a difference between the distance b and the distance a is greater than 1 μm and less than 3 μm. The semiconductor device according to any one of claims 1 to 3, which is provided with an insulating film, the insulating The film system covers the lower electrode on the outer side of the first interface along the outline of the first interface, and supports one of the first carrier-holding layers on the lower electrode. The semiconductor device according to claim 4, wherein the film thickness of the insulating film is 300 nm or more from the surface of the lower electrode. The semiconductor device according to claim 1, wherein the first carrier retention layer has a length of 5 μm or more and 20 μm or less along a surface of the lower electrode. The semiconductor device according to any one of claims 1 to 3, wherein the second interface is divided between the first carrier retention layer and the second carrier retention layer. A photoelectric conversion device characterized by having the semiconductor device according to any one of claims 1 to 7. An electronic device characterized by having the semiconductor device according to any one of claims 1 to 7.