TWI642092B - Deep junction electronic device and process for manufacturing thereof - Google Patents

Abstract

The invention relates to a method for manufacturing a deep junction electronic device, comprising the steps of: b) depositing a layer (5) of a non-single-crystal semiconductor material on a planar surface (9) of a substrate (1) of a single crystal semiconductor material; c) respectively , prior to step b), incorporating a non-activated dopant element into the substrate (1), and/or during or after step b), bonding into the layer (5) to form a non-activated a doped layer (7, 27); d) exposing the outer surface (19) of the layer (5) formed in step b) to a laser thermal annealing beam (30) to melt the layer (5) To the substrate (1) and activating the dopant element combined in step c); and e) stopping the exposure of the laser beam to induce epitaxial crystallization of the molten layer (5), The substrate (1) and/or the epitaxial single crystal semiconductor material (15) are each comprised of a layer (17, 27) of activated doped single crystal semiconductor material.

Description

Deep junction electronic device and manufacturing method thereof

The present invention relates to a method of manufacturing an integrated circuit (IC) including a deep electron junction.

More specifically, the present invention relates to apparatus and methods for forming a buffer layer in a deep electronic junction device with a low thermal budget.

The deep junction device is particularly useful for fabricating vertical power devices such as IGBTs (Insulated Gate Bipolar Transistors), or Power Golden Oxide Half Field Effect Transistors (MOS, ie, MOSFETs, MOS-FETs, or MOS FETs).

Numerous documents describe devices and methods for forming deep electronic junction devices. The IC manufacturing is achieved by first completing the previous processing steps and then following the subsequent processing steps. The first stage processing is a first part of the IC fabrication, wherein the first component of the deep junction device is patterned on the front side of the semiconductor wafer, and the second portion of the back processing IC is fabricated, wherein the opposite of the deep junction device The components are formed on the back side of the wafer. when When the front-end processing is completed by the metallization step, usually, the latter processing starts.

Therefore, in order to preserve the electrical junctions and IC metallization structures formed on the front side of the substrate, the subsequent processing steps must be performed at temperatures below about 450 °C. In addition, the latter processing is preferably achieved with a low thermal budget to reduce processing costs.

Within the present invention, the thermal budget of the processing step is defined as the product of the temperature and the duration of the processing step at that temperature. For example, in an oven at temperatures in excess of 1000 ° C, the thermal budget for the processing steps of a few minutes is very high and incompatible with the subsequent processing.

Vertical power devices in particular require the formation of a deep doped buffer layer on the back side of the integrated circuit. Within the present invention, deep means a layer embedded at a distance included in a range from 500 nm to about 5 μm from the back surface of the substrate.

Known techniques for forming deep doped layers rely on the use of standard implanters, followed by thermal diffusion and activation. Standard implanters are based on the accelerator system and can be categorized in two categories below. The medium current accelerator system produces an ion beam current between 10 microamps (μA) and 2 milliamps (mA) with an energy range comprised between 3 kiloelectron volts (KeV) and hundreds of KeV. The high current accelerator system produces ion beam currents up to about 30 milliamps (mA) for energies up to 0.2 KeV to 180 KeV. The depth of planting depends on the quality of the species being planted. Thermal diffusion involves placing the substrate in an oven above 700 ° C for a few minutes or hours, which means a high thermal budget. Thermal diffusion energy is deeply implanted in the bulk of the substrate Activation of the object. However, this technique cannot be applied to form a deep doped buffer layer on the back side of the IC because thermal diffusion exposes the front side of the sample to high temperatures and because its long duration (minutes or hours) becomes high. Hot budget.

The standard technology used today to form a deep doped buffer layer on the back side of an IC substrate is performed in two separate steps: a first step, using a high energy implanter to implant dopant elements to a typical single crystal Inside the substrate of the germanium wafer; and a second step, using laser thermal annealing (LTA) to activate the implanted dopant. The method of high energy implantation followed by the LTA is usually completed during the back processing step of the integrated circuit (IC) production line after the last step of the previous stage processing. Within the present invention, high energy implant means a dopant ion cloth using an ion implanter or ion gun containing energy in the range between 200 kiloelectron volts (KeV) and millions of electron volts (MeV). plant. The depth of planting depends on the quality of the species being planted. High energy implants are necessary to directly implant dopant elements into the buried layer in the monolith.

However, high energy implants are expensive and strongly dependent on dopant elements. In addition, laser thermal annealing, which is typically performed with a low thermal budget, is limited by the activation of some dopant elements with limited and species-dependent diffusion.

Other methods rely on a dual implant scheme: high energy implantation of the first dopant element at a distance of 1 to 2 microns from the surface, followed by a second dopant at a distance of approximately 500 nm from the surface The light of the elements is implanted to form a pn junction.

Patent document DE 10 2006 053182 A1 relates to the deposition of a cap layer by a first laser annealing step by a depth of less than 500 nanometers (nm) The product, another laser annealing step, and a step of the step of stepping at a temperature higher than 750 ° C, and a method of implanting aluminum or antimony dopant in the crucible. Ong et al., "A Low Cost Method for Forming Epitaxial SiGe on a Germanium Substrate by Laser Annealing" APL, Vol. 94, No. 8, 2009, pp. 82104 to 82104.

There is a need for a relatively simple back-end method for forming deep electronic junction devices and/or vertical power devices while maintaining the front section at relatively low temperatures (less than about 450 ° C). In particular, there is a need to form a deep doped buffer layer on the back side of an integrated circuit with a low thermal budget.

It is an object of the present invention to provide a low thermal budgeting technique for forming a deep doped buffer layer on the back side of an integrated circuit.

The above object is achieved in accordance with the present invention by providing a method of manufacturing a deep junction electronic device comprising the steps of: a) providing a substrate of a single crystal semiconductor material having a planar surface; b) depositing a non-single crystal semiconductor a layer of material on the planar surface, the layer of non-single crystal semiconductor material having an outer surface; c) separately, prior to step b), bonding a non-activated dopant element into the substrate, and/or During or after step b), the non-activated dopant elements are combined into the layer of the non-single-crystal semiconductor material to form an inactive doped layer and/or a non-single-crystal semiconductor material of the single crystal semiconductor material, respectively. a non-activated doped layer; d) after the step c), exposing the region of the outer surface formed by the step b) to a laser thermal annealing beam having an energy density higher than the determined threshold value, so as to a layer of the non-single crystal semiconductor material within the volume defined by the thermal annealing beam is melted into an interface with the substrate and activating the dopant elements combined in step c); and e) stopping the laser Exposing the region of the thermally annealed beam to induce epitaxial crystallization of the layer of non-single crystal semiconductor material from the interface with the substrate, up to the outer surface, and inducing the extension between the interface and the outer surface The formation of a bulky extended single crystal semiconductor material, and wherein the substrate and/or the epitaxial single crystal semiconductor material respectively comprise a layer of activated doped single crystal semiconductor material.

Thus, the epitaxial single crystal semiconductor material and the layer doped with the single crystal semiconductor material have the same lattice and crystal orientation as the substrate of the single crystal semiconductor material.

Step b) can be carried out at a low temperature generally less than 500 ° C, and preferably less than 300 ° C, or even less than 250 ° C. Step c) can be performed by standard or low energy implantation, and in a limited implant dose, and in any case where high energy is not possible due to the shallow depth of dopant element incorporation. Therefore, step c) does not require a high energy implanter and does not require high dose implants.

In a particular embodiment described in detail in the present invention, step c) can be performed during step b), the dopants being deposited with the non-single crystalline semiconductor material at a precise chemical dose.

Step d) producing full melting of the non-single crystal layer, and the melting space The ground is limited by the area determined by the size of the laser beam and is limited by the depth to melt the non-single crystal layer into an interface with the substrate. This melting does not substantially propagate within the substrate itself and, therefore, does not affect the opposing faces of the substrate, which is the front side of the electronic device. Furthermore, step d) is temporarily limited by the duration of the laser pulse, so this step typically lasts less than one second. Furthermore, the laser beam simultaneously produces localized epitaxial crystallization and efficient dopant activation.

In summary, the formation of a deep doped layer of a single crystal semiconductor material embedded in a single crystal substrate is thus obtained with a very limited thermal budget while maintaining the front side at a low temperature. This method is simpler than the post-processing of the prior art because it does not require a high energy implanter.

Furthermore, this method enables better control of doping levels and doping profiles. It enables the formation of a doped layer with a dopant profile that cannot be achieved using prior art methods.

Thus, this method enables a deep buffer layer of doped single crystal semiconductor material to be formed with a low thermal budget.

This method can be applied to the back surface of a substrate having a patterned front side, for example, to form an IGBT or MOSFET device.

This method is applied locally to the surface area that is limited by the area of the laser beam, and can be applied to adjacent areas of the same substrate using a one-step and repeated method. Preferably, the step of illuminating the back surface with a laser beam comprises illuminating at least two selected regions of the back surface with only one laser pulse for each selected region, the two selected regions overlapping by at most 1%.

The method of the present invention provides better control of the profile of the deep doped buffer layer.

According to a particular and advantageous aspect of the invention, during this step d), the laser beam is an excimer laser beam having a laser wavelength in the absorption range of the non-single crystal semiconductor material.

According to another particular point of view, this step c) comprises a step c1) which is carried out after step a) and before step b), the step c1) comprising an energy having a energy lower than several hundred kiloelectron volts (KeV) Exposing the surface of the substrate of the ion implant beam (as defined by the capabilities of a standard implanter) to implant the non-activated dopant elements into the single crystal semiconductor substrate, and A layer of single crystal semiconductor material doped with the non-activated dopant elements and extending from the planar surface to the single crystal semiconductor substrate is formed.

According to another particular point of view, the step c) comprises a step c2) performed during the step b), the step c2) comprising the bonding of the dopant elements into the layer of the non-single-crystal semiconductor material.

According to still another particular point of view, the step c) comprises a step c3) performed after the steps a) and b), the step c3) comprising a layer of the non-single-crystal semiconductor material that is ion beam implanted Exposure to implant the non-activated dopant elements into a layer of the non-single crystalline semiconductor material and forming a layer of non-single crystalline semiconductor material doped with the non-activated dopant elements.

According to a particular embodiment, the layer of the activated doped single crystal semiconductor is doped with a first dopant type, and the layer of the activated doped epitaxial single crystal semiconductor is doped with a second dopant type .

According to a preferred embodiment, the method further comprises the further step of cleaning the surface of the substrate prior to step b) to remove any oxide layer from the surface.

According to a particular and advantageous aspect of the invention, the substrate is made of crystalline germanium and/or the non-single crystal layer is made of amorphous or polycrystalline germanium, and/or the semiconductor material is selected among the germanium and germanium. .

According to another particular and advantageous aspect of the invention, this step c) in combination with the non-activated dopant element is completed in order to combine dopant elements along a gradient profile in a direction transverse to the planar surface of the substrate .

According to an embodiment, the epitaxial crystalline semiconductor layer is n-doped, and the crystalline semiconductor substrate is p-doped at the interface with the epitaxial crystalline semiconductor layer.

According to another embodiment, the epitaxial crystalline semiconductor layer is p-doped, and the crystalline semiconductor substrate is n-doped at the interface with the epitaxial crystalline semiconductor layer.

According to a preferred embodiment, the layer of epitaxial single crystal semiconductor material has a thickness comprised between 500 nm and 3 microns.

According to another particular and advantageous aspect of the invention, step d) comprises exposing the layer of non-single-crystal semiconductor material to an excimer laser beam having a refractive index of from 0.1 to 10 joules per square centimeter Energy density in the range and laser wavelengths below 600 nm.

Preferably, the steps d) and e) are carried out in a gas atmosphere and at a controlled pressure and temperature, the gas atmosphere being selected among inert gases, air, or vacuum.

Alternatively, the method further comprises the step of measuring a beam reflected on the outer surface of the layer of non-single crystal semiconductor material to control the total melting of the layer of non-single-crystal semiconductor material during step d), and Epitaxial crystallization of the layer during this step e).

It is a further object of the present invention to use the method of the present invention for forming a vertical transistor device selected among an insulated gate bipolar transistor or a power MOS field effect transistor.

It is a further object of the present invention to provide a deep junction electronic device comprising a single crystal semiconductor substrate comprising a layer having an outer surface and an epitaxial single crystal semiconductor material interfacing with the single crystal semiconductor substrate, and wherein the single crystal semiconductor The substrate and/or the layer of the epitaxial single crystal semiconductor material respectively comprise a layer of activated doped single crystal semiconductor material, wherein the interface is located at a depth comprised between 1 and 5 microns from the outer surface, and wherein The doped profile of the layer of activated doped single crystal semiconductor material is a non-Gaussian profile. As an example, the thickness of the single crystal layer doped with the semiconductor material is comprised between hundreds of nanometers and 2 microns. Preferably, the single crystal layer doped with a semiconductor material has a selected doped level profile selected from the group consisting of a stepped profile, a triangular profile, a gradient profile, and a Gaussian profile.

The invention also relates to the features disclosed in the following description, and which will be considered separately or in accordance with any possible combination of techniques.

1‧‧‧ single crystal substrate

2‧‧‧buried layer

3, 6, 8, 11‧‧ interface

4‧‧‧Doped layer

5‧‧‧Non-single crystal semiconductor layer

7‧‧‧Internal doping layer

9‧‧‧ planar surface

10‧‧‧High energy implant beam

15‧‧‧ Epitaxial single crystal semiconductor layer

17, 27, 37‧‧‧ embedded doped semiconductor epitaxial single crystal layer

19‧‧‧External surface

20‧‧‧Laser beam

30‧‧‧Laser thermal annealing beam

40‧‧‧Ion Beam

This description is for non-limiting illustrative purposes only, and when reference is made to the accompanying drawings It will be better understood, wherein: Figure 1 depicts a cross-sectional view of a single crystal semiconductor substrate in accordance with the prior art; and Figure 2 depicts the steps of implanting a dopant element into a semiconductor substrate in accordance with prior art high energy. Figure 3 depicts the steps of laser thermal annealing in accordance with the prior art; and Figure 4 depicts, in cross section, the deep doped buffer layer in the wafer wafer due to the processing steps depicted in Figures 1 through 3; Figure 5 is a cross-sectional view depicting a combination of process step b) or steps b) and c) of a first embodiment for depositing a non-single crystalline semiconductor layer on a crystalline substrate; Figure 6 depicts a basis for energy by standard or low Step c) of a variation of the first embodiment in which the dopant element is incorporated into the non-single-crystal semiconductor layer; FIG. 7 depicts a step d) of the laser thermal annealing according to the first embodiment of the present invention; 8 is a cross-sectional view depicting a layer of a monolithic doped semiconductor on the back side of a single crystal substrate resulting from the processing steps depicted on pages 5 and 7, or 5, 6, and 7; Figure 9 depicts standard or low energy in accordance with another particular embodiment of the present invention Step c) of implanting dopant elements into the semiconductor substrate; FIG. 10 is a cross-sectional view of another step b) of depositing a non-single-crystal semiconductor layer on the substrate after step c) depicted on FIG. Figure 11 depicts the laser after step c) depicted on Figure 10. Thermal annealing step d); and FIG. 12 depicts, in cross section, a deep buffer layer on the back side of the crystal substrate resulting from the processing steps depicted in Figures 9 through 11;

deal with

1 to 3 schematically depict a method for forming a deep doped buffer layer in a crystal substrate 1 of, for example, a single crystal germanium wafer according to the prior art.

The single crystal substrate 1 is used to form a power electronic device having a vertical electron junction, wherein the transistor has, for example, two contact regions of the gate and the emitter on the front side of the substrate, and, for example, on the back surface of the substrate At least one other junction of the collector. Vertical power devices require the formation of different doped layers on the front surface of the substrate 1 and on the back side.

The substrate 1 is typically made of a single crystal semiconductor material, preferably crystalline germanium (c-Si) or germanium (c-Ge). The substrate 1 has a flat surface 9 having, for example, a crystal orientation determined by (111) or (100). For example, the flat surface 9 represents the back surface of a patterned wafer having IC features on opposite sides.

FIGS. 1 to 3 depict a conventional method for forming a deep doped buffer layer on the surface 9 of the crystal substrate 1. Today, this prior art technique includes a first step of high energy implantation (Fig. 2) and a second step (Fig. 3) for laser annealing to activate dopants with a low thermal budget.

In Fig. 2, the high energy implantation step comprises exposing the back surface 9 of the crystal substrate 1 to the high energy implant beam 10 for implanting dopant elements. Ions are implanted into the substrate. For example, in the single crystal germanium substrate 1, the high energy implant system uses dopant elements selected to be implanted among boron, phosphorus, arsenic, aluminum, gallium, indium, antimony, bismuth, and antimony depending on the application. . The doped layer 2 is embedded and extends at a distance of about 2 to 5 microns from the back surface 9. The buried layer 2 thus formed comprises an inactive dopant element and has a thickness d2 comprised between 2 and 5 microns substantially in a Gaussian doped profile. However, high energy implants are expensive and strongly dependent on dopant elements. For example, implants of phosphorus atoms are used to form an n-doped buffer layer. High energy implantation of phosphorus ions means implanting phosphorus ions having an energy in the range between 500 kiloelectron volts (KeV) and millions of electron volts (MeV). The Gaussian profile (sigma and peak) depends on the characteristics of the ion beam implanter. Controlling the angle of incidence of the ion beam enables adjustment of the peak position of the Gaussian doping profile to be performed over a relatively limited range. Moreover, the implanted ions are not activated.

In Figure 3, the second step involves activating the implanted dopant elements. Figure 3 depicts, for example, the step of thermal annealing using a laser. The laser beam 20 is directed toward the back surface 9 of the substrate 1. The laser beam 20 has a determined power density to activate the implanted dopant elements in the buried layer 2 to form a single crystal layer 4 of doped semiconductor material. For example, the laser beam 20 is a quasi-molecular laser beam having a wavelength in the visible or ultraviolet (UV) range, preferably between 250 nanometers (nm) and 355 nanometers (nm), and In the second to sub-microsecond range, typically between 50 nanoseconds (ns) and 200 nanoseconds (ns), and preferably between 130 nanoseconds (ns) and 180 nanoseconds (ns) . The laser pulse exhibits a geometric cross-section of greater than 25 square millimeters (mm ² ), preferably greater than 200 square millimeters (mm ² ). The excimer laser beam produces a shallow heating that is limited to a depth of about 10 nanometers from the UV laser beam to a depth of about 1 micrometer of the visible laser beam. These operating conditions avoid thermal diffusion within the substrate. In any event, the excimer laser beam does not pass through the crystal substrate until the front side is melted in order to prevent deterioration of the front layer. Depending on the dopant element, the laser beam 20 can induce a limited diffusion of dopant elements up to the interface 3 of the substrate 1. Specifically, the light system is absorbed in the first layer according to the laser wavelength, and the exposed material is almost independent of the dopants. The depth of fusion that truly controls the penetration of the annealing bath is the laser energy density applied. Therefore, the dopants should also be within the melting depth or adjacent to the melting zone so as to be activated.

Figure 4 depicts a cross-sectional view of substrate 1 comprising a single crystal layer 4 of doped semiconductor material obtained as a result of the high energy implantation and laser thermal annealing steps depicted on Figures 2 and 3. The single crystal layer 4 doped with a semiconductor material has a thickness comprised in the range of several hundred nanometers to 5 micrometers. The interface 3 between the doped layer 4 and the substrate 1 is at a distance of about 1 to 5 μm from the back surface 9 of the substrate 1.

However, high energy implants are expensive and strongly dependent on dopant elements. In addition, low thermal budget annealing can only activate the dopants with limited and species dependent diffusion.

This method is typically completed in the production line of the integrated circuit (IC) during the post-processing steps. This method is after the last step of the previous paragraph carry out. The post-processing steps are thus performed with a low thermal budget to preserve the IC structure that has been formed on the front side of the substrate.

Nevertheless, deep doped buffer layers cannot be formed on the back side by using standard implanters and subsequent thermal diffusion because thermal diffusion implies a high thermal budget (700 ° C for a few minutes up to several hours duration) Above temperature), and exceeds the thermal budget limit for the post-processing. Within the present invention, standard energy implantation means implanting dopant elements in an energy range comprised between hundreds of electron volts (eV) and hundreds of electron volts (KeV).

The present invention proposes an alternative method for forming a deep doped buried layer with a low thermal budget.

First embodiment

Figures 5 through 7 depict a method for forming a doped buried layer in accordance with a first embodiment, and Figure 8 depicts the resulting structure.

Prior to the steps depicted on Figures 5 through 7, a single crystal semiconductor substrate 1 having a planar surface 9 (as depicted on Figure 1) is provided. The single crystal semiconductor substrate 1 is, for example, a crystal germanium (c-Si) substrate or a crystal germanium (c-Ge) substrate. The planar surface 9 is obtained, for example, by chemical mechanical milling or any other known technique. The planar surface 9 has, for example, a crystal orientation determined by (111) or (100).

Figure 5 depicts the step of depositing a layer 5 of non-single crystalline semiconductor material on the planar surface 9 of the single crystal semiconductor substrate 1. The semiconductor materials of layer 5 and substrate 1 have the same crystal lattice. Preferably, layer 5 and substrate 1 are made of the same semiconductor material, for example, tantalum or niobium. For example, non-single crystal semiconductor materials Layer 5 is made of amorphous germanium or polycrystalline germanium. The deposition step of layer 5 can be performed using known methods of thin film deposition such as sputtering, chemical vapor deposition (CVD), or plasma assisted chemical vapor deposition (PECVD).

The layer 5 of the non-single-crystal semiconductor material has a thickness d5 in the range of several hundred nanometers to several micrometers (the upper limit of 3 micrometers (μm)). Layer 5 has an outer surface 19. The surface 9 of the substrate 1 now forms an interface with the layer 5 of the non-single crystal semiconductor material.

Figure 6 depicts an alternative or option step of doping with a standard energy ion implant beam 40. In the case where layer 5 is doped during deposition, the steps of ion implantation are optional. The step of ion implantation comprises directing the ion implantation beam 40 on the outer surface 19 of the non-single crystalline semiconductor layer 5. The dopant elements are implanted in the non-single-crystal semiconductor layer 5, thereby forming a layer 7 comprising non-activated dopant elements in the non-single-crystal semiconductor material and/or in the interior of the single crystal substrate 1. The non-activated doped semiconductor non-single crystal layer 7 has a thickness d7 comprised between several hundred nanometers and several micrometers. Within the doped semiconductor non-single crystal layer 7, the dopant concentration profile may be approximately constant, or may specifically follow a gradient profile depending on the dopant species and depending on the ion implantation energy.

It should be noted that the dopant elements incorporated in the non-single-crystal semiconductor layer 5 after the ion implantation step are inactivated.

Standard energy implants can reduce cost over high energy implants, are compatible with many dopant elements, and provide stability with dopant species species.

After the combination of the dopant elements, Figure 7 depicts the application to The step of laser thermal annealing of layer 5 of a non-single crystal semiconductor material. More precisely, the laser beam 30 is directed towards the outer surface 19 of the non-single-crystal semiconductor layer 5, which layer is uniformly doped or comprises an inner doped layer 7.

The laser beam 30 is, for example, a pulsed excimer laser beam having a selected wavelength, pulse duration, and energy for absorption by the non-single crystal semiconductor layer 5. The laser beam 30 has an energy density above a determined threshold to produce full melting of the non-single crystal layer 5 over a depth d6 extending from the outer surface 19 to the interface 6 in the single crystal substrate 1. At the same time, the laser beam 30 induces activation of the dopant elements present in the doped layer 5 and/or implanted in the doped non-single crystal layer 7. In any event, the laser beam 30 does not induce substantial deep melting of the single crystal substrate 1, thereby preserving the opposite side of the substrate. In addition, the laser thermal annealing beam produces melting and dopant activation over a region that is spatially constrained by the size of the laser beam. As an example, a single laser pulse 30 having a wavelength of less than 1050 nanometers (nm) induces localized heating at a temperature higher than the melting point of 1414 °C. Thus, the laser pulse is suitable for melting a layer 5 of amorphous germanium or polycrystalline silicon up to a thickness of a few microns, for example up to 5 microns. The laser pulse has an energy density that can be adjusted according to the thickness of the layer 5 such that the melting occurs at or slightly below the interface with the single crystal substrate without substantially extending into the single crystal substrate.

The laser thermal annealing step d) is stopped when the non-single-crystal semiconductor layer 5 is completely melted to the interface 9 with the single crystal substrate 1. The depth of the laser thermal anneal can be controlled by measuring the dopant profile since laser thermal annealing is also used as dopant activation. In depth, the dopant element is in a piece of coffin that has not been illuminated yet The material remains non-activated. A reflectometer can be used to control the physical state (solid or liquid) of the epitaxial layer.

The laser thermal annealing step is performed with a limited thermal budget because the laser pulses are limited in duration and because the depth of fusion is limited by the thickness of the non-single crystal layer 5 and also by laser The size of the beam 30 is laterally limited.

After the laser thermal annealing step is stopped, the molten semiconductor layer cools down immediately, and more specifically, in less than several hundred nanoseconds up to less than one second. The decrease in temperature occurs by natural convection with the surrounding atmosphere and/or by conduction to the substrate. Preferably, the substrate is disposed on a sampling station that includes a system that is capable of controlling the temperature of the substrate and the temperature in contact with the wafer. Once the temperature of the molten layer drops below the solidus of the semiconductor material, the layer solidifies by crystallization. Crystallization originates from a single crystal substrate. The flat surface 9 of the single crystal substrate 1 serves as a seed crystal for epitaxial crystallization. More specifically, the non-single crystal layer 5 is crystallized into the epitaxial single crystal semiconductor layer 15. Furthermore, the extended single crystal semiconductor layer 15 is doped with an activated dopant and/or comprises a buried doped layer 17 having an activated dopant.

The step b) of depositing the non-single-crystal semiconductor layer is achieved in the deposition chamber depending on the deposition technique used. When step c) of dopant bonding is achieved during step b) of the deposition, this step c) is also achieved in the deposition chamber. The step d) of the laser thermal annealing and the step e) of the epitaxial crystallization are usually carried out in another reaction chamber or in air. Preferably, the processing steps d) and e) are carried out at controlled temperatures and pressures, for example, in the case of low pressure and/or in an atmosphere containing an inert gas.

The first embodiment of the method for forming a deep doped layer in a single crystal substrate avoids the use of a high energy implanter and, thus, avoids the generation of impact defects such as end defects in the range.

In addition, laser thermal annealing enables full doping activation. Thus, this method provides better contour control of the vertical device structure.

According to a variant of the first embodiment, the bonding of the dopant elements in the layer 5 of the non-single-crystal semiconductor material is completed during the deposition step (as depicted on Figure 5). For example, layer 5 is doped during the sputtering, CVD, or PECVD deposition step using a mixture of precursor gases. The advantage of doping during the deposition of layer 5 is that the doping profile inside layer 5 can be controlled. Furthermore, this variant of the first embodiment avoids the use of ion implanters, even standard or low energy, for implanting dopant elements, thereby reducing manufacturing costs. In an example, the doping of layer 5 is uniform over the overall thickness d5 of this layer 5, thus forming an n-doped or p-doped layer 5 of non-single crystal semiconductor material. In another example, the dopant species concentration varies during the deposition step, thereby creating a gradient of dopant concentration within the layer 5 in a direction perpendicular to the planar surface 9 of the substrate 1. As a result of the example, after the deposition step, layer 5 comprises a layer of undoped non-single crystalline semiconductor material and another inner layer 7 of doped non-single crystalline semiconductor material. After the deposition of the layer 5 of the non-single-crystal semiconductor material is completed, the layer 5 has a thickness d5 comprised in the range between several hundred nanometers and about 5 micrometers. Then, the process is continued with the step of laser thermal annealing (Fig. 7). The laser beam 30 is directed towards the outer surface 19 of the layer 5 of non-single crystal semiconductor, which layer is uniformly doped or comprises an inner doped layer 7.

Similarly, as described with respect to Figure 7, the laser beam 30 is selected to have wavelength, pulse duration, and energy for absorption by the non-single crystalline semiconductor layer 5. For example, the laser beam 30 is a pulsed excimer laser beam. The laser beam 30 is totally melted from the outer surface 19 to a depth d6 of the interface 6 with the single crystal substrate 1, resulting in complete melting of the non-single crystal layer 5. At the same time, the laser beam 30 induces activation of the dopant elements present in the doped layer 5 and/or internally doped in the non-single crystal layer 7. In general, the laser beam 30 does not induce substantial deep melting of the single crystal substrate 1. In addition, the laser thermal annealing beam produces melting and dopant activation on regions that are spatially confined laterally and in depth by laser beam characteristics such as size and energy density. After the single laser pulse irradiation, the non-single-crystal semiconductor layer 5 is completely melted to the interface 9 with the single crystal substrate 1. After the laser thermal annealing step is stopped, the molten semiconductor layer is cooled and solidified by crystallization. The single crystal substrate 1 is used as a seed crystal for epitaxial crystallization. More specifically, the non-single crystal layer 5 is crystallized into the epitaxial single crystal semiconductor layer 15. Further, the extended single crystal semiconductor layer 15 is doped with an activated dopant or an internal doped layer 17 having an activated dopant.

As depicted on Fig. 8, the vertical structure thus obtained comprises a single crystal semiconductor substrate 1 and a doped epitaxial single crystal semiconductor layer 15. Alternatively, the stack comprises an undoped epitaxial single crystal semiconductor layer 15 comprising a buried doped semiconductor epitaxial single crystal layer 17. The epitaxial single crystal semiconductor layer 15 has an interface with the single crystal semiconductor substrate 1. The layers 15, 17 of the doped epitaxial single crystal semiconductor material have the same lattice and crystal orientation as the substrate 1.

This structure has excellent conductivity properties.

On the front side of the substrate, other doped regions may have been formed during the front side processing steps, thereby enabling junction devices having excellent electronic properties such as low junction leakage.

As an alternative, laser annealing can induce deeper melting into the single crystal substrate, for example, from a few tens of nanometers to a depth of 3 micrometers (μm). This can be used to diffuse existing dopants in non-single crystals into the molten layer of the single crystal substrate.

Second embodiment

Figures 9 through 11 depict a method for forming a doped buried layer in accordance with a second embodiment, and Figure 12 depicts the resulting structure.

Prior to the steps depicted on Figures 9 through 11, a single crystal semiconductor substrate 1 having a planar surface 9 (as depicted on Figure 1) is provided.

In Fig. 9, a standard energy implanter is used to implant dopant ions in the single crystal substrate 1. As is known in the art, phosphorus ion implants are used to create n-type doping in the crucible, or boron ion implants are used to create p-type doping in the crucible. The ion implant beam 40 is directed onto the back surface 9 of the substrate 1. Preferably, the surface 9 is flat and ground. The dopant species are implanted in the single crystal substrate 1 to form a layer 27 of a single crystal semiconductor material comprising non-activated dopant elements. Layer 27 has a thickness d7 comprised between a few hundred nanometers (i.e., 500 nm) and a few microns (i.e., 3 μm). In other words, the layer 27 extends from the back surface 9 to a depth comprised between a few hundred nanometers (i.e., 500 nm) and a few microns (i.e., 3 μm). here Within the layer 27, the non-activated dopant concentration profile may be approximately constant, or may follow a gradient curve from the back surface 9 up to the depth d7, depending on the dopant species and depending on the ion implantation energy.

Figure 10 depicts a deposition step applied over surface 9 after the step of standard energy implantation depicted on Figure 9. A layer 5 of a non-single crystal semiconductor material is deposited on the flat surface 9 of the single crystal substrate 1. The semiconductor materials of layer 5 and substrate 1 have the same crystal lattice and are preferably made of the same semiconductor material. For example, the single crystal substrate 1 is made of crystalline germanium, and the non-single crystal layer 5 is made of amorphous or polycrystalline germanium. The non-single crystal layer 5 is deposited at a low temperature, preferably at a temperature lower than 500 ° C, by, for example, sputtering, chemical vapor deposition, or plasma-assisted chemical vapor deposition. The non-single crystal layer 5 is typically intrinsic or undoped. Alternatively, the non-single crystal layer 5 may be doped with the same or another dopant element, and/or another, as compared to the layer 27 of a single crystal semiconductor having a non-activated dopant element. Doping element concentration (see the third embodiment below).

The obtained stack comprises a single crystal substrate 1 comprising a layer 27 of a single crystal semiconductor having a non-activated dopant element and a layer 5 of a non-single crystal semiconductor. The non-single crystal layer 5 has a thickness d5 comprised between 1 micrometer and 3 micrometers. The surface of the single crystal substrate 1 is formed with the interface 11 of the non-single crystal layer 5. The non-single crystal layer 5 has an outer surface 19 that is substantially parallel to the interface 11 with the substrate 1.

Figure 11 depicts laser illumination applied to the back side of substrate 1 after the deposition step depicted on Figure 10. The laser beam 30 is directed onto the outer surface 19 of the non-single crystal layer 5. Preferably, the laser beam 30 is a single pulsed excimer laser beam having a selected wavelength and pulse duration The energy and the energy are absorbed by the non-single-crystal semiconductor layer 5. The laser beam 30 has an energy density above the determined threshold to produce a space-limited melting of the non-single crystal layer 5 from the outer surface 19 to the interface 11 with the substrate 1. At the same time, the laser beam 30 induces activation of the dopant elements implanted in the single crystal layer 27 at a depth d8 of the interface 8 in the single crystal substrate 1. The thickness d8 is comprised between a few nanometers (eg, 10 nm) and 5 micrometers (μm), and preferably between 500 nm and 5 μm. In any event, the laser beam 30 does not induce melting of the single crystal layer 27 or the single crystal substrate 1. In addition, the laser thermal annealing beam produces melting and dopant activation over a region that is spatially constrained by the size of the laser beam.

The laser thermal annealing step is interrupted when the non-single crystal semiconductor layer 5 is completely melted to the interface 11. A reflectometer can be used to control the physical state (solid or liquid) of the non-single crystal layer 5.

The laser thermal annealing step is performed with a limited thermal budget because the laser pulses are limited in duration and because the depth of fusion is limited by the thickness of the non-single crystal layer 5 and also by laser The size of the beam 30 is laterally limited.

After the laser thermal annealing step is stopped, the molten semiconductor layer is cooled and solidified by crystallization. The interface 11 has, for example, the crystal orientation defined by (111) because the underlying substrate is also monocrystalline. This interface 11 serves as a seed crystal for epitaxial crystallization. More specifically, the non-single crystal layer 5 is crystallized into the epitaxially crystallized semiconductor layer 15.

As shown in FIG. 12, the obtained stacked structure thus comprises a single crystal semiconductor substrate 1 having a first interface 8 with the single crystal semiconductor substrate 1 and The doped semiconductor single crystal layer 37, which is buried with the second interface 6 of the epitaxially crystallized semiconductor layer 15, is disposed between the epitaxially crystallized semiconductor layer 15 and the single crystal semiconductor substrate 1.

This structure has excellent conductivity properties.

Third embodiment

The third embodiment includes a combination of the first and second embodiments. In a first step of the third embodiment, similar to the description in Fig. 9, a standard energy cloth vegetation is applied to the flat surface 9 of the single crystal substrate 1 for implanting dopant elements on the substrate, and A layer 27 of a single crystal semiconductor material having a non-activated doping element of a first doping type is formed. Then, a layer 5 of non-single crystal semiconductor material is deposited on the flat surface 9 of the substrate 1. In this third embodiment, layer 5 can be intrinsic, undoped, or doped with an inactive dopant element of the same doping type or second doping type. This doping of layer 5 can be performed during deposition of layer 5, or after deposition of layer 5, using another standard energy implantation step (as depicted on Figure 6).

The laser thermal annealing beam 30 is then applied to the outer surface 19 of the layer 5 of non-single crystalline semiconductor material doped with a non-activated dopant element of the second doping type. The energy density of the laser thermal annealing beam 30 is selected to produce full melting up to the layer 5 with the interface 11 of the substrate 1. Furthermore, the laser thermal annealing beam 30 induces simultaneous activation of the dopant elements of the second doping type in layer 5, and the dopant elements of the first doping type in layer 27.

After the full melting of the layer, the laser thermal annealing beam 30 is interrupted to The epitaxial crystallization of the non-single crystal layer is induced. Thus, the obtained stacked structure includes a monolithic single crystal semiconductor substrate 1, a buried first type doped single crystal semiconductor layer 37, and a second type doped epitaxial single crystal semiconductor layer 15. The first type doped single crystal semiconductor layer 37 is disposed between the monolith substrate 1 and the second type doped epitaxial single crystal semiconductor layer 15.

The vertical electronic junction device is thus formed with a low thermal budget.

Those skilled in the art will recognize possible repetitions and/or combinations of one or several steps as disclosed herein. For example, the method may comprise the step c1) of implanting the first dopant element in the substrate; and the step d1) of laser thermal annealing of the first dopant element implanted in the substrate; Steps b) and c2) of deposition of layer 5 mixed with a second dopant element, and step d2) LTA of laser thermal annealing of a second dopant element in amorphous or polycrystalline layer 5; Step e) of epitaxial crystallization.

Device

The invention is applied to the fabrication of deep junction devices such as IGBTs, power MOS, diodes, and other microelectronic devices.

The invention enables the deep electronic junction device to be manufactured with a low thermal budget.

In a first embodiment, the device comprises a substrate 1 of a single crystalline semiconductor material and a layer 15 of doped extended single crystal semiconductor material.

In this first embodiment, the layer 15 of the doped epitaxial single crystal semiconductor material has a thickness comprised in the range of 500 nanometers (nm) to 3 micrometers (μm).

In a variation of the first embodiment, the apparatus comprises a substrate of single crystal semiconductor material, a layer 15 of undoped extended single crystal semiconductor material, and a layer 17 of doped extended single crystal semiconductor material, It is disposed between the flat surface of the substrate 1 and the layer 15. Each of the layers 15 and 17 has a thickness comprised in the range of 500 nanometers (nm) to 3 micrometers (μm).

According to an embodiment, the doped layer 15 or 17 of the epitaxial single crystal semiconductor material has a spatially uniform dopant density. According to another embodiment, the doped layer 15 or 17 of the epitaxial single crystal semiconductor material has a gradient dopant profile in a direction transverse to the planar surface of the substrate 1.

In a second embodiment, the apparatus comprises a substrate 1 of single crystal semiconductor material comprising a layer 37 of doped single crystal semiconductor material disposed beneath the flat surface of the substrate 1; and a layer 15 of epitaxial single crystal semiconductor material . Each of the layers 15 and 37 has a thickness comprised in the range of 500 nanometers (nm) to 3 micrometers (μm).

In a variation of the second embodiment, the layer 37 of the doped single crystal semiconductor material is doped with a first dopant type, and the layer 15 of the epitaxial single crystal semiconductor material is doped with a second dopant Types of.

In various examples according to the second embodiment, the doped layer 15 and/or the doped layer 37 individually have a spatially uniform dopant density, or have a gradient dopant in a direction transverse to the planar surface of the substrate 1. profile.

The invention enables the fabrication of deep doped layers embedded in a single crystal semiconductor material. Further, the present invention enables the deep electronic junction device to be manufactured with a low thermal budget.

Claims (13)

A method of manufacturing a deep junction electronic device, comprising a front processing step and a back processing step, wherein the back processing step is performed after the front processing step is completed, and wherein the back processing is while maintaining the front side at a temperature lower than 450 ° C Achieved, and wherein the subsequent processing comprises the steps of: a) providing a substrate (1) of a single crystal semiconductor material having a planar surface (9) on the back side; b) depositing a non-single crystal at a temperature below 500 ° C a layer (5) of a semiconductor material on the planar surface (9) of the substrate (1) of the single crystal germanium, the layer (5) of the non-single crystal semiconductor material having a thickness comprised between 1 micrometer and 3 micrometers, The layer (5) of the non-single-crystal semiconductor material has an outer surface (19); c) before the step b), bonding a non-activated dopant element into the substrate (1) to form a non-single semiconductor material The activated doped layer (27); d) after this step c), exposing the region of the outer surface (19) formed in step b) to have a high range from 0.1 to 10 joules per square centimeter Single laser thermal annealing beam at the energy density of the determined threshold (30), and a laser wavelength of less than 600 nm, such that the layer (5) of the non-single-crystal semiconductor material within the volume defined by the laser thermal annealing beam is melted into the interior of the substrate (1) Interfacing and activating the dopant elements combined in step c); and e) stopping exposure of the region of the laser thermal annealing beam so that Epitaxial crystallization of the layer (5) of the non-single-crystal semiconductor material is induced from the interface (6, 8) inside the substrate (1) and induced to extend over the volume between the interface and the outer surface (19) The formation of an epitaxial single crystal semiconductor material (15), wherein the substrate (1) comprises a layer (17, 27) of activated doped single crystal semiconductor material. The method of manufacturing a deep junction electronic device according to claim 1, wherein during the step d), the laser beam (30) is an excimer laser beam having absorption in the non-single crystal semiconductor material. The wavelength of the laser in the range. The method of manufacturing a deep junction electronic device according to claim 1, wherein the step c) comprises a step c1) performed after the step a) and before the step b), the step c1) comprising Exposing the surface (9) of the substrate (1) of the ion implant beam (40) to implant the non-activated dopant elements into the single crystal semiconductor substrate (1), and forming Doped with the non-activated dopant elements and extending from the planar surface (9) to the layer (27) of single crystalline semiconductor material within the single crystal semiconductor substrate (1). The method of manufacturing a deep junction electronic device according to claim 1, wherein the step c) further comprises the step c2) being performed during the step b), wherein the step c2) comprises the dopant elements The bonding into the layer (5) of the non-single crystalline semiconductor material. The method of manufacturing a deep junction electronic device according to claim 1, wherein the step c) further comprises a step c3) performed after the steps a) and b), the step c3) comprising a counter ion Exposing the layer (5) of the non-single-crystal semiconductor material of the implant beam (40) to implant the non-activated dopant elements into the layer (5) of the non-single-crystal semiconductor material, and forming A layer (7) of non-single crystal semiconductor material doped with such non-activated dopant elements. The method of manufacturing a deep junction electronic device according to claim 3-5, wherein the activated doped single crystal semiconductor layer (37) is doped with a first dopant type, and the activated doping The layer (17) of the epitaxial single crystal semiconductor is doped with a second dopant type. A method of manufacturing a deep junction electronic device according to claim 1 further comprising the further step of cleaning the surface (9) of the substrate (1) prior to step b) to remove any surface from the surface (9) Oxide layer. The method of manufacturing a deep junction electronic device according to claim 1, wherein the semiconductor material is selected from the group consisting of ruthenium and iridium. The method of manufacturing a deep junction electronic device according to claim 1, wherein the step c) of combining the non-activated dopant element is completed, The dopant element and the gradient profile are combined in a direction transverse to the planar surface (9) of the substrate (1). The method of manufacturing a deep junction electronic device according to claim 1, wherein in the step d), the laser beam is an excimer laser beam. The method of manufacturing a deep junction electronic device according to claim 1, wherein the steps d) and e) are performed in a gas atmosphere at a controlled pressure and temperature, the gas atmosphere being in an inert gas, Choose from air or vacuum. The method of manufacturing a deep junction electronic device according to claim 1, further comprising the step of measuring a light beam reflected on the outer surface of the layer (5) of the non-single crystal semiconductor material to control the step d) The complete melting of the layer (5) of the non-single crystal semiconductor material during the period and the epitaxial crystallization of the layer (15) during the step e). A deep junction electronic device comprising a single crystal semiconductor substrate (1) comprising an outer surface (19) on a back surface of the substrate (1) and an interface (6, 8) with the single crystal semiconductor substrate (1) a single layer (15) of epitaxial single crystal semiconductor material (15), and wherein the single crystal semiconductor substrate (1) comprises a layer (17, 27) of activated doped single crystal semiconductor material, wherein the interface (6, 8) Is located at a depth between 1 and 5 microns from the outer surface of the back surface of the substrate (1), and wherein the The doped profile of the layer (17, 27) of the doped single crystal semiconductor material is a non-Gaussian profile.