TWI641223B - Pseudo random bit sequence generation method and device, and integrated circuit generation system for generating pseudo random bit sequence generation device - Google Patents

Abstract

A pseudo random bit sequence generation method executed by an integrated circuit generation system includes: obtaining a segment value according to a total number of bits of the pseudo random bit sequence; and dividing the K bits into N according to the segment value Each of the bit portions having an unknown number of bits; generating N clock signals according to a clock signal input and the first to N-1th unknown bit numbers; according to the N unknown bit numbers and each time The pulse signal output determines a function associated with calculating a total number of flips of bit flip between adjacent pseudo-random bit sequences; calculating, based on the function, the number of each unknown bit when the total number of flips has a minimum value a value; and generating a pseudo-random bit sequence based on the total number of bits, the segment value, the value of each unknown bit number, and the N clock signal outputs.

Description

Pseudo random bit sequence generation method and device, and integrated circuit generation system for generating pseudo random bit sequence generation device

The invention relates to a bit sequence generation method and device and an integrated circuit generation system for generating a bit sequence generation device, in particular to a pseudo random bit sequence generation method and device and for generating pseudo random bit sequence generation. The integrated circuit generation system of the device.

As the size of semiconductor production continues to shrink, there are more and more failures in the process circuit. Therefore, a Pseudo Random Bit Sequence (PRBS) generating apparatus is required to generate a plurality of PRBSs (each PRBS has a plurality of bits) according to a PRBS generating method to test the function of the completed wafer. Is it normal?

However, according to the PRBS generation method, the number of inversions between any two adjacent PRBSs is large (the number of inversions is defined as: for example, the PRBS currently generated by the PRBS generating apparatus is 00111111, and the next generated PRBS Is 01000000, that is, from the current PRBS to the next generated PRBS When there are seven bits (ie, the second to the eighth bit) in the current PRBS, the flipping occurs (the bit changes from 0 to 1 or from 1 to 0), so the number of flips between adjacent PRBSs is seven. Times), resulting in a total number of inversions between all adjacent PRBSs of the PRBS. As a result, the flip rate of the internal circuit nodes of the wafer under test is also increased during the test, resulting in higher test power consumption of the wafer to be tested. Therefore, it is known that there is still room for improvement in the PRBS generation method.

Accordingly, it is an object of the present invention to provide a pseudo-random bit sequence generation method capable of reducing the total number of flips between all adjacent pseudo-random bit sequences.

Therefore, the pseudo random bit sequence generation method of the present invention is executed by an integrated circuit generation system, each pseudo random bit sequence has K bits, K>2, K is a positive integer, and the pseudo random bit sequence The generating method comprises the following steps: (A) obtaining a segment value n, 2≦n<K, n is a positive integer according to a total number of bits K of the pseudo random bit sequence; (B) according to the segment value n The K bits in the pseudo-random bit sequence are divided into N bit parts, each bit part has an unknown number of bits, and the number of N unknown bits satisfies the sum thereof equal to the total number of bits K Relationship, N=n; (C) generating, according to a clock signal input and the first number of unknown bits to the number of N-1 unknown bits, generating N clock signals respectively associated with generating the N bit portions; (D) according to The N unknown number of bits and a switching period of each clock signal output determine a function related to calculating a total of the inversion of bits between adjacent pseudo-random bit sequences in all pseudo-random bit sequences (E) calculating a value of each unknown number of bits when the total number of inversions has a minimum value according to the function; and (F) according to the total number of bits K, the segmentation value n, each The value of an unknown bit number, and the N clock signals are output to generate each pseudo random bit sequence.

Accordingly, it is another object of the present invention to provide a pseudo-random bit sequence generating apparatus capable of reducing the total number of flips between all adjacent pseudo-random bit sequences.

Thus, the pseudo random bit sequence generating apparatus of the present invention comprises a clock signal generator, a first bit portion generator, and a second bit portion generator.

The clock signal generator receives a clock signal input and a first unknown bit number, and outputs the clock signal input as a first clock signal output, and according to the first unknown bit number The clock signal input is divided to generate a second clock signal output.

The first bit portion generator receives a switching signal and electrically connects the clock signal generator to receive the first clock signal output, and according to the switching signal And the first clock signal output generates a plurality of first bit portions each having a plurality of bits.

The second bit portion generator receives the switching signal, and electrically connects the clock signal generator to receive the second clock signal output, and generates an output according to the switching signal and the second clock signal output. A second bit portion each having a plurality of bits, each second bit portion being combined with a corresponding one of the first bit portions into a pseudo random bit sequence.

Accordingly, it is still another object of the present invention to provide an integrated circuit generating system for generating a pseudo random bit sequence generating device.

The effect of the present invention is: by obtaining the function according to the number of N unknown bits and the output of each clock signal, and calculating a value of each unknown number of bits when the total number of inversions has a minimum value, such a And when the integrated circuit generating system generates all pseudorandom bits according to the known total number of bits K, the segmentation value n, the value of each unknown number of bits, and the output of the N clock signals. In the sequence, the total number of flips between all adjacent pseudo-random bit sequences can be effectively reduced.

2‧‧‧Pseudo-random bit sequence generation device

BS1, BS2‧‧‧ bit parts

Cs‧‧‧Switching signal

21‧‧‧ clock signal generator

CLK1‧‧‧ clock signal output

211‧‧‧ Frequency dividing circuit

CLK2‧‧‧ clock signal output

22‧‧‧The first bit part generator

K‧‧‧ total number of bits

221‧‧‧Linear Feedback Shift Register

L, H‧‧‧ Unknown number of bits

222‧‧‧Linear Feedback Shift Register

PRBS‧‧‧ pseudorandom bit sequence

223‧‧‧Linear Feedback Shift Register

T ₁ , T ₂ ‧‧‧ switching cycle

23‧‧‧Second bit part generator

11~16‧‧‧Steps

230‧‧‧ XOR gate

131, 132‧‧‧ substeps

231~242‧‧‧Linear Feedback Shift Register

151~154‧‧‧ substeps

Other features and effects of the present invention will be apparent from the embodiments of the drawings, in which: 1 is a flow chart illustrating an embodiment of a pseudo random bit sequence generation method of the present invention; FIG. 2 is a schematic diagram showing a pseudo random bit sequence of the embodiment divided into two bit portions; FIG. Is a timing diagram illustrating two clock signal outputs of the embodiment; FIG. 4 is a circuit block diagram illustrating a pseudo random bit sequence generation apparatus for generating a pseudo random bit sequence in the embodiment; and FIG. Is a measure of the total number of flips to the total number of bits between all adjacent pseudo-random bit sequences of this embodiment and the conventional pseudo-random bit sequence generation method.

Referring to FIG. 1, an embodiment of a pseudo-random bit sequence generation method of the present invention is executed by an integrated circuit generation system (not shown) for generating a plurality of pseudo-random bit sequences (PRBS). To test whether the function of the finished wafer is normal. During operation, the tester first sets a total number of bits K of a single PRBS according to the test requirements of the wafer to be tested. When the set single PRBS has K bits, the integrated body The circuit generation system generates a total of 2 ^K PRBS each having K bits, K>2, where K is a positive integer. For example, if the total number of bits K of a single PRBS is equal to eight, the integrated circuit generating system generates a total of ²⁸ PRBSs varying from 00000000-11111111. In this embodiment, the PRBS generation method performed by the integrated circuit generation system includes the following steps.

Step 11: Obtain a segment value n, 2 ≦ n < K, n is a positive integer according to the total number of bits K of the PRBS.

It should be noted that, in this embodiment, the segmentation value n can be obtained by using a lookup table containing a plurality of different total number of bits and relationship information between the plurality of segment values. The lookup table is that the tester pre-establishes the lookup table by counting the total number of flips between all adjacent PRBSs corresponding to each segment after the tester divides each total number of bits differently, when K≦20 The segment value n is preferably equal to two. It should be added that when n=2, the total number of inversions is not the least. In fact, the total number of inversions when n=3 is less than the total number of inversions when n=2, but the circuit will be caused by n=3. The design is more complicated. Therefore, after comprehensively evaluating the total number of inversions and the circuit design complexity, it is preferable to set the segmentation value n to two.

Step 12: Divide the K bits in the PRBS into N bit parts according to the segment value n, each bit part has an unknown number of bits, and the number of N unknown bits satisfies the sum thereof is equal to The relationship of the total number of bits K, N = n, the number of the i-th unknown bits is smaller than the number of the i+1th unknown bits, i < N, i is a positive integer.

Referring further to FIG. 2, for example, when n=2, the K bits in the PRBS are divided into two bit portions BS1, BS2, and the first bit portion BS1 has an unknown bit number L ( That is, the first bit portion BS1 has L bits), the second The bit unit portion BS2 has an unknown number of bits H (i.e., the second bit portion BS2 has H bits), and the sum of the two unknown bit numbers L, H is equal to the total number of bits K ( That is, L+H=K), the number of unknown bits L is smaller than the number H of unknown bits, and L and H are each a positive integer.

Step 13: According to a clock signal input and the first unknown bit number to the N-1th unknown bit number, N pieces of clock signals respectively outputting the N bit parts are generated. In detail, step 13 includes the following sub-steps 131, 132.

Sub-step 131: The clock signal input is output as a first clock signal, the first clock signal output being related to generating a first bit portion.

Sub-step 132: De-frequencying the clock signal input according to the first unknown bit number to the N-1th unknown bit number to generate a second clock signal output to the Nth clock Signal output, the second to the Nth clock signal outputs are respectively associated with generating a second bit portion to an Nth bit portion.

A switching period of the output of the jth clock signal is as shown in the formula (1), 2≦j≦N, j is a positive integer: T _j = 2 ^P × T _(j-1) Formula (1), where T _j represents the The switching period of the jth clock signal output, P represents the (j-1)th unknown number of bits, and T _(j-1) represents a switching period of the (j-1)th clock signal output. For example, when n=N=2, the first and second unknown bit numbers are L and H, respectively, and a switching period of the second clock signal output is T ₂ = 2 ^L × T ₁ . T ₁ represents a switching period of the first clock signal output (i.e., the clock signal input). When n=N=3, the PRBS is divided into three bit parts, and each of the three bit parts has an unknown number of bits L, M, H (L<M<H), and the three A switching period of the clock signal output corresponding to each of the bit portions is T _L = T ₁ , T _M = T ₂ = 2 ^L × T ₁ , T _H = T ₃ = 2 ^M × T ₂ , and M is a positive integer .

Step 14: Determine a function according to the number of N unknown bits and a switching period of each clock signal output, the function is related to calculating a total number of times of flipping between adjacent PRBSs in all PRBSs (flip) The definition of the number of times is the same as the definition of the number of times of flipping of the prior art, so it will not be described here.

In detail, for a single PRBS with K bits, the total number of inversions between adjacent PRBSs can be expressed as K×2 ^{K- in the} process of generating all sequences (2 ^k PRBS) by the integrated circuit generation system. ¹ (This representation is a statistical analysis by the tester by statistical analysis of the total number of inversions between all adjacent sequences in the PRBS generation process with arbitrary K bits, which can be used to approximate expression generation 2 ^k The total number of inversions between all adjacent PRBSs in a PRBS process with K bits each). Therefore, if the PRBS is subjected to two segments (that is, the segment value n is equal to two) to obtain the two bit portions (corresponding to the two unknown bit numbers L, H respectively), all the second ones are generated. the total number of inverted bits between adjacent portions of the sequence can be expressed as ^H × 2 ^H-1, the total number of generated sequences of all inverted between adjacent first bit portion can be expressed as ^L × 2 ^L-1.

With further reference to FIG. 3, the parameters associated with the representative CLK1 to generate the first bit of the first portion of a clock signal output, will be generated in the corresponding _one of each switching period in the first clock signal output from a T a first bit portion, the parameter CLK2 representing the second clock signal output associated with the second bit portion for each switching period T _{2 of} the second clock signal output A second bit portion is generated correspondingly. If a single PRBS has eight bits (K=8), the two unknown bit numbers L and H corresponding to the two bit portions are respectively three and five (L=3, H=5), and After the step 13, T ₂ = 2 ^L × T ₁ , so the internal sequence of the first bit portion has been changed from the current sequence (10101) to the next sequence (00100). Change eight (2 ^L ) times (111, 110, 101, 010, 100, 000, 001, 011), that is, according to Figure 3, each time the second bit is generated, 2 ^L of this will be generated. The first bit portion (the total number of inversions between adjacent sequences is L × 2 ^L-1 ), and the integrated circuit generating system generates a total of 2 ^H of the second according to the second clock signal output a bit portion (the total number of flips between adjacent sequences is H × 2 ^H-1 ), and the first bit portion will generate 2 ^H × 2 ^{L in} total, and all the first bits are generated In part of the process, the total number of inversions between adjacent sequences is 2 ^H × L × 2 ^L-1 , so that when n = 2, the integrated circuit generation system is based on the number of the two unknown bits L , H, and each clock signal output The switching cycle is used to calculate the determined sequence to generate all the (2 ^k th PRBS) generation process, the function of the total number of turns between all neighboring PRBS can be expressed as the formula (2): Y = H × 2 H- ¹ + 2 ^H × L × 2 ^L-1 (2) where Y represents the total number of inversions, and L and H represent the number of the first and second unknown bits, respectively.

Similarly, when n=3, the integrated circuit generating system can determine the function according to the three unknown bit numbers L, M, H (L<M<H), and the switching period of each clock signal output. Let formula (3): Y = H × 2 ^H-1 + 2 ^H × M × 2 ^M-1 + 2 ^H × 2 ^M × L × 2 ^L-1 (3) where L, M, and H represent The first unknown number of bits, the second number of unknown bits, and the third number of unknown bits, L+M+H=K, but are not limited thereto. When n>3, the relevant function can also be derived in the same way.

Step 15: Calculate a value of each unknown number of bits when the total number of inversions has a minimum value according to the function. In detail, the formula (2) is exemplified, but is not limited thereto, and the step 15 includes the following sub-steps 151, 152, 153, and 154.

Sub-step 151: The function (2) is adjusted to Y = H × 2 ^H-1 + 2 ^H × (KH) × 2 ^KH-1 according to L = KH.

Sub-step 152: Deriving the second unknown number of bits H of the function of sub-step 151 and obtaining the function at 2 ^K = 2 ^H × (1 + H × ln 2) (for example, the function H differentiates and differentiates the differential expression to zero to know the relationship between K and H. The total number of flips has a minimum value.

Sub-step 153: According to sub-step 152, 2 ^K = 2 ^H × (1 + H × ln 2) and the value of the total number of bits K (for a known number, the tester sets it first) To get the value of the second unknown bit number H.

Sub-step 154: obtain the value of the first unknown bit number L according to the total number of bits K, the value of the second unknown bit number H obtained in sub-step 153, and L=K-H.

Step 16: Generate each PRBS according to the known total number of bits K, the segmentation value n, the value of each unknown bit number, the N clock signal outputs, and a switching signal. When the switching signal has a high logic level, each PRBS is a reverse sequence, and when the switching signal has a low logic level, each PRBS is a forward sequence.

In detail, the integrated circuit generating system can generate the software by means of an existing PRBS generating program according to the known total number of bits K, the segment value n, and the number of each unknown bit. value, of the N output clock signal, and said switching signal generating the PRBS two 2 ^k, or in hardware generation mode to generate the 2 ^k th PRBS. When the hard body 2 ^k two ways to generate the PRBS, the integrated circuit generating system using a conventional digital circuit synthesis program to K according to the total number of bits known, the segment value is n, each of the unknown bits The value of the number obtains a circuit design diagram for manufacturing a PRBS generating device, and the PRBS generating device according to the circuit design diagram generates 2 ^k according to the N clock signal output and the switching signal. PRBS. It should be noted that the feature of the embodiment is that the total number of bits K is segmented first, and then the clock signal is input for frequency division, and the function is obtained to calculate that the total number of times of flipping has a minimum value. a value of each unknown bit number such that the total number of inversions between all adjacent PRBSs can be reduced when the integrated circuit generating system generates all PRBSs, and how the integrated circuit generating system generates such The manner of the PRBS is well known to those skilled in the art. For the sake of brevity, only the PRBS generating apparatus manufactured according to the circuit design diagram generates 2 ^k PRBS as an example, but is not limited thereto.

Referring to FIG. 4, for example, when the total number of bits K is equal to fifteen, and the segmentation value n is equal to two, the number of the unknown bits L obtained by the pseudo random bit sequence generation method in this embodiment is used. The value of H is three or twelve, respectively, and the PRBS generating device 2 made by the circuit design diagram generated by the integrated circuit generating system is as shown in FIG.

The PRBS generating device 2 includes a clock signal generator 21, and first and second bit portion generators 22, 23.

The clock signal generator 21 receives the clock signal input and the first unknown bit number L, and includes a frequency dividing circuit 211. The frequency dividing circuit 211 divides the clock signal input according to the first unknown bit number L to generate the second clock signal output CLK2, and the clock signal generator 21 sets the clock signal. The direct output is input and CLK1 is output as the first clock signal.

The first bit portion generator 22 includes three linear feedback shift registers (LFSR) 221, 222, 223. The first bit portion generator 22 receives the switching signal Cs, and electrically connects the clock signal generator 21 to receive the first clock signal output CLK1, and according to the switching signal Cs and the first time The pulse signal output CLK1 generates a plurality of first bit portions BS1 each having three bits.

The second bit portion generator 23 includes twelve LFSRs 231 to 239, 240 to 242. The second bit portion generator 23 receives the switching signal Cs and is electrically connected to the clock signal generator 21 to receive the second clock signal output CLK2, and according to the switching signal Cs and the second time The pulse signal output CLK2 generates a plurality of second bit portions BS2 each having twelve bits. Each second bit portion BS2 is combined with its corresponding first bit portion BS1 into the PRBS having fifteen bits.

It should be noted that, from the specification of the second bit portion generator 23, the primitive polynomial is H(X, 12)=X ⁰ +X ³ +X ⁴ +X ⁷ +X ¹² . And inverting H(X, 12), the second primitive part generator 23 generates an inverse sequence. The inverse primitive polynomial of the second bit part BS2 is G(X, 12)=X ¹² + X ⁹ +X ⁸ +X ⁵ +X ⁰ . When the switching signal Cs has the low logic level (ie, 0), the exclusive OR gate 230 receives the bits from the LFSRs 233, 234, 237, 242 (each LFSR 233, 234, 237, 242 as one) a feedback tap that affects the second bit portion BS2) that the second bit portion generator 23 outputs next, that is, corresponds to the primitive polynomial H(X, 12), and therefore, the second bit Each second bit portion BS2 generated by the partial generator 23 is a forward sequence. When the switching signal Cs has the high logic level (ie, 1), the XOR gate 230 receives the bits from the LFSRs 231, 235, 238, 234 (which are feedback taps), ie, the corresponding reverse The original polynomial G(X, 12), therefore, each second bit portion BS2 generated by the second bit portion generator 23 is a reverse sequence. Similarly, the first bit portion generator 22 is also controlled by the switching signal Cs such that each first bit portion BS1 generated by the first bit portion generator 22 is a forward sequence or A reverse sequence. Therefore, the PRBS formed by combining each second bit portion BS2 with its corresponding first bit portion BS1 may also be a forward sequence or a reverse sequence.

In addition, the clock signal generator 21, the configuration and operation of the first and second bit portion generators 22, 23 and how each of the first and second bit portions BS1, BS2 are generated, This is well known to those of ordinary skill in the art and will not be described herein for the sake of brevity.

Referring to FIG. 5, a comparison of the total number of flips between all adjacent pseudo-random bit sequences of the conventional pseudo-random bit sequence generation method and the pseudo-random bit sequence with different total number of bits is compared. Figure. Figure 5 shows that the total number of flips for this embodiment is significantly less than the total number of flips of the conventional pseudo-random bit sequence generation method, verifying that this embodiment does have the effect of reducing the total number of flips.

In summary, the PRBS generating method of the present invention, by segmenting the total number of bits K first, and then dividing the clock signal input to obtain the output of the N clock signals, and according to the N The number of unknown bits and each clock signal output to obtain the function and calculate the value of each unknown number of bits when the total number of inversions has a minimum value, such that when the integrated circuit generation system is known The total number of bits K, the segmentation value n, the value of each unknown number of bits, and the output of the N clock signals to generate all PRBSs, the total number of times of inversion between all adjacent PRBSs is the smallest, so that The test power consumption required for the wafer to be tested during the test is also reduced, so that the object of the present invention can be achieved.

However, the above is only the embodiment of the present invention, and the scope of the invention is not limited thereto, and all the equivalent equivalent changes and modifications according to the scope of the patent application and the patent specification of the present invention are still The scope of the invention is covered.

Claims (8)

A pseudo-random bit sequence generation method is performed by an integrated circuit generation system, each pseudo-random bit sequence has K bits, K>2, and K is a positive integer, and the pseudo-random bit sequence generation method includes The following steps: (A) obtaining a segment value n, 2 ≦ n < K, n is a positive integer according to a total number of bits K of the pseudo random bit sequence; (B) the pseudo value according to the segment value n The K bits in the random bit sequence are divided into N bit parts, each bit part has an unknown number of bits, and the number of N unknown bits satisfies the relationship that the sum is equal to the total number of bits K. N=n; (C) generating, according to a clock signal input and the first unknown bit number to the N-1th unknown bit number, generating N clock signal outputs respectively associated with generating the N bit parts; (D) determining a function according to the number of N unknown bits and a switching period of each clock signal output, the function being related to calculating the occurrence of bits between adjacent pseudo-random bit sequences in all pseudo-random bit sequences The total number of flips of the flip; (E) Calculate according to the function, the total number of flips has a minimum value, each unknown bit A value; and (F) based on the total number of bits K, the segment value n, the value of each of the number of unknown bits, and the N output clock signal to generate a pseudo-random sequence of bits each. The pseudo random bit sequence generation method according to claim 1, wherein in the step (B), the i-th unknown bit number is smaller than the i+1th unknown bit number, i<N, i is a positive integer . The pseudo random bit sequence generation method of claim 1, wherein the step (C) comprises the following substep (C1) of inputting the clock signal as a first clock signal, the first clock signal The output is related to generating a first bit portion, and (C2) is respectively frequency-divided according to the first unknown bit number to the N-1th unknown bit number to generate a second The clock signal is output to the Nth clock signal output. The pseudo random bit sequence generation method according to claim 3, wherein in the step (C2), a switching period of the jth clock signal output, 2≦j≦N,j is a positive integer, T _j = 2 ^P ×T _(j-1) , where T _j represents the switching period of the j-th clock signal output, P represents the number of (j-1) unknown bits, and T _(j-1) represents the first (j-1) One switching period of the clock signal output. The pseudo random bit sequence generation method according to claim 1, wherein n=3, in step (D), the integrated circuit generation system determines that the function is Y=H×2 ^H-1 +2 ^H ×M×2 ^M-1 +2 ^H ×2 ^M ×L×2 ^L-1 , where Y represents the total number of inversions, and L, M, and H represent the first unknown number of bits and the second unknown bit, respectively. The number of elements, and the third number of unknown bits, L, M, and H are each a positive integer, L+M+H=K. The pseudo random bit sequence generating method according to claim 1, wherein n=2, in step (D), the integrated circuit generating system determines that the function is Y=H×2 ^H-1 +2 ^H ×L×2 ^L-1 , where Y represents the total number of inversions, L and H represent the first unknown number of bits and the second unknown number of bits, respectively, L and H are positive integers, L+H= K. The pseudo random bit sequence generation method according to claim 6, wherein the step (E) comprises the following substep (E1) adjusting the function to Y=H×2 ^H-1 +2 ^H × according to L=KH ( ^KH) × 2 ^KH-1, the second number of unknown bits H (E2) sub-step (E1) of the derivative of the function, and the function obtained in the ^{2 K = 2 H × (1} + H × ln 2), the total number of inversions has a minimum value, and (E3) obtains the second number according to the value of 2 ^K = 2 ^H × (1 + H × ln 2) of the sub-step (E2) and the total number of bits K The value of the number of unknown bits H, and (E4) the value of the number of the first unknown bit L based on the total number of bits K, the value of the second number of unknown bits H, and L=KH . The pseudo random bit sequence generating method according to claim 1, wherein in the step (F), the integrated circuit generating system further generates each pseudo random bit sequence according to a switching signal, when the switching signal has a When the logic level is high, each pseudo random bit sequence is an inverse sequence. When the switching signal has a low logic level, each pseudo random bit sequence is a forward sequence.