TWI640012B - Block decoder of nonvolatile memory and level shifter - Google Patents

Abstract

A block decoder for non-volatile memory, including a level shifter and a decoder. The control end of the first transistor is coupled to the first control node, the first end of the first transistor is coupled to the output node, and the second end of the first transistor is coupled to the first supply potential. The control end of the second transistor is coupled to the second control node, the first end of the second transistor is coupled to the ground potential, and the second end of the second transistor is coupled to the output node. The control terminal of the third transistor is coupled to the output node, the first end of the third transistor is coupled to the first node, and the second end of the third transistor is coupled to the second supply potential. The control terminal of the fourth transistor is coupled to the second control node, the first end of the fourth transistor is coupled to the first node, and the second end of the fourth transistor is coupled to the output node.

Description

Block decoder and level shifter for non-volatile memory

The present invention relates to a block decoder and a level shifter, and more particularly to a block decoder for a nonvolatile memory that can reduce the overall layout area (Layout Area). With level shifter.

Nonvolatile Memory has the characteristics that stored data does not disappear when the power is turned off, including flash memory. Flash memory is an electronically-clearable, programmable read-only memory that allows multiple erasures and writes, which is suitable for general data storage and for the exchange of data between computers and other digital products.

The flash memory includes a plurality of blocks, each of which is accessed by a block decoder. As the density of circuits in memory increases, the number of block and block decoders increases dramatically, which requires a larger layout area for the production of flash memory. Therefore, it is necessary to propose a new solution to solve the problem of excessive circuit layout area of flash memory in the conventional technology.

In a preferred embodiment, the present invention provides a block decoder for non-volatile memory, comprising: a one-bit shifter comprising: a first transistor; Having a control terminal, a first terminal, and a second terminal, wherein the control terminal of the first transistor is coupled to a first control node, and the first end of the first transistor is coupled to An output node, the second end of the first transistor is coupled to a first supply potential; a second transistor having a control end, a first end, and a second end, wherein the second The control terminal of the second transistor is coupled to a second control node, the first end of the second transistor is coupled to a ground potential, and the second end of the second transistor is coupled to An output node; a third transistor having a control terminal, a first terminal, and a second terminal, wherein the control terminal of the third transistor is coupled to the output node, the third transistor The first end is coupled to a first node, and the second end of the third transistor is coupled to a second supply potential; and a fourth transistor having a control end and a first end And a second end, wherein the control end of the fourth transistor is coupled to the second control node, the fourth The first end of the crystal is coupled to the first node, and the second end of the fourth transistor is coupled to the output node; and a decoder coupled to a third supply potential, wherein the The decoder is configured to output a first control potential to the first control node and output a second control potential to the second control node.

In some embodiments, the first control potential and the second control potential have complementary logic levels.

In some embodiments, each of the first transistor, the second transistor, and the third transistor are each an N-type MOS field effect transistor.

In some embodiments, the fourth transistor is a P-type MOS field effect transistor.

In some embodiments, the first transistor, the second transistor, And each of the fourth transistors is each an enhanced transistor.

In some embodiments, the third transistor is a depletion transistor.

In some embodiments, the third supply potential is greater than or equal to one of the absolute values of one of the third transistors.

In some embodiments, the third supply potential is higher than the first supply potential.

In some embodiments, a potential difference between the third supply potential and the first supply potential is greater than or equal to a critical potential of the first transistor.

In some embodiments, the second supply potential is at least four times the first supply potential or the third supply potential.

In some embodiments, the decoder includes: a fifth transistor having a control terminal, a first terminal, and a second terminal, wherein the control terminal of the fifth transistor is coupled to a first An input node, the first end of the fifth transistor is coupled to the third supply potential, and the second end of the fifth transistor is coupled to the second control node; a sixth transistor, Having a control terminal, a first terminal, and a second terminal, wherein the control terminal of the sixth transistor is coupled to the first input node, and the first end of the sixth transistor is coupled to a second node, the second end of the sixth transistor is coupled to the second control node; a seventh transistor having a control end, a first end, and a second end, wherein the second node The control end of the seventh transistor is coupled to a second input node, the first end of the seventh transistor is coupled to a third node, and the second end of the seventh transistor is coupled Connected to the second node; and an eighth transistor having a control a first end, and a second end, wherein the control end of the eighth transistor is coupled to a third input node, the first end of the eighth transistor is coupled to the ground potential And the second end of the eighth transistor is coupled to the third node.

In some embodiments, the decoder further includes: a ninth transistor having a control terminal, a first terminal, and a second terminal, wherein the control terminal of the ninth transistor is coupled to the first a second input node, the first end of the ninth transistor is coupled to the third supply potential, and the second end of the ninth transistor is coupled to the second control node; a tenth transistor Having a control terminal, a first terminal, and a second terminal, wherein the control terminal of the tenth transistor is coupled to the third input node, and the first end of the tenth transistor is coupled Up to the third supply potential, the second end of the tenth transistor is coupled to the second control node; and an inverter coupled to the third supply potential and having an input end and a The output end is coupled to the second control node, and the output end of the inverter is coupled to the first control node.

In some embodiments, each of the fifth transistor, the ninth transistor, and the tenth transistor are each a P-type MOS field effect transistor.

In some embodiments, each of the sixth transistor, the seventh transistor, and the eighth transistor are each an N-type MOS field effect transistor.

In another preferred embodiment, the present invention provides a level shifter comprising: a first transistor having a control terminal, a first terminal, and a second terminal, wherein the first transistor The control end is coupled to a first control node, the first end of the first transistor is coupled to an output node, and the second end of the first transistor is coupled to a first supply Potential; a second transistor, The control unit has a control end, a first end, and a second end, wherein the control end of the second transistor is coupled to a second control node, and the first end of the second transistor is coupled to a ground potential, the second end of the second transistor is coupled to the output node; a third transistor having a control end, a first end, and a second end, wherein the third end The control end of the crystal is coupled to the output node, the first end of the third transistor is coupled to a first node, and the second end of the third transistor is coupled to a second a supply potential; and a fourth transistor having a control terminal, a first terminal, and a second terminal, wherein the control terminal of the fourth transistor is coupled to the second control node, the fourth The first end of the crystal is coupled to the first node, and the second end of the fourth transistor is coupled to the output node.

100, 200‧‧‧ block decoder

110‧‧‧ position shifter

120, 220‧‧‧ decoder

230‧‧‧Inverter

M1‧‧‧first transistor

M2‧‧‧second transistor

M3‧‧‧ third transistor

M4‧‧‧ fourth transistor

M5‧‧‧ fifth transistor

M6‧‧‧ sixth transistor

M7‧‧‧ seventh transistor

M8‧‧‧ eighth transistor

M9‧‧‧ ninth transistor

M10‧‧‧10th transistor

N1‧‧‧ first node

N2‧‧‧ second node

N3‧‧‧ third node

NC1‧‧‧ first control node

NC2‧‧‧second control node

NOUT‧‧‧ output node

VC1‧‧‧ first control potential

VC2‧‧‧second control potential

VDD1‧‧‧first supply potential

VDD2‧‧‧second supply potential

VDD3‧‧‧ third supply potential

VOUT‧‧‧ output potential

VSS‧‧‧ Ground potential

1 is a schematic diagram showing a block decoder of a non-volatile memory according to an embodiment of the invention; and FIG. 2 is a block decoder showing a non-volatile memory according to an embodiment of the invention. Schematic diagram; and FIG. 3 is a schematic diagram showing a level shifter according to an embodiment of the invention.

In order to make the objects, features and advantages of the present invention more comprehensible, the specific embodiments of the invention are set forth in the accompanying drawings.

Some words are used in the specification and patent application scope. Refers to a specific component. Those skilled in the art will appreciate that a hardware manufacturer may refer to the same component by a different noun. The scope of the present specification and the patent application do not use the difference in the name as the means for distinguishing the elements, but the difference in function of the elements as the criterion for distinguishing. The words "including" and "including" as used throughout the specification and patent application are open-ended terms and should be interpreted as "including but not limited to". The term "substantially" means that within the acceptable error range, those skilled in the art will be able to solve the technical problems within a certain error range to achieve the basic technical effects. In addition, the term "coupled" is used in this specification to include any direct and indirect electrical connection means. Therefore, if a first device is coupled to a second device, the first device can be directly electrically connected to the second device, or indirectly connected to the second device via other devices or connection means. Two devices.

1 is a schematic diagram showing a block decoder 100 of a nonvolatile memory according to an embodiment of the invention. The block decoder 100 can be applied to a flash memory, such as a NAND flash memory or a NOR flash memory, wherein the block decoder 100 is used for selecting and accessing flash memory. One of a plurality of blocks. As shown in FIG. 1, the block decoder 100 includes a one-bit shifter 110 and a decoder 120, wherein the level shifter 110 includes a first transistor M1, a second transistor M2, and a first A tri-crystal M3, and a fourth transistor M4.

Each of the first transistor M1, the second transistor M2, and the third transistor M3 may be any type of N-type transistor, and the fourth transistor M4 may be of any type One of the P-type transistors (P-type Transistor). For example, the first transistor M1, the second transistor M2, And each of the third transistors M3 may be an N-channel Metal-Oxide-Semiconductor Field-Effect Transistor (NMOS Transistor); and the fourth transistor M4 may be a P P-channel Metal-Oxide-Semiconductor Field-Effect Transistor (PMOS Transistor). In detail, each of the first transistor M1, the second transistor M2, and the fourth transistor M4 may each be an enhancement type-type transistor; and the third transistor M3 may be a Depletion-type Transistor.

The first transistor M1 has a control terminal, a first terminal, and a second terminal. The control terminal of the first transistor M1 is coupled to a first control node NC1 to receive a first control potential VC1. The first end of the transistor M1 is coupled to an output node NOUT, and the second end of the first transistor M1 is coupled to a first supply potential VDD1. The second transistor M2 has a control terminal, a first terminal, and a second terminal. The control terminal of the second transistor M2 is coupled to a second control node NC2 to receive a second control potential VC2. The first end of the second transistor M2 is coupled to a ground potential VSS, and the second end of the second transistor M2 is coupled to the output node NOUT to output an output potential VOUT. The third transistor M3 has a control terminal, a first terminal, and a second terminal, wherein the control terminal of the third transistor M3 is coupled to the output node NOUT to receive the aforementioned output potential VOUT, the third transistor M3. The first end is coupled to a first node N1, and the second end of the third transistor M3 is coupled to a second supply potential VDD2. The fourth transistor M4 has a control terminal, a first terminal, and a second terminal. The control terminal of the fourth transistor M4 is coupled to the second control node NC2 to receive the second control potential VC2. The first end of the fourth transistor M4 is coupled to the first section Point N1, and the second end of the fourth transistor M4 is coupled to the output node NOUT to output the aforementioned output potential VOUT. It should be noted that in each of the foregoing transistors, the control terminal may be a gate of the transistor, and one of the first end and the second end may be a source of the transistor. The other of the first end and the second end may be one of the drains of the transistor. The source symbol (arrow on the transistor) shown in Figure 1 is only a reference. In fact, the source and the drain of the transistor may be mutually adjusted due to the difference in applied potential.

The decoder 120 is coupled to a third supply potential VDD3, wherein the decoder 120 is configured to output the aforementioned first control potential VC1 to the first control node NC1, and output the aforementioned second control potential VC2 to the second control node. NC2. The first control potential VC1 and the second control potential VC2 may have complementary logic levels. For example, if the first control potential VC1 is equal to the third supply potential VDD3 (ie, the high logic level "1"), the second control potential VC2 will be equal to the ground potential VSS (ie, the low logic level "0" On the other hand, if the first control potential VC1 is equal to the ground potential VSS (ie, the low logic level is “0”), the second control potential VC2 will be equal to the third supply potential VDD3 (ie, the high logic level “ 1").

The principle of operation of block decoder 100 can be as follows. When the corresponding block is selected, the first control potential VC1 will have a high logic level, and the second control potential VC2 will have a low logic level to turn on the first transistor M1 and turn off (Turn Off) the second transistor M2. At this time, since the output potential VOUT of the output node NOUT is relatively high and the second control potential VC2 is relatively low, both the third transistor M3 and the fourth transistor M4 are turned on to form a positive feedback loop. (Positive Feedback Loop), which will continue The output potential VOUT is pulled high until the output potential VOUT is equal to or nearly equal to the second supply potential VDD2. It has to be noted that the second supply potential VDD2 is usually much higher than the first supply potential VDD1 and the third supply potential VDD3. For example, the second supply potential VDD2 is at least four times the first supply potential VDD1 or the third supply potential VDD3. For example, the first supply potential VDD1 and the third supply potential VDD3 may be between about 4V and 7V, and the second supply potential VDD2 may be about 30V or so, but this is merely an example, and the present invention is not limited thereto. On the other hand, when the corresponding block is not selected, the first control potential VC1 will have a low logic level, and the second control potential VC2 will have a high logic level to turn off the first transistor M1 and turn on the first Two transistors M2. At this time, since the output potential VOUT of the output node NOUT is relatively low and the second control potential VC2 is relatively high, both the third transistor M3 and the fourth transistor M4 are at least partially turned off, so that The turned-on second transistor M2 can further pull down the output potential VOUT of the output node NOUT to the ground potential VSS (for example, 0V).

In order to further improve the operational performance of the block decoder 100, its component parameters can be set as described in the following equations (1), (2).

Wherein "VDD3" represents the potential level of the third supply potential VDD3, and "VDEP" represents the potential level of a threshold voltage of the third transistor M3. In other words, the third supply potential VDD3 is greater than or equal to one of the absolute values of the threshold potential VDEP of the third transistor M3.

Since the third transistor M3 is a depleted transistor, its critical potential VDEP is usually a negative value (<0V, for example: -3V). When the corresponding block is not selected, the third transistor M3 and the fourth transistor M4 must be turned off to block the second The supply potential VDD2 is delivered to the output node NOUT. Therefore, if the third supply potential VDD3 is designed to be greater than or equal to the absolute value of the threshold potential VDEP of the third transistor M3, the potential of the high logic level of the second control potential VC2 should be sufficiently high to ensure the fourth transistor M4. It can be completely turned off to prevent the output potential VOUT from being disturbed by the second supply potential VDD2.

Wherein "VDD3" represents the potential level of the third supply potential VDD3, "VDD1" represents the potential level of the first supply potential VDD1, and "VTH" represents the potential level of a critical potential of the first transistor M1. In other words, the third supply potential VDD3 is higher than the first supply potential VDD1, and the potential difference between the third supply potential VDD3 and the first supply potential VDD1 is greater than or equal to the threshold potential VTH of the first transistor M1.

Since the first transistor M1 is an enhancement transistor, its critical potential VTH is usually a positive value (>0V, for example, +1V). When the corresponding block has been selected, the third transistor M3 must be turned on to form a positive feedback loop. Therefore, if the third supply potential VDD3 is designed to be greater than or equal to the threshold potential VTH of the first transistor M1 after subtracting the first supply potential VDD1, one of the gates generated when the first transistor M1 transmits a high logic level can be cancelled. Gate-to-Source Voltage Drop (ie, when the first transistor M1 is turned on, the output potential VOUT of the source of the first transistor M1 is generally lower than the first control potential of the gate VC1, and the potential difference between the two is approximately equal to the threshold potential VTH of the first transistor M1) to ensure that the third transistor M3 can be fully turned on, and can quickly pull the output potential VOUT to the second supply potential VDD2.

In some embodiments, the gate length of one of the first transistors M1 (also The "channel length" is set to be larger than the gate length of the second transistor M2, so that the first transistor M1 is more resistant to the higher voltage from its first end and the second end ( That is, the first supply potential VDD1 or (and) the second supply potential VDD2). The above component parameter setting is obtained based on the results of a plurality of experiments, which can effectively improve the overall system reliability of the block decoder 100 according to the actual measurement result.

In addition to improving overall system reliability, the present invention has at least the following advantages over the prior art. First, in the present invention, since both the first transistor M1 and the second transistor M2 are enhancement type transistors, both the first transistor M1 and the second transistor M2 can share the same semiconductor well during semiconductor fabrication. The area (Well) can further reduce the layout area of the level shifter 110. It must be noted that the conventional level shifter often requires more than two depleted transistors, because the depleted transistor cannot share the semiconductor well region with the enhanced transistor, so it must occupy a large layout area. Furthermore, in the present invention, when the corresponding block is not selected and the second control potential VC2 is at a high logic level, the output node NOUT can be coupled to the ground potential VSS via only a single second transistor M2, thereby being Grounding reliability of the output potential VOUT. Compared with the traditional design, the output node usually needs to be grounded through a plurality of transistors. Since the total resistance value of the plurality of transistors in series is relatively high, the grounding instability is naturally caused. Therefore, the level shifter 110 of the present invention can be used to solve various dilemmas faced by the prior art.

To meet different usage requirements, the decoder 120 can be implemented with a variety of different circuits. The following embodiments illustrate possible circuit configurations of the decoder 120, and it must be understood that it is merely illustrative and not intended to limit the patent of the present invention. range.

2 is a schematic diagram showing a block decoder 200 of a non-volatile memory according to an embodiment of the invention. Figure 2 is similar to Figure 1. In the embodiment of FIG. 2, the block decoder 200 includes a one-bit shifter 110 and a decoder 220, wherein the decoder 220 includes a fifth transistor M5, a sixth transistor M6, and a seventh The transistor M7, an eighth transistor M8, a ninth transistor M9, a tenth transistor M10, and an inverter 230 are provided. The structure and function of the level shifter 110 has been as described in the embodiment of Fig. 1. As shown in FIG. 2, each of the fifth transistor M5, the ninth transistor M9, and the tenth transistor M10 may each be any type of P-type transistor, and the sixth transistor M6, seventh. Each of the transistor M7 and the eighth transistor M8 may each be an N-type transistor of any kind. For example, each of the fifth transistor M5, the ninth transistor M9, and the tenth transistor M10 may each be a P-type MOS field effect transistor; and the sixth transistor M6, the seventh transistor M7, And each of the eighth transistors M8 can each be an N-type gold oxide half field effect transistor. In detail, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, the eighth transistor M8, the ninth transistor M9, and the tenth transistor M10 may each be an enhancement type transistor.

The fifth transistor M5 has a control terminal, a first terminal, and a second terminal. The control terminal of the fifth transistor M5 is coupled to a first input node NIN1, and the first end of the fifth transistor M5. The second terminal is coupled to the third supply node VDD3, and the second end of the fifth transistor M5 is coupled to the second control node NC2. The sixth transistor M6 has a control end, a first end, and a second end, wherein the control end of the sixth transistor M6 is coupled to the first input node NIN1, and the first end of the sixth transistor M6 Coupling to a second node N2, sixth transistor M6 The second end is coupled to the second control node NC2. The seventh transistor M7 has a control terminal, a first terminal, and a second terminal, wherein the control terminal of the seventh transistor M7 is coupled to a second input node NIN2, and the first end of the seventh transistor M7 The second end of the seventh transistor M7 is coupled to the second node N2. The eighth transistor M8 has a control end, a first end, and a second end, wherein the control end of the eighth transistor M8 is coupled to a third input node NIN3, and the first end of the eighth transistor M8 The second end of the eighth transistor M8 is coupled to the third node N3. The ninth transistor M9 has a control terminal, a first terminal, and a second terminal, wherein the control terminal of the ninth transistor M9 is coupled to the second input node NIN2, and the first end of the ninth transistor M9 is The second terminal of the ninth transistor M9 is coupled to the second control node NC2. The tenth transistor M10 has a control end, a first end, and a second end, wherein the control end of the tenth transistor M10 is coupled to the third input node NIN3, and the first end of the tenth transistor M10 The second terminal of the tenth transistor M10 is coupled to the second control node NC2. It should be noted that in each of the foregoing transistors, the control end may be one of the gates of the transistor, and one of the first end and the second end may be one of the sources of the transistor, and the first end and the first end The other of the two ends can be one of the transistors. The source symbol (arrow on the transistor) shown in Fig. 2 is only a reference, and the source and the drain of the transistor may be mutually adjusted due to the difference in applied potential. The inverter 230 is coupled to the third supply potential VDD3 and has an input end and an output end, wherein the input end of the inverter 230 is coupled to the second control node NC2, and the output end of the inverter 230 The system is coupled to the first control node NC1. In general, the decoder 230 is based on the first input node NIN1 and the second input node. NIN2, and three input potentials of the third input node NIN3 determine the first control potential VC1 of the first control node NC1 and the second control potential VC2 of the second control node NC2. Since the inverter 230 is coupled between the second control node NC2 and the first control node NC1, the first control potential VC1 and the second control potential VC2 must have complementary logic levels. For example, the high logic level may be equal to the third supply potential VDD3 and the low logic level may be equal to the ground potential VSS. The remaining features of the block decoder 200 of FIG. 2 are similar to the block decoder 100 of FIG. 1, so that the second embodiment can achieve similar operational effects.

Figure 3 is a schematic diagram showing a level shifter 110 in accordance with an embodiment of the present invention. The structure and function of the level shifter 110 has been as described in the embodiment of Fig. 1. In the embodiment of FIG. 3, the level shifter 110 can be used alone and can be combined with various circuits other than the decoders 120 and 220, and can also exert similar operational effects.

The invention proposes a novel block decoder and a level shifter design method. Compared with the conventional design, the present invention at least has the important advantages of improving the overall system reliability and reducing the overall circuit layout area, so it is suitable. It is used in a variety of flash memory devices.

It is to be noted that the above-mentioned component parameters and ranges are not limitations of the present invention. Designers can adjust these settings to suit different needs. The block decoder and level shifter of the present invention are not limited to the states illustrated in Figures 1-3. The present invention may include only any one or more of the features of any one or a plurality of embodiments of Figures 1-3. In other words, not all illustrated features must be implemented simultaneously in the block decoder and level shifter of the present invention.

The ordinal number in this specification and the scope of the patent application, for example, One, "second", "third", etc., have no sequential relationship with each other, and are only used to indicate that two different elements having the same name are distinguished.

The present invention has been described above with reference to the preferred embodiments thereof, and is not intended to limit the scope of the present invention, and the invention may be modified and modified without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

Claims (20)

A block decoder for a non-volatile memory, comprising: a quasi-shifter comprising: a first transistor having a control terminal, a first terminal, and a second terminal, wherein the first transistor The control end is coupled to a first control node, the first end of the first transistor is coupled to an output node, and the second end of the first transistor is coupled to a first a second transistor having a control terminal, a first terminal, and a second terminal, wherein the control terminal of the second transistor is coupled to a second control node, the second transistor The first end is coupled to a ground potential, and the second end of the second transistor is coupled to the output node; a third transistor has a control end, a first end, and a a second end, wherein the control end of the third transistor is coupled to the output node, the first end of the third transistor is coupled to a first node, and the third transistor The two ends are coupled to a second supply potential; and a fourth transistor has a control end and a first end. And a second end, wherein the control end of the fourth transistor is coupled to the second control node, the first end of the fourth transistor is coupled to the first node, and the fourth The second end of the crystal is coupled to the output node; and a decoder coupled to a third supply potential, wherein the decoder is configured to output a first control potential to the first control node, and output a second control potential to the second control node. A block decoder for non-volatile memory according to claim 1, wherein the first control potential and the second control potential have complementary logic bits. quasi. The block decoder of the non-volatile memory of claim 1, wherein each of the first transistor, the second transistor, and the third transistor is an N-type gold oxide Half field effect transistor. The block decoder of the non-volatile memory of claim 1, wherein the fourth transistor is a P-type MOS field effect transistor. The block decoder of the non-volatile memory of claim 1, wherein each of the first transistor, the second transistor, and the fourth transistor is an enhanced transistor . The block decoder of the non-volatile memory of claim 1, wherein the third transistor is a depletion transistor. The block decoder of the non-volatile memory of claim 1, wherein the third supply potential is greater than or equal to an absolute value of one of the threshold potentials of the third transistor. The block decoder of the non-volatile memory of claim 1, wherein the third supply potential is higher than the first supply potential. The block decoder of the non-volatile memory of claim 8, wherein a potential difference between the third supply potential and the first supply potential is greater than or equal to a critical potential of the first transistor. . The block decoder of the non-volatile memory of claim 1, wherein the second supply potential is at least four times the first supply potential or the third supply potential. A block decoder for non-volatile memory as described in claim 1, wherein the decoder comprises: a fifth transistor having a control terminal, a first terminal, and a second terminal, wherein the control terminal of the fifth transistor is coupled to a first input node, the fifth transistor One end is coupled to the third supply potential, and the second end of the fifth transistor is coupled to the second control node; a sixth transistor having a control end, a first end, and a second end, wherein the control end of the sixth transistor is coupled to the first input node, the first end of the sixth transistor is coupled to a second node, and the sixth transistor The second end is coupled to the second control node; a seventh transistor having a control end, a first end, and a second end, wherein the control end of the seventh transistor is coupled Up to a second input node, the first end of the seventh transistor is coupled to a third node, and the second end of the seventh transistor is coupled to the second node; and an eighth The transistor has a control end, a first end, and a second end, wherein the control end of the eighth transistor is coupled to A third input node, the first end of the line of the eighth transistor is coupled to the ground potential, and the second end of the line of the eighth transistor is coupled to the third node. The block decoder of the non-volatile memory of claim 11, wherein the decoder further comprises: a ninth transistor having a control end, a first end, and a second end, wherein The control terminal of the ninth transistor is coupled to the second input node, the first end of the ninth transistor is coupled to the third supply potential, and the second end of the ninth transistor Is coupled to the second control node; a tenth transistor having a control end, a first end, and a second end, wherein the control end of the tenth transistor is coupled to the third input node, The first end of the tenth transistor is coupled to the third supply potential, and the second end of the tenth transistor is coupled to the second control node; and an inverter coupled to The third supply potential has an input end and an output end, wherein the input end of the inverter is coupled to the second control node, and the output end of the inverter is coupled to the first A control node. The block decoder of the non-volatile memory of claim 12, wherein each of the fifth transistor, the ninth transistor, and the tenth transistor is a P-type gold oxide Half field effect transistor. The block decoder of the non-volatile memory of claim 12, wherein each of the sixth transistor, the seventh transistor, and the eighth transistor is an N-type gold oxide Half field effect transistor. A level shifter includes: a first transistor having a control terminal, a first terminal, and a second terminal, wherein the control terminal of the first transistor is coupled to a first control node The first end of the first transistor is coupled to an output node, and the second end of the first transistor is coupled to a first supply potential; and a second transistor has a control end a first end, and a second end, wherein the control end of the second transistor is coupled to a second control node, the first end of the second transistor is coupled to a ground potential, The second end of the second transistor is coupled to the output node; a third transistor has a control end, a first end, and a second end, wherein the control of the third transistor The first end of the third transistor is coupled to a first node, and the second end of the third transistor is coupled to a second supply potential; a fourth transistor having a control terminal, a first terminal, and a second terminal, wherein the control terminal of the fourth transistor is coupled to the second control node, the fourth transistor One end is coupled to the first node, and the second end of the fourth transistor is coupled to the output node. The level shifter of claim 15, wherein the first control potential of one of the first control nodes and the second control potential of the second control node have complementary logic levels. The level shifter of claim 15, wherein each of the first transistor, the second transistor, and the third transistor is an N-type MOS field effect transistor . The level shifter of claim 15, wherein the fourth transistor is a P-type MOS field effect transistor. The level shifter of claim 15, wherein each of the first transistor, the second transistor, and the fourth transistor is an enhancement transistor. The level shifter of claim 15, wherein the third transistor is a depletion transistor.