TWI639885B - Method for forming aligned mask, semiconductor device and method for forming a set of aligned mask - Google Patents

Abstract

A method of forming an alignment mask includes: etching a reference mark on a substrate to distinguish a boundary of an etched region; forming an etch mask on the substrate using an exposure setting value, the etch mask having a boundary; and measuring a reference mark and The distance between the boundaries. When the measured distance exceeds the tolerance of the target distance, the etching mask is removed from the substrate, the exposure setting is changed, the next exposure mask is formed using the changed exposure setting, and the measurement is repeated. A set of reference marks can be etched on the top level of a set of levels to distinguish the boundaries of each etched area. An etch-finishing process can be performed to form a step in the set of levels, wherein the etch-trimming process includes at least a first etch-trim cycle and a second etch-trim using a first reference mark and a second reference mark cycle.

Description

Method of forming an alignment mask, semiconductor device, and method of forming a set of alignment masks

The present technology is generally related to high density integrated circuit (IC) devices, and more particularly to methods of forming a mask having a large size.

Forming an etched mask having a large size can be challenging during the fabrication of the memory device. This is because the size of the etch mask between the two opposing boundaries may be so large that only one of the two opposing boundaries can be monitored inline at a time (eg using an online scanning electron microscope) Microscope, SEM)). In other words, the large size pattern of the etched mask may make the two opposing boundaries of the etch mask impossible to monitor at the same time. Therefore, it is difficult to directly measure the size and continuity of the large etching mask between two opposite boundaries on the line to adjust the size of the etching mask accordingly. When such large sizes must be measured, manufacturers may need to remove wafers from the manufacturing line and use specialized off-line measurement equipment.

It would be desirable to provide a technique that can form a detailed etch mask having a large size that may be difficult to measure online.

A method of forming an alignment mask is described. The method includes etching a reference mark on a substrate to distinguish a boundary of an etched region, forming an etch mask on the substrate using an exposure setting, the etch mask having a boundary, and measuring the The distance between the reference mark and the boundary of the etch mask. When the measured distance exceeds the tolerance of the target distance, the etching mask may be removed from the substrate, the exposure setting value may be changed, and the changed exposure setting value may be used to form a next The mask is etched and the measurement step can be repeated. The etch mask can be used in an etch process when the measured distance is within the tolerance.

The exposure setting may include exposure energy calibrated to form the etch mask and a focus center. The etching process can include etching a recess in the substrate using the etching mask to transfer the reference mark to a bottom of the recess. The etching process can include forming an array of memory in the recess.

Described a device comprising: a substrate comprising a recess extending into the substrate; and a reference mark on a bottom of the recess, between the reference mark and a side of the recess The distance is within the tolerance of the target distance. The target distance between the reference mark on the bottom of the depressed portion and one side of the depressed portion and the boundary between the reference mark on the upper surface of the substrate and the etching mask for etching the depressed portion may be They are different and have different values. The tolerance between the reference mark on the bottom of the recess and the target distance between one side of the recess is between the reference mark on the upper surface of the substrate and the boundary of the etch mask used to etch the recess The tolerance of the target distance can be different and have different values. The difference may be due to the slope of the boundary of the etch mask, the slope of the side of the recess, or other factors. The reference mark may be disposed parallel to the one side of the recess. A memory array can be disposed in the recess.

A method of forming a set of alignment masks is illustrated. The method includes etching a set of reference marks on a top level in a set of levels on a substrate to distinguish boundaries of each etched area; and performing an etch-trimming process to form the set of layers Forming a step at each of the steps in the step, wherein the etch-trimming process includes at least a first etch-trim cycle using a first one of the set of reference marks and a second one of the set of reference marks A second etch-trim cycle of the reference mark.

The first etch-trim cycle can include forming a first etch-trim mask on the top level using a first exposure setting, the first etch-trim mask having a first boundary; and measuring a first distance between the first reference mark of the set of reference marks and the first boundary of the first etch mask.

When the measured first distance exceeds the tolerance of the first target distance, the first etching mask may be removed from the top layer, and the first exposure setting may be changed; The subsequent first exposure setting forms a next first etch mask and the measurement step can be repeated. The first etch mask may be used in a first etch-trimming process when the measured first distance is within the tolerance. The first exposure setting may include exposure energy and a focal point that are calibrated to form the first etch-trim mask.

In one example described herein, the set of levels includes W levels L(i), where i is 1 to W. The first etch-trimming process may include repeatedly trimming the first etch-trim mask in the first etch-trim cycle and etching one using the trimmed first etch-trim mask Levels up to a first number of N1 repetitions to form N1 steps on N1 respective levels L(i), where i is W-N1 to W-1, wherein the N1 steps are set to A reference mark and the second reference mark. The first etch-trimming process may transfer the first reference mark from a top level L(W) of the set of levels to a level L of the set of levels (W-N1- 1).

The second etch-trim cycle can include forming a second etch-trim mask on the top level using a second exposure setting, the second etch-trim mask having a second boundary; and measuring a second distance between the second one of the set of reference marks and the second boundary of the second etched trim mask.

When the measured second distance exceeds the tolerance of the second target distance, the second etching mask may be removed from the top layer, and the second exposure setting may be changed; The subsequent second exposure setting forms a next second etching mask, and the step of measuring the second distance may be repeated. The second etch mask can be used in the second etch-trimming process when the measured second distance is within the tolerance. The second exposure setting may include exposure energy and a focal point that are calibrated to form the second etch-trim mask.

The set of levels includes W levels L(i), where i is 1 to W. The second etch-trimming process may include repeatedly trimming the second etch-trim mask in the second etch-trim cycle and etching one using the trimmed second etch-trim mask Levels up to a second number N2 repetitions to form N2 steps on N2 respective levels L(i), where i is W-N2 to W-1, wherein the N2 steps are set to Between the two reference marks and the third one of the set of reference marks. The second etch-trimming process may transfer the second reference mark from a top level L(W) of the set of levels to a level L of the set of levels (W-N2- 1) and transferring the first reference mark from the level L (W-N1-1) in the set of levels to a level L (W-N1- in the set of levels) N2-2).

The first exposure setting may be different from the second exposure setting, and the first target distance may be different from the second target distance. The first number of steps formed in the first etch-trim cycle may be different than the second number of steps formed in the second etch-trim cycle. The etch-trim process can include more than one etch-trim cycle using more than one etch-trim mask.

An apparatus is illustrated that includes a set of levels on a substrate, the set of levels comprising W steps L(i), where i is 0 to W. The set of levels includes a first subset of at least the level L(i), where i is 0 to N1, and the first reference mark is disposed in the level L(0) of the first subset. a distance between the first reference mark in the level L(0) in the first subset and a first boundary of the level L(1) in the first subset is at a first target distance Within the tolerance.

The set of levels includes a second subset of the levels L(i), where i is N1+1 to N1+1+N2, and the second reference mark is set to the level L (N1) in the second subset +1). a second distance between the second reference mark in the level L(N1+1) and a second boundary of the level L(N1+2) in the second subset is at a second target distance Within tolerance.

The second target distance may be different from the first target distance. The first subset of the set of levels has a first number of levels, the second subset of the set of levels has a second number of levels, and the first number of stages may be different The number of steps in the second layer. Each of the levels in the set of levels L(i) may comprise a layer of electrically conductive material and a layer of insulating material, where i is from 1 to W. Other aspects and advantages of the present techniques can be seen by reading the drawings, the detailed description, and the accompanying claims.

The following description will be generally made with reference to specific structural examples and methods. It should be understood that the present invention is not intended to be limited to the details of the embodiments disclosed herein. The preferred embodiments are set forth to illustrate the teachings of the present invention and are not intended to limit the scope of the present invention, which is defined by the scope of the claims. Those of ordinary skill in the art will recognize the various equivalent variations described below. The same elements in the various embodiments are generally referred to by the same reference numerals.

1 is a simplified cross-sectional view of a semiconductor device structure showing the result of forming an etch mask 141 on a substrate 110, wherein the etch mask 141 has a boundary 145, and the substrate can have a layer 120 of insulating material on the upper surface.

Although the boundary 145 of the etch mask is shown, another boundary at the opposite side of the etch mask 141 is not shown, which indicates that the size of the etch mask is too large so that the etch can only be easily monitored at a time One of the two opposing boundaries of the mask (eg, using a scanning electron microscope (SEM)). In other words, the large size of the etch mask makes it impossible to simultaneously monitor the two opposing boundaries of the etch mask. Therefore, it is difficult to directly measure the size of the etching mask between two opposing boundaries and adjust the etching mask accordingly.

In order for the etch mask to be formed to a specified size between two opposing boundaries, the two opposing boundaries should be two on each side of the etched mask and two ideal on the wafer. Positioning. One of the two ideal positions (eg, ideal position 105) is shown at one side of the etch mask, and the two ideal positions are not shown at the opposite side of the etch mask The other one. The ideal location may not be a physical feature on the substrate. Rather, the ideal location can be a nominally defined location in the layout of the device.

In this example, the ideal location 105 is between the boundary 145 of the etch mask 141 and another boundary of the etch mask 141 opposite the boundary 145, such that the distance 115 between the ideal location 105 and the boundary 145 may be too large, such that The position of the mask is not aligned. In other words, the distance between the boundary 145 and the other boundary of the etch mask 141 opposite the boundary 145 may be too large.

2 is a simplified cross-sectional view of the structure of a semiconductor device showing the result of forming an etch mask 142 on substrate 110, wherein etch mask 142 has a boundary 146. In this example, the boundary 146 is between the other boundary of the etch mask 142 opposite the boundary 146 and the ideal location 105, such that the distance 116 between the ideal location 105 and the boundary 146 may be too large in the opposite direction. In other words, the distance between the boundary 146 and the other boundary of the etch mask 142 opposite the boundary 146 may be too small.

3 through 9 illustrate an example of a process step used in the process of forming an alignment mask.

3 is a simplified cross-sectional view of a portion of an integrated circuit device structure showing the result of etching reference marks 330 on substrate 310 to distinguish the boundaries of the etched regions. The ideal position of the boundary of the etched region is shown by dashed line 305. The reference mark can be etched using a dry etch or a wet etch using a reference mark etch mask. The reference mark etch mask can be combined with other processes to save process steps and costs.

The substrate in this example may include a layer of insulating material 320 on the upper surface of the substrate. Reference mark 330 can penetrate the layer of insulating material 320 and into the underlying material in substrate 310. In one embodiment, the next process step after the process step for etching the reference mark may be to perform a deep N-well implant (not shown). The insulating material layer 320 prevents a tunneling effect from occurring at the next process step. The reference mark can have a depth of, for example, about 140 nanometers (nm) and a width of about 150 nanometers, and the layer of insulating material can have a thickness of about 20 nanometers.

4 is a simplified cross-sectional view showing the structure of the result of forming a mask material layer 440 (including a reference mark 330) on a substrate. The mask material can be a photoresist material or a different type of mask material.

FIG. 5 is a simplified cross-sectional view showing the structure of the result of forming a first etch mask 540 on a substrate using exposure setting values for the mask material layer 440. The first etch mask 540 has a boundary 545. The exposure settings may include exposure energy and focal point calibrated to form an etch mask, and the exposure settings will be further illustrated in conjunction with FIGS. 11-13 and 14A/FIG. 14B/FIG. 14C. Reference mark 330 is disposed parallel to the boundary 545 of the first etch mask 540. For example, an Esmolar (ASML) exposure scanner, a Canon exposure scanner, and a Nikon exposure scanner, etc., can be used in semiconductor manufacturing lithography equipment such as exposure energy and focus in lithography and etching processes. Point and other parameters.

Although the boundary 545 of the first etch mask is shown, another boundary at the opposite side of the first etch mask 540 is not shown, which indicates that the size of the first etch mask is too large for each time only One of the two opposing boundaries of the first etch mask is easily monitored (eg, using an on-line metrology tool, such as an on-line scanning electron microscope (SEM)).

The distance 520 between the reference mark 330 and the boundary 545 of the first etch mask 540 can be measured, for example, using an on-line scanning electron microscope. The first side of the reference mark is adjacent to the boundary and the second side is away from the boundary. In one embodiment, the distance is measured between the boundary and a first side of the reference mark proximate the boundary (as presented in a top view scanning electron microscope image), the distance may be indicated For example, the position of the boundary at the step where the bottom of the first etching mask is disposed. When the measured distance 520 exceeds the tolerance of the target distance (eg, +/- 5% to 10% of the target distance), the first etching mask 540 may be removed from the substrate 310, and the exposure setting value may be changed. The next exposure mask is formed using the changed exposure settings, and the measurement step can be repeated.

A target distance with tolerance is specified between the reference mark and the boundary of the etched area. In one embodiment, the target distance having a tolerance is defined between a boundary of the first etch mask and a first side of the reference mark, the first side being disposed at the bottom of the first etch mask The hierarchy is immediately adjacent to the boundary. Depending on the particular measurement tool or technique, measurements can be made between other features of the reference mark and the boundary. In one embodiment, the target distance can be between about 500 nanometers (nm) and 800 nanometers, and the tolerance can be +/- 50 nanometers. When the measured distance is within tolerance (this indicates that the boundary 545 of the first etch mask 540 is aligned with the ideal location 305), the first etch mask 540 can be used in the etch process.

6 is a simplified cross-sectional view showing the structure of the result of using the first etch mask 540 in the etching process when the measured distance is within tolerance, in the Z-Y plane. The etch process can include etching the recess 610 in the substrate 310 using dry etching or wet etching using the first etch mask 540. The depth 655 of the recess 610 can be, for example, about 1950 nm. In the case where a large memory array is implemented in the recess, the dimension between the two opposing boundaries of the recess may be, for example, between 500 micrometers (μm) and 10,000 micrometers. The etching process can transfer the reference mark 330 to the bottom of the recess. The slope of the side 615 of the recess 610, the measurement technique, or other factors such that the distance 620 between the transferred reference mark 630 and the side 615 of the recess 610 may be slightly different than the measured distance within the tolerance of the target distance. 520.

FIG. 7 is a simplified plan view showing the structure of a reference mark 630 disposed parallel to the side 615 of the recess 610 in the X direction orthogonal to the Z-Y plane.

FIG. 8 is a diagram showing the formation of an active layer (eg, 8.1 to) separated by an insulating material (eg, 810) over the recess 610 (including over the transferred reference mark 630 at the bottom of the recess 610). 8.8) A simplified top view of the resulting structure of the stack.

9 is a view showing a stack of active layers in an etched recess to form an array region 920 and a transferred reference mark 630 to be disposed in the recessed portion between an upper surface of the substrate and a bottom of the recess. A simplified cross-sectional view of the resulting structure of the spaced apart isolation regions 910. The array region can include a stack of active layers for forming a memory array in the recess. In one embodiment, as shown in the example shown in FIG. 9, the residue of material in the stack between the isolation region 910 and the perimeter region 930 will cover the transferred reference mark at the bottom of the recess. In an alternative embodiment, as described in connection with FIG. 16F, the transferred reference mark can be disposed at the bottom of the recess in the isolation region 910 and is not covered by the residue.

Figure 10 illustrates a simplified flow diagram of the process steps used in forming the alignment mask. At step 1011, reference marks are etched on the substrate to distinguish the boundaries of the etched regions as described in connection with FIG. At step 1012, an etch mask is formed on the substrate using exposure settings as described in connection with Figures 4 through 5, wherein the etch mask has a boundary.

At step 1013, the distance between the reference mark and the boundary of the etch mask is measured, for example, using an on-line scanning electron microscope. At step 1014, it is determined whether the measured distance exceeds the tolerance of the target distance or is within the tolerance of the target distance. At step 1015, when the measured distance exceeds the tolerance of the target distance, the etching mask can be removed from the substrate, the exposure setting value can be changed, and the next exposure mask can be formed using the changed exposure setting value (step 1012) And the measurement step 1013 can be repeated.

At step 1016, an etch mask can be used in the etch process when the measured distance is within tolerance. As described in connection with FIG. 6, the etching process can include etching the recesses in the substrate using an etch mask to transfer the reference marks to the bottom of the recesses.

Figure 11 illustrates a simplified flow diagram of the process steps used in calibrating the exposure setpoints for forming an alignment mask as described in connection with Figures 3-7 and 10. At step 1111, reference marks are etched on the substrate to distinguish the boundaries of the etched regions as described in connection with FIG.

At step 1112, an exposure setting is selected from a plurality of exposure settings, which will be explained in conjunction with FIG. At step 1113, an etch mask is formed on the substrate using the selected exposure setting, wherein the etch mask has a boundary. The process of forming an etch mask on a substrate is illustrated in conjunction with FIGS. 4 through 5.

At step 1114, the distance between the reference mark and the boundary of the etch mask is measured, for example, using an on-line scanning electron microscope. At step 1115, it is determined whether the measured distance exceeds the tolerance of the target distance or is within the tolerance of the target distance. At step 1116, the etch mask can be removed from the substrate when the measured distance exceeds the tolerance of the target distance. Different exposure settings may be selected (step 1112), the next exposure mask may be formed using the different exposure settings (step 1113), and the measurement step may be repeated (step 1114).

At step 1117, when the measured distance is within the tolerance of the target distance, then a set of exposure settings from the calibration can be stored, and thus the exposure settings from the calibration set can be selected to be in one or Process steps for forming an alignment mask when multiple wafers are produced on multiple wafers are used together. For example, an exposure setting from a calibration set can move the boundary of the etch mask in one direction to increase the distance between the reference mark and the boundary, while another exposure setting from the calibration set can be another The boundary of the etch mask is moved in one direction to reduce the distance between the reference mark and the boundary.

The calibration set can include a particular exposure setting that causes the measured distance to be within tolerance. This particular exposure setting can be stored as an optimal exposure setting and used as a first choice for the process steps of forming an alignment mask when producing multiple wafers on one or more wafers. For each exposure setting in the calibration set, the stored parameters may include exposure energy, a focal point, and a corresponding distance between the reference mark and the boundary of the etch mask.

Figure 12 illustrates an example of a model of exposure energy and focal point that exhibits multiple exposure settings. The model shows the measured distance (in nanometers (nm)) between the reference mark and the boundary of the etch mask as the exposure energy (in millijoules per square centimeter (milli-Joule/cm ² )) and the center of focus The point (in micrometers (μm)) varies. For example, for a target distance of 700 nm (tolerance of +/- 50 nm), the measured distance corresponding to the exposure energy of 40.26 mJ/cm 2 and the focal point of 1.61 μm is more than the other in the model. The measured distance is closer to the tolerance of the target distance. In this example, the optimal exposure setting includes an exposure energy of 40.26 mJ/cm 2 and a focal point of 1.61 micron. The stored exposure setpoint may include a nominally optimal exposure setpoint derived as a starting point during calibration, an exposure setpoint that forms a distance within a tolerance of the target distance, or all exposure settings having a measured distance value. Additionally, the performance indicator can be stored with the stored exposure settings to indicate how to select the next exposure setting to move the etch mask in a certain direction when the alignment mask is formed using the stored exposure settings. The boundary increases or decreases the distance between the reference mark and the boundary of the etch mask.

FIG. 13 is a graph showing a curve in which the measured distance between the reference mark and the boundary of the etching mask varies with exposure energy and a focal point. The area between the upper curve 1451 and the lower curve 1453 includes the measured distance within the tolerance of the target distance. Conversely, the area other than between the upper curve 1451 and the lower curve 1453 is the measured distance exceeding the tolerance of the target distance. In this example, the dashed curve 1452 corresponds to the distance predicted to reach or very close to the target distance of 700 nm as predicted using the experimental data shown in FIG. The dashed curve may include a nominally optimal exposure setting with an exposure energy of 40.26 millijoules per square centimeter and a focal point of 1.61 micron.

Figure 14A illustrates the distance 1420 between the reference mark 1430 and the boundary 1415 of the etch mask 1410 in a cross-sectional view of the structure. In one embodiment, as shown at 1420, the measurement can be made from the proximal side of the reference mark to the feature at the bottom edge of the etch mask. In an alternative form, as shown at 1420', the measurement can be made from the distal side of the reference mark to the feature at the top edge of the etch mask. The distance can be measured using an online metrology tool such as an on-line scanning electron microscope (SEM) for generating a bird's-eye view image that can be directly measured thereon. The measurement result can be compared to a tolerance of the target distance to determine an exposure setting value within the tolerance and an optimal exposure setting value that can be closer to the target distance than other exposure setting values. A set of exposure settings from the calibration (including the optimal exposure settings and some other exposure settings) can be stored, so the exposure settings from the calibration set can be selected to generate multiple wafers on one or more wafers. The process steps that form the alignment mask are used together.

Figure 14B illustrates that selecting an exposure setting from a plurality of exposure settings in a calibration process can create different distances between the reference mark and the boundary of the etch mask. For example, FIG. 14B illustrates a total of eight images of four columns and two rows in a top view of the structure shown in FIG. 14A. Each of the eight images illustrates a reference mark, a boundary of the etch mask, and a distance between the reference mark and a boundary of the etch mask. Each of the eight images corresponds to a respective exposure setting value and a distance obtained from the exposure setting value. For example, the image in the upper left corner corresponds to an exposure setting including an exposure energy of 32 millijoules per square centimeter and a focal point of -0.7 micrometers and a first distance. The image in the lower right corner corresponds to an exposure setting including 46 mJ/cm 2 of exposure energy and a 0.7 micron focal point and a second distance different from the first distance. The change in exposure energy and focal point causes the boundary width of the image in Fig. 14B to be different.

Figure 14C is an illustration of the reference mark 1430, the boundary 1415 of the etch mask 1410, and the distance 1420 between the reference mark and the boundary of the etch mask (same as the image in Figure 14B). The reference mark is placed parallel to the boundary of the etching mask. The width of the reference mark may be from about 150 nm to 1,000 nm as constrained by factors such as: on-line scanning electron microscope measurement magnification, on-line scanning electron microscope measurement failure rate, and for etching, for example, depressions or Process design of circuit features (including reference marks) such as stairs. For example, for a process that uses a reference mark to form a step, the width of the reference mark (eg, 150 nm) must be less than the width of the step in the step (eg, 500 nm).

Figure 15A illustrates a lithographic mask pattern 1510 for a mask for making reference marks on a substrate. The mask pattern 1510 includes a reference mark pattern 1515 for reference marks, the reference mark pattern 1515 is in the shape of a line surrounding a rectangular perimeter and is located in an array area for forming a memory array and a peripheral area for forming a peripheral circuit system. between.

Figure 15B illustrates a lithographic mask pattern 1520 for a mask for making a recess in a substrate. The mask pattern 1520 includes a rectangle (eg, 1525) in which a recess of the array region may be disposed.

15C is a simplified top plan view showing the structure of etching a reference mark 1530 on a substrate using a mask pattern 1510 and then using the mask pattern 1520 and forming an etch mask 1540 on the substrate using the exposure settings described herein. For clarity, the distance between the reference mark 1530 and the boundary of the etch mask 1540 is shown in FIG. 15D.

Figure 15D illustrates a cross-sectional view of the structure taken along line A-A' in Figure 15C. FIG. 15D illustrates the distance 1535 between the reference mark 1530 and the boundary 1545 of the etch mask 1540 on the substrate 310.

16A-16F illustrate an alternative lithographic mask pattern of reference marks in a reference mark etch mask for exposing photoresist during formation of a reference mark pattern. Figure 16A illustrates four "L" shaped lines (e.g., 1601a, 1601b, between the array regions used to form the memory array and the peripheral regions used to form the peripheral circuitry, at respective corners of the rectangular perimeter). 1601c, 1601d) A mask pattern of the shape formed, wherein each of the "L" shaped lines includes two sections oriented transversely to each other.

Figure 16B illustrates a mask pattern in the shape of an array region for forming a memory array and a peripheral region for forming a peripheral circuitry, in the form of two lines (e.g., 1602a, 1602b) around the perimeter of the rectangle. The two lines are arranged parallel to each other and opposite each other.

16C illustrates a mask pattern in a shape formed by four lines around a rectangular perimeter between an array region for forming a memory array and a peripheral region for forming a peripheral circuit system, wherein the four lines are not in each other Connected and includes a first two parallel lines (eg, 1603a, 1603b) and a second two parallel lines (eg, 1603c, 1603d) that are orthogonal to the first two parallel lines.

Figure 16D illustrates a mask pattern in the shape of a first pair of lines (e.g., 1604a, 1604b) and a second pair of lines (e.g., 1604c, 1604d), the first pair of lines being in the array area in a first direction The ends are opposite each other, the second pair of lines being opposite each other at both ends of the array region in a second direction orthogonal to the first direction, wherein the line in the second pair comprises a segmented segment .

Figure 16E illustrates a mask pattern in the shape of a concentric rectangular perimeter (e.g., 1605a, 1605b, 1605c). Figure 16F illustrates a cross-sectional view of the structure taken along line B-B' in Figure 16E. Figure 16F illustrates a first rectangle (e.g., 1605a) disposed at the bottom of the recess 610 in the isolation region 910 in the perimeter of the concentric rectangle, disposed at the bottom of the recess 610 between the isolation region 910 and the peripheral region 930 in the concentric rectangular perimeter The second rectangle (eg, 1605b) and the third rectangle (eg, 1605c) disposed in the perimeter region 930 in the perimeter of the concentric rectangle.

17 through 23 illustrate an example of a process step used in forming a set of alignment masks on a set of levels on a substrate. 17 is a simplified cross-sectional view of a portion of an integrated circuit device structure showing etching of a set of reference marks (eg, 1731 to 1736) on a top level in a set of levels (eg, 1720) on substrate 1710. The result of distinguishing the boundaries of each etched zone. In one embodiment, the set of levels may include 39 levels, and each of the set of layers may include a sacrificial material (eg, SiN) layer and an insulating material layer. The set of reference marks can be formed on the set of levels using a reference mark etch mask prior to forming any other etch mask on the set of layers. After etching the set of reference marks to form the reference mark, the reference mark etch mask is removed.

After the etch-trimming process described herein has been performed to form a step at each of the set of levels, a further process step can be taken to replace the sacrificial material in the set of layers with a conductive material to Each of the set of layers includes a layer of conductive material and a layer of insulating material. Replacing the sacrificial material with a conductive material can form a set of levels, wherein each of the set of layers can include a layer of conductive material and a layer of insulating material.

The conductive material in the set of layers may be: a conductive semiconductor, including heavily doped polysilicon (using dopants such as As, P, B, etc.); germanides, including TiSi, CoSi; oxide semiconductors, including InZnO, InGaZnO; and a combination of a semiconductor and a telluride. The conductive material may also be a metal, a conductive compound, or a combination of materials including Al, Cu, W, Ti, Co, Ni, TiN, TaN, TaAlN, and the like. The insulating material in the set of layers may comprise an oxide, a nitride, an oxynitride, a niobate or the like, depending on the applied fabrication technique. Preferably, a low dielectric constant material (for example, SiCHO _x ) having a dielectric constant smaller than the dielectric constant of cerium oxide can be used. A high dielectric constant (high k) material having a dielectric constant greater than the dielectric constant of cerium oxide (for example, HfO _x , HfON, AlO _x , RuO _x , TiO _x ) may also be included.

18 through 23 illustrate performing an etch-trimming process to form a step at each of the set of levels, wherein the etch-trimming process includes at least using a first one of the set of reference marks ( For example, a first etch-trim cycle of 1731) and a second etch-trim cycle using a second one of the set of reference marks (eg, 1732).

Figure 18 illustrates the result of forming a first etch-trim mask (e.g., 1840) on the top level of the set of levels 1720 using the first exposure setpoint in a first etch-trim cycle. The first exposure setting may include exposure energy and a focal point calibrated to form a first etch-trim mask. The first etch-trim mask has a first boundary 1845. A first distance 1850 between the first reference mark 1731 of the set of reference marks and the first boundary 1845 of the first etch-dressing mask 1840 can be measured, for example, using an on-line scanning electron microscope (SEM) or the like.

When the measured first distance exceeds the tolerance of the first target distance, the first etch-trim mask 1840 may be removed from the top level, the first exposure setting may be changed; the changed first exposure setting may be used The value forms a next first etch mask on the top level of the set of levels 1720, and the step of measuring the first distance can be repeated. A first target distance having a tolerance is defined between the first reference mark and the first boundary of the first etch-trim mask 1840. In one embodiment, the first target distance may be from about 100 nanometers (nm) to 1,000 nanometers, and the first target distance may have a tolerance of +/- 30 nanometers.

When the measured first distance 1850 is within tolerance of the first target distance, the first etch-trim mask 1840 can be used in the first etch-trimming process.

The set of levels includes W levels L(i), where i is 1 to W.

Figure 19 illustrates that the first etch-trim mask 1840 is repeatedly trimmed in a first etch-trim cycle and the first etch-trimming mask is used to etch a level up to a first number of N1 repetitions at N1 The result of forming N1 steps on the respective layer order L(i), where i is W-N1 to W-1, wherein the N1 steps are disposed between the first reference mark 1731 and the second reference mark 1732. The first etch-trimming process may transfer the first reference mark 1731 from the top level L(W) of the set of levels to the level L (W-N1-1) of the set of levels. The basic steps in the etch-trim cycle will be described in conjunction with Figures 24A, 24B, 24C, and 24D.

20 illustrates the result of forming a second etch-trim mask (eg, 2040) on the top level of the set of levels 1720 using the second exposure setpoint in a second etch-trim cycle. The second exposure setting may include exposure energy and a focal point calibrated to form a second etch-trim mask. The second etch-trim mask has a second boundary 2045. A second distance 2050 between the second reference mark 1732 of the set of reference marks and the second boundary 2045 of the second etch-dressing mask 2040 can be measured, for example, using an on-line scanning electron microscope or the like.

When the measured second distance 2050 exceeds the tolerance of the second target distance, the second etch-trimming mask 2040 may be removed from the top level, the second exposure setting may be changed; the changed second exposure may be used The set value forms a next second etch mask on the top level of the set of levels 1720, and the step of measuring the second distance can be repeated. A second target distance having a tolerance is defined between the second reference mark and the second boundary of the second etch-trim mask 2040. The tolerance of the second target distance and the second target distance may be different from the tolerance of the first target distance and the first target distance described in connection with FIG.

When the measured second distance 2050 is within the tolerance of the second target distance, the second etch-trim mask 2040 can be used in the second etch-trimming process.

Figure 21 illustrates that the second etch-trim mask 2040 is repeatedly trimmed in a second etch-trim cycle and the second etch-trimming mask is used to etch a layer to a second number N2 times to repeat at N2 a result of forming N2 steps on the respective layer order L(i), where i is W-N2 to W-1, wherein the N2 steps are disposed in the second reference mark 1732 and the first of the set of reference marks The three reference marks are between 1733. The second etch-trimming process may cause the second reference mark 1732 to be transferred from the top level L(W) of the set of levels to the level L (W-N2-1) of the set of levels And shifting the first reference mark from the level L (W-N1-1) in the set of levels to the level L (W-N1-N2-2) in the set of levels. The basic steps in the etch-trim cycle will be described in conjunction with Figures 24A, 24B, 24C, and 24D.

The first exposure setting may be different from the second exposure setting, and the first target distance may be different than the second target distance. The first number of steps formed in the first etch-trim cycle may be different than the second number of steps formed in the second etch-trim cycle. The etch-trimming process includes more than one etch-trim cycle using more than one etch-trim mask, such as a first etch-trim cycle using a first etch-trim mask and a second etch-trim mask A second etch-trim cycle is performed.

In one embodiment, the number of levels in the set of levels may be 39, and the first number N1 of repetitions in the first etch-trim cycle may be 7, repeating in the second etch-trim cycle The second number N2 may be 6, and the number of repetitions in the third etch-trim cycle to the sixth etch-trim cycle may be five. Those of ordinary skill in the art can determine the number of repetitions (including N1 and N2) in all etch-trim cycles in an etch-trim process based on, for example, the number of levels in a set of levels, The thickness of the layer of the sacrificial material layer and the insulating material layer, the thickness of the etching-trimming mask, the width of the step, and the etch recipe are included in a set of layers.

22 illustrates the results of forming a third etch-trim mask (eg, 2240) on the top level of the set of levels 1720 using a third exposure setting in a third etch-trim cycle. The third exposure setting may include exposure energy and a focal point that are calibrated to form a third etch-trim mask. The third etch-trim mask has a third boundary 2245. A third distance 2250 between the third reference mark 1733 of the set of reference marks and the third boundary 2245 of the third etch-dressing mask 2240 can be measured, for example, using an on-line scanning electron microscope or the like.

When the measured third distance 2250 exceeds the tolerance of the third target distance, the third etching-trimming mask 2240 may be removed from the top level to change the third exposure setting; the changed third exposure may be used. The set value forms a next third etch mask on the top level of the set of levels 1720, and the measuring step of measuring the third distance may be repeated. A third target distance having a tolerance is defined between the third reference mark and the third boundary of the third etch-trim mask 2240. The tolerance of the third target distance and the third target distance may be different from the tolerance of the second target distance and the second target distance described in connection with FIG.

When the measured third distance 2250 is within a tolerance of the third target distance, a third etch-trim mask 2240 can be used in the third etch-trimming process.

The etch-trim process described herein, including the process steps described in connection with Figures 17 through 23, may be repeated to achieve more etch-trim cycles using more etch-trim masks with more reference marks until All of the steps are formed at each of the set of levels shown in FIG. Further processing steps can be performed on the device structure shown in Figure 23 during the manufacture of a three dimensional (3D) memory device.

Figure 23 illustrates the structure of a device formed in accordance with the methods described herein. The structure includes a set of levels 1720 on a substrate 1710 that includes W levels L(i), where i is 0 to W. The set of levels includes a first subset of at least a level L(i), where i is 0 to N1, and a first reference mark 1731 is disposed in the level L(0) of the first subset. The distance between the first reference mark in the level L(0) of the first subset and the first boundary of the level L(1) in the first subset is within a tolerance of the first target distance. a first reference mark in the level L(0) of the first subset and a level L(1) of the first subset (eg, L(0) and L(1) in FIG. 23) The tolerance of the first target distance between the first boundaries and the first reference mark on the top level in a set of levels (eg, 1720) (eg, 1731 in FIG. 18) and the first etch-trimming hood The tolerance of the target distance between the first boundary of the curtain (eg, 1840 in FIG. 18) (eg, 1845 in FIG. 18) may be different and have different values.

The set of levels includes a second subset of the levels L(i), where i is N1+1 to N1+1+N2, and the level L(N1+1) in the second subset is set The second reference numeral 1732. A second distance between the second reference mark in the level L(N1+1) and the second boundary of the level L(N1+2) in the second subset is within a tolerance of the second target distance.

The second target distance may be different from the first target distance. The first subset of the set of levels has a first number of levels, the second subset of the set of levels has a second number of levels, and the first number may be different from the first Two numbers. In one embodiment, each of the set of levels L(i) may comprise a layer of sacrificial material and a layer of insulating material, where i is from 1 to W.

24A, 24B, 24C, and 24D are simplified diagrams illustrating the basic steps used in an etch-trim cycle that can be used in an example of the techniques described herein. These figures show that the multi-level circuit structure on the integrated circuit includes a stack 10 of interleaved sacrificial layers 12 and dielectric layers 14. The specific sacrificial layer and dielectric layer are identified as sacrificial layers 12.1, 12.2, 12.3 and dielectric layers 14.1, 14.2, 14.3. In this example, each level includes a sacrificial layer (eg, 12.2) and a dielectric layer (eg, 14.2) underlying the sacrificial layer. In an alternative embodiment, each level includes a dielectric layer and a sacrificial layer underlying the dielectric layer. In this alternative form, the etch chemistry is selected to terminate on the dielectric layer in each layer rather than terminating on the sacrificial layer.

Etching of the stack 10 of sacrificial layer 12 and dielectric layer 14 will use an etch-trim mask to expose the landing areas 28.1, 28.2, 28.3. FIG. 24A shows an etch-trim mask 16.0 that includes a mask region 18 and an open etch region 20. For the etch-trim mask 16.0, a first etching mask is used to etch a layer. A reference mark (eg, 31) is formed on a top level of a set of levels including a sacrificial layer (eg, 12.3) and a dielectric layer (eg, 14.3). The distance between the reference mark and the boundary of the etch-trim mask 16.0 (eg, 32) is within the tolerance of the first target distance. 24B shows the result of etching one level through the top sacrificial layer 12.3 and the dielectric layer 14.3 at the open etched region 20 and terminating at the second sacrificial layer 12.2, which transfers the reference mark 31 to the set of layers. The underlying layer includes a sacrificial layer (eg, 12.2) and a dielectric layer (eg, 14.2). Figure 24C shows that the result of trimming the first etch-trim mask 16.1 shown in Figure 24B will result in having a masked mask region 24, a new open etch region 25, and an extended open etch region 26 (region 26 equals region 20 plus The trimmed first etch-trim mask 16.1 of zone 25). 24D shows the result of etching a layer of the structure shown in FIG. 3C at the extended open etch region 26, which transfers the reference mark 31 to the underlying one of the set of layers including the sacrificial layer (eg, 12.1). And the level of the dielectric layer (for example, 14.1). The resulting structure has exposed sacrificial overlapping regions identified as 28.1, 28.2, and 28.3. Zone 28.3 is considered to be exposed because it will be exposed when the trimmed first etch-trim mask 16.1 is removed. The resulting structure includes reference marks (eg, 31) disposed at the bottom level of the stack 10.

24A, 24B, 24C, and 24D illustrate a two-step etch-trim cycle for forming a step structure having sequential overlapping regions on three levels. As described herein, an etch-trim cycle using a single start mask (eg, mask 16.0) can be used to form more than two steps (including, for example, 4, 5, 6, 8, or any number) Stairs).

To form a larger number of steps using an etch-trim cycle, the starting mask must be thicker to accommodate erosion of the mask during each of the trim cycles. When using a thicker mask, in some techniques, the size of the contact area must be relatively large to maintain sufficient tolerance for the lithographic steps.

In addition, an etch-dressing process including multiple etch-trim cycles can be used to form a larger number of steps using one start mask per cycle. For example, one start mask can be used to form eight steps within seven trim cycles, and a second start mask can be used to form the other eight of the total of 16 steps in sequence.

The photoresist can be used to etch-trim masks 16.0 and 16.1. The finishing process of the photoresist mask is usually isotropic or multi-directional. This causes loss of the photoresist mask in the X direction, the Y direction, and the Z direction. Loss in the Z direction may limit the number of levels that will be etched in a given etch-trim cycle.

Figure 25 illustrates a simplified flow diagram of the process steps used in forming an alignment mask on the top level of a set of levels on a substrate. At step 2511, reference marks in a set of reference marks are etched on the substrate to distinguish the boundaries of the etched regions as described in connection with FIG. At step 2512, a first etch-trim mask is formed on the top level using a first exposure setting as described in connection with FIG. 18, wherein the first etch-trim mask has a first boundary.

At step 2513, a first distance between the first reference mark and the first boundary of the first etch mask is measured, for example, using an on-line scanning electron microscope. At step 2514, it is determined whether the measured first distance exceeds the tolerance of the first target distance or is within the tolerance of the first target distance. At step 2515, when the measured first distance exceeds the tolerance of the first target distance, the first etching mask may be removed from the substrate, the first exposure setting may be changed, and the changed first exposure setting may be used. The value forms the next first etch mask (step 2512) and the measurement step 2513 can be repeated.

At step 2516, as described in connection with FIG. 19, when the measured first distance is within the tolerance of the first target distance, the first etching mask may be used to form N1 steps in the first etching-dressing process a subset of.

As described in connection with FIG. 20, when a subset of N1 steps is formed, a second etch-trim mask can be formed on the top level using the second exposure setting, wherein the second etch-trim mask has Two boundaries. A second distance is measured between the second reference mark and a second boundary of the second etch mask.

When the measured second distance exceeds the tolerance of the second target distance, the second etching mask may be removed from the substrate, the second exposure setting value may be changed, and the changed second exposure setting value may be used to form the next The mask is etched, and the measuring step of measuring the second distance may be repeated. As described in connection with FIG. 21, when the measured second distance is within the tolerance of the second target distance, a second etch mask can be used in the second etch-trimming process.

The various process steps as described in the process of forming the alignment mask can be continued in a similar manner to form all of the alignment masks required to form the steps at each of the set of levels. After forming a step at each of the set of levels, the sacrificial material in the set of layers may be replaced by a conductive material such that each of the set of layers includes a layer of conductive material and insulation Material layer.

Figure 26 illustrates a simplified flow diagram of the process steps used in the process of calibrating the exposure setpoints by forming an alignment mask on the top level of a set of levels on the substrate as described in connection with Figures 17-23. In one embodiment, each of the set of levels may include a sacrificial material (eg, SiN) layer and an insulating material layer. At step 2611, reference numerals in a set of reference marks are etched on the substrate to distinguish the boundaries of the etched regions, for example, as described in connection with FIG.

At step 2612, the first exposure setting is selected from a plurality of exposure settings, such as illustrated by the model of exposure energy and focal point in FIG. At step 2613, a first etch-trim mask is formed on the top level using the selected first exposure setting. For example, in conjunction with FIG. 18, the first etch-trim mask has a first boundary.

At step 2614, a first distance between the first reference mark and the first boundary of the first etch mask is measured, for example, using an on-line scanning electron microscope. At step 2615, it is determined whether the measured first distance exceeds the tolerance of the first target distance or is within the tolerance of the first target distance. At step 2616, the first etch mask can be removed from the substrate when the measured first distance exceeds the tolerance of the first target distance. Subsequently, different first exposure settings may be selected from the plurality of exposure settings (step 2612), and the next first exposure mask may be formed using the changed first exposure settings (step 2613), and The measurement step 2614 is repeated (step 2614).

At step 2617, when the measured first distance is within the tolerance of the first target distance, then a set of first exposure settings from the calibration may be stored, and thus the first exposure setting from the calibration set may be selected to Used in conjunction with the process steps of forming an alignment mask when producing multiple wafers on one or more wafers. For example, a first exposure setting from the calibration set can cause a first boundary of the first etch mask to be moved in a direction to increase a first distance between the first reference mark and the first boundary, And another first exposure setting from the calibration set may cause the first boundary of the first etch mask to be moved in another direction to reduce between the first reference mark and the first boundary The first distance.

The first set of calibrations can include a particular first exposure set point that causes the measured first distance to be within tolerance. This particular first exposure setting can be stored as an optimal first exposure setting and used to form an alignment mask on a set of levels on the substrate when the plurality of wafers are produced on one or more wafers The first choice of the process steps. For each exposure setting in the first set of calibrations, the stored parameters may include an exposure energy, a focal point, and a first reference mark of the set of reference marks and a first boundary of the first etch mask Corresponds to the first distance. For example, in conjunction with FIG. 19, when the measured first distance is within a tolerance of the first target distance, a first etching mask can be used in the first etch-trimming process to form a subset of N1 steps.

When a subset of N1 steps is formed, a second etch-trim mask can be formed on the top level using a second exposure setting selected from a second plurality of exposure settings. For example, in conjunction with FIG. 20, the second etch-trim mask has a second boundary. A second distance can be measured between the second reference mark and the second boundary of the second etch mask.

The various process steps as described in the process of calibrating the exposure setpoint can be continued in a similar manner to determine all of the alignment masks required to form the steps at each of the set of levels. Exposure settings.

27A, 27B, 27C, and 27D illustrate a lithographic mask pattern for a set of reference marks in a reference mark etch mask on a top level in a set of levels. The reference mark etch mask can be formed using one of the mask patterns for etching the set of reference marks, and then formed on the top layer in any etch-trim mask (eg, 1840 in FIG. 18) It was removed before the stage. Figure 27A illustrates a mask pattern comprising reference marks in a first reference mark area 2710 and in a second reference mark area 2720 opposite the first reference mark area at both ends of the array area for forming a memory array. The reference marks in each of the first reference mark zone and the second reference mark zone have substantially the same length. The term "substantially" as used herein is intended to encompass manufacturing tolerances.

A cross-sectional view taken along line B-B' in Fig. 27A can be explained by Fig. 17. In the example shown in FIG. 27A, the six reference marks in each of the first reference mark area and the second reference mark area may correspond to the six reference marks shown in FIG. In the first reference mark area, the first reference mark 2711 may correspond to the reference mark 1731 shown in FIG. 17, and the sixth reference mark 2716 may correspond to the reference mark 1736 shown in FIG. In the second reference mark area, the first reference mark 2721 may correspond to the reference mark 1731 shown in FIG. 17, and the sixth reference mark 2726 may correspond to the reference mark 1736 shown in FIG.

The array region has a plurality of sides including a first side (eg, 2751, 2753) and a second side (eg, 2752, 2754) oriented laterally to each other. In one embodiment, the first reference mark region and the second reference mark region (eg, 2710, 2720) are disposed on the first side, and the contact landing regions (eg, 2730, 2740) are disposed on the first On the two sides. The reference mark may be disposed in the first reference mark area and the second reference mark area, but is not disposed in the contact overlap area. The contacts may be overlapped in the contact overlap region but not in the first reference mark region and the second reference mark region.

Figure 27B illustrates a mask pattern similar to the mask pattern shown in Figure 27A. The difference is that the reference marks in each of the first reference mark area and the second reference mark area have different lengths. In one embodiment, each of the first reference mark zone and the second reference mark zone is closer to the reference mark of the array area than the reference mark (eg, 2711a) remote from the array area (eg, 2716a) ) has a shorter length.

Figure 27C illustrates a mask pattern similar to the mask pattern shown in Figure 27B. The difference is that the reference mark in each of the first reference mark area and the second reference mark area may have a first section (eg, 2711a) oriented in the first direction, and connected to the first And a second segment and a third segment (eg, 2711b, 2711c) oriented in a second direction orthogonal to the first direction.

Figure 27D illustrates a mask pattern similar to the mask pattern shown in Figure 27A. The difference is that the reference marks in each of the first reference mark area and the second reference mark area may include discontinuous sections (eg, 2711a1, 2711a2, 2711a3, 2711a4) oriented in the same direction.

Although the present invention has been disclosed with reference to the preferred embodiments and examples of the invention, it is understood that the examples are intended to be illustrative and not restrictive. It is to be understood that those skilled in the art will readily appreciate various modifications and combinations, and such retouching and combinations will be within the spirit of the present technology and the scope of the following claims. The disclosure of any and all patents, patent applications, and printed publications mentioned above is hereby incorporated by reference.

8.1, 8.2, 8.3, 8.4, 8.5, 8.6, 8.7, 8.8 ‧ ‧ active layers

10‧‧‧Stacking

12.1, 12.2, 12.3‧‧‧ sacrificial layer

14.1, 14.2, 14.3‧‧‧ dielectric layer

16.0, 16.1, 1840, 2040, 2240‧‧‧ etching-trimming mask

18‧‧‧ Covering area

20, 25, 26‧‧‧

24‧‧‧Finished mask area

28.1, 28.2, 28.3‧‧‧ lap area

31, 330, 630, 1430, 1530, 2711, 2716, 2716a, 2721, 2726‧‧ ‧ reference mark

32, 115, 116, 520, 620, 1420, 1535‧ ‧ distance

105, 305‧‧‧ ideal location

110, 310, 1710‧‧‧ base

120, 320‧‧‧Insulation material layer

141, 142, 1410, 1540‧‧‧ etching mask

145, 146, 545, 1415, 1545‧ ‧ borders

440‧‧‧ Cover material layer

540‧‧‧First etching mask

610‧‧‧Depression

615‧‧‧ side

655‧‧ depth

810‧‧‧Insulation

910‧‧ ‧Isolated area

920‧‧‧Array area

930‧‧‧ surrounding area

1011, 1012, 1013, 1014, 1015, 1016, 1111, 1112, 1113, 1114, 1115, 1116, 1117, 2511, 2512, 2513, 2514, 2515, 2516, 2611, 2612, 2613, 2614, 2615, 2616, 2617‧‧‧Steps

1451, 1452, 1453‧‧‧ curves

1510, 1520‧‧‧ mask pattern

1515‧‧‧ reference mark pattern

1525‧‧‧Rectangle

1601a, 1601b, 1601c, 1601d‧‧‧ "L" line

Lines 1602a, 1602b, 1603a, 1603b, 1603c, 1603d, 1604a, 1604b, 1604c, 1604d‧‧‧

1605a‧‧‧Rectangle perimeter/first rectangle

1605b‧‧‧Rectangle perimeter/second rectangle

1605c‧‧‧Rectangle perimeter/third rectangle

1720‧‧ ‧ level

1731, 1732, 1733, 1734, 1735, 1736‧‧‧ reference marks

1850‧‧‧First distance

2045‧‧‧ second border

2050‧‧‧Second distance

2245‧‧‧ third border

2250‧‧‧ third distance

2710‧‧‧First reference mark area

2711a‧‧‧First section

Sections 2711a1, 2711a2, 2711a3, 2711a4‧‧

2711b‧‧‧Second section

2711c‧‧‧ third section

2720‧‧‧Second reference mark area

2730, 2740‧‧‧Contact lap area

2751, 2753‧‧‧ first side

2752, 2754‧‧‧ second side

A-A’, B-B’‧‧‧ line

X, Y, Z‧‧ Direction

1 is a simplified cross-sectional view of a structure of a semiconductor device showing the result of forming an etch mask on a substrate, wherein the etch mask has a dimension such that the etch mask is between two opposing boundaries greater than a specified size And beyond the boundaries of manufacturing tolerances (prior art). 2 is a simplified cross-sectional view of the structure showing the result of forming an etch mask on a substrate, wherein the etch mask has a dimension such that the etch mask is less than a specified size between two opposing boundaries And beyond the boundaries of manufacturing tolerances (prior art). 3 through 9 illustrate an example of a process step used in the process of forming an alignment mask in accordance with the teachings of the present invention. Figure 10 illustrates a simplified flow diagram of the process steps used in forming the alignment mask. Figure 11 illustrates a simplified flow diagram of the process steps used in calibrating the exposure setpoints for forming an alignment mask. Figure 12 illustrates an example of a model of exposure energy and focus center that exhibits multiple exposure settings. FIG. 13 is a graph showing a curve in which the measured distance between the reference mark and the boundary of the etching mask varies with exposure energy and a focal point. Figure 14A illustrates the distance between the reference mark and the boundary of the etch mask. Figure 14B illustrates a top view image of the structure shown in Figure 14A. Figure 14C is an image illustrating the reference mark, the boundary of the etch mask, and the distance between the reference mark and the boundary of the etch mask. Figure 15A illustrates a lithographic mask pattern for a mask for making reference marks on a substrate. Figure 15B illustrates a lithographic mask pattern 1520 for a mask that is used to make a recess in a substrate. Figure 15C is a simplified top plan view of the structure showing the result of etching a reference mark on a substrate using the mask pattern shown in Figure 15A and then forming an etch mask on the substrate using the mask pattern shown in Figure 15B. . Figure 15D illustrates a cross-sectional view of the structure shown in Figure 15C. 16A-16F illustrate an alternative lithographic mask pattern of reference marks in a reference mark etch mask used in the formation of a reference mark pattern. 17 through 23 illustrate another example of a process step used in forming a set of alignment masks on a set of levels on a substrate. 24A, 24B, 24C, and 24D are a simplified set of illustrations illustrating an etch-trim cycle in accordance with the teachings of the present invention, wherein the stack of conductive layers is separated by a dielectric layer, etching a layer, The etch mask is trimmed and a layer is etched to form the structure shown in Figure 24D. Figure 25 illustrates a simplified flow diagram of the process steps used in forming an alignment mask on the top level of a set of levels on a substrate. Figure 26 illustrates a simplified flow diagram of the process steps used in calibrating the exposure setpoint for forming an alignment mask on the top level in a set of levels. 27A, 27B, 27C, and 27D illustrate a lithographic mask pattern for a set of reference marks in a reference mark etch mask on a top level in a set of levels.

Claims (20)

A method of forming an alignment mask comprising: etching a reference mark on a substrate to distinguish boundaries of an etched region; forming an etch mask on the substrate using an exposure setting, the etched mask having a boundary; Defining a distance between the reference mark and the boundary of the etching mask; when the measured distance exceeds a tolerance of the target distance, removing the etching mask from the substrate to change the exposure Setting a value, forming a next etching mask using the changed exposure setting value, and repeating the measuring; and when the measured distance is within the tolerance, then using the etching process Etching the mask. The method of forming an alignment mask as described in claim 1, wherein the exposure setting value includes an exposure energy and a focal point that are calibrated to form the etching mask. The method of forming an alignment mask as described in claim 1, the etching process comprising: etching a recess in the substrate using the etching mask to transfer the reference mark to the recess The bottom of the portion and an array of memory is formed in the recess. A semiconductor device comprising: a substrate including a recess extending into the substrate; and a reference mark on a bottom of the recess, the reference mark and the The distance between one side of the recess is within the tolerance of the target distance. The semiconductor device of claim 4, wherein the recess has a dimension between two opposite boundaries of the recess between about 500 microns and 10,000 microns, and the target distance is Between about 10 nm and 1,000 nm. The semiconductor device according to claim 4, wherein the reference mark is disposed parallel to the one side of the recessed portion, and the semiconductor device includes a memory array disposed in the recessed portion. A method of forming a set of alignment masks, comprising: etching a set of reference marks on a top level of a set of levels on a substrate to distinguish boundaries of each etched area; performing an etch-dressing process to Forming a step at each of a set of levels, wherein the etch-trimming process includes at least a first etch-trim cycle using a first one of the set of reference marks and using the set of reference marks a second etch-trim cycle of the second reference mark; and the first etch-trim cycle includes: forming a first etch-trim mask on the top level using a first exposure setting, the An etch-trim mask having a first boundary; measuring a first distance between the first one of the set of reference marks and the first boundary of the first etch-trim mask; When the measured first distance exceeds a tolerance of the first target distance, removing the first etch-trim mask from the top level, changing the first Exposing a set value, forming a next first etch-trim mask using the changed first exposure set value, and repeating the measuring to be within the tolerance when the measured first distance is Using the next first etch-trim mask in a first etch-trimming process; and when the measured first distance is within the tolerance, then at the first etch - The first etch-trim mask is used in a trim process, wherein the etch-trim process includes more than one etch-trim cycle using more than one etch-trim mask. A method of forming a set of alignment masks as described in claim 7, wherein the first exposure setting comprises an exposure energy and a focal point calibrated to form the first etch-trim mask. A method of forming a set of alignment masks as described in claim 7 wherein said set of levels comprises W steps L(i), wherein i is 1 to W, said first etching - The trimming process includes: repeatedly trimming the first etch-trim mask in the first etch-trim cycle and etching a layer to a first number N1 using the trimmed first etch-trim mask Repeating to form N1 steps on N1 respective levels L(i), where i is W-N1 to W-1, wherein the N1 steps are disposed on the first reference mark and the first Between the two reference marks. A method of forming a set of alignment masks according to claim 9 wherein said first etch-trimming process marks said first reference mark from a top level L of said set of levels ( W) shifts to the level L (W-N1-1) in the set of levels. A method of forming a set of alignment masks as recited in claim 7 wherein said second etch-trim cycle comprises: forming a second etch-trim on said top level using a second exposure setting a mask, the second etch-trim mask having a second boundary; measuring the second reference mark of the set of reference marks and the second boundary of the second etch-trim mask a second distance therebetween; when the measured second distance exceeds a tolerance of the second target distance, removing the second etch-trim mask from the top level to change the second exposure Setting a value, using the changed second exposure setting value to form a next second etch-trim mask, and repeating the operation of measuring the second distance to when the measured second distance is at When the tolerance is within, the next second etch-trim mask is used in the second etch-trimming process; and when the measured second distance is within the tolerance, then The second etch-trim mask is used in a second etch-trimming process. A method of forming a set of alignment masks as recited in claim 11, wherein the second exposure setting comprises an exposure energy and a focal point calibrated to form the second etch-trim mask. A method of forming a set of alignment masks according to claim 11, wherein the set of layers comprises W steps L(i), wherein i is 1 to W, the second etching - The trimming process includes: repeatedly trimming the second etch-trim mask in the second etch-trim cycle and etching a layer using the trimmed second etch-trim mask a second number N2 repetitions to form N2 steps on N2 respective levels L(i), where i is W-N2 to W-1, wherein the N2 steps are disposed on the second reference mark Between the third reference mark of the set of reference marks. The method of forming a set of alignment masks according to claim 13, wherein the second etching-trimming process marks the second reference mark from a top level L of the set of layers (W) Transferring to a level L (W-N2-1) in the set of levels, and labeling the first reference mark from the level L of the set of levels (W-N1-1) Transfer to the level L (W-N1-N2-2) in the set of levels. A method of forming a set of alignment masks according to claim 11, wherein the first exposure setting value is different from the second exposure setting value, and the first target distance is different from the first Two target distance. A method of forming a set of alignment masks as recited in claim 11, wherein a first number of steps formed in the first etch-trim cycle is different than in the second etch-trim cycle The second number of steps formed. A method of forming a set of alignment masks as described in claim 7 wherein each of the set of layers comprises a layer of sacrificial material and a layer of insulating material, the forming a set of alignment masks The method further includes: after performing the etching-dressing process to form the step at each of the set of layers, replacing the sacrificial material with a conductive material to make the set of layers Each of the layers includes a layer of electrically conductive material and a layer of the insulative material. A semiconductor device comprising: a set of layers on a substrate, the set of layers comprising W levels L(i), Where i is 0 to W; and the set of levels includes a first subset of at least a level L(i), where i is 0 to N1, and the first reference mark is set to a level in the first subset In L(0), and between the first reference mark in the level L(0) in the first subset and the first boundary of the level L(1) in the first subset The distance is within a tolerance of the first target distance, wherein each of the levels in the set of levels L(i) comprises a layer of electrically conductive material and a layer of insulating material, where i is from 1 to W. The semiconductor device of claim 18, wherein the set of levels comprises a second subset of the levels L(i), wherein i is N1+1 to N1+1+N2, the second reference mark is set In the second order of the second subset, L(N1+1), and the second reference mark in the level L(N1+1) and the level L in the second subset (N1) The second distance between the second boundaries of +2) is within a tolerance of the second target distance, wherein the second target distance is different from the first target distance. The semiconductor device of claim 19, wherein the first subset of the set of levels has a first number of levels, and the second subset of the set of layers has a Two number of levels, and the first number is different from the second number.