TWI639074B - Energy regulation circuit and operation system utilizing the same - Google Patents
Energy regulation circuit and operation system utilizing the same Download PDFInfo
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Abstract
一種能量調節電路,包括一第一電壓調節器、一第一能量儲存器、一第一開關、一第二能量儲存器、一第二電壓調節器以及一控制器。第一電壓調節器調節一輸入電壓,用以產生一調節電壓。第一能量儲存器根據輸入電壓或調節電壓而充電。第一開關耦接第一能量儲存器。第二能量儲存器耦接第一開關。當第一開關被導通時,第二能量儲存器並聯第一能量儲存器。當第一開關不導通時,第二電壓調節器根據第一能量儲存器的電壓產生一操作電壓。當第一開關導通時,第二電壓調節器根據第一及第二能量儲存器的電壓產生操作電壓。控制器根據操作電壓而動作。 An energy regulating circuit includes a first voltage regulator, a first energy storage device, a first switch, a second energy storage device, a second voltage regulator, and a controller. The first voltage regulator adjusts an input voltage to generate a regulated voltage. The first energy storage device is charged according to an input voltage or an adjustment voltage. The first switch is coupled to the first energy storage. The second energy storage is coupled to the first switch. When the first switch is turned on, the second energy storage is connected in parallel with the first energy storage. When the first switch is not conducting, the second voltage regulator generates an operating voltage according to the voltage of the first energy storage. When the first switch is turned on, the second voltage regulator generates an operating voltage according to the voltages of the first and second energy stores. The controller operates according to the operating voltage.
Description
本發明係有關於一種能量調節電路,特別是有關於一種耦接在一主機裝置與一週邊裝置之間的能量調節電路。 The present invention relates to an energy conditioning circuit, and more particularly to an energy conditioning circuit coupled between a host device and a peripheral device.
習知的能量調節電路係調節一第一外部裝置所提供的輸出電壓,再將調節後的結果提供予一第二外部裝置。然而,習知的能量調節電路卻無法調節第二外部裝置的輸出電壓,再將調整後的結果提供予第一外部裝置。 The conventional energy conditioning circuit adjusts the output voltage provided by a first external device and provides the adjusted result to a second external device. However, the conventional energy conditioning circuit cannot adjust the output voltage of the second external device, and then provides the adjusted result to the first external device.
本發明提供一種操作系統,包括一主機裝置、一週邊裝置、一傳送路徑以及一能量調節電路。主機裝置用以提供一主機電壓或接收一充電電壓。週邊裝置用以接收主機電壓或提供充電電壓。傳送路徑耦接於主機裝置與週邊裝置之間,用以傳送主機電壓或充電電壓。能量調節電路耦接於主機裝置與週邊裝置之間,並包括一第一電壓調節器、一第一能量儲存器、一第一開關、一第二能量儲存器、一第二電壓調節器以及一控制器。第一電壓調節器調節充電電壓,用以產生一調節電壓。第一能量儲存器根據充電電壓或調節電壓而充電。第一開 關耦接第一能量儲存器。第二能量儲存器耦接第一開關。當第一開關被導通時,第二能量儲存器並聯第一能量儲存器。當第一開關不導通時,第二電壓調節器根據第一能量儲存器的電壓產生操作電壓。當第一開關導通時,第二電壓調節器根據第一及第二能量儲存器的電壓產生操作電壓。控制器根據操作電壓而動作。 The invention provides an operating system comprising a host device, a peripheral device, a transmission path and an energy adjustment circuit. The host device is configured to provide a host voltage or receive a charging voltage. The peripheral device is configured to receive a host voltage or provide a charging voltage. The transmission path is coupled between the host device and the peripheral device for transmitting the host voltage or the charging voltage. The energy adjustment circuit is coupled between the host device and the peripheral device, and includes a first voltage regulator, a first energy storage device, a first switch, a second energy storage device, a second voltage regulator, and a Controller. The first voltage regulator adjusts the charging voltage to generate a regulated voltage. The first energy storage device is charged according to a charging voltage or an adjustment voltage. First open The coupling is coupled to the first energy storage. The second energy storage is coupled to the first switch. When the first switch is turned on, the second energy storage is connected in parallel with the first energy storage. When the first switch is not conducting, the second voltage regulator generates an operating voltage according to the voltage of the first energy storage. When the first switch is turned on, the second voltage regulator generates an operating voltage according to the voltages of the first and second energy stores. The controller operates according to the operating voltage.
本發明另提供一種能量調節電路,包括一第一電壓調節器、一第一能量儲存器、一第一開關、一第二能量儲存器、一第二電壓調節器以及一控制器。第一電壓調節器調節一輸入電壓,用以產生一調節電壓。第一能量儲存器根據輸入電壓或調節電壓而充電。第一開關耦接第一能量儲存器。第二能量儲存器耦接第一開關。當第一開關被導通時,第二能量儲存器並聯第一能量儲存器。當第一開關不導通時,第二電壓調節器根據第一能量儲存器的電壓產生一操作電壓。當第一開關導通時,第二電壓調節器根據第一及第二能量儲存器的電壓產生操作電壓。控制器根據操作電壓而動作。 The invention further provides an energy adjustment circuit comprising a first voltage regulator, a first energy storage device, a first switch, a second energy storage device, a second voltage regulator and a controller. The first voltage regulator adjusts an input voltage to generate a regulated voltage. The first energy storage device is charged according to an input voltage or an adjustment voltage. The first switch is coupled to the first energy storage. The second energy storage is coupled to the first switch. When the first switch is turned on, the second energy storage is connected in parallel with the first energy storage. When the first switch is not conducting, the second voltage regulator generates an operating voltage according to the voltage of the first energy storage. When the first switch is turned on, the second voltage regulator generates an operating voltage according to the voltages of the first and second energy stores. The controller operates according to the operating voltage.
100、700‧‧‧操作系統 100, 700‧‧‧ operating system
110、710‧‧‧主機裝置 110, 710‧‧‧ host device
120、720‧‧‧週邊裝置 120, 720‧‧‧ peripheral devices
130、730‧‧‧傳送路徑 130, 730‧‧‧ transmission path
140、740‧‧‧能量調節電路 140, 740‧‧‧ energy conditioning circuit
145、745‧‧‧控制器 145, 745‧‧ ‧ controller
410‧‧‧緩起動電路 410‧‧‧ Slow start circuit
Ra、Rb‧‧‧電阻 Ra, Rb‧‧‧ resistance
210‧‧‧調整電路 210‧‧‧Adjustment circuit
211~214、311~314‧‧‧調節器 211~214, 311~314‧‧‧ adjuster
ND1、ND2、GND‧‧‧節點 ND1, ND2, GND‧‧‧ nodes
ND3‧‧‧輸入端 ND3‧‧‧ input
ND4‧‧‧輸出端 ND4‧‧‧ output
Iref1~Iref4‧‧‧參考電流 Iref1~Iref4‧‧‧reference current
Ic‧‧‧輸出電流 Ic‧‧‧Output current
R1~8‧‧‧設定電阻 R1~8‧‧‧Set resistor
VFB‧‧‧回授電壓 VFB‧‧‧ feedback voltage
SC1~SC8、SC‧‧‧控制信號 SC1~SC8, SC‧‧‧ control signals
VA‧‧‧調節電壓 VA‧‧‧Adjust voltage
VOP‧‧‧操作電壓 VOP‧‧‧ operating voltage
VIN‧‧‧輸入電壓 VIN‧‧‧ input voltage
VCH‧‧‧充電電壓 VCH‧‧‧Charging voltage
VHT‧‧‧主機電壓 VHT‧‧‧ host voltage
Q11、Q12‧‧‧電晶體 Q11, Q12‧‧‧ transistor
SW1~SW6、Q1~Q4、Q31‧‧‧開關 SW1~SW6, Q1~Q4, Q31‧‧‧ switch
141、143、741、743‧‧‧電壓調節器 141, 143, 741, 743‧‧ ‧ voltage regulator
147、200、300、400A、400B、500、600、747‧‧‧處理器 147, 200, 300, 400A, 400B, 500, 600, 747‧‧ ‧ processors
Cout、Cout1、Cout2‧‧‧能量儲存器 Cout, Cout1, Cout2‧‧‧ energy storage
第1圖為本發明之操作系統之示意圖。 Figure 1 is a schematic diagram of the operating system of the present invention.
第2圖為本發明之處理器之一可能實施例。 Figure 2 is a possible embodiment of one of the processors of the present invention.
第3圖為本發明之處理器之另一可能實施例。 Figure 3 is another possible embodiment of the processor of the present invention.
第4A、4B圖為本發明之處理器的另一可能實施例。 4A, 4B are diagrams showing another possible embodiment of the processor of the present invention.
第5圖為本發明之處理器的另一可能實施例。 Figure 5 is another possible embodiment of the processor of the present invention.
第6圖為本發明之處理器的另一可能實施例。 Figure 6 is another possible embodiment of the processor of the present invention.
第7圖為本發明之操作系統之另一可能實施例。 Figure 7 is another possible embodiment of the operating system of the present invention.
為讓本發明之目的、特徵和優點能更明顯易懂,下文特舉出實施例,並配合所附圖式,做詳細之說明。本發明說明書提供不同的實施例來說明本發明不同實施方式的技術特徵。其中,實施例中的各元件之配置係為說明之用,並非用以限制本發明。另外,實施例中圖式標號之部分重覆,係為了簡化說明,並非意指不同實施例之間的關聯性。 In order to make the objects, features and advantages of the present invention more comprehensible, the embodiments of the invention are described in detail below. The present specification provides various embodiments to illustrate the technical features of various embodiments of the present invention. The arrangement of the various elements in the embodiments is for illustrative purposes and is not intended to limit the invention. In addition, the overlapping portions of the drawings in the embodiments are for the purpose of simplifying the description, and do not mean the relationship between the different embodiments.
第1圖為本發明之操作系統之示意圖。如圖所示,操作系統100包括一主機裝置110、一週邊裝置120、一傳送路徑130以及一能量調節電路140。主機裝置110透過傳送路徑130輸出一主機電壓VHT或是接收一充電電壓VCH,並與能量調節電路140溝通。在一可能實施例中,主機裝置110透過能量調節電路140與多個週邊裝置進行資料傳輸。在此例中,主機裝置110也可透過能量調節電路140輸出主機電壓VHT予其它週邊裝置。本發明並不限定主機裝置110的種類。在一可能實施例中,主機裝置110係為一電腦或是一智慧型手機。 Figure 1 is a schematic diagram of the operating system of the present invention. As shown, the operating system 100 includes a host device 110, a peripheral device 120, a transmission path 130, and an energy conditioning circuit 140. The host device 110 outputs a host voltage VHT through the transmission path 130 or receives a charging voltage VCH and communicates with the energy adjustment circuit 140. In a possible embodiment, the host device 110 performs data transmission with the plurality of peripheral devices through the energy adjustment circuit 140. In this example, the host device 110 can also output the host voltage VHT to other peripheral devices through the energy adjustment circuit 140. The invention does not limit the type of host device 110. In a possible embodiment, the host device 110 is a computer or a smart phone.
週邊裝置120耦接傳送路徑130與能量調節電路140。在本實施例中,週邊裝置120透過傳送路徑130接收主機電壓VHT或輸出充電電壓VCH。另外,週邊裝置120與能量調節電路140溝通。雖然第1圖的能量調節電路140僅耦接單一週邊裝置120,但並非用以限制本發明。在其它實施例中,能量調節電路140可能耦接複數週邊裝置。本發明並不限定週邊裝置的種類。在一可能實施例中,週邊裝置可能包括一儲存裝置、 一顯示裝置及/或充電器。 The peripheral device 120 is coupled to the transmission path 130 and the energy adjustment circuit 140. In the present embodiment, the peripheral device 120 receives the host voltage VHT or the output charging voltage VCH through the transmission path 130. Additionally, peripheral device 120 is in communication with energy conditioning circuit 140. Although the energy conditioning circuit 140 of FIG. 1 is only coupled to a single peripheral device 120, it is not intended to limit the invention. In other embodiments, the energy conditioning circuit 140 may couple to a plurality of peripheral devices. The invention does not limit the type of peripheral device. In a possible embodiment, the peripheral device may include a storage device, A display device and/or charger.
傳送路徑130耦接於主機裝置110與週邊裝置120之間,並具有開關SW1與SW2,用以傳送充電電壓VCH及主機電壓VHT。本發明並不限定開關SW1與SW2的種類。在一可能實施例中,開關SW1與SW2可由電晶體所實現。 The transmission path 130 is coupled between the host device 110 and the peripheral device 120, and has switches SW1 and SW2 for transmitting the charging voltage VCH and the host voltage VHT. The invention does not limit the types of switches SW1 and SW2. In a possible embodiment, switches SW1 and SW2 can be implemented by a transistor.
能量調節電路140分別與主機裝置110和週邊裝置120溝通,並根據溝通結果導通開關SW1與SW2之至少一者。舉例而言,當週邊裝置120係為一充電器時,能量調節電路140先導通開關SW2,並與主機裝置110溝通,用以得知主機裝置110所需的充電電壓,並命令週邊裝置120輸出主機裝置110所需的充電電壓。待週邊裝置120輸出主機裝置110所需的充電電壓VCH後,能量調節電路140再導通開關SW1,用以將充電電壓VCH提供予主機裝置110。當週邊裝置120並非充電器時,能量調節電路140可能導通開關SW1和SW2用以供電予週邊裝置120或是導通開關SW1與不導通開關SW2用以不供電予週邊裝置120。 The energy adjustment circuit 140 communicates with the host device 110 and the peripheral device 120, respectively, and turns on at least one of the switches SW1 and SW2 according to the communication result. For example, when the peripheral device 120 is a charger, the energy adjustment circuit 140 first turns on the switch SW2 and communicates with the host device 110 to learn the charging voltage required by the host device 110, and commands the peripheral device 120 to output. The charging voltage required by the host device 110. After the peripheral device 120 outputs the charging voltage VCH required by the host device 110, the energy adjusting circuit 140 turns on the switch SW1 to supply the charging voltage VCH to the host device 110. When the peripheral device 120 is not a charger, the energy adjustment circuit 140 may turn on the switches SW1 and SW2 for supplying power to the peripheral device 120 or the conduction switch SW1 and the non-conduction switch SW2 for not supplying power to the peripheral device 120.
在本實施例中,能量調節電路140包括電壓調節器141、143、一控制器145以及一處理器147。電壓調節器141調節一輸入電壓VIN,用以產生一調節電壓VA。本發明並不限定輸入電壓VIN的來源。當主機裝置110提供主機電壓VHT時,輸入電壓VIN約略等於主機電壓VHT。當週邊裝置120提供充電電壓VCH時,輸入電壓VIN約略等於充電電壓VCH。電壓調節器143調節調節電壓VA,用以產生一操作電壓VOP。本發明並不限定電壓調節器141與143的電路架構。舉例而言,電壓調節器 141與143之一者可能為一升壓電路,並且電壓調節器141與143之另一者可能為一降壓電路。 In the present embodiment, the energy adjustment circuit 140 includes voltage regulators 141, 143, a controller 145, and a processor 147. The voltage regulator 141 regulates an input voltage VIN for generating a regulated voltage VA. The invention does not limit the source of the input voltage VIN. When the host device 110 provides the host voltage VHT, the input voltage VIN is approximately equal to the host voltage VHT. When the peripheral device 120 provides the charging voltage VCH, the input voltage VIN is approximately equal to the charging voltage VCH. The voltage regulator 143 adjusts the regulation voltage VA to generate an operating voltage VOP. The present invention does not limit the circuit architecture of the voltage regulators 141 and 143. For example, a voltage regulator One of 141 and 143 may be a boost circuit, and the other of voltage regulators 141 and 143 may be a buck circuit.
在一可能實施例中,電壓調節器141係為一同步升壓電路(synchronous boost converter),用以提升輸入電壓VIN。舉例而言,當輸入電壓VIN為5V時,電壓調節器141所產生的調節電壓VA為6.5V。當輸入電壓VIN為9V、15V或20V時,調節電壓VA分別為9V、15V或20V。在另一可能實施例中,電壓調節器143係為一同步降壓電路(synchronous buck converter),用以調降調節電壓VA。舉例而言,當調節電壓VA為6.5V、9V、15V或20V時,操作電壓VOP都維持在一固定位準,如5V。 In a possible embodiment, the voltage regulator 141 is a synchronous boost converter for boosting the input voltage VIN. For example, when the input voltage VIN is 5V, the regulated voltage VA generated by the voltage regulator 141 is 6.5V. When the input voltage VIN is 9V, 15V or 20V, the regulation voltage VA is 9V, 15V or 20V, respectively. In another possible embodiment, the voltage regulator 143 is a synchronous buck converter for regulating the regulated voltage VA. For example, when the regulation voltage VA is 6.5V, 9V, 15V or 20V, the operating voltage VOP is maintained at a fixed level, such as 5V.
控制器145根據操作電壓VOP開始與主機裝置110和週邊裝置120溝通。控制器145根據溝通結果導通開關SW1與SW2之至少一者以及產生至少一控制信號(未顯示)。處理器147根據控制信號處理調節電壓VA,用以產生一處理結果(如VAR)。在一實施例中,控制器145係為一電源傳送控制器(Power Delivery Controller)。 The controller 145 starts communicating with the host device 110 and the peripheral device 120 in accordance with the operating voltage VOP. The controller 145 turns on at least one of the switches SW1 and SW2 and generates at least one control signal (not shown) according to the communication result. The processor 147 processes the regulated voltage VA according to the control signal to generate a processing result (such as VAR). In one embodiment, controller 145 is a Power Delivery Controller.
舉例而言,當控制器145得知主機裝置110輸出主機電壓VHT時,控制器145進入一第一模式。在第一模式下,控制器145導通開關SW1,並依據週邊裝置120的需求,導通或不導通開關SW2。此時,控制器145不觸發處理器147。因此,處理器147不處理調節電壓VA。當控制器145得知週邊裝置120提供充電電壓VCH時,控制器145進入一第二模式。在第二模式下,控制器145先導通開關SW2,並依照主機裝置110的需求命令週邊裝置120輸出適當的充電電壓VCH。等週邊裝置120輸 出合適的充電電壓後,控制器145再導通開關SW1。此時,在第二模式下,控制器145根據充電電壓VCH,產生至少一控制信號(未顯示)予處理器147。此時,處理器147根據控制信號處理調節電壓VA,用以產生一調升電壓VAR。電壓調節器143根據調升電壓VAR產生操作電壓VOP。 For example, when the controller 145 learns that the host device 110 outputs the host voltage VHT, the controller 145 enters a first mode. In the first mode, the controller 145 turns on the switch SW1 and turns on or off the switch SW2 according to the requirements of the peripheral device 120. At this time, the controller 145 does not trigger the processor 147. Therefore, the processor 147 does not process the regulation voltage VA. When the controller 145 knows that the peripheral device 120 provides the charging voltage VCH, the controller 145 enters a second mode. In the second mode, the controller 145 turns on the switch SW2 first, and commands the peripheral device 120 to output an appropriate charging voltage VCH according to the requirements of the host device 110. And other peripheral devices 120 lose After a suitable charging voltage is applied, the controller 145 turns on the switch SW1 again. At this time, in the second mode, the controller 145 generates at least one control signal (not shown) to the processor 147 according to the charging voltage VCH. At this time, the processor 147 processes the adjustment voltage VA according to the control signal to generate a boost voltage VAR. The voltage regulator 143 generates an operating voltage VOP based on the boosting voltage VAR.
由於調升電壓VAR大於調節電壓VA,因此,當週邊裝置120不再耦接能量調節電路140時,能量調節電路140可維持其它週邊裝置(未顯示)的運作,直到主機裝置110切換成一供電裝置,並輸出主機電壓VHT。 Since the boosting voltage VAR is greater than the regulated voltage VA, when the peripheral device 120 is no longer coupled to the energy regulating circuit 140, the energy regulating circuit 140 can maintain the operation of other peripheral devices (not shown) until the host device 110 switches to a power supply device. And output the host voltage VHT.
另外,當主機裝置110或是週邊裝置120剛耦接能量調節電路140時,開關SW1與SW2可能尚未被導通。然而,由於開關SW1與SW2具有一寄生二極體,其可傳送主機電壓VHT或是充電電壓VCH予能量調節電路140。在能量調節電路140接收到主機電壓VHT或充電電壓VCH後,便可正常控制開關SW1與SW2。 In addition, when the host device 110 or the peripheral device 120 is just coupled to the energy adjustment circuit 140, the switches SW1 and SW2 may not be turned on. However, since the switches SW1 and SW2 have a parasitic diode, they can transfer the host voltage VHT or the charging voltage VCH to the energy conditioning circuit 140. After the energy adjustment circuit 140 receives the host voltage VHT or the charging voltage VCH, the switches SW1 and SW2 can be normally controlled.
第2圖為本發明之處理器之一可能實施例。如圖所示,處理器200包括電阻Ra、Rb、一能量儲存器Cout以及一調整電路210。電阻Ra耦接於節點ND1與ND2之間。電阻Rb耦接於節點ND2與GND之間。能量儲存器Cout耦接於節點ND1與GND之間。本發明並不限定能量儲存器Cout的種類。在本實施例中,能量儲存器Cout係為一電容。能量儲存器Cout所儲存的能量W如下式所示:
W為能量儲存器Cout所儲存的能量,C為能量儲存 器Cout的容值,V為能量儲存器Cout兩端的壓差。 W is the energy stored in the energy storage Cout, and C is the energy storage. The capacitance of Cout, V is the pressure difference across the energy storage Cout.
假設,在第一模式下(即主機裝置110提供主機電壓VHT時),調節電壓VA為6.5V。在此例中,能量儲存器Cout所儲存的能量W1如下式:
在第二模式下(即週邊裝置120提供充電電壓VCH時),調整電路210調整回授電壓VFB,用以調升調節電壓VA,並產生調升電壓VAR。假設,調升電壓VAR為15V。在此例中,能量儲存器Cout所儲存的能量W2如下式:
由式(2)及(3)可知,在第二模式下,能量儲存器Cout所儲存的能量變大。因此,當週邊裝置120不再供電時,能量儲存器Cout所儲存的電量可維持其它週邊裝置的運作。 As can be seen from the equations (2) and (3), in the second mode, the energy stored in the energy storage device Cout becomes large. Therefore, when the peripheral device 120 is no longer powered, the amount of power stored by the energy storage device Cout can maintain the operation of other peripheral devices.
本發明並不限定調整電路210的內部架構。任何能夠調整調節電壓VA的電路,均可作為調整電路210。在本實施例中,調整電路210具有調節器211~214。調節器211~214並聯於節點ND2與GND之間。由於調節器211~214的內部架構均相同,故以下將以調節器211為例,說明調節器的動作原理。在其它實施例,調整電路210可能具有更多或更少的調節器。 The present invention does not limit the internal architecture of the adjustment circuit 210. Any circuit capable of adjusting the adjustment voltage VA can be used as the adjustment circuit 210. In the present embodiment, the adjustment circuit 210 has regulators 211 to 214. Regulators 211-214 are connected in parallel between node ND2 and GND. Since the internal structures of the regulators 211 to 214 are all the same, the operation principle of the regulator will be described below by taking the regulator 211 as an example. In other embodiments, the adjustment circuit 210 may have more or fewer regulators.
調節器211具有開關Q1以及一設定電阻R1。開關Q1耦接節點ND2。本發明並不限定開關Q1的種類。在本實施例中,開關Q1係為一N型電晶體,但並非用以限制本發明。在其它實施例中,開關Q1可能係為一P型電晶體。如圖所示,開關Q1的閘極接收一控制信號SC1,其汲極耦接節點ND2,其源極 耦接設定電阻R1的一端。設定電阻R1的另一端耦接節點GND。當開關Q1導通時,設定電阻R1並聯電阻Rb。因此,回授電壓VFB增加並且調節電壓VA也增加,其中增加後的調節電壓VA即為調升電壓VAR。 The regulator 211 has a switch Q1 and a set resistor R1. The switch Q1 is coupled to the node ND2. The invention does not limit the type of switch Q1. In the present embodiment, the switch Q1 is an N-type transistor, but is not intended to limit the present invention. In other embodiments, switch Q1 may be a P-type transistor. As shown, the gate of switch Q1 receives a control signal SC1, and its drain is coupled to node ND2, its source One end of the setting resistor R1 is coupled. The other end of the set resistor R1 is coupled to the node GND. When the switch Q1 is turned on, the resistor R1 is set in parallel with the resistor Rb. Therefore, the feedback voltage VFB increases and the regulation voltage VA also increases, wherein the increased regulation voltage VA is the boost voltage VAR.
在本實施例中,調節器211~214的設定電阻R1~R4的阻值並不相同。另外,調節器211~214的開關Q1~Q4分別由控制信號SC1~SC4所控制,其中控制信號SC1~SC4係由控制器145所產生。在一可能實施例中,控制器145係根據週邊裝置120所提供的充電電壓VCH產生控制信號SC1~SC4。 In the present embodiment, the resistances of the set resistors R1 to R4 of the regulators 211 to 214 are not the same. Further, the switches Q1 to Q4 of the regulators 211 to 214 are controlled by the control signals SC1 to SC4, respectively, wherein the control signals SC1 to SC4 are generated by the controller 145. In a possible embodiment, the controller 145 generates the control signals SC1 SCSC4 according to the charging voltage VCH provided by the peripheral device 120.
舉例而言,當充電電壓VCH等於一第一預設值(如5V)時,控制器145只導通開關Q1。因此,設定電阻R1並聯電阻Rb。此時,調升電壓VAR可能等於一第一電壓(如15V)。在另一可能實施例中,當充電電壓VCH等於一第二預設值(如9V)時,控制器145只導通開關Q2。因此,設定電阻R2並聯電阻Rb。此時,調升電壓VAR可能等於一第二電壓(如18V)。在一些可能實施例中,當充電電壓VCH等於一第三預設值(如15V)或一第四預設值(如20V)時,控制器145只導通開關Q3或Q4。因此,設定電阻R3或R4並聯電阻Rb。此時,調升電壓VAR可能等於一第三電壓(如21V)或一第四電壓(如24V)。 For example, when the charging voltage VCH is equal to a first preset value (eg, 5V), the controller 145 only turns on the switch Q1. Therefore, the resistor R1 is set in parallel with the resistor Rb. At this time, the boost voltage VAR may be equal to a first voltage (eg, 15V). In another possible embodiment, when the charging voltage VCH is equal to a second preset value (such as 9V), the controller 145 only turns on the switch Q2. Therefore, the resistor R2 is set in parallel with the resistor Rb. At this time, the boost voltage VAR may be equal to a second voltage (eg, 18V). In some possible embodiments, when the charging voltage VCH is equal to a third preset value (such as 15V) or a fourth preset value (such as 20V), the controller 145 only turns on the switch Q3 or Q4. Therefore, the resistor R3 or R4 is set in parallel with the resistor Rb. At this time, the boost voltage VAR may be equal to a third voltage (such as 21V) or a fourth voltage (such as 24V).
第3圖為本發明之處理器之另一可能實施例。第3圖相似第2圖,不同之處在於第3圖的調整電路310。調整電路310接收操作電壓VOP,並耦接節點ND2與GND。在本實施例中,調整電路310具有調節器311~314以及一電流鏡315。調節器311~314彼此並聯。由於調節器311~314的架構相似,故以下僅 以調節器311為例。在其它實施例中,調整電路310可能具有更多或更少的調節器。 Figure 3 is another possible embodiment of the processor of the present invention. Fig. 3 is similar to Fig. 2, except for the adjustment circuit 310 of Fig. 3. The adjustment circuit 310 receives the operating voltage VOP and couples the nodes ND2 and GND. In this embodiment, the adjustment circuit 310 has regulators 311-314 and a current mirror 315. The regulators 311 to 314 are connected in parallel with each other. Since the structures of the regulators 311 to 314 are similar, the following are only The regulator 311 is taken as an example. In other embodiments, the adjustment circuit 310 may have more or fewer regulators.
調節器311具有一開關SW3以及一設定電阻R5。開關SW3接收操作電壓VOP,並耦接設定電阻R5。在一可能實施例中,開關SW3係為一P型電晶體或一N型電晶體。設定電阻R5耦接在開關SW3與電流鏡315的輸入端ND3之間。在本實施例中,控制器145根據輸入電壓VIN產生控制信號SC5,用以導通或不導通開關SW3。當開關SW3被導通時,一參考電流Iref1經過設定電阻R5。在本實施例中,設定電阻R5~R8具有不同的阻值,因此,當開關SW3~SW6導通時,流經電阻R5~R8的參考電流Iref1~Iref4各不相同。 The regulator 311 has a switch SW3 and a set resistor R5. The switch SW3 receives the operating voltage VOP and is coupled to the set resistor R5. In a possible embodiment, the switch SW3 is a P-type transistor or an N-type transistor. The setting resistor R5 is coupled between the switch SW3 and the input terminal ND3 of the current mirror 315. In the present embodiment, the controller 145 generates a control signal SC5 according to the input voltage VIN for turning on or off the switch SW3. When the switch SW3 is turned on, a reference current Iref1 passes through the set resistor R5. In the present embodiment, the setting resistors R5 to R8 have different resistance values. Therefore, when the switches SW3 to SW6 are turned on, the reference currents Iref1 to Iref4 flowing through the resistors R5 to R8 are different.
電流鏡315具有一輸入端ND3以及一輸出端ND4。輸出端ND4耦接節點ND2。在本實施例中,電流鏡315包括電晶體Q11與Q12。當一輸入電流流經輸入端ND3時,電流鏡315複製輸入電流,用以產生一輸出電流,其中該輸出電流流經予輸出端ND4,並等於輸入電流。舉例而言,當參考電流Iref1流經輸入端ND3時,電流鏡315產生一輸出電流Ic。因此,流經電阻Ra的電流Ia增加,進而增加調節電壓VA,用以產生調升電壓VAR。 The current mirror 315 has an input ND3 and an output ND4. The output terminal ND4 is coupled to the node ND2. In the present embodiment, the current mirror 315 includes transistors Q11 and Q12. When an input current flows through the input terminal ND3, the current mirror 315 replicates the input current for generating an output current, wherein the output current flows through the pre-output terminal ND4 and is equal to the input current. For example, when the reference current Iref1 flows through the input terminal ND3, the current mirror 315 generates an output current Ic. Therefore, the current Ia flowing through the resistor Ra increases, thereby increasing the regulation voltage VA for generating the boosting voltage VAR.
在本實施例中,控制器145根據充電電壓VCH,產生控制信號SC5~SC8,用以導通開關SW3~SW6之一者。舉例而言,當充電電壓VCH等於一第一預設值(如5V)時,控制器145導通開關SW3。因此,參考電流Iref1流經輸入端ND3。此時,調升電壓VAR可能等於一第一設定值。在另一可能實施例中, 當充電電壓VCH等於一第二預設值(如9V)時,控制器145導通開關SW4。因此,參考電流Iref2流經輸入端ND3。此時,調升電壓VAR可能等於一第二設定值。在一些可能實施例中,當充電電壓VCH等於一第三預設值(如15V)或一第四預設值(如20V)時,控制器145導通開關SW5或SW6。因此,參考電流Iref3或Iref4流經輸入端ND3。此時,調升電壓VAR可能等於一第三設定值或一第四設定值。在一可能實施例中,第一至第四設定值均不相同。 In the present embodiment, the controller 145 generates control signals SC5 to SC8 for turning on one of the switches SW3 to SW6 according to the charging voltage VCH. For example, when the charging voltage VCH is equal to a first preset value (eg, 5V), the controller 145 turns on the switch SW3. Therefore, the reference current Iref1 flows through the input terminal ND3. At this time, the boosting voltage VAR may be equal to a first set value. In another possible embodiment, When the charging voltage VCH is equal to a second predetermined value (eg, 9V), the controller 145 turns on the switch SW4. Therefore, the reference current Iref2 flows through the input terminal ND3. At this time, the boosting voltage VAR may be equal to a second set value. In some possible embodiments, when the charging voltage VCH is equal to a third preset value (such as 15V) or a fourth preset value (such as 20V), the controller 145 turns on the switch SW5 or SW6. Therefore, the reference current Iref3 or Iref4 flows through the input terminal ND3. At this time, the boosting voltage VAR may be equal to a third set value or a fourth set value. In a possible embodiment, the first to fourth set values are all different.
第4A圖為本發明之處理器的另一可能實施例。在本實施例中,處理器400A包括能量儲存器Cout1、Cout2以及一開關Q31。能量儲存器Cout1耦接於節點ND1與GND之間。開關Q31耦接於能量儲存器Cout1與Cout2之間。在本實施例中,開關Q31係為一P型電晶體,其閘極接收一控制信號SC,其源極耦接能量儲存器Cout1,其汲極耦接能量儲存器Cout2。在其它實施例中,開關Q31可能由一N型電晶體所實現。能量儲存器Cout2耦接於開關Q31與節點GND之間。在一可能實施例,能量儲存器Cout1與Cout2係為電容。 Figure 4A is another possible embodiment of the processor of the present invention. In the present embodiment, the processor 400A includes energy storage devices Cout1, Cout2 and a switch Q31. The energy storage device Cout1 is coupled between the node ND1 and GND. The switch Q31 is coupled between the energy storage devices Cout1 and Cout2. In this embodiment, the switch Q31 is a P-type transistor, the gate thereof receives a control signal SC, the source thereof is coupled to the energy storage device Cout1, and the drain is coupled to the energy storage device Cout2. In other embodiments, switch Q31 may be implemented by an N-type transistor. The energy storage device Cout2 is coupled between the switch Q31 and the node GND. In a possible embodiment, the energy stores Cout1 and Cout2 are capacitors.
在第一模式下,控制信號SC不被觸發,因此,開關Q31不被導通。此時,只有能量儲存器Cout1儲存能量。能量儲存器Cout1所儲存的能量W3如下式:
因此,第1圖的電壓調節器143根據能量儲存器Cout1所儲存的能量W3產生操作電壓VOP,其中式(4)的符號V為能量儲存器Cout1兩端的壓差。 Therefore, the voltage regulator 143 of FIG. 1 generates the operating voltage VOP based on the energy W3 stored in the energy storage device Cout1, wherein the symbol V of the equation (4) is the voltage difference across the energy storage device Cout1.
在一第二模式下,控制信號SC被觸發,故開關Q31被導通。能量儲存器Cout2並聯能量儲存器Cout1。因此,能量儲存器Cout1與Cout2共同儲存能量。能量儲存器Cout1與Cout2所儲存的能量W4如下式所示:
式(5)的符號V為能量儲存器Cout1與Cout2兩端的壓差。由式(5)與(4)可知,能量儲存器Cout1與Cout2所儲存的能量W4大於能量儲存器Cout1所儲存的能量W3。因此,當週邊裝置120不再供電予能量調節電路140時,電壓調節器143根據能量儲存器Cout1與Cout2所儲存的能量W4產生操作電壓VOP,以維持控制器145的運作,還可供給多餘能量給其他週邊裝置使用。在一可能實施例中,控制信號SC係由第1圖的控制器145所產生。 The symbol V of equation (5) is the voltage difference across the energy stores Cout1 and Cout2. It can be seen from equations (5) and (4) that the energy W4 stored in the energy storage devices Cout1 and Cout2 is greater than the energy W3 stored in the energy storage device Cout1. Therefore, when the peripheral device 120 no longer supplies power to the energy regulating circuit 140, the voltage regulator 143 generates an operating voltage VOP according to the energy W4 stored in the energy storage devices Cout1 and Cout2 to maintain the operation of the controller 145, and also supply excess energy. Used by other peripheral devices. In a possible embodiment, the control signal SC is generated by the controller 145 of FIG.
第4B圖為本發明之處理器的另一可能實施例。第4B圖相似第4A圖,不同之處在於第4B圖的處理器400B多了一緩起動電路410。緩起動電路410用以避免在開關Q31導通的瞬間,一突波電流(inrush current)進入能量儲存器Cout2。緩起動電路410耦接於能量儲存器Cout1與Cout2之間。當開關Q31導通時,流入能量儲存器Cout2的電流逐漸增加。本發明並不限定緩起動電路410的內部電路架構。任何可避免突波電流的電路均可作為緩起動電路410。 Figure 4B is another possible embodiment of the processor of the present invention. Figure 4B is similar to Figure 4A, except that processor 400B of Figure 4B has a slow start circuit 410. The slow start circuit 410 is used to prevent an inrush current from entering the energy storage Cout2 at the instant when the switch Q31 is turned on. The slow start circuit 410 is coupled between the energy storage devices Cout1 and Cout2. When the switch Q31 is turned on, the current flowing into the energy storage device Cout2 gradually increases. The present invention does not limit the internal circuit architecture of the slow start circuit 410. Any circuit that can avoid surge current can be used as the slow start circuit 410.
第5圖為本發明之處理器的另一可能實施例。處理器500係整合處理器200與400A。如圖所示,處理器500包括電阻Ra、Rb、能量儲存器Cout1、Cout2、開關Q31以及一調整電 路210。由於第5圖的電阻Ra、Rb與調整電路210相同於第2圖的電阻Ra、Rb與調整電壓210,故不再贅述。另外,第5圖的能量儲存器Cout1、Cout2與開關Q31的特性與第4A圖的能量儲存器Cout1、Cout2、開關Q31的特性相同,故不再贅述。在其它實施例中,第4B圖的緩起動電路410亦可應用在第5圖中。 Figure 5 is another possible embodiment of the processor of the present invention. The processor 500 integrates the processors 200 and 400A. As shown, the processor 500 includes resistors Ra, Rb, energy storage devices Cout1, Cout2, switch Q31, and an adjustment power Road 210. Since the resistors Ra and Rb in FIG. 5 are the same as the resistors Ra and Rb and the adjustment voltage 210 in FIG. 2, the adjustment circuit 210 will not be described again. In addition, the characteristics of the energy storage devices Cout1, Cout2 and the switch Q31 of Fig. 5 are the same as those of the energy storage devices Cout1, Cout2 and Q31 of Fig. 4A, and therefore will not be described again. In other embodiments, the slow start circuit 410 of FIG. 4B can also be applied to FIG.
在第一模式下,控制信號SC與SC1~SC4不被觸發,因此,開關Q31與調節器211~214不被導通。此時,能量儲存器Cout1所儲存的能量W5如下式:
在一第二模式下,控制信號SC被觸發,故開關Q31被導通。能量儲存器Cout2並聯能量儲存器Cout1。此時,如果控制信號SC1被觸發,則可增加回授電壓VFB,因而產生調升電壓VAR。此時,能量儲存器Cout1與Cout2所儲存的能量W6如下式:
由式(6)及(7)可知,在第二模式下,能量儲存器Cout1與Cout2所儲存的能量W6大於在第一模式下,能量儲存器Cout1所儲存的能量W5。 It can be seen from equations (6) and (7) that in the second mode, the energy W6 stored in the energy storage devices Cout1 and Cout2 is greater than the energy W5 stored in the energy storage device Cout1 in the first mode.
第6圖為本發明之處理器的另一可能實施例。處理器600係整合處理器300與400A。如圖所示,處理器600包括電阻Ra、Rb、能量儲存器Cout1、Cout2、開關Q31以及一調整電路310。由於第6圖的電阻Ra、Rb與調整電路310的特性與第3圖的電阻Ra、Rb與調整電路310的特性相同,故不再贅述。另外,第6圖的能量儲存器Cout1、Cout2與開關Q31的特性與第4A 圖的能量儲存器Cout1、Cout2、開關Q31相同,故不再贅述。在其它實施例中,第4B圖的緩起動電路410亦可應用在第6圖中。 Figure 6 is another possible embodiment of the processor of the present invention. The processor 600 integrates the processors 300 and 400A. As shown, the processor 600 includes resistors Ra, Rb, energy stores Cout1, Cout2, a switch Q31, and an adjustment circuit 310. Since the characteristics of the resistors Ra and Rb in FIG. 6 and the adjustment circuit 310 and the characteristics of the resistors Ra and Rb in FIG. 3 are the same as those of the adjustment circuit 310, they will not be described again. In addition, the characteristics of the energy storage devices Cout1, Cout2 and switch Q31 of Fig. 6 and the 4A The energy storage devices Cout1, Cout2 and Q31 of the figure are the same, and therefore will not be described again. In other embodiments, the slow start circuit 410 of FIG. 4B can also be applied to FIG.
第7圖為本發明之操作系統之另一可能實施例。第7圖相似第1圖,不同之處在於第7圖的操作系統700的處理器747係處理輸入電壓VIN,用以產生一處理結果VINR。在本實施例中,控制器745根據輸入電壓VIN產生至少一控制信號(未顯示)予處理器747。處理器747根據控制信號產生適當的處理結果VINR。電壓調節器741根據處理結果VINR產生調節電壓VA。電壓調節器743根據調節電壓VA產生操作電壓VOP予控制器745。 Figure 7 is another possible embodiment of the operating system of the present invention. Figure 7 is similar to Figure 1, except that the processor 747 of the operating system 700 of Figure 7 processes the input voltage VIN to produce a processing result VINR. In the present embodiment, controller 745 generates at least one control signal (not shown) to processor 747 based on input voltage VIN. The processor 747 generates an appropriate processing result VINR based on the control signal. The voltage regulator 741 generates a regulated voltage VA according to the processing result VINR. The voltage regulator 743 generates an operating voltage VOP to the controller 745 according to the regulated voltage VA.
在一可能實施例中,處理器747處理輸入電壓VIN的方式與第2、3、4A、4B、5、6圖的處理器200、300、400A、400B、500、600處理調節電壓VA的方式相似,故不再贅述。另外,第7圖的主機裝置710、週邊裝置720、傳送路徑730、電壓調節器741、743、控制器745以及處理器747的動作原理與第1圖的主機裝置110、週邊裝置120、傳送路徑130、電壓調節器141、143、控制器145以及處理器147的動作原理相似,故不再贅述。 In a possible embodiment, the manner in which the processor 747 processes the input voltage VIN and the processor 200, 300, 400A, 400B, 500, 600 of the 2, 3, 4A, 4B, 5, and 6 diagrams process the regulated voltage VA Similar, so I won't go into details. The operation principle of the host device 710, the peripheral device 720, the transmission path 730, the voltage regulators 741 and 743, the controller 745, and the processor 747 in FIG. 7 and the host device 110, the peripheral device 120, and the transmission path in FIG. 130, the voltage regulators 141, 143, the controller 145 and the processor 147 operate similarly, and therefore will not be described again.
當一充電裝置耦接能量調節電路時,能量調節電路便開始儲存較大的能量。當充電裝置不再耦接能量調節電路時,由於主機裝置需一段時間才能開始供給主機電壓,故能量調節電路藉由先前所儲存的大能量維持本身(包含連接中的其他週邊裝置)的運作,以等待主機裝置輸出主機電壓。因此, 即使能量調節電路未接收到充電電壓及主機電壓時,能量調節電路仍可正常地與其它大功率的負載(如儲存裝置或顯示裝置)進行溝通。 When a charging device is coupled to the energy conditioning circuit, the energy conditioning circuit begins to store a large amount of energy. When the charging device is no longer coupled to the energy regulating circuit, since the host device takes a period of time to start supplying the host voltage, the energy regulating circuit maintains its own operation (including other peripheral devices in the connection) by the previously stored large energy. Wait for the host device to output the host voltage. therefore, Even if the energy conditioning circuit does not receive the charging voltage and the host voltage, the energy conditioning circuit can normally communicate with other high power loads (such as storage devices or display devices).
除非另作定義,在此所有詞彙(包含技術與科學詞彙)均屬本發明所屬技術領域中具有通常知識者之一般理解。此外,除非明白表示,詞彙於一般字典中之定義應解釋為與其相關技術領域之文章中意義一致,而不應解釋為理想狀態或過分正式之語態。 Unless otherwise defined, all terms (including technical and scientific terms) are used in the ordinary meaning Moreover, unless expressly stated, the definition of a vocabulary in a general dictionary should be interpreted as consistent with the meaning of an article in its related art, and should not be interpreted as an ideal state or an overly formal voice.
雖然本發明已以較佳實施例揭露如上,然其並非用以限定本發明,任何所屬技術領域中具有通常知識者,在不脫離本發明之精神和範圍內,當可作些許之更動與潤飾。舉例來,本發明實施例所系統、裝置或是方法可以硬體、軟體或硬體以及軟體的組合的實體實施例加以實現。因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。 Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. . For example, the system, apparatus or method of the embodiments of the present invention may be implemented in a physical embodiment of a combination of hardware, software or hardware and software. Therefore, the scope of the invention is defined by the scope of the appended claims.
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