WO2020024212A1 - Voltage regulator, control circuit for voltage regulator, and control method for voltage regulator - Google Patents

Voltage regulator, control circuit for voltage regulator, and control method for voltage regulator Download PDF

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Publication number
WO2020024212A1
WO2020024212A1 PCT/CN2018/098296 CN2018098296W WO2020024212A1 WO 2020024212 A1 WO2020024212 A1 WO 2020024212A1 CN 2018098296 W CN2018098296 W CN 2018098296W WO 2020024212 A1 WO2020024212 A1 WO 2020024212A1
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WIPO (PCT)
Prior art keywords
voltage
terminal
output terminal
transistor
coupled
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PCT/CN2018/098296
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French (fr)
Chinese (zh)
Inventor
庄朝贵
徐建昌
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深圳市汇顶科技股份有限公司
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Application filed by 深圳市汇顶科技股份有限公司 filed Critical 深圳市汇顶科技股份有限公司
Priority to PCT/CN2018/098296 priority Critical patent/WO2020024212A1/en
Priority to CN201880001078.1A priority patent/CN109074112B/en
Publication of WO2020024212A1 publication Critical patent/WO2020024212A1/en

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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
    • G05F1/575—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices characterised by the feedback circuit

Definitions

  • the present invention relates to voltage stabilization technology, and in particular, to a voltage regulator using a plurality of charge pumps coupled in parallel to alternately provide a driving voltage, and a control circuit and control method thereof.
  • Low-dropout regulators are commonly used in power management systems to reduce crosstalk caused by power lines.
  • LDOs Low-dropout regulators
  • the output voltage stability and power supply rejection ratio of the low-dropout regulator still need to be improved.
  • signal processing operations occur only at certain time slots within a period of time. In other words, the low-dropout regulator does not need to be in the startup state all the time.
  • One of the objectives of the present invention is to disclose a regulator using a plurality of charge pumps coupled in parallel to alternately provide a driving voltage and a control circuit and a control method thereof to solve the above problems.
  • An embodiment of the invention discloses a voltage regulator.
  • the voltage regulator includes an amplifier, a charge pump circuit, a first transistor, and a regulated output terminal.
  • the amplifier has a first input terminal, a second input terminal and an amplified output terminal.
  • the first input terminal is coupled to a first reference voltage
  • the second input terminal is coupled to a feedback voltage
  • the amplified output terminal is used to output an amplified voltage.
  • the charge pump circuit has a voltage input terminal and a voltage output terminal, and the voltage input terminal is coupled to the amplified output terminal.
  • the charge pump circuit includes a first charge pump and a second charge pump, and the first charge pump and the second charge pump are coupled in parallel between the voltage input terminal and the voltage output terminal.
  • the first charge pump and the second charge pump are used to alternately convert the amplified voltage to output a driving voltage from the voltage output terminal.
  • the control terminal of the first transistor is configured to receive the driving voltage through the voltage output terminal.
  • the regulated output terminal is coupled to a first connection terminal of the first transistor, and is configured to output an output voltage.
  • An embodiment of the invention discloses a control circuit of a voltage regulator.
  • the regulator includes a first transistor, a regulated output terminal, and an amplifier. A first connection terminal of the first transistor is coupled to the regulated output terminal.
  • the control circuit includes a charge pump circuit and a switch module.
  • the charge pump circuit has a voltage input terminal and a voltage output terminal, and the voltage input terminal is coupled to the amplifier output terminal of the amplifier to receive the amplified voltage.
  • the charge pump circuit includes a first charge pump and a second charge pump, and the first charge pump and the second charge pump are coupled in parallel between the voltage input terminal and the voltage output terminal. The first charge pump and the second charge pump are used to alternately convert the amplified voltage to output a driving voltage from the voltage output terminal.
  • the switch module is used to selectively couple the voltage output terminal to a control terminal of the first transistor.
  • An embodiment of the invention discloses a control method of a voltage regulator.
  • the regulator includes a first transistor, a regulated output terminal, and an amplifier.
  • a first connection terminal of the first transistor is coupled to the regulated output terminal.
  • the control method includes: alternately coupling a first capacitor between an amplifier output terminal and a voltage output terminal of the amplifier and between a predetermined voltage and a reference voltage to generate a driving voltage at the voltage output terminal; Two capacitors are alternately coupled between the predetermined voltage and the reference voltage and between the amplifier output terminal and the voltage output terminal of the amplifier to generate the driving voltage at the voltage output terminal.
  • the first capacitor and the second capacitor When one of the first capacitor and the second capacitor is coupled between the amplifier output terminal and the voltage output terminal of the amplifier, the first capacitor and the second capacitor Another capacitor is coupled between the predetermined voltage and the reference voltage; and the voltage output terminal is selectively coupled to the control terminal of the first transistor.
  • FIG. 1 is a functional block diagram of an embodiment of the voltage regulator of the present invention.
  • FIG. 2 is a schematic diagram of an embodiment of the control circuit 140 shown in FIG. 1.
  • FIG. 3 is a schematic diagram of an example of a control signal timing of each switch shown in FIG. 2.
  • FIG. 4 is a waveform diagram of an embodiment of a voltage signal generated in response to the control signal timing shown in FIG. 3.
  • FIG. 5 illustrates a functional block diagram of another embodiment of the voltage regulator of the present invention.
  • FIG. 6 is a flowchart of an embodiment of a method for controlling a voltage regulator according to the present invention.
  • the first charge pump is the first charge pump.
  • the second voltage source is the second voltage source.
  • the second transistor is a second transistor.
  • the second resistor is the second resistor.
  • the third resistor is the third resistor.
  • the fourth resistor is the fourth resistor.
  • T11, T21 The first connection terminal
  • the first input terminal is the first input terminal.
  • the second input terminal is the second input terminal.
  • the first capacitor is the first capacitor.
  • the second capacitor is the second capacitor.
  • the second switch is the second switch.
  • the third switch is the third switch.
  • the fourth switch is the fourth switch.
  • the fifth switch is the fifth switch.
  • the sixth switch is the sixth switch.
  • the seventh switch is the seventh switch.
  • the eighth switch is the following:
  • the first control voltage is the first control voltage.
  • the second control voltage is the second control voltage.
  • the first output current is the first output current.
  • the second output current is the second output current.
  • VR1 The first reference voltage is VR1.
  • VR2 The second reference voltage is VR2.
  • VFB The feedback voltage
  • VSS Predetermined voltage
  • the driving voltage is:
  • the fourth control signal is the fourth control signal.
  • the fifth control signal is the fifth control signal.
  • the sixth control signal is the sixth control signal.
  • the normal start signal is the normal start signal.
  • the voltage regulator structure disclosed by the present invention can use the driving voltage alternately generated by a plurality of charge pumps to control the operation of the pass transistor to maintain good output voltage stability.
  • the voltage regulator structure disclosed in the present invention can selectively provide driving voltages generated by a plurality of charge pumps to a plurality of transmission transistors according to different voltage regulator operation modes, and has low power consumption. Effect. Further explanation is as follows.
  • FIG. 1 is a functional block diagram of an embodiment of the voltage regulator of the present invention.
  • the voltage regulator 100 may be implemented as, but not limited to, a low dropout voltage regulator.
  • the regulator 100 may include a regulated output terminal NR, a transmission transistor module 110, an amplifier 120, a feedback circuit 130, and a control circuit 140.
  • the regulated output terminal NR is coupled to a
  • the load capacitor CL is used to output the adjusted voltage (that is, the output voltage VOUT).
  • the transmission transistor module 110 is coupled between a power supply voltage VP and the regulated output terminal NR, and may include one or more transmission transistors, wherein each of the transmission transistors can output an output current to the regulated output terminal NR.
  • the transmission transistor module 110 may include a first transistor M1 and a second transistor M2.
  • the first transistor M1 has a control terminal TC1, a first connection terminal T11, and a second connection terminal T12.
  • the second transistor M2 has a control terminal TC2, a first connection terminal T21, and a second connection terminal T22.
  • a connection terminal T11 and a first connection terminal T21 are both coupled to the power supply voltage VP, and a second connection terminal T12 and a second connection terminal T22 are coupled to the regulated output terminal NR.
  • the first transistor M1 can output a first output current I1 from the second connection terminal T12 according to a first control voltage M1G received by the control terminal TC1.
  • the second transistor M2 can output a second output current I2 from the second connection terminal T22 according to a second control voltage M2G received by the control terminal TC2.
  • the amplifier 120 has a first input terminal NI1, a second input terminal NI2, and an amplified output terminal NT.
  • the first input terminal NI1 is coupled to a first reference voltage VR1
  • the second input terminal NI2 is coupled to a Feedback voltage VFB.
  • the amplifier 110 is configured to output an amplified voltage OPV at the amplified output terminal NT according to the first reference voltage VR1 and the feedback voltage VFB.
  • the first reference voltage VR1 may be provided by a first voltage source VS1, such as a bandgap reference voltage source.
  • the present invention is not limited to this.
  • the amplifier 120 may further have a power input terminal NS, which is coupled to the regulated output terminal NR to receive the output voltage VOUT. That is, the power of the amplifier 120 may be provided by the adjusted voltage (ie, the output voltage VOUT), rather than by a non-segmented voltage (such as the power supply voltage VP). This helps to improve the power supply rejection ratio of the regulator 100.
  • the feedback circuit 130 is coupled between the regulated output terminal NR and the second input terminal NI2 to generate a feedback voltage VFB according to the output voltage VOUT.
  • the feedback circuit 130 may be implemented by a voltage dividing circuit, which may include a first resistor R1 and a second resistor R2.
  • the first resistor R1 is coupled between the second input terminal NI2 and a predetermined voltage VSS (such as a ground voltage), and the second resistor R2 is coupled between the regulated output terminal NR and the second input terminal NI2.
  • VSS such as a ground voltage
  • the present invention is not limited to this. Feedback circuits using other circuit structures are feasible.
  • the control circuit 140 is coupled to the amplification output terminal NT of the amplifier 120 and is configured to generate a first control voltage M1G and a second control voltage M2G according to the amplified voltage OPV.
  • the control circuit 140 may perform a level shift (such as a boosting process) on the amplified voltage OPV ) To generate a driving voltage VD, and selectively use the driving voltage VD as the first control voltage M1G to control the operation of the first transistor M1.
  • the control circuit 140 may perform a level shift (such as a step-down process) on the amplified voltage OPV to generate a driving voltage VD, and selectively drive the The voltage VD is used as the first control voltage M1G to control the operation of the first transistor M1.
  • the control circuit 140 may perform level conversion on the amplified voltage OPV to generate a driving voltage VD, and selectively use the driving voltage VD as the second control voltage M2G to control the operation of the second transistor M2.
  • the control circuit 140 may perform level conversion on the amplified voltage OPV according to a second reference voltage VR2 to generate a driving voltage VD.
  • the second reference voltage VR2 may be provided by a voltage generating circuit 150.
  • the voltage generating circuit 150 may include (but is not limited to) a second voltage source VS2, a third resistor R3, and a fourth resistor R4.
  • the second reference voltage VR2 may also be a reference voltage provided inside the control circuit 140.
  • FIG. 2 is a schematic diagram of an embodiment of the control circuit 140 shown in FIG. 1.
  • the control circuit 140 includes a charge pump circuit 242, a switch module 246, and a timing controller 248.
  • the charge pump circuit 242 has a voltage input terminal NVI and a voltage output terminal NVO.
  • the voltage input terminal NVI is coupled to the amplification output terminal NT to receive the amplified voltage OPV generated by the amplifier 120.
  • the charge pump circuit 242 may include a plurality of charge pumps which may alternately convert (such as step-up or step-down level conversion) the amplified voltage OPV to generate the driving voltage VD.
  • the charge pump circuit 242 includes a first charge pump 243 and a second charge pump 244.
  • the first charge pump 243 and the second charge pump 244 are coupled in parallel between the voltage input terminal NVI and the voltage output terminal NVO.
  • the first charge pump 243 and the second charge pump 244 are used to alternately convert the amplified voltage OPV to output the driving voltage VD from the voltage output terminal NVO. That is, the first charge pump 243 and the second charge pump 244 may output the driving voltage VD from the voltage output terminal NVO in turn.
  • the first charge pump 243 may include, but is not limited to, a first capacitor C1, a first switch SW1, a second switch SW2, a third switch SW3, and a fourth switch SW4.
  • the first capacitor C1 has a first terminal TA1 and a second terminal TA2.
  • the first switch SW1 is used to selectively couple the predetermined voltage VSS to the first terminal TA1.
  • the second switch SW2 is used to selectively couple the second reference voltage VR2 to the second terminal TA2.
  • the third switch SW3 is used to selectively couple the amplified output terminal NT to the first terminal TA1.
  • the fourth switch SW4 is used to selectively couple the voltage output terminal NVO to the second terminal TA2.
  • the fourth switch SW4 can be implemented by a transmission gate. However, it is possible to implement the first switch SW1 / the second switch SW2 / the third switch SW3 / the fourth switch SW4 using various types of switches.
  • the first charge pump 244 may include, but is not limited to, a second capacitor C2, a first switch SW5, a second switch SW6, a third switch SW7, and a fourth switch SW8.
  • the second capacitor C2 has a first terminal TB1 and a second terminal TB2.
  • the first switch SW5 is used to selectively couple the predetermined voltage VSS to the first terminal TB1.
  • the second switch SW6 is used to selectively couple the second reference voltage VR2 to the second terminal TB2.
  • the third switch SW7 is used to selectively couple the amplified output terminal NT to the first terminal TB1.
  • the fourth switch SW8 is used to selectively couple the voltage output terminal NVO to the second terminal TB2.
  • the fourth switch SW8 can be implemented by a transmission gate. However, it is possible to implement the first switch SW5 / the second switch SW6 / the third switch SW7 / the fourth switch SW8 with various types of switches.
  • the switch module 246 is used for selectively coupling the voltage output terminal NVO to the control terminal TC1 of the first transistor M1, so as to selectively use the driving voltage VD as the first control voltage M1G.
  • the switch module 246 can also selectively couple the voltage output terminal NVO to the control terminal TC2 of the second transistor M1 to selectively use the driving voltage VD as the second control voltage M2G.
  • the switch module 246 may include a fifth switch SW9, a sixth switch SW10, a seventh switch SW11, and an eighth switch SW12.
  • the fifth switch SW9 is used to selectively couple the predetermined voltage VSS to the control terminal TC1 of the first transistor M1.
  • the sixth switch SW10 is used to selectively couple the voltage output terminal NVO to the control terminal TC1 of the first transistor M1.
  • the seventh switch SW11 is used to selectively couple the predetermined voltage VSS to the control terminal TC2 of the second transistor M2.
  • the eighth switch SW12 is used to selectively couple the voltage output terminal NVO to the control terminal TC2 of the second transistor M2.
  • the timing controller 248 is coupled to the charge pump circuit 242 and the switch module 246, and is used to control the operation timing of each switch in the charge pump circuit 242 and the switch module 246.
  • the timing controller 248 may generate a first control signal P1H, a second control signal P1L, a third control signal P2H, and a fourth control signal P2L, so as to control the operation timing of each switch in the charge pump circuit 242 .
  • the second control signal P1L may be an inverted signal of the first control signal P1H
  • the fourth control signal P2L may be an inverted signal of the third control signal P2H.
  • the present invention is not limited to this.
  • the first switch SW1 can be switched according to the third control signal P2H
  • the second switch SW2 can be switched according to the fourth control signal P2L
  • the third switch SW3 can be switched according to the first control signal P1H And the second control signal P1L for switching
  • the fourth switch SW4 can be switched according to the second control signal P1L.
  • the first switch SW1 may be turned on when the third control signal P2H has a high level (for example, corresponding to a logic level "1"), and the second switch SW2 may be low when the fourth control signal P2L is low.
  • the third switch SW3 may be turned on when the first control signal P1H has a high level (or the second control signal P1L has a low level), and
  • the fourth switch SW4 can be turned on when the second control signal P1L has a low level.
  • the first switch SW5 can be switched according to the first control signal P1H
  • the second switch SW6 can be switched according to the second control signal P1L
  • the third switch SW7 can be switched according to the third control signal P2H
  • the fourth control signal P2L for switching and the fourth switch SW8 can be switched according to the fourth control signal P2L.
  • the timing controller 248 can also generate a fifth control signal SG3, a sixth control signal SG4, a seventh control signal SG5, and an eighth control signal SG6, so as to control the operation timing of each switch in the switch module 246.
  • the fifth switch SW9 can be switched according to the fifth control signal SG3, the sixth switch SW10 can be switched according to the fifth control signal SG4, the seventh switch SW11 can be switched according to the seventh control signal SG5, and the eighth switch SW12 can be switched according to the eighth control signal SG6.
  • the fifth switch SW9 can be turned on when the fifth control signal SG3 has a high level
  • the sixth switch SW10 can be turned on when the sixth control signal SG4 has a low level
  • the seventh switch SW11 can be turned on in the seventh
  • the control signal SG5 is turned on when it has a high level
  • the eighth switch SW12 can be turned on when the eighth control signal SG6 has a low level.
  • the timing controller 248 may generate a control signal for controlling each switch according to a charge pump control signal CLK, a normal start signal PWD, and a soft start signal SS, thereby controlling the switching operation of each switch.
  • a charge pump control signal CLK a charge pump control signal
  • PWD normal start signal
  • SS soft start signal
  • FIG. 3 is a schematic diagram of an example of a control signal timing of each switch shown in FIG. 2.
  • FIG. 4 is a waveform diagram of an embodiment of a voltage signal generated in response to the control signal timing shown in FIG. 3.
  • the charge pump control signal CLK and the normal start signal PWD each have a high level (for example, corresponding to a logic level "1"), so that the voltage regulator (ie, the voltage regulator 100 shown in FIG.
  • the timing controller 248 may generate a first control signal P1H having a low level (for example, corresponding to a logic level “0”) and a third control signal P2H having a high level. This causes the first switch SW1 and the second switch SW2 of the first charge pump 243 to be turned on, and the third switch SW3 and the fourth switch SW4 to be turned off to pre-charge the first capacitor C1. For example, in a case where the predetermined voltage VSS is a ground voltage, the first capacitor C1 may be charged to the second reference voltage VR2.
  • the fifth control signal SG3, the sixth control signal SG4, the seventh control signal SG5, and the eighth control signal SG6 all have a high level. This turns on the fifth switch SW9, the sixth switch SW10 is turned off, the seventh switch SW11 is turned on, and the eighth switch SW12 is turned off.
  • the switching module 246 can couple the predetermined voltage VSS to the control terminal TC1 of the first transistor M1 and the control terminal TC2 of the second transistor M2. That is, the control circuit 140 may use the predetermined voltage VSS as the first control voltage M1G and the second control voltage M2G, thereby turning off the first transistor M1 and the second transistor M2.
  • the charge pump control signal CLK and the normal start signal PWD are at a low level, and the soft start signal SS is at a high level.
  • the voltage regulator can be operated in a soft-startup mode to avoid excessive surge current and reduce the reliability of the circuit.
  • the first control signal P1H is at a high level and the third control signal P2H is at a low level (time point t1)
  • the first switch SW1 and the second switch SW2 of the first charge pump 243 are turned off, and the third switch SW3 and the first switch The four switches SW4 are turned on.
  • the level of the second terminal TA2 of the first capacitor C1 is converted into an amplified voltage OPV plus the original voltage drop across the first capacitor C1.
  • the first charge pump 243 may convert the amplified voltage OPV into a driving voltage VD.
  • the first switch SW5 and the second switch SW6 of the second charge pump 244 are turned on, and the third switch SW7 and the fourth switch SW8 are turned off to charge the second capacitor C2.
  • the fifth control signal SG3 and the sixth control signal SG4 are at a high level, and the seventh control signal SG5 and the eighth control signal SG6 are at a low level.
  • This turns on the fifth switch SW9, the sixth switch SW10 is turned off, the seventh switch SW11 is turned off, and the eighth switch SW12 is turned on.
  • the switching module 246 can couple the predetermined voltage VSS to the control terminal TC1 of the first transistor M1, and couple the voltage output terminal NVO to the control terminal TC2 of the second transistor M2. That is, the control circuit 140 may use the predetermined voltage VSS as the first control voltage M1G to turn off the first transistor M1, and use the driving voltage VD as the second control voltage M2G to turn on the second transistor M2.
  • the second transistor M2 may have a smaller width-to-length ratio (W / L ratio), and therefore may have a smaller on-current. Therefore, in the soft-start mode, by driving the second transistor M2 with a smaller aspect ratio, the convergence of the output voltage VOUT is relatively gentle (the required convergence time is marked as TS1), and the inrush current during startup is reduced.
  • the voltage regulator can be operated in a normal start mode (normal mode).
  • the fifth control signal SG3, the sixth control signal SG4, the seventh control signal SG5, and the eighth control signal SG6 are all at a low level. This turns off the fifth switch SW9, the sixth switch SW10 is turned on, the seventh switch SW11 is turned off, and the eighth switch SW12 is turned on.
  • the switch module 246 can couple the voltage output terminal NVO to the control terminal TC1 of the first transistor M1 and the control terminal TC2 of the second transistor M2.
  • control circuit 140 may use the driving voltage VD as the first control voltage M1G and the second control voltage M2G, thereby turning on the first transistor M1 and the second transistor M2. Since the control circuit 140 can simultaneously drive the first transistor M1 and the second transistor M2, the output current flowing to the load capacitor CL is increased, and the convergence time of the output voltage VOUT is shortened (not labeled in FIG. 4).
  • the first capacitor C1 and the second capacitor C2 may be alternately coupled between the voltage input terminal NVI and the voltage output terminal NVO, so that the first charge pump 243 and the second charge pump 244 alternately amplify The voltage OPV is converted into a driving voltage VD.
  • the first capacitor C1 is coupled between the voltage input terminal NVI and the voltage output terminal NVO
  • the first charge pump 243 outputs the driving voltage VD from the voltage output terminal NVO
  • the second capacitor C2 is coupled to the predetermined voltage VSS and the second capacitor.
  • Reference voltage VR2 Reference voltage
  • the second charge pump 244 When the second capacitor C2 is coupled between the voltage input terminal NVI and the voltage output terminal NVO, the second charge pump 244 outputs the driving voltage VD from the voltage output terminal NVO, and the first capacitor C1 is coupled to the predetermined voltage VSS and the second capacitor. Reference voltage VR2.
  • the first control signal P1H may be switched from high level to low level (time point t3) to turn off the first charge pump 243
  • the third control signal P2H can be switched from a low level to a high level (time point t4) to turn on the first switch SW1 and the second switch SW2 of the first charge pump 243, and turn on the second charge pump 244.
  • the third switch SW7 and the fourth switch SW8 are examples of the third switch SW7 and the fourth switch SW8.
  • the first capacitor C1 can be charged for a predetermined time TP2, and the level of the second terminal TB2 of the second capacitor C2 can be converted into an amplified voltage OPV plus the original voltage drop across the second capacitor C2 (such as the second reference Voltage difference between the voltage VR2 and the predetermined voltage VSS). That is, the second charge pump 244 can convert the amplified voltage OPV into a driving voltage VD, which can be provided to the control terminal TC1 of the first transistor M1 and the control terminal TC2 of the second transistor M2 through the voltage output terminal NVO.
  • the third control signal P2H may be switched from high level to low level (time point t5) to turn off the first charge pump 243.
  • the first control signal P1H can be switched from a low level to a high level (time point t6) to turn on the third switch SW3 and the fourth switch SW4 of the first charge pump 243, and turn on the second charge pump 244.
  • the first switch SW5 and the second switch SW6 are examples of the third switch SW3 and the fourth switch SW4 of the first charge pump 243.
  • the level of the second terminal TA2 of the first capacitor C1 can be converted into the amplified voltage OPV plus the original voltage drop across the first capacitor C1 (such as the voltage difference between the second reference voltage VR2 and the predetermined voltage VSS).
  • the second capacitor C2 can be charged for a predetermined time TP1. That is, the first charge pump 243 can convert the amplified voltage OPV into a driving voltage VD, which can be provided to the control terminal TC1 of the first transistor M1 and the control terminal TC2 of the second transistor M2 through the voltage output terminal NVO.
  • the first control signal P1H and the third control signal P2H can be implemented by non-overlapping signals to improve the reliability of the circuit. For example, the point in time when the first control signal P1H is switched from high to low (such as time point t3) and the point in time when the third control signal P2H is switched from low to high (such as time point t4) ) After a predetermined time TNOV, the point in time when the third control signal P2H is switched from high to low (such as time point t5) and the point in time when the first control signal P1H is switched from low to high (such as Time point t6) is separated by a predetermined time TNOV.
  • the first charge pump 243 and the second charge pump 244 alternately output the driving voltage VD from the voltage output terminal NVO, so that the driving voltage VD can be maintained at a stable level, thereby improving the stability of the output voltage VOUT.
  • the switching circuit topology of at least one of the first charge pump 243 and the second charge pump 244 shown in FIG. 2 may be implemented by other circuit structures.
  • the second switch SW2 and the fourth switch SW4 of the first charge pump 243 may be implemented by a three-way switch to couple the second terminal TA2 of the first capacitor C1 to the second reference voltage VR2 and One of the voltage output terminals NVO.
  • the second switch SW6 and the fourth switch SW8 of the second charge pump 244 may be implemented by a three-way switch to couple the second terminal TB2 of the second capacitor C2 to the second reference voltage VR2. And one of the voltage output terminals NVO.
  • the switching circuit topology of the switching module 246 shown in FIG. 2 may be implemented by other circuit structures.
  • the fifth switch SW9 and the sixth switch SW10 may be implemented by three switches to couple the control terminal C1 of the first transistor M1 to one of the voltage output terminal NVO and the predetermined voltage VSS.
  • the first charge pump 243 and the second charge pump 244 shown in FIG. 2 may perform step-down level conversion on the amplified voltage OPV and alternately generate the driving voltage VD.
  • the first charge pump 243 and the second charge pump 244 may be a buck type.
  • the charge pump is implemented to alternately use the driving voltage VD with a low level as the first control voltage M1G (or the second control voltage M2G).
  • FIG. 5 illustrates a functional block diagram of another embodiment of the voltage regulator of the present invention.
  • the structure of the voltage regulator 500 is based on the structure of the voltage regulator 100 shown in FIG. 1.
  • the main difference between the two is that the pass transistor module 510 of the voltage regulator 500 is implemented by a single transistor.
  • the voltage regulator 500 includes (but is not limited to) a pass transistor module 510, a control circuit 540, and a regulated output terminal NR, an amplifier 120, and a feedback circuit 140 shown in FIG. 1, where the pass transistor module 510 includes the First transistor M1.
  • the control circuit 540 includes a charge pump circuit 242 and a switch module 546 shown in FIG. 2.
  • the switch module 546 is used to selectively couple the voltage output terminal NVO to the control terminal TC1 of the first transistor M1.
  • the switch module 546 may include a fifth switch SW9 and a sixth switch SW10 shown in FIG. 2.
  • the switch module 546 can couple the voltage output terminal NVO to the control terminal TC1 of the first transistor M1 to turn on the first transistor M1.
  • the fifth switch SW9 is turned off and the sixth switch SW10 is turned on, so that the driving voltage VD output by the first charge pump 243 and the second charge pump 244 alternately is used as the first control voltage M1G.
  • the switching module 546 may couple the predetermined voltage VSS to the control terminal TC1 of the first transistor M1 to turn off the first transistor M1.
  • the fifth switch SW9 is turned on and the sixth switch SW10 is turned off to use the predetermined voltage VSS as the first control voltage M1G.
  • FIG. 6 is a flowchart of an embodiment of a method for controlling a voltage regulator according to the present invention.
  • the regulator includes a first transistor, a regulated output terminal, and an amplifier.
  • a first connection terminal of the first transistor is coupled to the regulated output terminal.
  • the steps are not necessarily performed in the order shown in FIG. 6. For example, some steps can be inserted in it.
  • the control method shown in FIG. 6 is described below with reference to the control circuit 140 shown in FIG. 2. However, it is also feasible to apply the control method shown in FIG. 6 to the control circuit 540 shown in FIG. 5.
  • the control method shown in FIG. 6 can be briefly summarized as follows.
  • Step 602 A first capacitor is alternately coupled between an amplification output terminal and a voltage output terminal of the amplifier and between a predetermined voltage and a reference voltage to generate a driving voltage at the voltage output terminal.
  • the timing controller 248 may switch the conducting states of the first switch SW1, the second switch SW2, the third switch SW3, and the fourth switch SW4 of the first charge pump 243, so that the first capacitor C1 is alternately coupled to the amplifier. Between the output terminal NT and the voltage output terminal NVO and between the predetermined voltage VSS and the second reference voltage VR2, and the first charge pump 243 is caused to generate a driving voltage VD at the voltage output terminal NVO.
  • Step 604 Alternately coupling a second capacitor between the predetermined voltage and the reference voltage, and between the amplifier output terminal and the voltage output terminal of the amplifier, so that the voltage output terminal The driving voltage is generated.
  • the timing controller 248 may switch the conducting states of the first switch SW5, the second switch SW6, the third switch SW7, and the fourth switch SW8 of the second charge pump 244, so that the second capacitor C2 is alternately coupled to a predetermined Between the voltage VSS and the second reference voltage VR2, and between the amplified output terminal NT and the voltage output terminal NVO, the second charge pump 244 is caused to generate a driving voltage VD at the voltage output terminal NVO.
  • Step 606 The voltage output terminal is selectively coupled to a control terminal of the first transistor.
  • the switch module 246 selectively couples the voltage output terminal NVO to the control terminal TC1 of the first transistor M1.
  • step 602 and step 604 when one of the first capacitor and the second capacitor is coupled between the amplifier output terminal of the amplifier and the control terminal of the transmission transistor, The other of the first capacitor and the second capacitor is coupled between the predetermined voltage and the reference voltage.
  • the other capacitor of the first capacitor C1 and the second capacitor C2 is coupled to a predetermined capacitor.
  • the voltage VSS is between the second reference voltage VR2. That is, the first capacitor C1 and the second capacitor C2 are alternately coupled between the amplification output terminal NT and the voltage output terminal NVO.
  • step 606 when the voltage regulator operates in a normal startup mode, the voltage output terminal may be coupled to the control terminal of the first transistor.
  • the predetermined voltage may be coupled to the control terminal of the first transistor.
  • the switch module 246 can couple the voltage output terminal NVO to the control terminal TC1 of the first transistor M1.
  • the switching module 246 may couple the predetermined voltage VSS to the control terminal TC1 of the first transistor M1.
  • the voltage regulator may further include a second transistor.
  • the control method disclosed in the present invention may also selectively couple the voltage output terminal to a control terminal of the second transistor.
  • the switch module 246 can couple the predetermined voltage VSS to the control terminal TC2 of the second transistor M2.
  • the switch module 246 can couple the voltage output terminal NVO to the control terminal TC2 of the second transistor M2.
  • the voltage stabilization control mechanism disclosed in the present invention can use multiple charge pumps to alternately convert the voltage output by the amplifier, so that the multiple charge pumps alternately generate the driving voltage of the transmission transistor, thereby improving the stability of the output voltage.
  • the disclosed regulator control mechanism can selectively provide driving voltages alternately generated by multiple charge pumps to a plurality of transmission transistors according to different regulator operation modes, and has the effect of low energy consumption.

Abstract

A voltage regulator (100), and a control circuit and a control method for the voltage regulator (100). The voltage regulator (100) comprises an amplifier (120), a charge pump circuit (242), a first transistor (M1), and a regulated voltage output end (NR). A first input end (NI1) and a second input end (NI2) of the amplifier (120) are respectively coupled to a first reference voltage (VR1) and a feedback voltage (VFB). An amplifier output end (NT) of the amplifier (120) is used for outputting an amplified voltage (OPV).The charge pump circuit (242) comprises a first charge pump (243) and a second charge pump (244) coupled in parallel between a voltage input end (NVI) and a voltage output end (NVO). The first charge pump (243) and the second charge pump (244) are used for alternately converting the amplified voltage (OPV) to output a driving voltage (VD) from the voltage output end (NVO). A control end (TC1) of the first transistor (M1) receives the driving voltage (VD) by means of the voltage output end (NVO). The regulated voltage output end (VR) is coupled to a first connection end (T11) of the first transistor (M1), and is used for outputting an output voltage (VOUT). The voltage regulator (100) can improve the stability of the output voltage (VOUT) and has the effect of low power consumption.

Description

稳压器、稳压器的控制电路以及稳压器的控制方法Voltage regulator, control circuit of voltage regulator, and method for controlling voltage regulator 技术领域Technical field
本发明涉及稳压技术，尤其涉及一种利用并联耦接的多个电荷泵交替地提供驱动电压的稳压器及其相关的稳压器的控制电路和控制方法。The present invention relates to voltage stabilization technology, and in particular, to a voltage regulator using a plurality of charge pumps coupled in parallel to alternately provide a driving voltage, and a control circuit and control method thereof.
背景技术Background technique
通常电源管理系统会使用低压差稳压器(low dropout regulator，LDO)以减少电源线所引起的串扰。然而，受到工艺因素及漏电流的影响，低压差稳压器的输出电压稳定性和电源抑制比仍有待改善。此外，在某些应用场合中(诸如数字无线通信)，信号处理操作仅发生在一段时间内的某些时隙(time slot)。也就是说，低压差稳压器不需要时时刻刻处在启动状态。Low-dropout regulators (LDOs) are commonly used in power management systems to reduce crosstalk caused by power lines. However, due to the influence of process factors and leakage current, the output voltage stability and power supply rejection ratio of the low-dropout regulator still need to be improved. In addition, in some applications (such as digital wireless communications), signal processing operations occur only at certain time slots within a period of time. In other words, the low-dropout regulator does not need to be in the startup state all the time.
因此，需要一种创新的稳压结构，其可同时满足良好的输出电压稳定性和电源抑制比，以及低耗能的需求。Therefore, there is a need for an innovative voltage stabilization structure that can simultaneously meet the requirements of good output voltage stability, power supply rejection ratio, and low power consumption.
发明内容Summary of the invention
本发明的目的之一在于公开一种利用并联耦接的多个电荷泵交替地提供驱动电压的稳压器及其相关的稳压器的控制电路和控制方法，来解决上述问题。One of the objectives of the present invention is to disclose a regulator using a plurality of charge pumps coupled in parallel to alternately provide a driving voltage and a control circuit and a control method thereof to solve the above problems.
本发明的一实施例公开了一种稳压器。所述稳压器包括放大器、电荷泵电路、第一晶体管以及稳压输出端。所述放大器具有第一输入端、第二输入端和放大输出端。所述第一输入端耦接于第一参考电压，所述第二输入端耦接于回授电压，以及所述放大输出端用以 输出放大电压。所述电荷泵电路具有电压输入端和电压输出端，所述电压输入端耦接于所述放大输出端。所述电荷泵电路包括第一电荷泵和第二电荷泵，所述第一电荷泵和所述第二电荷泵并联耦接于所述电压输入端与所述电压输出端之间。所述第一电荷泵和所述第二电荷泵用以交替地转换所述放大电压，以从所述电压输出端输出驱动电压。所述第一晶体管的控制端用以通过所述电压输出端接收所述驱动电压。所述稳压输出端耦接于所述第一晶体管的第一连接端，用以输出输出电压。An embodiment of the invention discloses a voltage regulator. The voltage regulator includes an amplifier, a charge pump circuit, a first transistor, and a regulated output terminal. The amplifier has a first input terminal, a second input terminal and an amplified output terminal. The first input terminal is coupled to a first reference voltage, the second input terminal is coupled to a feedback voltage, and the amplified output terminal is used to output an amplified voltage. The charge pump circuit has a voltage input terminal and a voltage output terminal, and the voltage input terminal is coupled to the amplified output terminal. The charge pump circuit includes a first charge pump and a second charge pump, and the first charge pump and the second charge pump are coupled in parallel between the voltage input terminal and the voltage output terminal. The first charge pump and the second charge pump are used to alternately convert the amplified voltage to output a driving voltage from the voltage output terminal. The control terminal of the first transistor is configured to receive the driving voltage through the voltage output terminal. The regulated output terminal is coupled to a first connection terminal of the first transistor, and is configured to output an output voltage.
本发明的一实施例公开了一种稳压器的控制电路。所述稳压器包括第一晶体管、稳压输出端以及放大器。所述第一晶体管的第一连接端耦接于所述稳压输出端。所述控制电路包括电荷泵电路和开关模块。所述电荷泵电路具有电压输入端和电压输出端，所述电压输入端耦接于所述放大器的放大输出端以接收放大电压。所述电荷泵电路包括第一电荷泵和第二电荷泵，所述第一电荷泵和所述第二电荷泵并联耦接于所述电压输入端与所述电压输出端之间。所述第一电荷泵和所述第二电荷泵用以交替地转换所述放大电压，以从所述电压输出端输出驱动电压。所述开关模块用以选择性地将所述电压输出端耦接于所述第一晶体管的控制端。An embodiment of the invention discloses a control circuit of a voltage regulator. The regulator includes a first transistor, a regulated output terminal, and an amplifier. A first connection terminal of the first transistor is coupled to the regulated output terminal. The control circuit includes a charge pump circuit and a switch module. The charge pump circuit has a voltage input terminal and a voltage output terminal, and the voltage input terminal is coupled to the amplifier output terminal of the amplifier to receive the amplified voltage. The charge pump circuit includes a first charge pump and a second charge pump, and the first charge pump and the second charge pump are coupled in parallel between the voltage input terminal and the voltage output terminal. The first charge pump and the second charge pump are used to alternately convert the amplified voltage to output a driving voltage from the voltage output terminal. The switch module is used to selectively couple the voltage output terminal to a control terminal of the first transistor.
本发明的一实施例公开了一种稳压器的控制方法。所述稳压器包括第一晶体管、稳压输出端以及放大器。所述第一晶体管的第一连接端耦接于所述稳压输出端。所述控制方法包括：将第一电容交替地耦接于所述放大器的放大输出端与电压输出端之间以及预定电压与参考电压之间，以在所述电压输出端产生驱动电压；将第二电容交替地耦接于所述预定电压与所述参考电压之间以及所述放大器的所述放大输出端与所述电压输出端之间，以在所述电压输出端产生所述驱动电压，其中当所述第一电容与所述第二电容其中的一电容耦接于所述放大器的所述放大输出端与所述电压输出端之间时，所述第一电容与所述第二电容其中的另一电容耦接于所述预定电压与所述参考电压之间；以及选择性地将所述电压输出端耦接于所述第一晶体管的控制端。An embodiment of the invention discloses a control method of a voltage regulator. The regulator includes a first transistor, a regulated output terminal, and an amplifier. A first connection terminal of the first transistor is coupled to the regulated output terminal. The control method includes: alternately coupling a first capacitor between an amplifier output terminal and a voltage output terminal of the amplifier and between a predetermined voltage and a reference voltage to generate a driving voltage at the voltage output terminal; Two capacitors are alternately coupled between the predetermined voltage and the reference voltage and between the amplifier output terminal and the voltage output terminal of the amplifier to generate the driving voltage at the voltage output terminal. When one of the first capacitor and the second capacitor is coupled between the amplifier output terminal and the voltage output terminal of the amplifier, the first capacitor and the second capacitor Another capacitor is coupled between the predetermined voltage and the reference voltage; and the voltage output terminal is selectively coupled to the control terminal of the first transistor.
附图说明BRIEF DESCRIPTION OF THE DRAWINGS
图1是本发明稳压器的一实施例的功能方框示意图。FIG. 1 is a functional block diagram of an embodiment of the voltage regulator of the present invention.
图2是图1所示的控制电路140的一实施例的示意图。FIG. 2 is a schematic diagram of an embodiment of the control circuit 140 shown in FIG. 1.
图3是图2所示的各开关的控制信号时序的一实施例的示意图。FIG. 3 is a schematic diagram of an example of a control signal timing of each switch shown in FIG. 2.
图4是回应图3所示的控制信号时序所产生的电压信号的一实施例的波形图。FIG. 4 is a waveform diagram of an embodiment of a voltage signal generated in response to the control signal timing shown in FIG. 3.
图5绘示了本发明稳压器的另一实施例的功能方框示意图。FIG. 5 illustrates a functional block diagram of another embodiment of the voltage regulator of the present invention.
图6是本发明稳压器的控制方法的一实施例的流程图。FIG. 6 is a flowchart of an embodiment of a method for controlling a voltage regulator according to the present invention.
其中，附图标记说明如下：Among them, the reference signs are described as follows:
100、500                         稳压器100, 500: voltage regulator
110、510                         传输晶体管模块110, 510: transmission transistor module
120                              放大器120. Amplifier
130                              回授电路130. Feedback circuit
140、540                         控制电路140, 540 control circuit
150                              电压产生电路150. Voltage generation circuit
242                              电荷泵电路242 charge pump circuit
243                              第一电荷泵243 The first charge pump is the first charge pump.
244                              第二电荷泵244 Second charge pump
246、546                         开关模块246, 546: Switching module
248                              时序控制器248: timing controller
602、604、606                    步骤602, 604, 606 Steps
VS1                              第一电压源VS1: The first voltage source
VS2                              第二电压源VS2 The second voltage source is the second voltage source.
NR                               稳压输出端NR: Regulated output terminal
CL                               负载电容CL: Load capacitance
M1                                第一晶体管M1: the first transistor
M2                                第二晶体管M2 The second transistor is a second transistor.
R1                                第一电阻R1: the first resistance
R2                                第二电阻R2 The second resistor is the second resistor.
R3                                第三电阻R3 The third resistor is the third resistor.
R4                                第四电阻R4 The fourth resistor is the fourth resistor.
TC1、TC2                          控制端TC1, TC2, control terminal
T11、T21                          第一连接端T11, T21: The first connection terminal
T12、T22                          第二连接端T12, T22 The second connection terminal
NI1                               第一输入端NI1 The first input terminal is the first input terminal.
NI2                               第二输入端NI2 The second input terminal is the second input terminal.
NT                                放大输出端NT: Amplified output terminal
NS                                电源输入端NS: Power input terminal
NVI                               电压输入端NVI: voltage input terminal
NVO                               电压输出端NVO: voltage output terminal
C1                                第一电容C1: The first capacitor is the first capacitor.
C2                                第二电容C2 The second capacitor is the second capacitor.
TA1、TB1                          第一端TA1, TB1, the first end
TA2、TB2                          第二端TA2, TB2, the second end
SW1、SW5                          第一开关SW1, SW5: the first switch
SW2、SW6                          第二开关SW2, SW6 The second switch is the second switch.
SW3、SW7                          第三开关SW3, SW7 The third switch is the third switch.
SW4、SW8                          第四开关SW4, SW8 The fourth switch is the fourth switch.
SW9                               第五开关SW9 The fifth switch is the fifth switch.
SW10                              第六开关SW10 The sixth switch is the sixth switch.
SW11                              第七开关SW11 The seventh switch is the seventh switch.
SW12                              第八开关SW12 The eighth switch is the following:
VOUT                              输出电压VOUT: output voltage
VP                                电源电压VP: power supply voltage
M1G                               第一控制电压M1G The first control voltage is the first control voltage.
M2G                             第二控制电压M2G The second control voltage is the second control voltage.
I1                              第一输出电流I1 The first output current is the first output current.
I2                              第二输出电流I2 The second output current is the second output current.
VR1                             第一参考电压VR1 The first reference voltage is VR1.
VR2                             第二参考电压VR2 The second reference voltage is VR2.
VFB                             回授电压VFB: The feedback voltage
OPV                             放大电压OPV: Amplified voltage
VSS                             预定电压VSS: Predetermined voltage
VD                              驱动电压VD The driving voltage is:
P1H                             第一控制信号P1H: The first control signal
P1L                             第二控制信号P1L: the second control signal
P2H                             第三控制信号P2H: the third control signal
P2L                             第四控制信号P2L The fourth control signal is the fourth control signal.
SG3                             第五控制信号SG3 The fifth control signal is the fifth control signal.
SG4                             第六控制信号SG4 The sixth control signal is the sixth control signal.
SG5                             第七控制信号SG5: Seventh control signal
SG6                             第八控制信号SG6: the eighth control signal
CLK                             电荷泵控制信号CLK: charge pump control signal
PWD                             正常启动信号PWD: The normal start signal is the normal start signal.
SS                              软启动信号SS: soft start signal
t0、t1、t2、t3、t4、t5、t6      时间点t0, t1, t2, t3, t4, t5, t6
TS1                             收敛时间TS1 Convergence time
TP1、TP2、TNOV                  预定时间TP1, TP2, TNOV, scheduled time
具体实施方式detailed description
在说明书及之前的权利要求书当中使用了某些词汇来指称特定的组件。本领域的技术人员应可理解，制造商可能会用不同的名词来称呼同样的组件。本说明书及之前的权利要求书并不以名称的差异来作为区分组件的方式，而是以组件在功能上的差异来作为区分 的基准。在通篇说明书及之前的权利要求书当中所提及的“包括”为一开放式的用语，故应解释成“包括但不限定于”。此外，“耦接”一词在此包括任何直接和间接的电连接手段。因此，若文中描述一第一装置耦接于一第二装置，则代表所述第一装置可直接电连接于所述第二装置，或通过其它装置或连接手段间接地电连接到所述第二装置。Certain words have been used in the description and the preceding claims to refer to particular components. Those skilled in the art will understand that manufacturers may use different terms to refer to the same components. This specification and the previous claims do not use the differences in names as a way to distinguish components, but rather use the differences in functions of components as a basis for distinguishing components. In the entire specification and in the preceding claims, "including" is an open-ended term and should be interpreted as "including but not limited to". Furthermore, the term "coupled" includes any direct and indirect means of electrical connection. Therefore, if a first device is described as being coupled to a second device, it means that the first device can be directly electrically connected to the second device, or indirectly electrically connected to the first device through other devices or connection means.二 装置。 Two devices.
本发明所公开的稳压器结构可利用多个电荷泵交替产生的驱动电压，控制传输晶体管的操作，以维持良好的输出电压稳定性。在某些实施例中，本发明所公开的稳压器结构可根据不同的稳压器操作模式，将多个电荷泵交替产生的驱动电压选择性地提供给多个传输晶体管，具备低耗能的功效。进一步的说明如下。The voltage regulator structure disclosed by the present invention can use the driving voltage alternately generated by a plurality of charge pumps to control the operation of the pass transistor to maintain good output voltage stability. In some embodiments, the voltage regulator structure disclosed in the present invention can selectively provide driving voltages generated by a plurality of charge pumps to a plurality of transmission transistors according to different voltage regulator operation modes, and has low power consumption. Effect. Further explanation is as follows.
图1是本发明稳压器的一实施例的功能方框示意图。稳压器100可实施为(但不限于)一低压差稳压器。于此实施例中，稳压器100可包括一稳压输出端NR、一传输晶体管模块110、一放大器120、一回授电路130以及一控制电路140，其中稳压输出端NR耦接于一负载电容CL，用以输出调节后的电压(即，输出电压VOUT)。FIG. 1 is a functional block diagram of an embodiment of the voltage regulator of the present invention. The voltage regulator 100 may be implemented as, but not limited to, a low dropout voltage regulator. In this embodiment, the regulator 100 may include a regulated output terminal NR, a transmission transistor module 110, an amplifier 120, a feedback circuit 130, and a control circuit 140. The regulated output terminal NR is coupled to a The load capacitor CL is used to output the adjusted voltage (that is, the output voltage VOUT).
传输晶体管模块110耦接于一电源电压VP与稳压输出端NR之间，并可包括一个或多个传输晶体管，其中各传输晶体管可输出一输出电流至稳压输出端NR。举例来说(但本发明不限于此)，传输晶体管模块110可包括一第一晶体管M1和一第二晶体管M2。第一晶体管M1具有一控制端TC1、一第一连接端T11和一第二连接端T12，第二晶体管M2具有一控制端TC2、一第一连接端T21和一第二连接端T22，其中第一连接端T11和第一连接端T21均耦接于电源电压VP，第二连接端T12和第二连接端T22均耦接于稳压输出端NR。第一晶体管M1可根据控制端TC1所接收的一第一控制电压M1G，从第二连接端T12输出一第一输出电流I1。第二晶体管M2可根据控制端TC2所接收的一第二控制电压M2G，从第二连接端T22输出一第二输出电流I2。The transmission transistor module 110 is coupled between a power supply voltage VP and the regulated output terminal NR, and may include one or more transmission transistors, wherein each of the transmission transistors can output an output current to the regulated output terminal NR. For example (but the present invention is not limited thereto), the transmission transistor module 110 may include a first transistor M1 and a second transistor M2. The first transistor M1 has a control terminal TC1, a first connection terminal T11, and a second connection terminal T12. The second transistor M2 has a control terminal TC2, a first connection terminal T21, and a second connection terminal T22. A connection terminal T11 and a first connection terminal T21 are both coupled to the power supply voltage VP, and a second connection terminal T12 and a second connection terminal T22 are coupled to the regulated output terminal NR. The first transistor M1 can output a first output current I1 from the second connection terminal T12 according to a first control voltage M1G received by the control terminal TC1. The second transistor M2 can output a second output current I2 from the second connection terminal T22 according to a second control voltage M2G received by the control terminal TC2.
放大器120具有一第一输入端NI1、一第二输入端NI2和一放 大输出端NT，其中第一输入端NI1耦接于一第一参考电压VR1，第二输入端NI2则是耦接于一回授电压VFB。放大器110用以根据第一参考电压VR1和回授电压VFB，于放大输出端NT输出一放大电压OPV。于此实施例中，第一参考电压VR1可由一第一电压源VS1(诸如带隙基准电压源)来提供。然而，本发明并不以此为限。The amplifier 120 has a first input terminal NI1, a second input terminal NI2, and an amplified output terminal NT. The first input terminal NI1 is coupled to a first reference voltage VR1, and the second input terminal NI2 is coupled to a Feedback voltage VFB. The amplifier 110 is configured to output an amplified voltage OPV at the amplified output terminal NT according to the first reference voltage VR1 and the feedback voltage VFB. In this embodiment, the first reference voltage VR1 may be provided by a first voltage source VS1, such as a bandgap reference voltage source. However, the present invention is not limited to this.
放大器120还可具有一电源输入端NS，其耦接于稳压输出端NR以接收输出电压VOUT。也就是说，放大器120的电源可由调节后的电压(即，输出电压VOUT)所提供，而不是由未节的电压(诸如电源电压VP)所提供。这有助于提升稳压器100的电源抑制比。The amplifier 120 may further have a power input terminal NS, which is coupled to the regulated output terminal NR to receive the output voltage VOUT. That is, the power of the amplifier 120 may be provided by the adjusted voltage (ie, the output voltage VOUT), rather than by a non-segmented voltage (such as the power supply voltage VP). This helps to improve the power supply rejection ratio of the regulator 100.
回授电路130耦接于稳压输出端NR与第二输入端NI2之间，用以根据输出电压VOUT产生回授电压VFB。于此实施例中，回授电路130可由一分压电路来实施，其可包括一第一电阻R1和一第二电阻R2。第一电阻R1耦接于第二输入端NI2与一预定电压VSS(诸如接地电压)之间，第二电阻R2耦接于稳压输出端NR与第二输入端NI2之间。然而，本发明并不以此为限。采用其他电路结构的回授电路均是可行的。The feedback circuit 130 is coupled between the regulated output terminal NR and the second input terminal NI2 to generate a feedback voltage VFB according to the output voltage VOUT. In this embodiment, the feedback circuit 130 may be implemented by a voltage dividing circuit, which may include a first resistor R1 and a second resistor R2. The first resistor R1 is coupled between the second input terminal NI2 and a predetermined voltage VSS (such as a ground voltage), and the second resistor R2 is coupled between the regulated output terminal NR and the second input terminal NI2. However, the present invention is not limited to this. Feedback circuits using other circuit structures are feasible.
控制电路140耦接于放大器120的放大输出端NT，用以根据放大电压OPV产生第一控制电压M1G和第二控制电压M2G。举例来说(但本发明不限于此)，在第一晶体管M1由N型金氧半场效晶体管来实施的实施例中，控制电路140可对放大电压OPV执行电平转换(诸如升压处理)以产生一驱动电压VD，选择性地将驱动电压VD作为第一控制电压M1G，以控制第一晶体管M1的操作。在第一晶体管M1由P型金氧半场效晶体管来实施的实施例中，控制电路140可对放大电压OPV执行电平转换(诸如降压处理)以产生驱动电压VD，选择性地将驱动电压VD作为第一控制电压M1G，以控制第一晶体管M1的操作。相似地，控制电路140可对放大电压OPV执行电平转换以产生驱动电压VD，选择性地将驱动电压VD作为第二控制电压M2G，以控制第二晶体管M2的操作。The control circuit 140 is coupled to the amplification output terminal NT of the amplifier 120 and is configured to generate a first control voltage M1G and a second control voltage M2G according to the amplified voltage OPV. For example (but the invention is not limited thereto), in an embodiment where the first transistor M1 is implemented by an N-type metal-oxide-semiconductor field-effect transistor, the control circuit 140 may perform a level shift (such as a boosting process) on the amplified voltage OPV ) To generate a driving voltage VD, and selectively use the driving voltage VD as the first control voltage M1G to control the operation of the first transistor M1. In an embodiment where the first transistor M1 is implemented by a P-type metal-oxide-semiconductor field-effect transistor, the control circuit 140 may perform a level shift (such as a step-down process) on the amplified voltage OPV to generate a driving voltage VD, and selectively drive the The voltage VD is used as the first control voltage M1G to control the operation of the first transistor M1. Similarly, the control circuit 140 may perform level conversion on the amplified voltage OPV to generate a driving voltage VD, and selectively use the driving voltage VD as the second control voltage M2G to control the operation of the second transistor M2.
于此实施例中，控制电路140可根据一第二参考电压VR2对放 大电压OPV执行电平转换，以产生驱动电压VD。第二参考电压VR2可由一电压产生电路150来提供，其中电压产生电路150可包括(但不限于)一第二电压源VS2、一第三电阻R3和一第四电阻R4。在某些实施例中，第二参考电压VR2也可以是控制电路140内部提供的一参考电压。In this embodiment, the control circuit 140 may perform level conversion on the amplified voltage OPV according to a second reference voltage VR2 to generate a driving voltage VD. The second reference voltage VR2 may be provided by a voltage generating circuit 150. The voltage generating circuit 150 may include (but is not limited to) a second voltage source VS2, a third resistor R3, and a fourth resistor R4. In some embodiments, the second reference voltage VR2 may also be a reference voltage provided inside the control circuit 140.
为了便于理解本发明的技术特征，以下采用一示范性电路结构来说明本发明所公开的稳压器的控制细节。然而，这只是方便说明而已。任何采用交替执行电平转换的多个电荷泵的电路实施方式均是可行的。请连同图1参阅图2。图2是图1所示的控制电路140的一实施例的示意图。于此实施例中，控制电路140包括一电荷泵电路242、一开关模块246以及一时序控制器248。电荷泵电路242具有一电压输入端NVI和一电压输出端NVO。电压输入端NVI耦接于放大输出端NT以接收放大器120所产生的放大电压OPV。电荷泵电路242可包括多个电荷泵，其可交替地转换(诸如升压或降压的电平转换)放大电压OPV以产生驱动电压VD。In order to facilitate understanding of the technical features of the present invention, an exemplary circuit structure is used below to explain the control details of the voltage regulator disclosed in the present invention. However, this is just for convenience. Any circuit implementation using multiple charge pumps that alternately perform level shifting is possible. Please refer to FIG. 2 together with FIG. 1. FIG. 2 is a schematic diagram of an embodiment of the control circuit 140 shown in FIG. 1. In this embodiment, the control circuit 140 includes a charge pump circuit 242, a switch module 246, and a timing controller 248. The charge pump circuit 242 has a voltage input terminal NVI and a voltage output terminal NVO. The voltage input terminal NVI is coupled to the amplification output terminal NT to receive the amplified voltage OPV generated by the amplifier 120. The charge pump circuit 242 may include a plurality of charge pumps which may alternately convert (such as step-up or step-down level conversion) the amplified voltage OPV to generate the driving voltage VD.
于此实施例中，电荷泵电路242包括一第一电荷泵243和一第二电荷泵244。第一电荷泵243和第二电荷泵244并联耦接于电压输入端NVI与电压输出端NVO之间。此外，第一电荷泵243和第二电荷泵244用以交替地转换放大电压OPV，以从电压输出端NVO输出驱动电压VD。也就是说，第一电荷泵243和第二电荷泵244可轮流从电压输出端NVO输出驱动电压VD。In this embodiment, the charge pump circuit 242 includes a first charge pump 243 and a second charge pump 244. The first charge pump 243 and the second charge pump 244 are coupled in parallel between the voltage input terminal NVI and the voltage output terminal NVO. In addition, the first charge pump 243 and the second charge pump 244 are used to alternately convert the amplified voltage OPV to output the driving voltage VD from the voltage output terminal NVO. That is, the first charge pump 243 and the second charge pump 244 may output the driving voltage VD from the voltage output terminal NVO in turn.
第一电荷泵243可包括(但不限于)一第一电容C1、一第一开关SW1、一第二开关SW2、一第三开关SW3和一第四开关SW4。第一电容C1具有一第一端TA1和一第二端TA2。第一开关SW1用以选择性地将预定电压VSS耦接于第一端TA1。第二开关SW2用以选择性地将第二参考电压VR2耦接于第二端TA2。第三开关SW3用以选择性地将放大输出端NT耦接于第一端TA1。第四开关SW4用以选择性地将电压输出端NVO耦接于第二端TA2。于此实施例中，第四开关SW4可由一传输门来实施。然而，采用各种类型的开关来实施第一 开关SW1/第二开关SW2/第三开关SW3/第四开关SW4均是可行的。The first charge pump 243 may include, but is not limited to, a first capacitor C1, a first switch SW1, a second switch SW2, a third switch SW3, and a fourth switch SW4. The first capacitor C1 has a first terminal TA1 and a second terminal TA2. The first switch SW1 is used to selectively couple the predetermined voltage VSS to the first terminal TA1. The second switch SW2 is used to selectively couple the second reference voltage VR2 to the second terminal TA2. The third switch SW3 is used to selectively couple the amplified output terminal NT to the first terminal TA1. The fourth switch SW4 is used to selectively couple the voltage output terminal NVO to the second terminal TA2. In this embodiment, the fourth switch SW4 can be implemented by a transmission gate. However, it is possible to implement the first switch SW1 / the second switch SW2 / the third switch SW3 / the fourth switch SW4 using various types of switches.
第一电荷泵244可包括(但不限于)一第二电容C2、一第一开关SW5、一第二开关SW6、一第三开关SW7和一第四开关SW8。第二电容C2具有一第一端TB1和一第二端TB2。第一开关SW5用以选择性地将预定电压VSS耦接于第一端TB1。第二开关SW6用以选择性地将第二参考电压VR2耦接于第二端TB2。第三开关SW7用以选择性地将放大输出端NT耦接于第一端TB1。第四开关SW8用以选择性地将电压输出端NVO耦接于第二端TB2。于此实施例中，第四开关SW8可由一传输门来实施。然而，采用各种类型的开关来实施第一开关SW5/第二开关SW6/第三开关SW7/第四开关SW8均是可行的。The first charge pump 244 may include, but is not limited to, a second capacitor C2, a first switch SW5, a second switch SW6, a third switch SW7, and a fourth switch SW8. The second capacitor C2 has a first terminal TB1 and a second terminal TB2. The first switch SW5 is used to selectively couple the predetermined voltage VSS to the first terminal TB1. The second switch SW6 is used to selectively couple the second reference voltage VR2 to the second terminal TB2. The third switch SW7 is used to selectively couple the amplified output terminal NT to the first terminal TB1. The fourth switch SW8 is used to selectively couple the voltage output terminal NVO to the second terminal TB2. In this embodiment, the fourth switch SW8 can be implemented by a transmission gate. However, it is possible to implement the first switch SW5 / the second switch SW6 / the third switch SW7 / the fourth switch SW8 with various types of switches.
开关模块246用以选择性地将电压输出端NVO耦接于第一晶体管M1的控制端TC1，以选择性地将驱动电压VD作为第一控制电压M1G。此外，开关模块246还可选择性地将电压输出端NVO耦接于第二晶体管M1的控制端TC2，以选择性地将驱动电压VD作为第二控制电压M2G。举例来说(但本发明不限于此)，开关模块246可包括一第五开关SW9、一第六开关SW10、一第七开关SW11和一第八开关SW12。第五开关SW9用以选择性地将预定电压VSS耦接于第一晶体管M1的控制端TC1。第六开关SW10用以选择性地将电压输出端NVO耦接于第一晶体管M1的控制端TC1。第七开关SW11用以选择性地将预定电压VSS耦接于第二晶体管M2的控制端TC2。第八开关SW12用以选择性地将电压输出端NVO耦接于第二晶体管M2的控制端TC2。The switch module 246 is used for selectively coupling the voltage output terminal NVO to the control terminal TC1 of the first transistor M1, so as to selectively use the driving voltage VD as the first control voltage M1G. In addition, the switch module 246 can also selectively couple the voltage output terminal NVO to the control terminal TC2 of the second transistor M1 to selectively use the driving voltage VD as the second control voltage M2G. For example (but the invention is not limited thereto), the switch module 246 may include a fifth switch SW9, a sixth switch SW10, a seventh switch SW11, and an eighth switch SW12. The fifth switch SW9 is used to selectively couple the predetermined voltage VSS to the control terminal TC1 of the first transistor M1. The sixth switch SW10 is used to selectively couple the voltage output terminal NVO to the control terminal TC1 of the first transistor M1. The seventh switch SW11 is used to selectively couple the predetermined voltage VSS to the control terminal TC2 of the second transistor M2. The eighth switch SW12 is used to selectively couple the voltage output terminal NVO to the control terminal TC2 of the second transistor M2.
时序控制器248耦接于电荷泵电路242和开关模块246，用以控制电荷泵电路242和开关模块246中各开关的操作时序。举例来说，时序控制器248可产生一第一控制信号P1H、一第二控制信号P1L、一第三控制信号P2H以及一第四控制信号P2L，从而控制电荷泵电路242中各开关的操作时序。第二控制信号P1L可以是第一控制信号P1H的反相信号，第四控制信号P2L可以是第三控制信号P2H的反相信号。然而，本发明并不以此为限。The timing controller 248 is coupled to the charge pump circuit 242 and the switch module 246, and is used to control the operation timing of each switch in the charge pump circuit 242 and the switch module 246. For example, the timing controller 248 may generate a first control signal P1H, a second control signal P1L, a third control signal P2H, and a fourth control signal P2L, so as to control the operation timing of each switch in the charge pump circuit 242 . The second control signal P1L may be an inverted signal of the first control signal P1H, and the fourth control signal P2L may be an inverted signal of the third control signal P2H. However, the present invention is not limited to this.
对于第一电荷泵243来说，第一开关SW1可根据第三控制信号P2H来进行切换，第二开关SW2可根据第四控制信号P2L来进行切换，第三开关SW3可根据第一控制信号P1H和第二控制信号P1L来进行切换，第四开关SW4可根据第二控制信号P1L来进行切换。于此实施例中，第一开关SW1可于第三控制信号P2H具有高电平(例如，对应于逻辑电平“1”)时导通，第二开关SW2可于第四控制信号P2L具有低电平(例如，对应于逻辑电平“0”)时导通，第三开关SW3可于第一控制信号P1H具有高电平(或第二控制信号P1L具有低电平)时导通，以及第四开关SW4可于第二控制信号P1L具有低电平时导通。For the first charge pump 243, the first switch SW1 can be switched according to the third control signal P2H, the second switch SW2 can be switched according to the fourth control signal P2L, and the third switch SW3 can be switched according to the first control signal P1H And the second control signal P1L for switching, and the fourth switch SW4 can be switched according to the second control signal P1L. In this embodiment, the first switch SW1 may be turned on when the third control signal P2H has a high level (for example, corresponding to a logic level "1"), and the second switch SW2 may be low when the fourth control signal P2L is low. Is turned on at a level (eg, corresponding to a logic level "0"), the third switch SW3 may be turned on when the first control signal P1H has a high level (or the second control signal P1L has a low level), and The fourth switch SW4 can be turned on when the second control signal P1L has a low level.
对于第二电荷泵244来说，第一开关SW5可根据第一控制信号P1H来进行切换，第二开关SW6可根据第二控制信号P1L来进行切换，第三开关SW7可根据第三控制信号P2H和第四控制信号P2L来进行切换，第四开关SW8可根据第四控制信号P2L来进行切换。于此实施例中，第一开关SW5可于第一控制信号P1H具有高电平时导通，第二开关SW6可于第二控制信号P1L具有低电平时导通，第三开关SW7可于第三控制信号P2H具有高电平(或第四控制信号P2L具有低电平)时导通，以及第四开关SW8可于第四控制信号P2L具有低电平时导通。For the second charge pump 244, the first switch SW5 can be switched according to the first control signal P1H, the second switch SW6 can be switched according to the second control signal P1L, and the third switch SW7 can be switched according to the third control signal P2H And the fourth control signal P2L for switching, and the fourth switch SW8 can be switched according to the fourth control signal P2L. In this embodiment, the first switch SW5 can be turned on when the first control signal P1H has a high level, the second switch SW6 can be turned on when the second control signal P1L has a low level, and the third switch SW7 can be turned on in the third The control signal P2H is turned on when it has a high level (or the fourth control signal P2L has a low level), and the fourth switch SW8 can be turned on when the fourth control signal P2L has a low level.
时序控制器248还可产生一第五控制信号SG3、一第六控制信号SG4、一第七控制信号SG5以及一第八控制信号SG6，从而控制开关模块246中各开关的操作时序。其中，第五开关SW9可根据第五控制信号SG3来进行切换，第六开关SW10可根据第五控制信号SG4来进行切换，第七开关SW11可根据第七控制信号SG5来进行切换，第八开关SW12可根据第八控制信号SG6来进行切换。于此实施例中，第五开关SW9可于第五控制信号SG3具有高电平时导通，第六开关SW10可于第六控制信号SG4具有低电平时导通，第七开关SW11可于第七控制信号SG5具有高电平时导通，以及第八开关SW12可于第八控制信号SG6具有低电平时导通。The timing controller 248 can also generate a fifth control signal SG3, a sixth control signal SG4, a seventh control signal SG5, and an eighth control signal SG6, so as to control the operation timing of each switch in the switch module 246. The fifth switch SW9 can be switched according to the fifth control signal SG3, the sixth switch SW10 can be switched according to the fifth control signal SG4, the seventh switch SW11 can be switched according to the seventh control signal SG5, and the eighth switch SW12 can be switched according to the eighth control signal SG6. In this embodiment, the fifth switch SW9 can be turned on when the fifth control signal SG3 has a high level, the sixth switch SW10 can be turned on when the sixth control signal SG4 has a low level, and the seventh switch SW11 can be turned on in the seventh The control signal SG5 is turned on when it has a high level, and the eighth switch SW12 can be turned on when the eighth control signal SG6 has a low level.
于此实施例中，时序控制器248可根据一电荷泵控制信号CLK、一正常启动信号PWD和一软启动信号SS，产生用以控制各开关的控制信号，从而控制各开关的切换操作。请一并参阅图2、图3和图4。图3是图2所示的各开关的控制信号时序的一实施例的示意图。图4是回应图3所示的控制信号时序所产生的电压信号的一实施例的波形图。在时间点t0之前，电荷泵控制信号CLK和正常启动信号PWD均具有高电平(例如，对应于逻辑电平“1”)，致使稳压器(即，图1所示的稳压器100)操作在掉电模式(power-down mode)。时序控制器248可产生具有低电平(例如，对应于逻辑电平“0”)的第一控制信号P1H和具有高电平的第三控制信号P2H。这使得第一电荷泵243的第一开关SW1和第二开关SW2导通，第三开关SW3和第四开关SW4关闭，以对第一电容C1进行预充电(pre-charge)。举例来说，在预定电压VSS是接地电压的情形下，第一电容C1可被充电至第二参考电压VR2。In this embodiment, the timing controller 248 may generate a control signal for controlling each switch according to a charge pump control signal CLK, a normal start signal PWD, and a soft start signal SS, thereby controlling the switching operation of each switch. Please refer to FIG. 2, FIG. 3 and FIG. 4 together. FIG. 3 is a schematic diagram of an example of a control signal timing of each switch shown in FIG. 2. FIG. 4 is a waveform diagram of an embodiment of a voltage signal generated in response to the control signal timing shown in FIG. 3. Before the time point t0, the charge pump control signal CLK and the normal start signal PWD each have a high level (for example, corresponding to a logic level "1"), so that the voltage regulator (ie, the voltage regulator 100 shown in FIG. 1 ) Operate in power-down mode. The timing controller 248 may generate a first control signal P1H having a low level (for example, corresponding to a logic level “0”) and a third control signal P2H having a high level. This causes the first switch SW1 and the second switch SW2 of the first charge pump 243 to be turned on, and the third switch SW3 and the fourth switch SW4 to be turned off to pre-charge the first capacitor C1. For example, in a case where the predetermined voltage VSS is a ground voltage, the first capacitor C1 may be charged to the second reference voltage VR2.
此外，第五控制信号SG3、第六控制信号SG4、第七控制信号SG5和第八控制信号SG6均具有高电平。这使得第五开关SW9导通、第六开关SW10关闭、第七开关SW11导通以及第八开关SW12关闭。开关模块246可将预定电压VSS耦接于第一晶体管M1的控制端TC1和第二晶体管M2的控制端TC2。也就是说，控制电路140可将预定电压VSS作为第一控制电压M1G和第二控制电压M2G，从而关闭第一晶体管M1和第二晶体管M2。In addition, the fifth control signal SG3, the sixth control signal SG4, the seventh control signal SG5, and the eighth control signal SG6 all have a high level. This turns on the fifth switch SW9, the sixth switch SW10 is turned off, the seventh switch SW11 is turned on, and the eighth switch SW12 is turned off. The switching module 246 can couple the predetermined voltage VSS to the control terminal TC1 of the first transistor M1 and the control terminal TC2 of the second transistor M2. That is, the control circuit 140 may use the predetermined voltage VSS as the first control voltage M1G and the second control voltage M2G, thereby turning off the first transistor M1 and the second transistor M2.
于时间点t0，电荷泵控制信号CLK和正常启动信号PWD处于低电平，而软启动信号SS处于高电平。此时，稳压器可操作在软启动模式(soft-startup mode)，避免过大的浪涌电流(surge current)产生而降低电路的可靠性。当第一控制信号P1H处于高电平且第三控制信号P2H处于低电平时(时间点t1)，第一电荷泵243的第一开关SW1和第二开关SW2关闭，而第三开关SW3和第四开关SW4导通。第一电容C1的第二端TA2的电平会被转换为放大电压OPV加上第一电容C1两端原本的电压降。也就是说，第一电荷泵243可将放大电压OPV转换为驱动电压VD。此外，第二电荷泵244的第一开关 SW5和第二开关SW6导通，而第三开关SW7和第四开关SW8关闭，以对第二电容C2充电。At time t0, the charge pump control signal CLK and the normal start signal PWD are at a low level, and the soft start signal SS is at a high level. At this time, the voltage regulator can be operated in a soft-startup mode to avoid excessive surge current and reduce the reliability of the circuit. When the first control signal P1H is at a high level and the third control signal P2H is at a low level (time point t1), the first switch SW1 and the second switch SW2 of the first charge pump 243 are turned off, and the third switch SW3 and the first switch The four switches SW4 are turned on. The level of the second terminal TA2 of the first capacitor C1 is converted into an amplified voltage OPV plus the original voltage drop across the first capacitor C1. That is, the first charge pump 243 may convert the amplified voltage OPV into a driving voltage VD. In addition, the first switch SW5 and the second switch SW6 of the second charge pump 244 are turned on, and the third switch SW7 and the fourth switch SW8 are turned off to charge the second capacitor C2.
在软启动模式中，第五控制信号SG3和第六控制信号SG4处于高电平，而第七控制信号SG5和第八控制信号SG6处于低电平。这使得第五开关SW9导通、第六开关SW10关闭、第七开关SW11关闭以及第八开关SW12导通。开关模块246可将预定电压VSS耦接于第一晶体管M1的控制端TC1，以及将电压输出端NVO耦接于第二晶体管M2的控制端TC2。也就是说，控制电路140可将预定电压VSS作为第一控制电压M1G以关闭第一晶体管M1，以及将驱动电压VD作为第二控制电压M2G以导通第二晶体管M2。In the soft start mode, the fifth control signal SG3 and the sixth control signal SG4 are at a high level, and the seventh control signal SG5 and the eighth control signal SG6 are at a low level. This turns on the fifth switch SW9, the sixth switch SW10 is turned off, the seventh switch SW11 is turned off, and the eighth switch SW12 is turned on. The switching module 246 can couple the predetermined voltage VSS to the control terminal TC1 of the first transistor M1, and couple the voltage output terminal NVO to the control terminal TC2 of the second transistor M2. That is, the control circuit 140 may use the predetermined voltage VSS as the first control voltage M1G to turn off the first transistor M1, and use the driving voltage VD as the second control voltage M2G to turn on the second transistor M2.
值得注意的是，相比于第一晶体管M1，第二晶体管M2可具有较小的宽长比(W/L ratio)，故可具有较小的导通电流。因此，在软启动模式中，通过驱动具有较小宽长比的第二晶体管M2，输出电压VOUT的收敛较为和缓(所需的收敛时间标记为TS1)，降低了启动时的浪涌电流。It is worth noting that, compared with the first transistor M1, the second transistor M2 may have a smaller width-to-length ratio (W / L ratio), and therefore may have a smaller on-current. Therefore, in the soft-start mode, by driving the second transistor M2 with a smaller aspect ratio, the convergence of the output voltage VOUT is relatively gentle (the required convergence time is marked as TS1), and the inrush current during startup is reduced.
接下来，当软启动信号SS和正常启动信号PWD均处于低电平时(于时间点t2)，稳压器可操作在正常启动模式(normal mode)。第五控制信号SG3、第六控制信号SG4、第七控制信号SG5和第八控制信号SG6均处于低电平。这使得第五开关SW9关闭、第六开关SW10导通、第七开关SW11关闭以及第八开关SW12导通。开关模块246可将电压输出端NVO耦接于第一晶体管M1的控制端TC1以及第二晶体管M2的控制端TC2。也就是说，控制电路140可将驱动电压VD作为第一控制电压M1G和第二控制电压M2G，从而导通第一晶体管M1和第二晶体管M2。由于控制电路140可同时驱动第一晶体管M1和第二晶体管M2，增加了流向负载电容CL的输出电流，缩短了输出电压VOUT的收敛时间(图4未标记)。Next, when the soft start signal SS and the normal start signal PWD are both at a low level (at time point t2), the voltage regulator can be operated in a normal start mode (normal mode). The fifth control signal SG3, the sixth control signal SG4, the seventh control signal SG5, and the eighth control signal SG6 are all at a low level. This turns off the fifth switch SW9, the sixth switch SW10 is turned on, the seventh switch SW11 is turned off, and the eighth switch SW12 is turned on. The switch module 246 can couple the voltage output terminal NVO to the control terminal TC1 of the first transistor M1 and the control terminal TC2 of the second transistor M2. That is, the control circuit 140 may use the driving voltage VD as the first control voltage M1G and the second control voltage M2G, thereby turning on the first transistor M1 and the second transistor M2. Since the control circuit 140 can simultaneously drive the first transistor M1 and the second transistor M2, the output current flowing to the load capacitor CL is increased, and the convergence time of the output voltage VOUT is shortened (not labeled in FIG. 4).
此外，在正常启动模式中，第一电容C1和第二电容C2可交替耦接于电压输入端NVI与电压输出端NVO之间，使第一电荷泵243和第二电荷泵244交替地将放大电压OPV转换为驱动电压VD。当第 一电容C1耦接于电压输入端NVI与电压输出端NVO之间时，第一电荷泵243从电压输出端NVO输出驱动电压VD，以及第二电容C2耦接于预定电压VSS与第二参考电压VR2之间。当第二电容C2耦接于电压输入端NVI与电压输出端NVO之间时，第二电荷泵244从电压输出端NVO输出驱动电压VD，以及第一电容C1耦接于预定电压VSS与第二参考电压VR2之间。In addition, in the normal startup mode, the first capacitor C1 and the second capacitor C2 may be alternately coupled between the voltage input terminal NVI and the voltage output terminal NVO, so that the first charge pump 243 and the second charge pump 244 alternately amplify The voltage OPV is converted into a driving voltage VD. When the first capacitor C1 is coupled between the voltage input terminal NVI and the voltage output terminal NVO, the first charge pump 243 outputs the driving voltage VD from the voltage output terminal NVO, and the second capacitor C2 is coupled to the predetermined voltage VSS and the second capacitor. Reference voltage VR2. When the second capacitor C2 is coupled between the voltage input terminal NVI and the voltage output terminal NVO, the second charge pump 244 outputs the driving voltage VD from the voltage output terminal NVO, and the first capacitor C1 is coupled to the predetermined voltage VSS and the second capacitor. Reference voltage VR2.
举例来说，在电荷泵控制信号CLK由低电平切换为高电平的情形下，第一控制信号P1H可由高电平切换为低电平(时间点t3)，以关闭第一电荷泵243的第三开关SW3和第四开关SW4，以及关闭第二电荷泵244的第一开关SW5和第二开关SW6。此外，第三控制信号P2H可由低电平切换为高电平(时间点t4)，以导通第一电荷泵243的第一开关SW1和第二开关SW2，以及导通第二电荷泵244的第三开关SW7和第四开关SW8。因此，第一电容C1可被充电一预定时间TP2，第二电容C2的第二端TB2的电平可被转换为放大电压OPV加上第二电容C2两端原本的电压降(诸如第二参考电压VR2与预定电压VSS之间的电压差)。也就是说，第二电荷泵244可将放大电压OPV转换为驱动电压VD，其可通过电压输出端NVO提供给第一晶体管M1的控制端TC1和第二晶体管M2的控制端TC2。For example, when the charge pump control signal CLK is switched from low level to high level, the first control signal P1H may be switched from high level to low level (time point t3) to turn off the first charge pump 243 The third switch SW3 and the fourth switch SW4, and the first switch SW5 and the second switch SW6 that turn off the second charge pump 244. In addition, the third control signal P2H can be switched from a low level to a high level (time point t4) to turn on the first switch SW1 and the second switch SW2 of the first charge pump 243, and turn on the second charge pump 244. The third switch SW7 and the fourth switch SW8. Therefore, the first capacitor C1 can be charged for a predetermined time TP2, and the level of the second terminal TB2 of the second capacitor C2 can be converted into an amplified voltage OPV plus the original voltage drop across the second capacitor C2 (such as the second reference Voltage difference between the voltage VR2 and the predetermined voltage VSS). That is, the second charge pump 244 can convert the amplified voltage OPV into a driving voltage VD, which can be provided to the control terminal TC1 of the first transistor M1 and the control terminal TC2 of the second transistor M2 through the voltage output terminal NVO.
接下来，在电荷泵控制信号CLK由高电平切换为低电平的情形下，第三控制信号P2H可由高电平切换为低电平(时间点t5)，以关闭第一电荷泵243的第一开关SW1和第二开关SW2，以及关闭第二电荷泵244的第三开关SW7和第四开关SW8。此外，第一控制信号P1H可由低电平切换为高电平(时间点t6)，以导通第一电荷泵243的第三开关SW3和第四开关SW4，以及导通第二电荷泵244的第一开关SW5和第二开关SW6。因此，第一电容C1的第二端TA2的电平可被转换为放大电压OPV加上第一电容C1两端原本的电压降(诸如第二参考电压VR2与预定电压VSS之间的电压差)，第二电容C2可被充电一预定时间TP1。也就是说，第一电荷泵243可将放大电压OPV转换为驱动电压VD，其可通过电压输出端NVO提供给第一晶体管M1的控制端TC1和第二晶体管M2的控制端TC2。Next, when the charge pump control signal CLK is switched from high level to low level, the third control signal P2H may be switched from high level to low level (time point t5) to turn off the first charge pump 243. The first switch SW1 and the second switch SW2, and the third switch SW7 and the fourth switch SW8 that turn off the second charge pump 244. In addition, the first control signal P1H can be switched from a low level to a high level (time point t6) to turn on the third switch SW3 and the fourth switch SW4 of the first charge pump 243, and turn on the second charge pump 244. The first switch SW5 and the second switch SW6. Therefore, the level of the second terminal TA2 of the first capacitor C1 can be converted into the amplified voltage OPV plus the original voltage drop across the first capacitor C1 (such as the voltage difference between the second reference voltage VR2 and the predetermined voltage VSS). The second capacitor C2 can be charged for a predetermined time TP1. That is, the first charge pump 243 can convert the amplified voltage OPV into a driving voltage VD, which can be provided to the control terminal TC1 of the first transistor M1 and the control terminal TC2 of the second transistor M2 through the voltage output terminal NVO.
于此实施例中，第一控制信号P1H与第三控制信号P2H可由非重叠信号(non-overlapping signal)来实施，以提升电路的可靠性。举例来说，第一控制信号P1H由高电平切换为低电平的时间点(诸如时间点t3)与第三控制信号P2H由低电平切换为高电平的时间点(诸如时间点t4)间隔了预定时间TNOV，第三控制信号P2H由高电平切换为低电平的时间点(诸如时间点t5)与第一控制信号P1H由低电平切换为高电平的时间点(诸如时间点t6)间隔了预定时间TNOV。In this embodiment, the first control signal P1H and the third control signal P2H can be implemented by non-overlapping signals to improve the reliability of the circuit. For example, the point in time when the first control signal P1H is switched from high to low (such as time point t3) and the point in time when the third control signal P2H is switched from low to high (such as time point t4) ) After a predetermined time TNOV, the point in time when the third control signal P2H is switched from high to low (such as time point t5) and the point in time when the first control signal P1H is switched from low to high (such as Time point t6) is separated by a predetermined time TNOV.
通过第一电荷泵243和第二电荷泵244交替地从电压输出端NVO输出驱动电压VD，可使驱动电压VD维持稳定的电平，从而提升输出电压VOUT的稳定性。The first charge pump 243 and the second charge pump 244 alternately output the driving voltage VD from the voltage output terminal NVO, so that the driving voltage VD can be maintained at a stable level, thereby improving the stability of the output voltage VOUT.
值得注意的是，以上所述只是方便说明而已，并非用来限制本发明。在一设计变化例中，图2所示的第一电荷泵243与第二电荷泵244两者的至少其一的开关电路拓扑可采用其他电路结构来实施。例如，第一电荷泵243的第二开关SW2和第四开关SW4可由三路开关(three-way switch)来实施，以将第一电容C1的第二端TA2耦接到第二参考电压VR2与电压输出端NVO的其中之一。又例如，第二电荷泵244的第二开关SW6和第四开关SW8可由三路开关(three-way switch)来实施，以将第二电容C2的第二端TB2耦接到第二参考电压VR2与电压输出端NVO的其中之一。It is worth noting that the above description is only for convenience of description and is not intended to limit the present invention. In a design variation, the switching circuit topology of at least one of the first charge pump 243 and the second charge pump 244 shown in FIG. 2 may be implemented by other circuit structures. For example, the second switch SW2 and the fourth switch SW4 of the first charge pump 243 may be implemented by a three-way switch to couple the second terminal TA2 of the first capacitor C1 to the second reference voltage VR2 and One of the voltage output terminals NVO. As another example, the second switch SW6 and the fourth switch SW8 of the second charge pump 244 may be implemented by a three-way switch to couple the second terminal TB2 of the second capacitor C2 to the second reference voltage VR2. And one of the voltage output terminals NVO.
在另一设计变化例中，图2所示的开关模组246的开关电路拓扑可采用其他电路结构来实施。举例来说，第五开关SW9和第六开关SW10可由三路开关来实施，以将第一晶体管M1的控制端C1耦接到电压输出端NVO与预定电压VSS的其中之一。In another design variation, the switching circuit topology of the switching module 246 shown in FIG. 2 may be implemented by other circuit structures. For example, the fifth switch SW9 and the sixth switch SW10 may be implemented by three switches to couple the control terminal C1 of the first transistor M1 to one of the voltage output terminal NVO and the predetermined voltage VSS.
在另一设计变化例中，图2所示的第一电荷泵243和第二电荷泵244可对放大电压OPV执行降压的电平转换，并交替产生驱动电压VD。举例来说，在图1所示的第一晶体管M1和第二晶体管M2是由P型金氧半场效晶体管来实施的情形下，第一电荷泵243和第二电荷泵244可由降压型的电荷泵来实施，以交替地将具有低电平的 驱动电压VD作为第一控制电压M1G(或第二控制电压M2G)。In another design variation, the first charge pump 243 and the second charge pump 244 shown in FIG. 2 may perform step-down level conversion on the amplified voltage OPV and alternately generate the driving voltage VD. For example, in a case where the first transistor M1 and the second transistor M2 shown in FIG. 1 are implemented by a P-type MOSFET, the first charge pump 243 and the second charge pump 244 may be a buck type. The charge pump is implemented to alternately use the driving voltage VD with a low level as the first control voltage M1G (or the second control voltage M2G).
此外，在某些实施例中，将本发明所公开的稳压控制机制应用于具有单一传输晶体管的稳压器也是可行的。图5绘示了本发明稳压器的另一实施例的功能方框示意图。于此实施例中，稳压器500的结构基于图1所示的稳压器100的结构，两者之间主要的差别在于稳压器500的传输晶体管模块510是由单一晶体管来实施。In addition, in some embodiments, it is also feasible to apply the voltage regulation control mechanism disclosed in the present invention to a voltage regulator with a single pass transistor. FIG. 5 illustrates a functional block diagram of another embodiment of the voltage regulator of the present invention. In this embodiment, the structure of the voltage regulator 500 is based on the structure of the voltage regulator 100 shown in FIG. 1. The main difference between the two is that the pass transistor module 510 of the voltage regulator 500 is implemented by a single transistor.
稳压器500包括(但不限于)传输晶体管模块510，控制电路540，以及图1所示的稳压输出端NR、放大器120和回授电路140，其中传输晶体管模块510包括图1所示的第一晶体管M1。此外，控制电路540包括图2所示的电荷泵电路242和开关模块546。开关模块546用以选择性地将电压输出端NVO耦接于第一晶体管M1的控制端TC1。于此实施例中，开关模块546可包括图2所示的第五开关SW9和第六开关SW10。The voltage regulator 500 includes (but is not limited to) a pass transistor module 510, a control circuit 540, and a regulated output terminal NR, an amplifier 120, and a feedback circuit 140 shown in FIG. 1, where the pass transistor module 510 includes the First transistor M1. In addition, the control circuit 540 includes a charge pump circuit 242 and a switch module 546 shown in FIG. 2. The switch module 546 is used to selectively couple the voltage output terminal NVO to the control terminal TC1 of the first transistor M1. In this embodiment, the switch module 546 may include a fifth switch SW9 and a sixth switch SW10 shown in FIG. 2.
当稳压器500操作在正常启动模式时，开关模块546可将电压输出端NVO耦接于第一晶体管M1的控制端TC1，以导通第一晶体管M1。例如，第五开关SW9关闭，第六开关SW10导通，以将第一电荷泵243和第二电荷泵244交替输出的驱动电压VD作为第一控制电压M1G。当稳压器500未操作在正常启动模式时(例如，操作在掉电模式)，开关模块546可将预定电压VSS耦接于第一晶体管M1的控制端TC1，以关闭第一晶体管M1。例如，第五开关SW9导通，第六开关SW10关闭，以将预定电压VSS作为第一控制电压M1G。When the voltage regulator 500 operates in the normal startup mode, the switch module 546 can couple the voltage output terminal NVO to the control terminal TC1 of the first transistor M1 to turn on the first transistor M1. For example, the fifth switch SW9 is turned off and the sixth switch SW10 is turned on, so that the driving voltage VD output by the first charge pump 243 and the second charge pump 244 alternately is used as the first control voltage M1G. When the voltage regulator 500 is not operating in the normal startup mode (for example, operating in the power-down mode), the switching module 546 may couple the predetermined voltage VSS to the control terminal TC1 of the first transistor M1 to turn off the first transistor M1. For example, the fifth switch SW9 is turned on and the sixth switch SW10 is turned off to use the predetermined voltage VSS as the first control voltage M1G.
由于本领域的技术人员通过阅读图1到图4相关的段落说明之后，应可了解图5所示的稳压器500的操作细节及其相关的变化例，因此，进一步的说明在此便不再赘述。As a person skilled in the art can understand the operation details of the voltage regulator 500 shown in FIG. 5 and related variations after reading the description of the relevant paragraphs of FIG. 1 to FIG. 4, further description is not provided here. More details.
本发明所公开的稳压控制机制可简单归纳为图6所示的流程图。图6是本发明稳压器的控制方法的一实施例的流程图。所述稳压器包括一第一晶体管、一稳压输出端以及一放大器。所述第一晶体管的一第一连接端耦接于所述稳压输出端。假若所得到的结果实质上大致相同，则步骤不一定要按照图6所示的顺序来进行。举例 来说，某些步骤可安插于其中。为了方便说明，以下搭配图2所示的控制电路140来说明图6所示的控制方法。然而，将图6所示的控制方法应用于图5所示的控制电路540也是可行的。图6所示的控制方法可简单归纳如下。The voltage regulation control mechanism disclosed in the present invention can be simply summarized as a flowchart shown in FIG. 6. FIG. 6 is a flowchart of an embodiment of a method for controlling a voltage regulator according to the present invention. The regulator includes a first transistor, a regulated output terminal, and an amplifier. A first connection terminal of the first transistor is coupled to the regulated output terminal. If the obtained results are substantially the same, the steps are not necessarily performed in the order shown in FIG. 6. For example, some steps can be inserted in it. For convenience of explanation, the control method shown in FIG. 6 is described below with reference to the control circuit 140 shown in FIG. 2. However, it is also feasible to apply the control method shown in FIG. 6 to the control circuit 540 shown in FIG. 5. The control method shown in FIG. 6 can be briefly summarized as follows.
步骤602：将一第一电容交替地耦接于所述放大器的一放大输出端与一电压输出端之间以及一预定电压与一参考电压之间，以在所述电压输出端产生一驱动电压。例如，时序控制器248可切换第一电荷泵243的第一开关SW1、第二开关SW2、第三开关SW3和第四开关SW4各自的导通状态，致使第一电容C1交替地耦接于放大输出端NT与电压输出端NVO之间以及预定电压VSS与第二参考电压VR2之间，并且致使第一电荷泵243在电压输出端NVO产生驱动电压VD。Step 602: A first capacitor is alternately coupled between an amplification output terminal and a voltage output terminal of the amplifier and between a predetermined voltage and a reference voltage to generate a driving voltage at the voltage output terminal. . For example, the timing controller 248 may switch the conducting states of the first switch SW1, the second switch SW2, the third switch SW3, and the fourth switch SW4 of the first charge pump 243, so that the first capacitor C1 is alternately coupled to the amplifier. Between the output terminal NT and the voltage output terminal NVO and between the predetermined voltage VSS and the second reference voltage VR2, and the first charge pump 243 is caused to generate a driving voltage VD at the voltage output terminal NVO.
步骤604：将一第二电容交替地耦接于所述预定电压与所述参考电压之间以及所述放大器的所述放大输出端与所述电压输出端之间，以在所述电压输出端产生所述驱动电压。例如，时序控制器248可切换第二电荷泵244的第一开关SW5、第二开关SW6、第三开关SW7和第四开关SW8各自的导通状态，致使第二电容C2交替地耦接于预定电压VSS与第二参考电压VR2之间以及放大输出端NT与电压输出端NVO之间，并且致使第二电荷泵244在电压输出端NVO产生驱动电压VD。Step 604: Alternately coupling a second capacitor between the predetermined voltage and the reference voltage, and between the amplifier output terminal and the voltage output terminal of the amplifier, so that the voltage output terminal The driving voltage is generated. For example, the timing controller 248 may switch the conducting states of the first switch SW5, the second switch SW6, the third switch SW7, and the fourth switch SW8 of the second charge pump 244, so that the second capacitor C2 is alternately coupled to a predetermined Between the voltage VSS and the second reference voltage VR2, and between the amplified output terminal NT and the voltage output terminal NVO, the second charge pump 244 is caused to generate a driving voltage VD at the voltage output terminal NVO.
步骤606：选择性地将所述电压输出端耦接于所述第一晶体管的一控制端。例如，开关模块246选择性地将电压输出端NVO耦接于第一晶体管M1的控制端TC1。Step 606: The voltage output terminal is selectively coupled to a control terminal of the first transistor. For example, the switch module 246 selectively couples the voltage output terminal NVO to the control terminal TC1 of the first transistor M1.
于步骤602和步骤604中，当所述第一电容与所述第二电容其中的一电容耦接于所述放大器的所述放大输出端与所述传输晶体管 的所述控制端之间时，所述第一电容与所述第二电容其中的另一电容耦接于所述预定电压与所述参考电压之间。例如，当第一电容C1与第二电容C2其中的一电容耦接于放大输出端NT与电压输出端NVO之间时，第一电容C1与第二电容C2其中的另一电容耦接于预定电压VSS与第二参考电压VR2之间。也就是说，第一电容C1与第二电容C2交替耦接于放大输出端NT与电压输出端NVO之间In step 602 and step 604, when one of the first capacitor and the second capacitor is coupled between the amplifier output terminal of the amplifier and the control terminal of the transmission transistor, The other of the first capacitor and the second capacitor is coupled between the predetermined voltage and the reference voltage. For example, when one of the first capacitor C1 and the second capacitor C2 is coupled between the amplification output terminal NT and the voltage output terminal NVO, the other capacitor of the first capacitor C1 and the second capacitor C2 is coupled to a predetermined capacitor. The voltage VSS is between the second reference voltage VR2. That is, the first capacitor C1 and the second capacitor C2 are alternately coupled between the amplification output terminal NT and the voltage output terminal NVO.
于步骤606中，当所述稳压器操作在一正常启动模式时，所述电压输出端可耦接于所述第一晶体管的所述控制端。当所述稳压器未操作在所述正常启动模式时，所述预定电压可耦接于所述第一晶体管的所述控制端。例如，当稳压器操作在正常启动模式时，开关模块246可将电压输出端NVO耦接于第一晶体管M1的控制端TC1。又例如，当稳压器未操作在正常启动模式时(诸如掉电模式或软启动模式)，开关模块246可将预定电压VSS可耦接于第一晶体管M1的控制端TC1。In step 606, when the voltage regulator operates in a normal startup mode, the voltage output terminal may be coupled to the control terminal of the first transistor. When the voltage regulator is not operated in the normal startup mode, the predetermined voltage may be coupled to the control terminal of the first transistor. For example, when the regulator operates in a normal startup mode, the switch module 246 can couple the voltage output terminal NVO to the control terminal TC1 of the first transistor M1. As another example, when the regulator is not operating in a normal startup mode (such as a power-down mode or a soft-start mode), the switching module 246 may couple the predetermined voltage VSS to the control terminal TC1 of the first transistor M1.
在某些实施例中，所述稳压器还可包括一第二晶体管，本发明公开的控制方法还可选择性地将所述电压输出端耦接于所述第二晶体管的一控制端。例如，当稳压器操作在掉电模式时，开关模块246可将预定电压VSS耦接于第二晶体管M2的控制端TC2。又例如，当稳压器操作在软启动模式或正常启动模式时，开关模块246可将电压输出端NVO耦接于第二晶体管M2的控制端TC2。In some embodiments, the voltage regulator may further include a second transistor. The control method disclosed in the present invention may also selectively couple the voltage output terminal to a control terminal of the second transistor. For example, when the regulator operates in a power-down mode, the switch module 246 can couple the predetermined voltage VSS to the control terminal TC2 of the second transistor M2. For another example, when the regulator operates in a soft start mode or a normal start mode, the switch module 246 can couple the voltage output terminal NVO to the control terminal TC2 of the second transistor M2.
由于本领域的技术人员通过阅读图1到图5相关的段落说明之后，应可了解图6所示的控制方法中每一步骤的细节，因此进一步的说明在此便不再赘述。As those skilled in the art can understand the details of each step in the control method shown in FIG. 6 after reading the description of the relevant paragraphs in FIG. 1 to FIG. 5, further description will not be repeated here.
由上可知，本发明所公开的稳压控制机制可利用多个电荷泵交替地转换放大器所输出的电压，致使多个电荷泵轮流产生传输晶体管的驱动电压，提升输出电压的稳定性。此外，本发明所公开的稳压器控制机制可根据不同的稳压器操作模式，将多个电荷泵交替产生的驱动电压选择性地提供给多个传输晶体管，具备低耗能的功效。It can be known from the above that the voltage stabilization control mechanism disclosed in the present invention can use multiple charge pumps to alternately convert the voltage output by the amplifier, so that the multiple charge pumps alternately generate the driving voltage of the transmission transistor, thereby improving the stability of the output voltage. In addition, the disclosed regulator control mechanism can selectively provide driving voltages alternately generated by multiple charge pumps to a plurality of transmission transistors according to different regulator operation modes, and has the effect of low energy consumption.
以上所述仅为本发明的优选实施例而已，并不用于限制本发明， 对于本领域的技术人员来说，本发明可以有各种更改和变化。凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包括在本发明的保护范围之内。The above descriptions are merely preferred embodiments of the present invention and are not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and changes. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims (20)

  1. 一种稳压器，其特征在于，包括：A voltage regulator includes:
    一放大器，具有一第一输入端、一第二输入端和一放大输出端，其中所述第一输入端耦接于一第一参考电压，所述第二输入端耦接于一回授电压，以及所述放大输出端用以输出一放大电压；An amplifier having a first input terminal, a second input terminal, and an amplified output terminal, wherein the first input terminal is coupled to a first reference voltage, and the second input terminal is coupled to a feedback voltage. And the amplified output terminal is used to output an amplified voltage;
    一电荷泵电路，具有一电压输入端和一电压输出端，所述电压输入端耦接于所述放大输出端，其中所述电荷泵电路包括一第一电荷泵和一第二电荷泵，所述第一电荷泵和所述第二电荷泵并联耦接于所述电压输入端与所述电压输出端之间；所述第一电荷泵和所述第二电荷泵用以交替地转换所述放大电压，以从所述电压输出端输出一驱动电压；A charge pump circuit has a voltage input terminal and a voltage output terminal. The voltage input terminal is coupled to the amplified output terminal. The charge pump circuit includes a first charge pump and a second charge pump. The first charge pump and the second charge pump are coupled in parallel between the voltage input terminal and the voltage output terminal; the first charge pump and the second charge pump are used to alternately convert the Amplifying the voltage to output a driving voltage from the voltage output terminal;
    一第一晶体管，所述第一晶体管的一控制端用以通过所述电压输出端接收所述驱动电压；以及A first transistor, a control terminal of the first transistor is configured to receive the driving voltage through the voltage output terminal; and
    一稳压输出端，耦接于所述第一晶体管的一第一连接端，用以输出一输出电压。A regulated output terminal is coupled to a first connection terminal of the first transistor to output an output voltage.
  2. 如权利要求1所述的稳压器，其特征在于，所述第一电荷泵包括一第一电容，所述第二电荷泵包括一第二电容；所述第一电容和所述第二电容交替耦接于所述电压输入端与所述电压输出端之间；当所述第一电容耦接于所述电压输入端与所述电压输出端之间时，所述第一电荷泵从所述电压输出端输出所述驱动电压，以及所述第二电容耦接于一预定电压与一第二参考电压之间；当所述第二电容耦接于所述电压输入端与所述电压输出端之间时，所述第二电荷泵从所述电压输出端输出所述驱动电压，以及所述第一电容耦接于所述预定电压与所述第二参考电压之间。The voltage regulator of claim 1, wherein the first charge pump comprises a first capacitor, and the second charge pump comprises a second capacitor; the first capacitor and the second capacitor Alternately coupled between the voltage input terminal and the voltage output terminal; when the first capacitor is coupled between the voltage input terminal and the voltage output terminal, the first charge pump starts from The voltage output terminal outputs the driving voltage, and the second capacitor is coupled between a predetermined voltage and a second reference voltage; when the second capacitor is coupled between the voltage input terminal and the voltage output When connected between terminals, the second charge pump outputs the driving voltage from the voltage output terminal, and the first capacitor is coupled between the predetermined voltage and the second reference voltage.
  3. 如权利要求2所述的稳压器，其特征在于，所述第一电荷泵还包括：The voltage regulator according to claim 2, wherein the first charge pump further comprises:
    一第一开关，用以选择性地将一预定电压耦接于所述第一电容的一第一端；A first switch for selectively coupling a predetermined voltage to a first terminal of the first capacitor;
    一第二开关，用以选择性地将所述第二参考电压耦接于所述第一电容的一第二端；A second switch for selectively coupling the second reference voltage to a second terminal of the first capacitor;
    一第三开关，用以选择性地将所述放大输出端耦接于所述第一端；以及A third switch for selectively coupling the amplified output terminal to the first terminal; and
    一第四开关，用以选择性地将所述电压输出端耦接于所述第二端。A fourth switch is used to selectively couple the voltage output terminal to the second terminal.
  4. 如权利要求2所述的稳压器，其特征在于，所述第二电荷泵还包括：The voltage regulator of claim 2, wherein the second charge pump further comprises:
    一第一开关，用以选择性地将一预定电压耦接于所述第二电容的一第一端；A first switch for selectively coupling a predetermined voltage to a first terminal of the second capacitor;
    一第二开关，用以选择性地将所述第二参考电压耦接于所述第二电容的一第二端；A second switch for selectively coupling the second reference voltage to a second terminal of the second capacitor;
    一第三开关，用以选择性地将所述放大输出端耦接于所述第一端；以及A third switch for selectively coupling the amplified output terminal to the first terminal; and
    一第四开关，用以选择性地将所述电压输出端耦接于所述第二端。A fourth switch is used to selectively couple the voltage output terminal to the second terminal.
  5. 如权利要求1所述的稳压器，其特征在于，还包括：The voltage regulator of claim 1, further comprising:
    一开关模块，用以选择性地将所述电压输出端耦接于所述第一晶体管的所述控制端。A switch module is used to selectively couple the voltage output terminal to the control terminal of the first transistor.
  6. 如权利要求5所述的稳压器，其特征在于，当所述稳压器操作在一正常启动模式时，所述开关模块将所述电压输出端耦接于所述第一晶体管的所述控制端；当所述稳压器未操作在所述正常启动模式时，所述开关模块将一预定电压耦接于所述第一晶体管的所述控制端。The voltage regulator of claim 5, wherein when the voltage regulator operates in a normal startup mode, the switch module couples the voltage output terminal to the first transistor. A control terminal; when the voltage regulator is not operated in the normal startup mode, the switch module couples a predetermined voltage to the control terminal of the first transistor.
  7. 如权利要求5所述的稳压器，其特征在于，还包括：The voltage regulator according to claim 5, further comprising:
    一第二晶体管，所述第二晶体管的一第一连接端耦接于所述稳压输出端，其中所述开关模块还用以选择性地将所述电压输出端耦接于所述第二晶体管的所述控制端。A second transistor, a first connection terminal of the second transistor is coupled to the voltage stabilizing output terminal, and the switch module is further configured to selectively couple the voltage output terminal to the second voltage output terminal; The control terminal of the transistor.
  8. 如权利要求7所述的稳压器，其特征在于，当所述稳压器操作在一掉电模式时，所述开关模块将一预定电压耦接于所述第一晶体管的所述控制端和所述第二晶体管的所述控制端；当所述稳压器操作在一软启动模式时，所述开关模块将所述预定电压耦接于所述第一晶体管的所述控制端，以及将所述电压输出端耦接于所述第二晶体管的所述控制端；当所述稳压器操作在一正常启动模式时，所述开关模块将所述电压输出端耦接于所述第一晶体管的所述控制端和所述第二晶体管的所述控制端。The voltage regulator of claim 7, wherein when the voltage regulator is operated in a power-down mode, the switch module couples a predetermined voltage to the control terminal of the first transistor. And the control terminal of the second transistor; when the regulator operates in a soft-start mode, the switch module couples the predetermined voltage to the control terminal of the first transistor, and The voltage output terminal is coupled to the control terminal of the second transistor; when the regulator operates in a normal startup mode, the switch module couples the voltage output terminal to the first transistor; The control terminal of a transistor and the control terminal of the second transistor.
  9. 如权利要求7所述的稳压器，其特征在于，所述第一晶体管的一第二连接端和所述第二晶体管的一第二连接端均连接一电源电压。The voltage regulator of claim 7, wherein a second connection terminal of the first transistor and a second connection terminal of the second transistor are both connected to a power supply voltage.
  10. 如权利要求1所述的稳压器，其特征在于，还包括：The voltage regulator of claim 1, further comprising:
    一回授电路，耦接于所述稳压输出端与所述第二输入端之间，用以根据所述输出电压产生所述回授电压。A feedback circuit is coupled between the regulated output terminal and the second input terminal to generate the feedback voltage according to the output voltage.
  11. 如权利要求1所述的稳压器，其特征在于，所述放大器还具有一电源输入端，所述电源输入端耦接于所述稳压输出端。The voltage regulator according to claim 1, wherein the amplifier further has a power input terminal, and the power input terminal is coupled to the voltage stabilization output terminal.
  12. 一种稳压器的控制电路，所述稳压器包括一第一晶体管、一稳压输出端以及一放大器，所述第一晶体管的一第一连接端耦接于所述稳压输出端，所述控制电路的特征在于，包括：A control circuit for a voltage regulator. The voltage regulator includes a first transistor, a voltage regulator output terminal and an amplifier. A first connection terminal of the first transistor is coupled to the voltage regulator output terminal. The control circuit is characterized by comprising:
    一电荷泵电路，具有一电压输入端和一电压输出端，所述电压输入端耦接于所述放大器的一放大输出端以接收一放大电压，其中所述电荷泵电路包括一第一电荷泵和一第二电荷泵，所述第一电荷泵和所述第二电荷泵并联耦接于所述电压输入端与所述电压输出端之间；所述第一电荷泵和所述第二电荷泵用以交替地转换所述放大电压，以从所述电压输出端输出一驱动电压；以及A charge pump circuit having a voltage input terminal and a voltage output terminal, the voltage input terminal is coupled to an amplifier output terminal of the amplifier to receive an amplified voltage, wherein the charge pump circuit includes a first charge pump And a second charge pump, the first charge pump and the second charge pump are coupled in parallel between the voltage input terminal and the voltage output terminal; the first charge pump and the second charge A pump for alternately converting the amplified voltage to output a driving voltage from the voltage output terminal; and
    一开关模块，用以选择性地将所述电压输出端耦接于所述第一晶体管的一控制端。A switch module is used to selectively couple the voltage output terminal to a control terminal of the first transistor.
  13. 如权利要求12所述的控制电路，其特征在于，所述第一电荷泵包括一第一电容，所述第二电荷泵包括一第二电容；所述第一电容和所述第二电容交替耦接于所述电压输入端与所述电压输出端之间；当所述第一电容耦接于所述电压输入端与所述电压输出端之间时，所述第一电荷泵从所述电压输出端输出所述驱动电压，以及所述第二电容耦接于一预定电压与一第二参考电压之间；当所述第二电容耦接于所述电压输入端与所述电压输出端之间时，所述第二电荷泵从所述电压输出端输出所述驱动电压，以及所述第一电容耦接于所述预定电压与所述第二参考电压之间。The control circuit according to claim 12, wherein the first charge pump includes a first capacitor, and the second charge pump includes a second capacitor; the first capacitor and the second capacitor alternate The first charge pump is coupled between the voltage input terminal and the voltage output terminal; when the first capacitor is coupled between the voltage input terminal and the voltage output terminal The voltage output terminal outputs the driving voltage, and the second capacitor is coupled between a predetermined voltage and a second reference voltage; when the second capacitor is coupled between the voltage input terminal and the voltage output terminal In between, the second charge pump outputs the driving voltage from the voltage output terminal, and the first capacitor is coupled between the predetermined voltage and the second reference voltage.
  14. 如权利要求12所述的控制电路，其特征在于，当所述稳压器操作在一正常启动模式时，所述开关模块将所述电压输出端耦接于所述第一晶体管的所述控制端；当所述稳压器未操作在所述正常启动模式时，所述开关模块将一预定电压耦接于所述第一晶体管的所述控制端。The control circuit of claim 12, wherein when the voltage regulator is operated in a normal startup mode, the switch module couples the voltage output terminal to the control of the first transistor. Terminal; when the regulator is not operating in the normal startup mode, the switch module couples a predetermined voltage to the control terminal of the first transistor.
  15. 如权利要求14所述的控制电路，其特征在于，当所述稳压器操作在所述正常启动模式时，所述开关模块还将所述电压输出端耦接于所述稳压器的一第二晶体管的一控制端，所述第二晶体管的一第一连接端耦接于所述稳压输出端。The control circuit according to claim 14, wherein, when the voltage regulator operates in the normal startup mode, the switch module further couples the voltage output terminal to a voltage regulator. A control terminal of the second transistor, and a first connection terminal of the second transistor is coupled to the regulated output terminal.
  16. 如权利要求14所述的控制电路，其特征在于，当所述稳压器操作在一软启动模式时，所述开关模块还将所述电压输出端耦接于所述稳压器的一第二晶体管的一控制端，所述第二晶体管的一第一连接端耦接于所述稳压输出端。The control circuit of claim 14, wherein when the voltage regulator is operated in a soft-start mode, the switch module further couples the voltage output terminal to a first voltage regulator. A control terminal of the two transistors, and a first connection terminal of the second transistor is coupled to the regulated output terminal.
  17. 如权利要求14所述的控制电路，其特征在于，当所述稳压器操作在一掉电模式时，所述开关模块还将所述预定电压耦接于所述稳压器的一第二晶体管的一控制端，所述第二晶体管的一第一连接端耦接于所述稳压输出端。The control circuit according to claim 14, wherein when the voltage regulator is operated in a power-down mode, the switch module further couples the predetermined voltage to a second voltage of the voltage regulator. A control terminal of the transistor and a first connection terminal of the second transistor are coupled to the regulated output terminal.
  18. 一种稳压器的控制方法，所述稳压器包括一第一晶体管、一稳压输出端以及一放大器，所述第一晶体管的一第一连接端耦接于所述稳压输出端，所述控制方法的特征在于，包括：A method for controlling a voltage regulator, the voltage regulator includes a first transistor, a voltage regulator output terminal and an amplifier, and a first connection terminal of the first transistor is coupled to the voltage regulator output terminal, The control method is characterized by comprising:
    将一第一电容交替地耦接于所述放大器的一放大输出端与一电压输出端之间以及一预定电压与一参考电压之间，以在所述电压输出端产生一驱动电压；Firstly coupling a first capacitor between an amplification output terminal and a voltage output terminal of the amplifier and between a predetermined voltage and a reference voltage to generate a driving voltage at the voltage output terminal;
    将一第二电容交替地耦接于所述预定电压与所述参考电压之间以及所述放大器的所述放大输出端与所述电压输出端之间，以在所述电压输出端产生所述驱动电压，其中当所述第一电容与所述第二电容其中的一电容耦接于所述放大器的所述放大输出端与所述电压输出端之间时，所述第一电容与所述第二电容其中的另一电容耦接于所述预定电压与所述参考电压之间；以及A second capacitor is alternately coupled between the predetermined voltage and the reference voltage, and between the amplifier output terminal and the voltage output terminal of the amplifier to generate the voltage output terminal A driving voltage, wherein when one of the first capacitor and the second capacitor is coupled between the amplifier output terminal and the voltage output terminal of the amplifier, the first capacitor and the second capacitor Another capacitor of the second capacitor is coupled between the predetermined voltage and the reference voltage; and
    选择性地将所述电压输出端耦接于所述第一晶体管的一控制端。The voltage output terminal is selectively coupled to a control terminal of the first transistor.
  19. 如权利要求18所述的控制方法，其特征在于，选择性地将所述电压输出端耦接于所述第一晶体管的所述控制端包括：The control method according to claim 18, wherein selectively coupling the voltage output terminal to the control terminal of the first transistor comprises:
    当所述稳压器操作在一正常启动模式时，将所述电压输出端耦接于所述第一晶体管的所述控制端；以及When the voltage regulator is operating in a normal startup mode, the voltage output terminal is coupled to the control terminal of the first transistor; and
    当所述稳压器未操作在所述正常启动模式时，将所述预定电压耦接于所述第一晶体管的所述控制端。When the voltage regulator is not operated in the normal startup mode, the predetermined voltage is coupled to the control terminal of the first transistor.
  20. 如权利要求19所述的控制方法，其特征在于，还包括：The control method according to claim 19, further comprising:
    当所述稳压器操作在一掉电模式时，将所述预定电压耦接于所述稳压器的一第二晶体管的一控制端，所述第二晶体管的一第一连接端耦接于所述稳压输出端；以及When the regulator operates in a power-down mode, the predetermined voltage is coupled to a control terminal of a second transistor of the regulator, and a first connection terminal of the second transistor is coupled. At the regulated output terminal; and
    当所述稳压器操作在一软启动模式或所述正常启动模式时，将所述电压输出端耦接于所述第二晶体管的所述控制端。When the voltage regulator is operated in a soft start mode or the normal start mode, the voltage output terminal is coupled to the control terminal of the second transistor.
PCT/CN2018/098296 2018-08-02 2018-08-02 Voltage regulator, control circuit for voltage regulator, and control method for voltage regulator WO2020024212A1 (en)

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