TWI638311B - Data processing method and processor - Google Patents

Data processing method and processor Download PDF

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Publication number
TWI638311B
TWI638311B TW103118606A TW103118606A TWI638311B TW I638311 B TWI638311 B TW I638311B TW 103118606 A TW103118606 A TW 103118606A TW 103118606 A TW103118606 A TW 103118606A TW I638311 B TWI638311 B TW I638311B
Authority
TW
Taiwan
Prior art keywords
data
processor
llc
private cache
directory
Prior art date
Application number
TW103118606A
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English (en)
Chinese (zh)
Other versions
TW201537454A (zh
Inventor
馬凌
姚四海
張磊
Original Assignee
阿里巴巴集團服務有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
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Application filed by 阿里巴巴集團服務有限公司 filed Critical 阿里巴巴集團服務有限公司
Publication of TW201537454A publication Critical patent/TW201537454A/zh
Application granted granted Critical
Publication of TWI638311B publication Critical patent/TWI638311B/zh

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0811—Multiuser, multiprocessor or multiprocessing cache systems with multilevel cache hierarchies
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0808—Multiuser, multiprocessor or multiprocessing cache systems with cache invalidating means
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/466—Transaction processing
    • G06F9/467—Transactional memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/28—Using a specific disk cache architecture
    • G06F2212/283—Plural cache memories
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Information Retrieval, Db Structures And Fs Structures Therefor (AREA)
TW103118606A 2014-03-26 2014-05-28 Data processing method and processor TWI638311B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
??201410117556.9 2014-03-26
CN201410117556.9A CN104951240B (zh) 2014-03-26 2014-03-26 一种数据处理方法及处理器

Publications (2)

Publication Number Publication Date
TW201537454A TW201537454A (zh) 2015-10-01
TWI638311B true TWI638311B (zh) 2018-10-11

Family

ID=54165922

Family Applications (1)

Application Number Title Priority Date Filing Date
TW103118606A TWI638311B (zh) 2014-03-26 2014-05-28 Data processing method and processor

Country Status (8)

Country Link
US (2) US9715450B2 (ja)
EP (2) EP3441886B1 (ja)
JP (2) JP6470300B2 (ja)
KR (1) KR102398912B1 (ja)
CN (2) CN104951240B (ja)
HK (1) HK1211102A1 (ja)
TW (1) TWI638311B (ja)
WO (1) WO2015148679A1 (ja)

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KR102593362B1 (ko) * 2016-04-27 2023-10-25 에스케이하이닉스 주식회사 메모리 시스템 및 메모리 시스템의 동작 방법
GB2551529B (en) 2016-06-21 2018-09-12 Advanced Risc Mach Ltd Switching between private cache and shared memory to handle atomic operations
US10268580B2 (en) * 2016-09-30 2019-04-23 Intel Corporation Processors and methods for managing cache tiering with gather-scatter vector semantics
US10528471B2 (en) * 2016-12-27 2020-01-07 Eta Scale Ab System and method for self-invalidation, self-downgrade cachecoherence protocols
US11119923B2 (en) * 2017-02-23 2021-09-14 Advanced Micro Devices, Inc. Locality-aware and sharing-aware cache coherence for collections of processors
CN111066007B (zh) * 2017-07-07 2023-10-31 美光科技公司 对受到管理的nand的rpmb改进
CN109614220B (zh) * 2018-10-26 2020-06-30 阿里巴巴集团控股有限公司 一种多核系统处理器和数据更新方法
CN109684237B (zh) * 2018-11-20 2021-06-01 华为技术有限公司 基于多核处理器的数据访问方法和装置
CN109784930B (zh) * 2019-02-18 2023-07-18 深圳市迅雷网络技术有限公司 一种区块链交易数据的处理方法、装置、电子设备及介质
CN110265029A (zh) * 2019-06-21 2019-09-20 百度在线网络技术（北京）有限公司 语音芯片和电子设备
CN112307067B (zh) * 2020-11-06 2024-04-19 支付宝(杭州)信息技术有限公司 一种数据处理方法及装置
US11429910B1 (en) 2021-08-05 2022-08-30 Transit Labs Inc. Dynamic scheduling of driver breaks in a ride-sharing service
CN114356949A (zh) * 2022-01-11 2022-04-15 政采云有限公司 一种保持缓存数据一致性的方法、装置及介质

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Also Published As

Publication number Publication date
EP3123351A1 (en) 2017-02-01
CN109240945B (zh) 2023-06-06
JP6685437B2 (ja) 2020-04-22
US9715450B2 (en) 2017-07-25
EP3441886A1 (en) 2019-02-13
EP3441886B1 (en) 2020-11-18
EP3123351B1 (en) 2018-12-12
JP2017509985A (ja) 2017-04-06
WO2015148679A1 (en) 2015-10-01
CN104951240A (zh) 2015-09-30
HK1211102A1 (en) 2016-05-13
EP3123351A4 (en) 2017-10-25
JP2019083045A (ja) 2019-05-30
CN109240945A (zh) 2019-01-18
US20150278094A1 (en) 2015-10-01
US20170277635A1 (en) 2017-09-28
KR102398912B1 (ko) 2022-05-17
KR20160138025A (ko) 2016-12-02
US9858186B2 (en) 2018-01-02
TW201537454A (zh) 2015-10-01
CN104951240B (zh) 2018-08-24
JP6470300B2 (ja) 2019-02-13

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