TWI637504B - Pixel structure - Google Patents

Pixel structure Download PDF

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TWI637504B
TWI637504B TW106103031A TW106103031A TWI637504B TW I637504 B TWI637504 B TW I637504B TW 106103031 A TW106103031 A TW 106103031A TW 106103031 A TW106103031 A TW 106103031A TW I637504 B TWI637504 B TW I637504B
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gate
organic semiconductor
strip
semiconductor layer
source
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TW106103031A
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TW201828464A (en
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陳維翰
劉冠顯
蔡佳宏
吳安茹
許世華
涂峻豪
劉竹育
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友達光電股份有限公司
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Priority to CN201710208230.0A priority patent/CN106898622B/en
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312Gate electrodes for field effect devices
    • H01L29/42316Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356Disposition, e.g. buried gate electrode
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312Gate electrodes for field effect devices
    • H01L29/42316Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Thin Film Transistor (AREA)

Abstract

一種畫素結構包含資料線、閘極線、主動元件、第二有機半導體層與畫素電極。閘極線與資料線交錯設置。主動元件電性連接資料線與閘極線。主動元件包含源極、汲極、第一有機半導體層與閘極。源極電性連接於資料線。第一有機半導體層覆蓋源極與汲極。第一有機半導體層於源極與汲極之間具有通道寬度方向。閘極設置於第一有機半導體層上,並電性連接閘極線。閘極沿著通道寬度方向突出於第一有機半導體層。第二有機半導體層覆蓋資料線並連接於第一有機半導體層。畫素電極與汲極電性連接。 A pixel structure includes a data line, a gate line, an active element, a second organic semiconductor layer, and a pixel electrode. The gate and data lines are staggered. The active component is electrically connected to the data line and the gate line. The active device includes a source, a drain, a first organic semiconductor layer, and a gate. The source is electrically connected to the data line. The first organic semiconductor layer covers a source electrode and a drain electrode. The first organic semiconductor layer has a channel width direction between the source and the drain. The gate is disposed on the first organic semiconductor layer and is electrically connected to the gate line. The gate electrode protrudes from the first organic semiconductor layer along the channel width direction. The second organic semiconductor layer covers the data line and is connected to the first organic semiconductor layer. The pixel electrode is electrically connected to the drain electrode.

Description

畫素結構 Pixel structure

本發明是有關於一種畫素結構,特別是關於一種有機顯示裝置的畫素結構。 The invention relates to a pixel structure, in particular to a pixel structure of an organic display device.

隨著製程技術的進步,各類型的顯示器應用不斷推陳出新。因應顯示器應用的輕、薄、短、小以及可攜式等需求,下一世代的顯示器應用朝向易攜帶的趨勢發展。在顯示器中被大量使用到的薄膜電晶體,其結構設計或是材料的選擇更是會直接影響到產品的性能。 With the progress of process technology, various types of display applications are constantly being updated. In response to the light, thin, short, small, and portable requirements of display applications, the next generation of display applications is trending toward portability. The thin-film transistors that are widely used in displays, the structure design or the choice of materials will directly affect the performance of the product.

一般來說,薄膜電晶體至少具有閘極、源極、汲極以及通道層等構件,其中可透過控制閘極的電壓來改變通道層的導電性,以使源極與汲極之間形成導通(開啟)或絕緣(關閉)的狀態。然而,由於製程因素的影響,靠近薄膜電晶體的通道邊緣處與通道中間處的電流特性可能不同,使得薄膜電晶體邊緣處的轉移特性會提前引發,造成在臨界區出現駝峰現象,進而影響薄膜電晶體的電性。 Generally, a thin film transistor has at least components such as a gate, a source, a drain, and a channel layer. The conductivity of the channel layer can be changed by controlling the voltage of the gate to form a conduction between the source and the drain. (Open) or insulated (closed). However, due to the influence of process factors, the current characteristics near the edge of the channel near the thin film transistor and the middle of the channel may be different, so that the transfer characteristics at the edge of the thin film transistor will be triggered in advance, causing a hump phenomenon in the critical region, which will affect the thin film. Electrical properties of transistors.

本發明提供一種畫素結構,包含資料線、閘極 線、主動元件、第二有機半導體層與畫素電極。閘極線與資料線交錯設置。主動元件電性連接資料線與閘極線。主動元件包含源極、汲極、第一有機半導體層與閘極。源極電性連接於資料線。第一有機半導體層覆蓋源極與汲極。第一有機半導體層於源極與汲極之間具有通道寬度方向。閘極設置於第一有機半導體層上,並電性連接閘極線。閘極沿著通道寬度方向突出於第一有機半導體層。第二有機半導體層覆蓋資料線並連接於第一有機半導體層。畫素電極與汲極電性連接。 The invention provides a pixel structure including a data line and a gate electrode. Line, active element, second organic semiconductor layer and pixel electrode. The gate and data lines are staggered. The active component is electrically connected to the data line and the gate line. The active device includes a source, a drain, a first organic semiconductor layer, and a gate. The source is electrically connected to the data line. The first organic semiconductor layer covers a source electrode and a drain electrode. The first organic semiconductor layer has a channel width direction between the source and the drain. The gate is disposed on the first organic semiconductor layer and is electrically connected to the gate line. The gate electrode protrudes from the first organic semiconductor layer along the channel width direction. The second organic semiconductor layer covers the data line and is connected to the first organic semiconductor layer. The pixel electrode is electrically connected to the drain electrode.

在一或多個實施例中,源極與汲極之間具有間隙。間隙沿通道寬度方向具有相對的兩端部。閘極與第一有機半導體層之間具有堆疊方向,閘極於堆疊方向上與間隙的端部的至少其中之一重疊。 In one or more embodiments, there is a gap between the source and the drain. The gap has two opposite ends in the channel width direction. There is a stacking direction between the gate and the first organic semiconductor layer, and the gate overlaps at least one of the ends of the gap in the stacking direction.

在一或多個實施例中,源極與汲極之間具有間隙。間隙沿通道寬度方向具有相對的兩端部。閘極覆蓋端部,並且沿著通道寬度方向突出於鄰近端部的第一有機半導體層的側壁。 In one or more embodiments, there is a gap between the source and the drain. The gap has two opposite ends in the channel width direction. The gate covers the end portion, and protrudes from the sidewall of the first organic semiconductor layer adjacent to the end portion along the channel width direction.

在一或多個實施例中,第二有機半導體層與資料線的側壁接觸,以及第一有機半導體層與源極和汲極的側壁接觸。 In one or more embodiments, the second organic semiconductor layer is in contact with the sidewall of the data line, and the first organic semiconductor layer is in contact with the sidewall of the source and the drain.

在一或多個實施例中,源極和汲極其中之一者的端部與源極和汲極的另一者之間具有邊緣電場區域。閘極覆蓋邊緣電場區域並突出於第一有機半導體層。 In one or more embodiments, there is a fringe electric field region between an end of one of the source and the drain and the other of the source and the drain. The gate electrode covers a fringe electric field region and protrudes from the first organic semiconductor layer.

在一或多個實施例中,源極包含至少一第一條 狀部以及一第一連接部。第一連接部連接資料線與至少一第一條狀部。第一連接部與第一條狀部之間具有大於0度的夾角。閘極於堆疊方向上與第一條狀部至少部分重疊,且未與第一連接部重疊。 In one or more embodiments, the source includes at least one first And a first connecting portion. The first connecting portion connects the data line and the at least one first strip-shaped portion. An included angle between the first connecting portion and the first strip portion is greater than 0 degrees. The gate electrode at least partially overlaps the first strip-shaped portion in the stacking direction, and does not overlap the first connection portion.

在一或多個實施例中,汲極包含兩第二條狀部以及第二連接部,第二連接部連接兩第二條狀部,且兩第二條狀部與第一條狀部交替設置,並且閘極於堆疊方向上與兩第二條狀部至少部分重疊。 In one or more embodiments, the drain electrode includes two second strip portions and a second connection portion, the second connection portion connects the two second strip portions, and the two second strip portions alternate with the first strip portion. And the gate electrode at least partially overlaps with the two second strips in the stacking direction.

在一或多個實施例中,源極包含至少一條狀部,汲極包含至少一條狀部,且源極的至少一條狀部與汲極的至少一條狀部之間具有間隙,且閘極覆蓋間隙。 In one or more embodiments, the source includes at least one strip, the drain includes at least one strip, and there is a gap between the at least one strip of the source and the at least one strip of the drain, and the gate covers gap.

在一或多個實施例中,閘極包含二第一子閘極部與第二子閘極部。第二子閘極部連接第一子閘極部。第一子閘極部的寬度大於第二子閘極部的寬度。第一子閘極部於堆疊方向上與源極的條狀部的兩端部和汲極的條狀部的兩端部重疊,且第二子閘極部於堆疊方向上與源極的條狀部和汲極的條狀部部分重疊。 In one or more embodiments, the gate includes two first sub-gate portions and a second sub-gate portion. The second sub-gate part is connected to the first sub-gate part. The width of the first sub-gate portion is greater than the width of the second sub-gate portion. The first sub-gate portion overlaps with both ends of the stripe portion of the source and the both ends of the strip-like portion of the drain in the stacking direction, and the second sub-gate portion overlaps with the bar of the source in the stacking direction. The lip and the strip of the drain partially overlap.

在一或多個實施例中,第一有機半導體層於源極的條狀部與汲極的條狀部之間更具有通道長度方向,閘極更沿通道長度方向突出於源極的條狀部與汲極的條狀部。 In one or more embodiments, the first organic semiconductor layer further has a channel length direction between the stripe portion of the source electrode and the stripe portion of the drain electrode, and the gate electrode further protrudes from the stripe portion of the source electrode along the channel length direction. And the strip-like portion of the drain.

在一或多個實施例中,第一有機半導體層的材質包含稠五苯(pentacene)、寡噻吩(oligothiophene)、酞菁(phtalocyanine)、碳六十或其衍生物、多芳胺 (polyarylamine)、聚芴(polyfluorene)、聚噻吩(polythiophene)或其衍生物。 In one or more embodiments, the material of the first organic semiconductor layer includes pentacene, oligothiophene, phtalocyanine, carbon sixty or its derivative, and polyarylamine. (polyarylamine), polyfluorene, polythiophene, or a derivative thereof.

本發明另提供一種畫素結構,包含基板、第一圖案化導電層、圖案化有機半導體層、絕緣層、第二圖案化導電層與畫素電極。第一圖案化導電層置於基板上。第一圖案化導電層包含資料線、源極與汲極。源極電性連接資料線。圖案化有機半導體層覆蓋第一圖案化導電層。圖案化有機半導體層於源極與汲極之間具有一通道寬度方向。絕緣層設置於圖案化有機半導體層上。第二圖案化導電層設置於圖案化有機半導體層與絕緣層上。第二圖案化導電層包含閘極線與閘極,閘極電性連接閘極線,且閘極沿著通道寬度方向突出於圖案化有機半導體層。畫素電極與汲極電性連接。 The present invention further provides a pixel structure including a substrate, a first patterned conductive layer, a patterned organic semiconductor layer, an insulating layer, a second patterned conductive layer, and a pixel electrode. The first patterned conductive layer is disposed on the substrate. The first patterned conductive layer includes a data line, a source, and a drain. The source is electrically connected to the data line. The patterned organic semiconductor layer covers the first patterned conductive layer. The patterned organic semiconductor layer has a channel width direction between the source and the drain. The insulating layer is disposed on the patterned organic semiconductor layer. The second patterned conductive layer is disposed on the patterned organic semiconductor layer and the insulating layer. The second patterned conductive layer includes a gate line and a gate electrode, the gate electrode is electrically connected to the gate line, and the gate electrode protrudes from the patterned organic semiconductor layer along the channel width direction. The pixel electrode is electrically connected to the drain electrode.

在一或多個實施例中,源極與汲極之間具有間隙。間隙沿通道寬度方向具有相對的兩端部。閘極與圖案化有機半導體層之間具有堆疊方向,閘極於堆疊方向上與間隙的端部的至少其中之一重疊。 In one or more embodiments, there is a gap between the source and the drain. The gap has two opposite ends in the channel width direction. There is a stacking direction between the gate and the patterned organic semiconductor layer, and the gate overlaps at least one of the ends of the gap in the stacking direction.

在一或多個實施例中,圖案化有機半導體層與資料線的側壁、源極的側壁和汲極的側壁接觸。 In one or more embodiments, the patterned organic semiconductor layer is in contact with a sidewall of the data line, a sidewall of the source, and a sidewall of the drain.

在一或多個實施例中,源極包含至少一第一條狀部以及第一連接部。第一連接部連接資料線與至少一第一條狀部。汲極包含兩第二條狀部以及一第二連接部。第二連接部連接兩第二條狀部,且兩第二條狀部與第一條狀部交替設置。其中第一條狀部與兩第二條狀部之間具有間 隙,間隙具有相對的兩端部。閘極與圖案化有機半導體層之間具有一堆疊方向,閘極於堆疊方向上與兩端部重疊,並突出於圖案化有機半導體層的側壁。 In one or more embodiments, the source electrode includes at least a first strip portion and a first connection portion. The first connecting portion connects the data line and the at least one first strip-shaped portion. The drain electrode includes two second strip-shaped portions and a second connection portion. The second connecting portion connects the two second strip-shaped portions, and the two second strip-shaped portions and the first strip-shaped portions are alternately disposed. There is a space between the first strip-shaped portion and the two second strip-shaped portions. The gap has opposite ends. There is a stacking direction between the gate and the patterned organic semiconductor layer. The gate overlaps both ends in the stacking direction and protrudes from the sidewall of the patterned organic semiconductor layer.

在一或多個實施例中,源極包含至少一條狀部。汲極包含至少一條狀部,且源極的至少一條狀部與汲極的至少一條狀部之間具有間隙,且閘極覆蓋間隙。閘極包含第一子閘極部與第二子閘極部。第二子閘極部連接第一子閘極寬部。第一子閘極部的寬度大於第二子閘極部的寬度。第一子閘極部於堆疊方向上與源極的條狀部的兩端部和汲極的條狀部的兩端部重疊,且第二子閘極部於堆疊方向上與源極的條狀部和汲極的條狀部部分重疊。 In one or more embodiments, the source includes at least one strip. The drain electrode includes at least one strip, and there is a gap between the at least one strip of the source and the at least one strip of the drain, and the gate covers the gap. The gate includes a first sub-gate portion and a second sub-gate portion. The second sub-gate part is connected to the first sub-gate wide part. The width of the first sub-gate portion is greater than the width of the second sub-gate portion. The first sub-gate portion overlaps with both ends of the stripe portion of the source and the both ends of the strip-like portion of the drain in the stacking direction, and the second sub-gate portion overlaps with the bar of the source in the stacking direction. The lip and the strip of the drain partially overlap.

在一或多個實施例中,圖案化有機半導體層於源極的條狀部與汲極的條狀部之間更具有通道長度方向。閘極更沿通道長度方向突出於源極的條狀部與汲極的條狀部。 In one or more embodiments, the patterned organic semiconductor layer further has a channel length direction between the stripe portion of the source electrode and the stripe portion of the drain electrode. The gate electrode protrudes from the stripe portion of the source electrode and the stripe portion of the drain electrode along the length of the channel.

上述實施例的畫素結構可改善主動元件的電性。因第一有機半導體層覆蓋源極與汲極,且第二有機半導體層覆蓋資料線,因此可將源極、汲極與第二有機半導體層隔絕於外界環境,以避免設備腔體被污染的問題。另外,因閘極沿通道寬度方向突出於第一有機半導體層,因此可提高於源極與汲極的端部之間的電場控制能力,以修飾邊緣電流,藉此改善駝峰現象。 The pixel structure of the above embodiments can improve the electrical properties of the active device. Because the first organic semiconductor layer covers the source and the drain, and the second organic semiconductor layer covers the data line, the source, the drain, and the second organic semiconductor layer can be isolated from the external environment to prevent the device cavity from being contaminated. problem. In addition, since the gate protrudes from the first organic semiconductor layer in the channel width direction, the electric field control capability between the source and the end of the drain can be improved to modify the edge current, thereby improving the hump phenomenon.

12、14、16、18、22、24、26、28、32、34、36、38‧‧‧曲線 12, 14, 16, 18, 22, 24, 26, 28, 32, 34, 36, 38‧‧‧ curves

100‧‧‧畫素結構 100‧‧‧ pixel structure

110‧‧‧基板 110‧‧‧ substrate

120‧‧‧第一圖案化導電層 120‧‧‧ the first patterned conductive layer

122‧‧‧資料線 122‧‧‧ Data Line

124‧‧‧源極 124‧‧‧Source

122s、124s、126s、132s‧‧‧側壁 122s, 124s, 126s, 132s

122t、124t、126t‧‧‧上表面 122t, 124t, 126t‧‧‧

124a、124a‧‧‧條狀部 124a, 124a‧‧‧ Strip

124b、124b、157‧‧‧連接部 124b, 124b, 157‧‧‧ Connection

126‧‧‧汲極 126‧‧‧ Drain

130‧‧‧有機半導體層 130‧‧‧Organic semiconductor layer

132‧‧‧第一有機半導體層 132‧‧‧first organic semiconductor layer

134‧‧‧第二有機半導體層 134‧‧‧Second organic semiconductor layer

140‧‧‧絕緣層 140‧‧‧ Insulation

142、144‧‧‧有機介電層 142, 144‧‧‧ organic dielectric layer

150‧‧‧第二圖案化導電層 150‧‧‧ the second patterned conductive layer

152‧‧‧閘極線 152‧‧‧Gate line

154‧‧‧閘極 154‧‧‧Gate

155‧‧‧第一子閘極部 155‧‧‧The first sub-gate part

156‧‧‧第二子閘極部 156‧‧‧Second Sub-Gate

160‧‧‧平坦層 160‧‧‧ flat layer

170‧‧‧畫素電極 170‧‧‧pixel electrode

A-A、B-B‧‧‧線段 A-A, B-B‧‧‧ line segments

d1、d2‧‧‧距離 d1, d2‧‧‧ distance

Z‧‧‧堆疊方向 Z‧‧‧ stacking direction

E‧‧‧邊緣電場區域 E‧‧‧ Fringe electric field region

Ga、Gb、124c、126c‧‧‧端部 Ga, Gb, 124c, 126c ‧‧‧ end

L‧‧‧通道長度方向 L‧‧‧ channel length direction

P‧‧‧區域 P‧‧‧Area

V‧‧‧貫穿孔 V‧‧‧through hole

T‧‧‧主動元件 T‧‧‧active element

W‧‧‧通道寬度方向 W‧‧‧Channel width direction

W1、W2‧‧‧寬度 W1, W2‧‧‧Width

θ1、θ2‧‧‧夾角 θ1, θ2‧‧‧angle

第1A圖至第4A圖為本發明第一實施例的畫素結構的製造方法於各階段的上視圖。 FIGS. 1A to 4A are top views of the pixel structure manufacturing method according to the first embodiment of the present invention at each stage.

第1B圖至第4B圖分別為第1A圖至第4A圖沿線段A-A與B-B的剖面圖。 1B to 4B are cross-sectional views along lines A-A and B-B of FIGS. 1A to 4A, respectively.

第5圖為第4A圖的區域P的放大圖。 Fig. 5 is an enlarged view of a region P in Fig. 4A.

第6圖為本發明第二實施例的主動元件的上視圖。 FIG. 6 is a top view of an active element according to a second embodiment of the present invention.

第7圖為本發明第三實施例的主動元件的上視圖。 FIG. 7 is a top view of an active element according to a third embodiment of the present invention.

第8圖為本發明第四實施例的主動元件的上視圖。 FIG. 8 is a top view of an active element according to a fourth embodiment of the present invention.

第9圖為第8圖中的主動元件於不同汲極驅動電壓下的汲極電流-閘極電壓曲線圖。 FIG. 9 is a graph of the drain current-gate voltage of the active device in FIG. 8 under different drain driving voltages.

第10圖與第11圖為二比較例的主動元件於不同汲極驅動電壓下的汲極電流-閘極電壓曲線圖。 FIG. 10 and FIG. 11 are graphs of the drain current-gate voltage curves of the active device of the two comparative examples under different drain driving voltages.

以下將以圖式揭露本發明的複數個實施方式,為明確說明起見,許多實務上的細節將在以下敘述中一併說明。然而,應瞭解到,這些實務上的細節不應用以限制本發明。也就是說,在本發明部分實施方式中,這些實務上的細節是非必要的。此外,為簡化圖式起見,一些習知慣用的結構與元件在圖式中將以簡單示意的方式繪示之。 In the following, a plurality of embodiments of the present invention will be disclosed graphically. For the sake of clarity, many practical details will be described in the following description. It should be understood, however, that these practical details should not be used to limit the invention. That is, in some embodiments of the present invention, these practical details are unnecessary. In addition, in order to simplify the drawings, some conventional structures and components will be shown in the drawings in a simple and schematic manner.

第1A圖至第4A圖為本發明第一實施例的畫素結構100的製造方法於各階段的上視圖,而第1B圖至第4B圖分別為第1A圖至第4A圖沿線段A-A與B-B的剖面圖。請先參照第1A圖與第1B圖。提供一基板110。基板110的材質 可為玻璃、石英、有機聚合物、或是其它適用的材料。接著,在基板110上形成第一圖案化導電層120。第一圖案化導電層120包含資料線122、源極124與汲極126。資料線122與源極124電性連接,而汲極126與源極124相隔一間隙G。在一些實施例中,第一圖案化導電層120可以包含有固定線寬的線性圖案以及連接於線性圖案的分支圖案,其中資料線122可以是由此具有固定線寬的線性圖案所構成,而源極124與汲極126可以由分支圖案所構成。但不以此為限。 FIGS. 1A to 4A are top views of the manufacturing method of the pixel structure 100 according to the first embodiment of the present invention at each stage, and FIGS. 1B to 4B are respectively along the line AA and FIG. Sectional view of BB. Please refer to Figures 1A and 1B. A substrate 110 is provided. Material of the substrate 110 It can be glass, quartz, organic polymers, or other suitable materials. Next, a first patterned conductive layer 120 is formed on the substrate 110. The first patterned conductive layer 120 includes a data line 122, a source 124 and a drain 126. The data line 122 is electrically connected to the source electrode 124, and the drain electrode 126 is separated from the source electrode 124 by a gap G. In some embodiments, the first patterned conductive layer 120 may include a linear pattern having a fixed line width and a branch pattern connected to the linear pattern. The data line 122 may be formed by the linear pattern having a fixed line width. The source electrode 124 and the drain electrode 126 may be formed by a branch pattern. But not limited to this.

第一圖案化導電層120的材質可以為金屬材料(例如為銀)或是其他可導電的材料。在此,第一圖案化導電層120的製作方法可以包含於基板110上先形成導電材料層,再將導電材料層圖案化以形成第一圖案化導電層120。圖案化的步驟例如可以包含微影及蝕刻或者雷射燒蝕。另外,第一圖案化導電層120亦可直接將含金屬微粒的溶液利用直接印刷(Direct-Write Printing)的方法形成於基板110上。在其他的實施方式中,基板110上可具有緩衝層(未繪示),而第一圖案化導電層120製作於緩衝層上,緩衝層可減少基板110表面的粗糙度。 The material of the first patterned conductive layer 120 may be a metal material (for example, silver) or other conductive materials. Here, the manufacturing method of the first patterned conductive layer 120 may include forming a conductive material layer on the substrate 110 first, and then patterning the conductive material layer to form the first patterned conductive layer 120. The patterning step may include, for example, lithography and etching or laser ablation. In addition, the first patterned conductive layer 120 may directly form a solution containing metal particles on the substrate 110 by a direct-write printing method. In other embodiments, the substrate 110 may have a buffer layer (not shown), and the first patterned conductive layer 120 is fabricated on the buffer layer, and the buffer layer may reduce the roughness of the surface of the substrate 110.

接著請參照第2A圖與第2B圖。形成有機半導體層130以覆蓋第一圖案化導電層120。在一些實施例中,有機半導體層130完全覆蓋第一圖案化導電層120。藉由如此的結構,第一圖案化導電層120可與外界環境隔離,因此能夠避免第一圖案化導電層120於後續製程中污染外界環境(例如設備腔體)。有機半導體層130的製作方法可以包含 噴印(Inkjet Printing)法、軟性微影印刷(Soft Lithographic Printing)法、光微影圖案化(Photolithographic Patterning)法、平版印刷(Offset Printing)法、旋轉塗佈(Spin-Coating)法、刮刀塗佈(Blade Coating)法、浸塗(Dip Coating)法、薄鍍(Curtain Coating)法、液面彎曲式塗佈(meniscus coating)法、噴塗(Spray Coating)法或擠壓塗佈(Extrusion Coating)法。在一些實施例中,有機半導體層130的材質可為稠五苯(pentacene)、寡噻吩(oligothiophene)、酞菁(phtalocyanine)、碳六十或其衍生物、多芳胺(polyarylamine)、聚芴(polyfluorene)、聚噻吩(polythiophene)或其衍生物。 Please refer to FIGS. 2A and 2B. An organic semiconductor layer 130 is formed to cover the first patterned conductive layer 120. In some embodiments, the organic semiconductor layer 130 completely covers the first patterned conductive layer 120. With such a structure, the first patterned conductive layer 120 can be isolated from the external environment, so the first patterned conductive layer 120 can be prevented from polluting the external environment (such as a device cavity) in a subsequent process. The manufacturing method of the organic semiconductor layer 130 may include Inkjet Printing Method, Soft Lithographic Printing Method, Photolithographic Patterning Method, Offset Printing Method, Spin-Coating Method, Blade Coating Blade coating method, dip coating method, curtain coating method, meniscus coating method, spray coating method or extrusion coating law. In some embodiments, the material of the organic semiconductor layer 130 may be pentacene, oligothiophene, phtalocyanine, carbon sixty or its derivative, polyarylamine, polyfluorene (polyfluorene), polythiophene, or a derivative thereof.

在本實施例中,有機半導體層130包含第一有機半導體層132與第二有機半導體層134,在本實施例中,第一有機半導體層132與第二有機半導體層134為一體成型。第一有機半導體層132覆蓋源極124與汲極126,而第二有機半導體層134覆蓋資料線122。更進一步的,第一有機半導體層132接觸源極124的側壁124s與上表面124t以及汲極126的側壁126s與上表面126t,且第二有機半導體層134接觸資料線122的側壁122s與上表面122t。值得說明的是,第一有機半導體層132位於源極124與汲極126之間(請參照第1B圖的間隙G的部分)的區域即為通道區(未繪示)。 In this embodiment, the organic semiconductor layer 130 includes a first organic semiconductor layer 132 and a second organic semiconductor layer 134. In this embodiment, the first organic semiconductor layer 132 and the second organic semiconductor layer 134 are integrally formed. The first organic semiconductor layer 132 covers the source 124 and the drain 126, and the second organic semiconductor layer 134 covers the data line 122. Furthermore, the first organic semiconductor layer 132 contacts the sidewall 124s and the upper surface 124t of the source 124 and the sidewall 126s and the upper surface 126t of the drain 126, and the second organic semiconductor layer 134 contacts the sidewall 122s and the upper surface of the data line 122. 122t. It is worth noting that the region where the first organic semiconductor layer 132 is located between the source 124 and the drain 126 (please refer to the part of the gap G in FIG. 1B) is the channel region (not shown).

接著請參照第3A圖與第3B圖。形成一絕緣層 140於第2A圖與第2B圖的結構上。在本實施例中,例如可形成二層有機介電層142與144。有機介電層142可為低介電係數有機介電層,而有機介電層144可為高介電係數有機介電層。在一些實施例中,有機介電層142的材質可為聚酸甲酯(polymethylmethacrylate,PMMA)、聚異丁烯(polyisobutylene,PIB)、聚乙烯(polyethylene,PE)、聚丙烯(polypropylene,PP)、聚苯乙烯(polystyrene,PS)、聚(4-乙基苯酚)(poly-4-vinylphenol,PVP)、聚乙烯醇(polyvinylalcohol,PVA)或其共聚物。有機介電層144的材質可為聚對二甲苯(parylene)。 Please refer to FIGS. 3A and 3B. Form an insulating layer 140 is in the structure of FIG. 2A and FIG. 2B. In this embodiment, for example, two organic dielectric layers 142 and 144 may be formed. The organic dielectric layer 142 may be a low dielectric constant organic dielectric layer, and the organic dielectric layer 144 may be a high dielectric constant organic dielectric layer. In some embodiments, the material of the organic dielectric layer 142 may be polymethylmethacrylate (PMMA), polyisobutylene (PIB), polyethylene (PE), polypropylene (PP), polymer Polystyrene (PS), poly-4-vinylphenol (PVP), polyvinyl alcohol (PVA), or copolymers thereof. The material of the organic dielectric layer 144 may be parylene.

接著,形成第二圖案化導電層150於絕緣層140上。第二圖案化導電層150包含閘極線152與閘極154。閘極線152與閘極154電性連接。在一些實施例中,第二圖案化導電層150可以包含有固定線寬的線性圖案以及連接於線性圖案的分支圖案,其中閘極線152可以是由此具有固定線寬的線性圖案所構成,而閘極154可以由分支圖案所構成。但不以此為限。 Next, a second patterned conductive layer 150 is formed on the insulating layer 140. The second patterned conductive layer 150 includes a gate line 152 and a gate 154. The gate line 152 is electrically connected to the gate 154. In some embodiments, the second patterned conductive layer 150 may include a linear pattern having a fixed line width and a branch pattern connected to the linear pattern. The gate line 152 may be formed by the linear pattern having a fixed line width. The gate electrode 154 may be formed by a branch pattern. But not limited to this.

第二圖案化導電層150的材質可以為金屬材料(例如為金)或是其他可導電的材料。在此,第二圖案化導電層150的製作方法可以包含於絕緣層140上先形成導電材料層,再將導電材料層圖案化以形成第二圖案化導電層150。形成導電材料層的步驟例如可以包含將金屬微粒以塗佈的方式形成於絕緣層140上。圖案化的步驟例如可以包含微影及蝕刻或者雷射燒蝕。在另一實施例中,第二圖案化導電 層150亦可直接將含金屬微粒的溶液利用直接印刷(Direct-Write Printing)的方法形成於絕緣層140上。 The material of the second patterned conductive layer 150 may be a metal material (for example, gold) or other conductive materials. Here, the manufacturing method of the second patterned conductive layer 150 may include forming a conductive material layer on the insulating layer 140 first, and then patterning the conductive material layer to form the second patterned conductive layer 150. The step of forming the conductive material layer may include, for example, forming metal particles on the insulating layer 140 in a coating manner. The patterning step may include, for example, lithography and etching or laser ablation. In another embodiment, the second patterned conductive The layer 150 may be directly formed on the insulating layer 140 by a direct-write printing method using a solution containing metal particles.

接著請參照第4A圖與第4B圖。形成平坦層160於第3A圖與第3B圖的結構上。平坦層160的材質可與有機介電層142與144相同或不同。接著,形成畫素電極170於平坦層160上,並電性連接至汲極126。舉例而言,可先在平坦層160、有機介電層142與144以及有機半導體層130中形成貫穿孔V,接著形成一層導電材料層,再將導電材料層圖案化為畫素電極170。如此一來,畫素結構100的製程即完成。 Please refer to FIGS. 4A and 4B. A flat layer 160 is formed on the structures in FIGS. 3A and 3B. The material of the flat layer 160 may be the same as or different from the organic dielectric layers 142 and 144. Next, a pixel electrode 170 is formed on the flat layer 160 and is electrically connected to the drain electrode 126. For example, a through hole V may be formed in the flat layer 160, the organic dielectric layers 142 and 144, and the organic semiconductor layer 130, and then a conductive material layer is formed, and then the conductive material layer is patterned into the pixel electrode 170. In this way, the manufacturing process of the pixel structure 100 is completed.

請一併參照第4A圖至第5圖,其中第5圖為第4A圖的區域P的放大圖。從結構的角度來看,畫素結構100包含資料線122、閘極線152、主動元件T、第二有機半導體層134與畫素電極170。閘極線152與資料線122交錯設置。主動元件T電性連接資料線122與閘極線152。主動元件T包含源極124、汲極126、第一有機半導體層132與閘極154。源極124電性連接於資料線122。第一有機半導體層132覆蓋源極124與汲極126。第一有機半導體層132於源極124與汲極126之間具有通道寬度方向W。閘極154設置於第一有機半導體層132上,並電性連接閘極線152。閘極154沿著通道寬度方向W突出於第一有機半導體層132。例如在第5圖中,閘極154突出於第一有機半導體層132一距離d1,此距離d1可為約5微米,然而本發明不以此為限。第二有機半導體層134覆蓋資料線122並連接於第一有機半導體 層132。畫素電極170與汲極126電性連接。 Please refer to FIGS. 4A to 5 together, and FIG. 5 is an enlarged view of the region P in FIG. 4A. From a structural point of view, the pixel structure 100 includes a data line 122, a gate line 152, an active device T, a second organic semiconductor layer 134, and a pixel electrode 170. The gate lines 152 and the data lines 122 are staggered. The active device T is electrically connected to the data line 122 and the gate line 152. The active device T includes a source 124, a drain 126, a first organic semiconductor layer 132, and a gate 154. The source electrode 124 is electrically connected to the data line 122. The first organic semiconductor layer 132 covers the source 124 and the drain 126. The first organic semiconductor layer 132 has a channel width direction W between the source 124 and the drain 126. The gate electrode 154 is disposed on the first organic semiconductor layer 132 and is electrically connected to the gate line 152. The gate electrode 154 protrudes from the first organic semiconductor layer 132 along the channel width direction W. For example, in FIG. 5, the gate electrode 154 protrudes from the first organic semiconductor layer 132 by a distance d1, and the distance d1 may be about 5 micrometers, but the present invention is not limited thereto. The second organic semiconductor layer 134 covers the data line 122 and is connected to the first organic semiconductor. Layer 132. The pixel electrode 170 is electrically connected to the drain electrode 126.

本實施例的畫素結構100可改善主動元件T的電性。具體而言,在主動元件T的組成中,源極124與汲極126的材質可選擇使用銀,以與有機半導體層130之間具有良好的電性匹配。然而因銀電極可能有污染設備腔體的問題,因此有機半導體層130可覆蓋銀材料(如上所述,第一有機半導體層132覆蓋源極124與汲極126,且第二有機半導體層134覆蓋資料線122),隔絕銀與外界環境,以避免銀污染環境。不過,當第一有機半導體層132覆蓋源極124與汲極126的端部時,源極124與汲極126的端部之間會產生邊緣電流(Fringe Currents)。這些邊緣電流會使得主動元件T的汲極電流-閘極電壓曲線(Id-Vg Curve)圖出現駝峰(Hump)現象,其指的是汲極電流於Id-Vg曲線圖中分階段上升,而產生不必要的電流消耗。然而在本實施例中,因閘極154沿通道寬度方向W突出於第一有機半導體層132,因此可提高於源極124與汲極126的端部之間的電場控制能力,以修飾邊緣電流,藉此改善駝峰現象。 The pixel structure 100 of this embodiment can improve the electrical properties of the active device T. Specifically, in the composition of the active device T, the source 124 and the drain 126 can be selected from silver to have a good electrical match with the organic semiconductor layer 130. However, because the silver electrode may pollute the device cavity, the organic semiconductor layer 130 may cover the silver material (as described above, the first organic semiconductor layer 132 covers the source 124 and the drain electrode 126 and the second organic semiconductor layer 134 Data line 122), to isolate silver from the external environment to prevent silver from polluting the environment. However, when the first organic semiconductor layer 132 covers the ends of the source 124 and the drain 126, fringe currents are generated between the source 124 and the end of the drain 126. These edge currents will cause a Hump phenomenon in the Id-Vg Curve of the active device T, which means that the drain current rises in stages in the Id-Vg curve, and Generate unnecessary current consumption. However, in this embodiment, since the gate electrode 154 protrudes from the first organic semiconductor layer 132 along the channel width direction W, the electric field control ability between the source 124 and the end of the drain electrode 126 can be improved to modify the edge current. To improve hump.

在本實施例中,第一圖案化導電層120、有機半導體層130、絕緣層140與第二圖案化導電層150沿著堆疊方向Z依序形成並堆疊。換言之,堆疊方向Z可為基板110上表面的法線方向。源極124與汲極126之間具有間隙G。間隙G沿通道寬度方向W具有相對的兩端部Ga與Gb。閘極154於堆疊方向Z上與間隙G的至少一端部Ga與Gb重疊。例如,在第5圖中,閘極154於堆疊方向Z上與間隙G的兩端部 Ga與Gb皆重疊;另外,閘極154沿通道寬度方向W突出於鄰近兩端部Ga與Gb的第一有機半導體層132的側壁132s;因此,可修飾兩端部Ga與Gb上方的第一有機半導體層132附近的電流。 In this embodiment, the first patterned conductive layer 120, the organic semiconductor layer 130, the insulating layer 140, and the second patterned conductive layer 150 are sequentially formed and stacked along the stacking direction Z. In other words, the stacking direction Z may be a normal direction of the upper surface of the substrate 110. There is a gap G between the source 124 and the drain 126. The gap G has opposite end portions Ga and Gb in the channel width direction W. The gate electrode 154 overlaps at least one end portion Ga and Gb of the gap G in the stacking direction Z. For example, in FIG. 5, the gate electrode 154 and the two ends of the gap G in the stacking direction Z Both Ga and Gb overlap; in addition, the gate electrode 154 protrudes from the sidewall 132s of the first organic semiconductor layer 132 adjacent to Ga and Gb at both ends in the channel width direction W; therefore, the first over the Ga and Gb at both ends can be modified. Current near the organic semiconductor layer 132.

請參照第4A圖與第5圖。在本實施例中,源極124包含至少一條狀部124a與連接部124b。連接部124b連接資料線122與至少一條狀部124a。連接部124b與條狀部124a之間具有夾角θ1,且夾角θ1大於0度,例如為90度,亦即連接部124b與條狀部124a互相垂直,然而本發明不以此為限。另外,汲極126包含至少一條狀部126a與連接部126b。連接部126b連接至畫素電極170與至少一條狀部126a。連接部126b與條狀部126a之間具有夾角θ2,且夾角θ2大於0度,例如為90度,亦即連接部126b與條狀部126a互相垂直,然而本發明不以此為限。 Please refer to Figure 4A and Figure 5. In this embodiment, the source electrode 124 includes at least one strip-shaped portion 124 a and a connection portion 124 b. The connecting portion 124b connects the data line 122 and at least one of the shaped portions 124a. There is an included angle θ1 between the connecting portion 124b and the strip portion 124a, and the included angle θ1 is greater than 0 degrees, for example, 90 degrees, that is, the connecting portion 124b and the strip portion 124a are perpendicular to each other, but the present invention is not limited thereto. In addition, the drain electrode 126 includes at least one strip-shaped portion 126 a and a connection portion 126 b. The connection portion 126b is connected to the pixel electrode 170 and at least one strip-shaped portion 126a. There is an included angle θ2 between the connecting portion 126b and the strip portion 126a, and the included angle θ2 is greater than 0 degrees, for example, 90 degrees, that is, the connecting portion 126b and the strip portion 126a are perpendicular to each other, but the present invention is not limited thereto.

請參照第5圖。在本實施例中,閘極154於堆疊方向Z(於第5圖中為出紙面方向)上與源極124的條狀部124a至少部分重疊,例如在第5圖中閘極154與條狀部124a部分重疊,且未與連接部124b重疊。再者,閘極154於堆疊方向Z上亦與汲極126的條狀部126a至少部分重疊,例如在第5圖中閘極154與條狀部126a部分重疊,且未與連接部126b重疊。如此的結構不但可增加畫素結構100的開口率,因閘極154與條狀部124a、126a為部分重疊,因此也不致於增加閘極-源極之間(或者第4A圖的資料線122與閘極線152之間)的寄生電容。另外,閘極154覆蓋間隙G。 Please refer to Figure 5. In this embodiment, the gate electrode 154 at least partially overlaps the strip-shaped portion 124 a of the source electrode 124 in the stacking direction Z (the direction of the paper exit surface in FIG. 5). For example, in FIG. 5, the gate electrode 154 and the strip-shaped portion The portion 124a partially overlaps and does not overlap the connection portion 124b. Furthermore, the gate electrode 154 also overlaps at least partially with the stripe portion 126a of the drain electrode 126 in the stacking direction Z. For example, in FIG. 5, the gate electrode 154 and the stripe portion 126a partially overlap with each other, and do not overlap with the connection portion 126b. Such a structure can not only increase the aperture ratio of the pixel structure 100, but because the gate 154 and the strips 124a and 126a partially overlap, it does not increase the gate-source (or the data line 122 in FIG. 4A) And gate line 152). In addition, the gate electrode 154 covers the gap G.

請參照第6圖,其為本發明第二實施例的主動元件T的上視圖。第6圖與第5圖的差異處在於閘極154的形狀。在第6圖中,閘極154包含二第一子閘極部155與一第二子閘極部156。第二子閘極部156連接第一子閘極部155,例如一個第二子閘極部156位於兩個第一子閘極部155之間,因此閘極154由俯視方向(堆疊方向Z)觀看為I字型。第一子閘極部155的寬度W1大於第二子閘極部156的寬度W2;更進一步來說,第一子閘極部155的沿者通道長度方向L的寬度W1大於第二子閘極部156的沿者通道長度方向L寬度W2。其中通道長度方向L為第一有機半導體層132在電流(或電子流)的流動方向上的長度的方向,而通道寬度方向W則是第一有機半導體層132中垂直於通道長度方向L的方向。第一子閘極部155於堆疊方向Z上與源極124的條狀部124a的兩端部124c和汲極126的條狀部126a的兩端部126c重疊,且第二子閘極部156於堆疊方向Z上與源極124的條狀部124a和汲極126的條狀部126a部分重疊。以另一角度來看,源極124的端部124c與汲極126的端部126c之間具有邊緣電場區域E。邊緣電場為導電體靠近邊緣的區域因邊緣效應所產生的不均勻電場,而邊緣電場區域E則為源極124與汲極126之間會產生邊緣電場的區域。在本實施例中,邊緣電場區域E包含源極124的端部124c、汲極126的端部126c與其之間的區域。閘極157覆蓋邊緣電場區域E並突出於第一有機半導體層132。如此一來,第一子閘極部155能改善源極124與汲極126之間的邊緣電流效應, 且第二子閘極部156可以增加畫素結構100的開口率,且減少閘極-源極之間的寄生電容。其中,兩端部124c指的是源極124的條狀部124a沿通道寬度方向W的相對兩端的部分條狀部124a,且兩端部126c指的是汲極126的條狀部126a沿通道寬度方向W的相對兩端的部分條狀部126a。另外,主動元件T可更包含連接部157,連接第一子閘極部155與閘極線152(如第4A圖所示)。至於本實施例的其他細節因與第5圖相同,因此便不再贅述。 Please refer to FIG. 6, which is a top view of an active element T according to a second embodiment of the present invention. The difference between FIG. 6 and FIG. 5 is the shape of the gate electrode 154. In FIG. 6, the gate electrode 154 includes two first sub-gate portions 155 and a second sub-gate portion 156. The second sub-gate portion 156 is connected to the first sub-gate portion 155. For example, a second sub-gate portion 156 is located between the two first sub-gate portions 155. Therefore, the gate 154 is viewed from above (stacking direction Z). Watch as I-shaped. The width W1 of the first sub-gate portion 155 is larger than the width W2 of the second sub-gate portion 156; more specifically, the width W1 of the first sub-gate portion 155 along the length L of the channel is larger than the second sub-gate The portion 156 has a width W2 along the longitudinal direction L of the passage. The channel length direction L is the direction of the length of the first organic semiconductor layer 132 in the current (or electron flow) flow direction, and the channel width direction W is the direction perpendicular to the channel length direction L in the first organic semiconductor layer 132. . The first sub-gate portion 155 overlaps both end portions 124 c of the strip portion 124 a of the source 124 and both end portions 126 c of the strip portion 126 a of the drain electrode 126 in the stacking direction Z, and the second sub-gate portion 156 It partially overlaps the strip-shaped portion 124 a of the source electrode 124 and the strip-shaped portion 126 a of the drain electrode 126 in the stacking direction Z. From another perspective, there is a fringe electric field region E between an end portion 124c of the source 124 and an end 126c of the drain 126. The fringe electric field is a non-uniform electric field generated by the edge effect in a region near the edge of the conductor, and the fringe electric field region E is a region where a fringe electric field is generated between the source 124 and the drain 126. In this embodiment, the fringe electric field region E includes an end portion 124c of the source 124, an end 126c of the drain electrode 126, and a region therebetween. The gate electrode 157 covers the fringe electric field region E and protrudes from the first organic semiconductor layer 132. In this way, the first sub-gate portion 155 can improve the edge current effect between the source 124 and the drain 126, In addition, the second sub-gate portion 156 can increase the aperture ratio of the pixel structure 100 and reduce the parasitic capacitance between the gate and the source. Wherein, the two end portions 124c refer to the partial strip portions 124a of the opposite ends of the strip portion 124a of the source 124 along the channel width direction W, and the two end portions 126c refer to the strip portions 126a of the drain electrode 126 along the channel Part of the strip-shaped portion 126 a at opposite ends in the width direction W. In addition, the active device T may further include a connecting portion 157 to connect the first sub-gate portion 155 and the gate line 152 (as shown in FIG. 4A). As for other details of this embodiment, since they are the same as those in FIG. 5, they will not be described again.

請參照第7圖,其為本發明第三實施例的主動元件T的上視圖。第7圖與第5圖的差異處在於閘極154的形狀。在第7圖中,閘極154更沿通道長度方向L突出於源極124的條狀部124a與汲極126的條狀部126a。另外,閘極154亦沿通道長度方向L突出於第一有機半導體層132一距離d2。換言之,閘極154於通道長度方向L與通道寬度方向W皆突出於第一有機半導體層132,因此閘極154完整覆蓋源極124的條狀部124a與汲極126的條狀部126a。如此的結構亦能達成修飾邊緣電流的目的。至於本實施例的其他細節因與第5圖相同,因此便不再贅述。 Please refer to FIG. 7, which is a top view of an active element T according to a third embodiment of the present invention. The difference between FIG. 7 and FIG. 5 lies in the shape of the gate electrode 154. In FIG. 7, the gate electrode 154 protrudes further from the stripe portion 124 a of the source 124 and the stripe portion 126 a of the drain electrode 126 along the channel length direction L. In addition, the gate electrode 154 also protrudes from the first organic semiconductor layer 132 by a distance d2 along the channel length direction L. In other words, the gate electrode 154 protrudes from the first organic semiconductor layer 132 in both the channel length direction L and the channel width direction W. Therefore, the gate electrode 154 completely covers the stripe portion 124 a of the source 124 and the stripe portion 126 a of the drain electrode 126. Such a structure can also achieve the purpose of modifying the edge current. As for other details of this embodiment, since they are the same as those in FIG. 5, they will not be described again.

請參照第8圖,其為本發明第四實施例的主動元件T的上視圖。第8圖與第5圖的差異處在於源極124與汲極126的形狀。在第8圖中,源極124包含至少一第一條狀部124a以及一第一連接部124b。汲極126包含兩第二條狀部126a以及一第二連接部126b。第二連接部126b連接兩第二條狀部126a,且兩第二條狀部126a與第一條狀部124a 交替設置,例如第一條狀部124a位於兩第二條狀部126a之間,亦即源極124與汲極126形成指叉狀結構。汲極126與源極124相隔一間隙G。在本實施例中,閘極154沿著通道寬度方向W突出於第一有機半導體層132的側壁132s,亦即閘極154覆蓋間隙G的兩端部Ga與Gb,且突出於第一有機半導體層132一距離d1。另外,閘極154於堆疊方向Z與源極124的第一條狀部124a以及汲極126的第二條狀部126a至少部分重疊,例如在第8圖中,閘極154完全重疊第一條狀部124a,並且部分重疊第二條狀部126a。然而在其他的實施例中,閘極154可完全重疊第一條狀部124a與第二條狀部126a。另外,主動元件T可更包含連接部157,連接閘極154與閘極線152(如第4A圖所示)。至於本實施例的其他細節因與第5圖相同,因此便不再贅述。 Please refer to FIG. 8, which is a top view of an active element T according to a fourth embodiment of the present invention. The difference between FIG. 8 and FIG. 5 lies in the shapes of the source 124 and the drain 126. In FIG. 8, the source electrode 124 includes at least a first strip-shaped portion 124 a and a first connection portion 124 b. The drain electrode 126 includes two second strip portions 126 a and a second connection portion 126 b. The second connecting portion 126b connects the two second strip portions 126a, and the two second strip portions 126a and the first strip portion 124a Alternately, for example, the first strip-shaped portions 124a are located between two second strip-shaped portions 126a, that is, the source electrode 124 and the drain electrode 126 form an interdigitated structure. The drain electrode 126 is separated from the source electrode 124 by a gap G. In this embodiment, the gate electrode 154 protrudes beyond the sidewall 132s of the first organic semiconductor layer 132 along the channel width direction W, that is, the gate electrode 154 covers both ends Ga and Gb of the gap G and protrudes beyond the first organic semiconductor. The layer 132 is a distance d1. In addition, the gate electrode 154 at least partially overlaps the first strip portion 124a of the source electrode 124 and the second strip portion 126a of the drain electrode 126 in the stacking direction Z. For example, in FIG. The shaped portion 124a, and partially overlaps the second strip shaped portion 126a. However, in other embodiments, the gate electrode 154 may completely overlap the first strip-shaped portion 124a and the second strip-shaped portion 126a. In addition, the active device T may further include a connecting portion 157 to connect the gate 154 and the gate line 152 (as shown in FIG. 4A). As for other details of this embodiment, since they are the same as those in FIG. 5, they will not be described again.

第9圖為第8圖中的主動元件T於不同汲極驅動電壓下的汲極電流-閘極電壓曲線圖,而第10圖與第11圖為二比較例的主動元件於不同汲極驅動電壓下的汲極電流-閘極電壓曲線圖。在第9圖中,主動元件的閘極於通道寬度方向突出於第一有機半導體層約5微米的距離,且於通道長度方向未突出於第一有機半導體層。通道層的通道長度為約20微米,通道寬度為約200微米。曲線12的汲極驅動電壓為約-0.1伏特,曲線14的汲極驅動電壓為約-10.1伏特,曲線16的汲極驅動電壓為約-20.1伏特,且曲線18的汲極驅動電壓為約-30.1伏特。另外,在第10圖中,主動元件的閘極於通道寬度方向與於通道長度方向皆未突出於第一有機半 導體層。通道層的通道長度為約20微米,通道寬度為約200微米。曲線22的汲極驅動電壓為約-0.1伏特,曲線24的汲極驅動電壓為約-10.1伏特,曲線26的汲極驅動電壓為約-20.1伏特,且曲線28的汲極驅動電壓為約-30.1伏特。由第9圖與第10圖可知,當主動元件的閘極於通道寬度方向突出於第一有機半導體層時,可改善汲極電流,以消除駝峰現象。 FIG. 9 is a graph of the drain current-gate voltage of the active device T in FIG. 8 under different drain driving voltages, and FIG. 10 and FIG. 11 are active devices in two comparative examples driven at different drains. Drain current vs. gate voltage curve at voltage. In FIG. 9, the gate electrode of the active device protrudes from the first organic semiconductor layer by a distance of about 5 micrometers in the channel width direction, and does not protrude beyond the first organic semiconductor layer in the channel length direction. The channel layer has a channel length of about 20 microns and a channel width of about 200 microns. The drain drive voltage of curve 12 is about -0.1 volts, the drain drive voltage of curve 14 is about -10.1 volts, the drain drive voltage of curve 16 is about -20.1 volts, and the drain drive voltage of curve 18 is about- 30.1 Volts. In addition, in FIG. 10, the gate of the active device does not protrude beyond the first organic half in the channel width direction and the channel length direction. Conductor layer. The channel layer has a channel length of about 20 microns and a channel width of about 200 microns. The drain drive voltage of curve 22 is about -0.1 volts, the drain drive voltage of curve 24 is about -10.1 volts, the drain drive voltage of curve 26 is about -20.1 volts, and the drain drive voltage of curve 28 is about- 30.1 Volts. It can be seen from FIGS. 9 and 10 that when the gate of the active device protrudes beyond the first organic semiconductor layer in the channel width direction, the drain current can be improved to eliminate the hump phenomenon.

另外,在第11圖中,主動元件的閘極於通道長度方向突出於第一有機半導體層約5微米的距離,且於通道寬度方向未突出於第一有機半導體層。通道層的通道長度為約20微米,通道寬度為約200微米。曲線32的汲極驅動電壓為約-0.1伏特,曲線34的汲極驅動電壓為約-10.1伏特,曲線36的汲極驅動電壓為約-20.1伏特,且曲線38的汲極驅動電壓為約-30.1伏特。由第11圖可知,即使主動元件的閘極於通道長度方向突出於第一有機半導體層,駝峰現象仍存在,且與第10圖比較,第11圖的駝峰現象亦無改善。另外,即使閘極於通道長度方向突出於第一有機半導體層的距離增加至17微米,仍存在駝峰現象。綜合上述,駝峰現象可藉由閘極於通道寬度方向突出於第一有機半導體層的設計而改善。 In addition, in FIG. 11, the gate of the active device protrudes from the first organic semiconductor layer by a distance of about 5 micrometers in the channel length direction, and does not protrude beyond the first organic semiconductor layer in the channel width direction. The channel layer has a channel length of about 20 microns and a channel width of about 200 microns. The drain drive voltage of curve 32 is about -0.1 volts, the drain drive voltage of curve 34 is about -10.1 volts, the drain drive voltage of curve 36 is about -20.1 volts, and the drain drive voltage of curve 38 is about- 30.1 Volts. It can be seen from FIG. 11 that even if the gate of the active device protrudes beyond the first organic semiconductor layer in the channel length direction, the hump phenomenon still exists, and compared with FIG. 10, the hump phenomenon of FIG. 11 has not been improved. In addition, even if the distance that the gate protrudes from the first organic semiconductor layer in the channel length direction is increased to 17 micrometers, a hump phenomenon still exists. To sum up, the hump phenomenon can be improved by the design of the gate protruding beyond the first organic semiconductor layer in the channel width direction.

雖然本發明已以實施方式揭露如上,然其並非用以限定本發明,任何熟習此技藝者,在不脫離本發明之精神和範圍內,當可作各種之更動與潤飾,因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。 Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and retouches without departing from the spirit and scope of the present invention. Therefore, the protection of the present invention The scope shall be determined by the scope of the attached patent application.

Claims (15)

一種畫素結構,包含:一資料線;一閘極線,與該資料線交錯設置;一主動元件,電性連接該資料線與該閘極線,該主動元件包含:一汲極;一源極,電性連接於該資料線;一第一有機半導體層,覆蓋該源極與該汲極,其中該第一有機半導體層於該源極與該汲極之間具有一通道寬度方向;以及一閘極,設置於該第一有機半導體層之上,並電性連接該閘極線,其中該閘極沿著該通道寬度方向突出於該第一有機半導體層;一第二有機半導體層,覆蓋該資料線並連接於該第一有機半導體層;一平坦層,設置於閘極之上;以及一畫素電極,設置於該平坦層上並與該汲極電性連接,其中該源極包含至少一條狀部,該汲極包含至少一條狀部,該源極的該至少一條狀部與該汲極的該至少一條狀部之間具有一間隙,該閘極覆蓋該間隙,其中該閘極與該第一有機半導體層之間具有一堆疊方向,且該閘極包含:二第一子閘極部;以及一第二子閘極部,連接該等第一子閘極部,其中各該第一子閘極部的寬度大於該第二子閘極部的寬度,該等第一子閘極部於該堆疊方向上與該源極的該條狀部的兩端部和該汲極的該條狀部的兩端部重疊,且該第二子閘極部於該堆疊方向上與該源極的該條狀部和該汲極的該條狀部部分重疊。A pixel structure includes: a data line; a gate line interleaved with the data line; an active element electrically connecting the data line and the gate line, the active element including: a drain; a source A first organic semiconductor layer covering the source and the drain, wherein the first organic semiconductor layer has a channel width direction between the source and the drain; and A gate electrode disposed on the first organic semiconductor layer and electrically connected to the gate line, wherein the gate electrode protrudes from the first organic semiconductor layer along the width direction of the channel; a second organic semiconductor layer, Covering the data line and connected to the first organic semiconductor layer; a flat layer disposed on the gate electrode; and a pixel electrode disposed on the flat layer and electrically connected to the drain electrode, wherein the source electrode Including at least one strip, the drain electrode includes at least one strip, the gap between the at least one strip of the source and the at least one strip of the drain, and the gate covers the gap, wherein the gate Pole with the first organic semiconductor There is a stacking direction between the layers, and the gate includes: two first sub-gate portions; and a second sub-gate portion connected to the first sub-gate portions, wherein each of the first sub-gate portions The width of the first sub-gate part is greater than the width of the second sub-gate part, and the first sub-gate part is in the stacking direction with two ends of the strip part of the source electrode and two of the strip part of the drain electrode. The ends overlap, and the second sub-gate portion partially overlaps the strip portion of the source electrode and the strip portion of the drain electrode in the stacking direction. 如請求項1的畫素結構,其中該間隙沿該通道寬度方向具有相對的兩端部,該閘極於該堆疊方向上與該間隙的該些端部的至少其中之一重疊。The pixel structure of claim 1, wherein the gap has two opposite ends along the width direction of the channel, and the gate electrode overlaps at least one of the ends of the gap in the stacking direction. 如請求項1的畫素結構,其中該間隙沿該通道寬度方向具有相對的兩端部,該閘極覆蓋該些端部,並且沿著該通道寬度方向突出於鄰近該些端部的該第一有機半導體層的側壁。As in the pixel structure of claim 1, wherein the gap has two opposite ends along the width direction of the channel, the gate covers the ends, and protrudes along the width direction of the channel adjacent to the first ends adjacent to the ends. A sidewall of an organic semiconductor layer. 如請求項1的畫素結構,其中該第二有機半導體層與該資料線的側壁接觸,以及該第一有機半導體層與該源極和該汲極的側壁接觸。The pixel structure of claim 1, wherein the second organic semiconductor layer is in contact with a sidewall of the data line, and the first organic semiconductor layer is in contact with a sidewall of the source and the drain. 如請求項1的畫素結構,其中該源極和該汲極其中之一者的該些端部與該源極和該汲極的另一者之間具有一邊緣電場區域,該閘極覆蓋該邊緣電場區域並突出於該第一有機半導體層。As in the pixel structure of claim 1, wherein there is a fringe electric field region between the ends of one of the source and the drain and the other of the source and the drain, the gate covers The fringe electric field region protrudes from the first organic semiconductor layer. 如請求項1的畫素結構,其中該源極包含一第一連接部,該第一連接部連接該資料線與該至少一第一條狀部,其中該第一連接部與該第一條狀部之間具有一大於0度的夾角,其中該閘極於該堆疊方向上與該第一條狀部至少部分重疊,且未與該第一連接部重疊。As in the pixel structure of claim 1, wherein the source includes a first connection portion, the first connection portion connects the data line and the at least one first strip portion, wherein the first connection portion and the first strip portion There is an included angle between the sections that is greater than 0 degrees, wherein the gate electrode at least partially overlaps the first strip section in the stacking direction and does not overlap the first connection section. 如請求項6的畫素結構,其中該汲極包含兩第二條狀部以及一第二連接部,該第二連接部連接該兩第二條狀部,該兩第二條狀部與該第一條狀部交替設置,並且該閘極於該堆疊方向上與該兩第二條狀部至少部分重疊。As in the pixel structure of claim 6, wherein the drain electrode includes two second strips and a second connection portion, the second connection portion connects the two second strips, and the two second strips and the The first strips are arranged alternately, and the gate electrode at least partially overlaps the two second strips in the stacking direction. 如請求項1的畫素結構,其中該第一有機半導體層於該源極的該第一條狀部與該汲極的該第二條狀部之間更具有一通道長度方向,該閘極更沿該通道長度方向突出於該源極的該第一條狀部與該汲極的該第二條狀部。As in the pixel structure of claim 1, wherein the first organic semiconductor layer further has a channel length direction between the first stripe portion of the source electrode and the second stripe portion of the drain electrode, the gate electrode Furthermore, the first strip-shaped portion of the source electrode and the second strip-shaped portion of the drain electrode protrude further along the length of the channel. 如請求項1的畫素結構,其中該第一有機半導體層的材質包含稠五苯(pentacene)、寡噻吩(oligothiophene)、酞菁(phtalocyanine)、碳六十或其衍生物、多芳胺(polyarylamine)、聚芴(polyfluorene)、聚噻吩(polythiophene)或其衍生物。The pixel structure of claim 1, wherein the material of the first organic semiconductor layer comprises pentacene, oligothiophene, phtalocyanine, carbon sixty or its derivative, polyarylamine ( polyarylamine), polyfluorene, polythiophene, or derivatives thereof. 一種畫素結構,包含:一基板;一第一圖案化導電層,置於該基板上,該第一圖案化導電層包含一資料線、一源極與一汲極,其中該源極電性連接該資料線;一圖案化有機半導體層,覆蓋於該第一圖案化導電層上,該圖案化有機半導體層包覆該源極和該汲極的側壁,以及沿該資料線的延伸方向包覆該資料線的側壁,其中該圖案化有機半導體層於該源極與該汲極之間具有一通道寬度方向;一絕緣層,設置於該圖案化有機半導體層上;一第二圖案化導電層,設置於該圖案化有機半導體層與該絕緣層上,該第二圖案化導電層包含一閘極線與一閘極,該閘極電性連接該閘極線,且該閘極沿著該通道寬度方向突出於該圖案化有機半導體層;一平坦層,設置於該第二圖案化導電層上;以及一畫素電極,設置於該平坦層上並與該汲極電性連接。A pixel structure includes: a substrate; a first patterned conductive layer disposed on the substrate; the first patterned conductive layer includes a data line, a source, and a drain, wherein the source is electrically Connected to the data line; a patterned organic semiconductor layer covering the first patterned conductive layer, the patterned organic semiconductor layer covering the sidewalls of the source and the drain electrode, and a package along the extension direction of the data line Covering the sidewall of the data line, wherein the patterned organic semiconductor layer has a channel width direction between the source and the drain; an insulating layer is disposed on the patterned organic semiconductor layer; a second patterned conductive A layer disposed on the patterned organic semiconductor layer and the insulating layer, the second patterned conductive layer includes a gate line and a gate, the gate is electrically connected to the gate line, and the gate is along The channel width direction protrudes from the patterned organic semiconductor layer; a flat layer is disposed on the second patterned conductive layer; and a pixel electrode is disposed on the flat layer and is electrically connected to the drain electrode. 如請求項10的畫素結構,其中該源極與該汲極之間具有一間隙,該間隙沿該通道寬度方向具有相對的兩端部,該閘極與該圖案化有機半導體層之間具有一堆疊方向,該閘極於該堆疊方向上與該間隙的該些端部的至少其中之一重疊。The pixel structure of claim 10, wherein there is a gap between the source and the drain, the gap has two opposite ends along the width of the channel, and the gate and the patterned organic semiconductor layer have a gap. In a stacking direction, the gate electrode overlaps at least one of the ends of the gap in the stacking direction. 如請求項10的畫素結構,其中該圖案化有機半導體層與該資料線的側壁、該源極的側壁和該汲極的側壁接觸,且該閘極沿著該通道寬度方向突出於該圖案化有機半導體層至少突出5微米。The pixel structure of claim 10, wherein the patterned organic semiconductor layer is in contact with a sidewall of the data line, a sidewall of the source, and a sidewall of the drain, and the gate protrudes from the pattern along the width of the channel. The organic semiconductor layer protrudes at least 5 microns. 如請求項10的畫素結構,其中該源極包含至少一第一條狀部以及一第一連接部,該第一連接部連接該資料線與該至少一第一條狀部;該汲極包含兩第二條狀部以及一第二連接部,該第二連接部連接該兩第二條狀部,且該兩第二條狀部與該第一條狀部交替設置;其中該第一條狀部與該兩第二條狀部之間具有一間隙,該間隙具有相對的兩端部,該閘極與該圖案化有機半導體層之間具有一堆疊方向,該閘極於該堆疊方向上與該兩端部重疊,並突出於該圖案化有機半導體層的側壁。The pixel structure of claim 10, wherein the source electrode includes at least a first strip-shaped portion and a first connection portion, and the first connection portion connects the data line with the at least one first strip-shaped portion; the drain electrode It includes two second strip-shaped portions and a second connection portion. The second connection portion is connected to the two second strip-shaped portions, and the two second strip-shaped portions and the first strip-shaped portion are alternately arranged; wherein the first There is a gap between the strip-shaped portion and the two second strip-shaped portions, the gap has opposite ends, the gate and the patterned organic semiconductor layer have a stacking direction, and the gate is in the stacking direction The upper portion overlaps the two end portions and protrudes from a sidewall of the patterned organic semiconductor layer. 如請求項10的畫素結構,其中該源極包含至少一條狀部,該汲極包含至少一條狀部,且該源極的該至少一條狀部與該汲極的該至少一條狀部之間具有一間隙;以及該閘極覆蓋該間隙,且該閘極包含:二第一子閘極部;以及一第二子閘極部,連接該等第一子閘極部,其中各該第一子閘極部的寬度大於該第二子閘極部的寬度,該閘極與該圖案化有機半導體層之間具有一堆疊方向,該等第一子閘極部於該堆疊方向上與該源極的該條狀部的兩端部和該汲極的該條狀部的兩端部重疊,且該第二子閘極部於該堆疊方向上與該源極的該條狀部和該汲極的該條狀部部分重疊。The pixel structure of claim 10, wherein the source includes at least one strip, the drain includes at least one strip, and between the at least one strip of the source and the at least one strip of the drain There is a gap; and the gate covers the gap, and the gate includes: two first sub-gate portions; and a second sub-gate portion connected to the first sub-gate portions, wherein each of the first The width of the sub-gate part is larger than the width of the second sub-gate part, and there is a stacking direction between the gate and the patterned organic semiconductor layer, and the first sub-gate part is in contact with the source in the stacking direction. Both end portions of the strip portion of the electrode and both end portions of the strip portion of the drain electrode overlap, and the second sub-gate portion is in the stacking direction with the strip portion and the drain portion of the source electrode. The stripe portions of the poles partially overlap. 如請求項14的畫素結構,其中該圖案化有機半導體層於該源極的該條狀部與該汲極的該條狀部之間更具有一通道長度方向,該閘極更沿該通道長度方向突出於該源極的該條狀部與該汲極的該條狀部。As in the pixel structure of claim 14, wherein the patterned organic semiconductor layer further has a channel length direction between the strip portion of the source electrode and the strip portion of the drain electrode, the gate electrode further extends along the channel. The length direction protrudes from the strip portion of the source electrode and the strip portion of the drain electrode.
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