TWI637388B - Memory system and memory module and control method for memory module - Google Patents

Memory system and memory module and control method for memory module Download PDF

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TWI637388B
TWI637388B TW106105033A TW106105033A TWI637388B TW I637388 B TWI637388 B TW I637388B TW 106105033 A TW106105033 A TW 106105033A TW 106105033 A TW106105033 A TW 106105033A TW I637388 B TWI637388 B TW I637388B
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clock signal
memory
reverse
module
memory module
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TW201742070A (en
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陳尚斌
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聯發科技股份有限公司
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076—Timing circuits
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G06F13/4086—Bus impedance matching, e.g. termination
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4093—Input/output [I/O] data interface arrangements, e.g. data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/04—Supports for storage elements, e.g. memory modules; Mounting or fixing of storage elements on such supports
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1048—Data bus control circuits, e.g. precharging, presetting, equalising
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/225—Clock input buffers
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/0264—Arrangements for coupling to transmission lines
    • H04L25/0298—Arrangement for terminating transmission lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/10—Aspects relating to interfaces of memory device to external buses
    • G11C2207/105—Aspects related to pads, pins or terminals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1087—Data input latches
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1093—Input synchronization
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0005—Modifications of input or output impedance

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  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
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  • Microelectronics & Electronic Packaging (AREA)
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Abstract

記憶體系統包括記憶體控制器，以及記憶體模組，其中，該記憶體控制器用於至少產生第一時鐘信號和反向第一時鐘信號；該記憶體模組用於從該記憶體控制至少接收該第一時鐘信號和該反向第一時鐘信號；此外，該記憶體模組包括第一終端模組，該第一時鐘信號通過該第一終端模組與該反向第一時鐘信號耦接。 The memory system includes a memory controller, and the memory module, wherein the memory controller is configured to generate at least a first clock signal and a reverse first clock signal; the memory module is configured to control at least from the memory Receiving the first clock signal and the reverse first clock signal; further, the memory module includes a first terminal module, and the first clock signal is coupled to the reverse first clock signal by the first terminal module Pick up.

Description

記憶體系統、記憶體模組以及記憶體模組的控制方法 Memory system, memory module, and control method of memory module

本發明涉及記憶體控制領域，尤其涉及一種記憶體系統、記憶體模組以及記憶體模組的控制方法。 The present invention relates to the field of memory control, and in particular, to a memory system, a memory module, and a method for controlling a memory module.

傳統的動態隨機訪問記憶體(Dynamic Random Access Memory，DRAM)模組通常包括終端電阻(on-die termination)，該終端電阻用於信號線的阻抗匹配，並降低信號失真。傳統的終端電阻通常耦接至參考電壓，例如接地電壓。但是，這樣的設計不能使信號品質最優。 Conventional Dynamic Random Access Memory (DRAM) modules typically include on-die termination, which is used for impedance matching of signal lines and reduces signal distortion. Conventional termination resistors are typically coupled to a reference voltage, such as a ground voltage. However, such a design does not optimize signal quality.

本發明提供記憶體系統、記憶體模組以及記憶體模組的控制方法。可提高信號的完整性。 The invention provides a memory system, a memory module and a control method of the memory module. Improve signal integrity.

本發明提供的一種記憶體系統，可包括：記憶體控制器，用於至少產生第一時鐘信號和反向第一時鐘信號；以及記憶體模組，耦接於該記憶體控制器，用於從該記憶體控制至少接收該第一時鐘信號和該反向第一時鐘信號；其中，該記憶體模組包括第一終端模組，該 第一時鐘信號通過該第一終端模組與該反向第一時鐘信號耦接。 The present invention provides a memory system, which may include: a memory controller for generating at least a first clock signal and a reverse first clock signal; and a memory module coupled to the memory controller for Receiving at least the first clock signal and the reverse first clock signal from the memory control; wherein the memory module includes a first terminal module, The first clock signal is coupled to the reverse first clock signal through the first terminal module.

本發明提供的一種記憶體模組，可包括：記憶體介面電路，用於從記憶體控制器至少接收第一時鐘信號和反向第一時鐘信號；以及第一終端模組，耦接於該記憶體介面電路；其中，該第一時鐘信號通過該第一終端模組耦接於該反向第一時鐘信號。 The memory module of the present invention may include: a memory interface circuit for receiving at least a first clock signal and a reverse first clock signal from a memory controller; and a first terminal module coupled to the a memory interface circuit, wherein the first clock signal is coupled to the reverse first clock signal through the first terminal module.

本發明提供的一種記憶體模組的控制方法，可應用與本發明的記憶體模組及記憶體系統中，該控制方法可包括：從記憶體控制器接收時鐘信號和反向時鐘信號；以及在該記憶體模組內，通過該終端模組耦接該時鐘信號和該反向時鐘信號。 The method for controlling a memory module provided by the present invention can be applied to the memory module and the memory system of the present invention. The control method can include: receiving a clock signal and a reverse clock signal from the memory controller; In the memory module, the clock signal and the reverse clock signal are coupled through the terminal module.

由上可知，在本發明的技術方案中，通過終端模組使時鐘信號和反向時鐘信號可在晶片上建立耦接。因此，阻抗匹配可更準確，信號的反射被降低，由此提高了信號的完整性。 It can be seen from the above that in the technical solution of the present invention, the clock signal and the reverse clock signal can be coupled on the wafer through the terminal module. Therefore, impedance matching can be more accurate, and reflection of the signal is reduced, thereby improving signal integrity.

100‧‧‧記憶體系統 100‧‧‧ memory system

110‧‧‧記憶體控制器 110‧‧‧ memory controller

120‧‧‧記憶體模組 120‧‧‧ memory module

122‧‧‧記憶體介面電路 122‧‧‧Memory interface circuit

124‧‧‧控制電路 124‧‧‧Control circuit

126‧‧‧記憶體陣列 126‧‧‧ memory array

VDD‧‧‧電源電壓 VDD‧‧‧Power supply voltage

DQ‧‧‧資料信號 DQ‧‧‧ data signal

WCK‧‧‧寫時鐘信號 WCK‧‧‧ write clock signal

WCKB‧‧‧反向寫時鐘信號 WCKB‧‧‧Reverse write clock signal

CMD‧‧‧命令信號 CMD‧‧‧ command signal

CLK‧‧‧時鐘信號 CLK‧‧‧ clock signal

CLKB‧‧‧反向時鐘信號 CLKB‧‧‧reverse clock signal

201，202，203，204‧‧‧驅動器 201,202,203,204‧‧‧ drive

210_1，210_2，210_3，210_4‧‧‧通道 210_1, 210_2, 210_3, 210_4‧‧‧ channels

N1，N2，N3，N4‧‧‧襯墊 N1, N2, N3, N4‧‧‧ pads

ODT1，ODT2，ODT3，ODT4‧‧‧終端電阻 ODT1, ODT2, ODT3, ODT4‧‧‧ terminating resistor

通過閱讀後續的詳細描述和實施例可以更全面地理解本發明，該實施例參照附圖給出，其中：第1圖根據本發明的一個實施例示出記憶體系統100。 The invention may be more completely understood by reading the following detailed description and embodiments, which are illustrated by the accompanying drawings in which: FIG. 1 illustrates a memory system 100 in accordance with an embodiment of the present invention.

第2圖根據本發明的一個實施例示出記憶體系統100的終端電阻的設計方案。 Figure 2 shows a design of the termination resistance of the memory system 100 in accordance with one embodiment of the present invention.

第3圖根據本發明的另一個實施例示出記憶體系統100的終端電阻的設計方案。 Figure 3 illustrates a design of the termination resistance of the memory system 100 in accordance with another embodiment of the present invention.

以下描述為本發明實施的較佳實施例。以下實施例僅用來例舉闡釋本發明的技術特徵，並非用來限制本發明的範疇。在通篇說明書及申請專利範圍當中使用了某些詞彙來指稱特定的元件。所屬領域技術人員應可理解，製造商可能會用不同的名詞來稱呼同樣的元件。本說明書及申請專利範圍並不以名稱的差異來作為區別元件的方式，而是以元件在功能上的差異來作為區別的基準。本發明的範圍應當參考后附的申請專利範圍來確定。本發明中使用的術語“元件”、“系統”和“裝置”可以是與電腦相關的實體，其中，該電腦可以是硬體、軟體、或硬體和軟體的結合。在以下描述和申請專利範圍當中所提及的術語“包含”和“包括”為開放式用語，故應解釋成“包含，但不限定於…”的意思。此外，術語“耦接”意指間接或直接的電氣連接。因此，若文中描述一個裝置耦接至另一裝置，則代表該裝置可直接電氣連接於該另一裝置，或者透過其它裝置或連接手段間接地電氣連接至該另一裝置。 The following description is of a preferred embodiment of the invention. The following examples are merely illustrative of the technical features of the present invention and are not intended to limit the scope of the present invention. Certain terms are used throughout the specification and claims to refer to particular elements. Those skilled in the art will appreciate that manufacturers may refer to the same elements by different nouns. The scope of the present specification and the patent application do not use the difference of the names as the means for distinguishing the elements, but the differences in the functions of the elements as the basis for the distinction. The scope of the invention should be determined with reference to the appended claims. The terms "element", "system" and "device" as used in the present invention may be a computer-related entity, where the computer may be a hardware, a soft body, or a combination of hardware and software. The terms "comprising" and "including" as used in the following description and claims are intended to be interpreted as "included, but not limited to". Furthermore, the term "coupled" means an indirect or direct electrical connection. Thus, if a device is described as being coupled to another device, it is meant that the device can be directly electrically connected to the other device or indirectly electrically connected to the other device through other means or means.

請參考第1圖，其根據本發明的一個實施例示出記憶體系統100。如第1圖所示，記憶體系統100包括記憶體控制器110和由電源電壓VDD供電的記憶體模組120，其中，記憶體模組120包括記憶體介面電路122、控制電路124以及記憶體陣列126。在本實施例中，記憶體控制器110和記憶體模組120通過複數個耦接線互連，該複數個耦接線用於傳輸複數個雙向(bi-directional)資料信號DQ、寫時鐘信號WCK、反向寫時鐘信號WCKB、複數個命令信號CMD、時鐘信號CLK以及反向時鐘信號CKB。在一個實施例中，記憶體系統100為易失性記憶體系統，例如，DRAM系統，記憶體控制器110為DRAM記憶體控制器，而記憶體模組120為DRAM記憶體模組。 Referring to Figure 1, a memory system 100 is illustrated in accordance with one embodiment of the present invention. As shown in FIG. 1, the memory system 100 includes a memory controller 110 and a memory module 120 powered by a power supply voltage VDD. The memory module 120 includes a memory interface circuit 122, a control circuit 124, and a memory. Array 126. In this embodiment, the memory controller 110 and the memory module 120 are interconnected by a plurality of coupling wires for transmitting a plurality of bi-directional data signals DQ, write clock signals WCK, The clock signal WCKB, the plurality of command signals CMD, the clock signal CLK, and the reverse clock signal CKB are reversely written. In one embodiment, the memory system 100 is a volatile memory system, such as a DRAM system, the memory controller 110 is a DRAM memory controller, and the memory module 120 is a DRAM memory module.

當記憶體系統100為DRAM系統，該複數個命令信號至少包 括列位址選通(row address strobe)、行地址選通(column address strobe)以及寫使能信號。此外，寫時鐘信號WCK和反向寫時鐘信號WCKB用於將資料信號DQ鎖存至記憶體模組120，時鐘信號CLK和反向時鐘信號CLKB用於將命令信號CMD鎖存至記憶體模組120，且寫時鐘信號WCK的頻率大於或等於時鐘信號CLK的頻率。例如，記憶體120可使用寫時鐘信號WCK和反向寫時鐘信號WCKB對該資料信號DQ進行採樣和存儲，以供後續的信號處理。記憶體模組120可使用時鐘信號CLK和反向時鐘信號CLKB對該命令信號CMD進行採樣和存儲，以供後續的信號處理。 When the memory system 100 is a DRAM system, the plurality of command signals are at least included A row address strobe, a column address strobe, and a write enable signal are included. In addition, the write clock signal WCK and the reverse write clock signal WCKB are used to latch the data signal DQ to the memory module 120, and the clock signal CLK and the reverse clock signal CLKB are used to latch the command signal CMD to the memory module. 120, and the frequency of the write clock signal WCK is greater than or equal to the frequency of the clock signal CLK. For example, the memory 120 can sample and store the data signal DQ using the write clock signal WCK and the reverse write clock signal WCKB for subsequent signal processing. The memory module 120 can sample and store the command signal CMD using the clock signal CLK and the inverted clock signal CLKB for subsequent signal processing.

在記憶體系統100的操作中，記憶體控制器110用於從主機或處理器接收請求，並將資料信號DQ、寫時鐘信號WCK、反向寫時鐘信號WCKB、複數個命令信號CMD、時鐘信號CLK以及反向時鐘信號CKB中的一部分傳輸至記憶體模組120用於訪問記憶體模組120。此外，記憶體控制110可包括相關的電路，例如，位址解碼器、處理電路、讀/寫緩衝器、控制邏輯和仲裁器等，用於執行相應的操作。記憶體介面電路122包括複數個針腳(或襯墊)以及相關的接收電路。記憶體介面電路122用於從記憶體控制器110接收資料信號DQ、寫時鐘信號WCK、反向寫時鐘信號WCKB、複數個命令信號CMD、時鐘信號CLK以及反向時鐘信號CKB，並選擇性地輸出該接收的信號給控制電路124。控制電路124可包括讀/寫控制器、列解碼器和行解碼器。控制電路124用於從記憶體介面電路122接收信號以訪問記憶體陣行126。 In operation of the memory system 100, the memory controller 110 is configured to receive a request from a host or a processor and to apply a data signal DQ, a write clock signal WCK, a reverse write clock signal WCKB, a plurality of command signals CMD, and a clock signal. A portion of the CLK and reverse clock signal CKB is transmitted to the memory module 120 for accessing the memory module 120. In addition, memory control 110 can include associated circuitry, such as address decoders, processing circuitry, read/write buffers, control logic, and arbiter, for performing corresponding operations. Memory interface circuit 122 includes a plurality of pins (or pads) and associated receiving circuitry. The memory interface circuit 122 is configured to receive the data signal DQ, the write clock signal WCK, the reverse write clock signal WCKB, the plurality of command signals CMD, the clock signal CLK, and the reverse clock signal CKB from the memory controller 110, and selectively The received signal is output to the control circuit 124. Control circuitry 124 may include a read/write controller, a column decoder, and a row decoder. Control circuitry 124 is operative to receive signals from memory interface circuitry 122 to access memory array row 126.

由於本發明實施例主要關注終端電阻的耦接，因此，本發明將省略其他組件的詳細的描述。 Since the embodiments of the present invention mainly focus on the coupling of the terminating resistors, the detailed description of the other components will be omitted in the present invention.

請參考第2圖，其根據本發明的一個實施例示出記憶體系統 100的終端電阻的設計方案。如第2圖所示，記憶體模組120包括兩個終端電阻ODT1和ODT2，且終端電阻ODT1和ODT2彼此相連以允許寫時鐘信號WCK和反向寫時鐘信號WCKB在晶片上互連。終端電阻ODT1和ODT2可由金屬氧化物半導體、金屬線、多晶矽中的任意一種實現，或者，ODT1和ODT2為任意的阻抗可調的電阻器。終端電阻ODT1和ODT2不與任意的偏置電壓耦接，例如，接地電壓或電源電壓。具體而言，當寫時鐘信號WCK為高電壓電平，反向寫時鐘信號WCKB為低電壓電平，電流流經驅動器201、通道210_1、襯墊N1、終端電阻ODT1和ODT2、襯墊N2以及通道210_2後到達驅動器202；而當寫時鐘信號WCK為低電壓電平，反向寫時鐘信號WCKB為高電壓電平，電流流經驅動器202、通道210_2、襯墊N2、終端電阻ODT1和ODT2、襯墊N1以及通道210_1後到達驅動器201。在本實施例中，通道210_1和210_2可為封裝或印刷電路板上的傳輸線。 Please refer to FIG. 2, which illustrates a memory system according to an embodiment of the present invention. The design of the terminal resistance of 100. As shown in FIG. 2, the memory module 120 includes two termination resistors ODT1 and ODT2, and the termination resistors ODT1 and ODT2 are connected to each other to allow the write clock signal WCK and the reverse write clock signal WCKB to be interconnected on the wafer. The termination resistors ODT1 and ODT2 may be implemented by any one of a metal oxide semiconductor, a metal line, and a polysilicon, or ODT1 and ODT2 may be any impedance-adjustable resistor. The termination resistors ODT1 and ODT2 are not coupled to any bias voltage, such as a ground voltage or a supply voltage. Specifically, when the write clock signal WCK is at a high voltage level, the reverse write clock signal WCKB is at a low voltage level, and current flows through the driver 201, the channel 210_1, the pad N1, the termination resistors ODT1 and ODT2, the pad N2, and Channel 210_2 arrives at driver 202; and when write clock signal WCK is at a low voltage level, reverse write clock signal WCKB is at a high voltage level, current flows through driver 202, channel 210_2, pad N2, termination resistors ODT1 and ODT2. The pad N1 and the channel 210_1 arrive at the driver 201. In this embodiment, channels 210_1 and 210_2 can be transmission lines on a package or printed circuit board.

第2圖中示出的終端電阻的數量僅用於描述的目地，並不是對本發明的限定。只需要記憶體120包括終端模組(該終端模組包括至少一個終端電阻)用於使寫時鐘信號WCK與反向寫時鐘信號WCKB建立耦接即可。實踐中，記憶體模組120中的終端電阻的數量可由設計需要確定。 The number of terminating resistors shown in Figure 2 is for illustrative purposes only and is not intended to limit the invention. The memory 120 only needs to include a terminal module (the terminal module includes at least one terminating resistor) for coupling the write clock signal WCK and the reverse write clock signal WCKB. In practice, the number of termination resistors in the memory module 120 can be determined by design requirements.

如第2圖所示，通過使用終端電阻，阻抗匹配可更準確，信號的反射被降低，由此提高了信號的完整性。 As shown in Figure 2, by using termination resistors, impedance matching can be more accurate and signal reflections are reduced, thereby increasing signal integrity.

第2圖示出記憶體模組120包括兩個終端電阻ODT1和ODT2用於耦接寫時鐘信號WCK和反向寫時鐘信號WCKB。在另一個實施例中，記憶體晶片120可進一步包括其他終端電阻用於耦接時鐘信號CLK和反向時鐘信號CLKB。請參考第3圖，記憶體模組120進一步包括終端 電阻ODT3和ODT4，終端電阻ODT3和ODT4彼此相連以允許時鐘信號CLK和反向寫時鐘信號CLKB互連。在本實施例中，終端電阻可由金屬氧化物半導體、金屬線、多晶矽中的任意一種實現，或者，ODT3和ODT3為任意的阻抗可調的電阻器。且終端電阻ODT3和ODT4不與任意的偏置電壓耦接，例如，接地電壓或電源電壓。具體而言，當時鐘信號CLK為高電壓電平，反向時鐘信號CLKB為低電壓電平，電流流經驅動器203、通道210_3、襯墊N3、終端電阻ODT3和ODT4、襯墊N4以及通道210_4後到達驅動器204；而當時鐘信號CLK為低電壓電平，反向時鐘信號CLKB為高電壓電平，電流流經驅動器204、通道210_4、襯墊N4、終端電阻ODT3和ODT4、襯墊N3以及通道210_3後到達驅動器203。在本實施例中，通道210_3和210_4可為封裝或印刷電路板上的傳輸線。 2 shows that the memory module 120 includes two termination resistors ODT1 and ODT2 for coupling the write clock signal WCK and the reverse write clock signal WCKB. In another embodiment, the memory chip 120 may further include other termination resistors for coupling the clock signal CLK and the inverted clock signal CLKB. Referring to FIG. 3, the memory module 120 further includes a terminal. The resistors ODT3 and ODT4, the termination resistors ODT3 and ODT4 are connected to each other to allow the clock signal CLK and the reverse write clock signal CLKB to be interconnected. In this embodiment, the termination resistor may be implemented by any one of a metal oxide semiconductor, a metal line, and a polysilicon, or ODT3 and ODT3 may be any resistors of adjustable impedance. And the termination resistors ODT3 and ODT4 are not coupled to any bias voltage, such as a ground voltage or a power supply voltage. Specifically, when the clock signal CLK is at a high voltage level, the reverse clock signal CLKB is at a low voltage level, and current flows through the driver 203, the channel 210_3, the pad N3, the termination resistors ODT3 and ODT4, the pad N4, and the channel 210_4. After reaching the driver 204; when the clock signal CLK is at a low voltage level, the reverse clock signal CLKB is at a high voltage level, and current flows through the driver 204, the channel 210_4, the pad N4, the termination resistors ODT3 and ODT4, the pad N3, and The channel 210_3 arrives at the driver 203. In this embodiment, the channels 210_3 and 210_4 can be transmission lines on a package or printed circuit board.

此外，第3圖中示出的終端電阻的數量僅用於描述的目地，並不是對本發明的限定。只需要記憶體120包括終端模組(該終端模組包括至少一個終端電阻)用於使時鐘信號CLK與反向時鐘信號CLKB建立耦接即可。實踐中，記憶體模組120中的終端電阻的數量可由設計需要確定。 Further, the number of terminating resistors shown in FIG. 3 is for the purpose of description only and is not intended to limit the invention. It is only required that the memory 120 includes a terminal module (the terminal module includes at least one terminating resistor) for coupling the clock signal CLK and the inverted clock signal CLKB. In practice, the number of termination resistors in the memory module 120 can be determined by design requirements.

簡言之，在本發明的終端電阻結構中，允許時鐘信號和反向時鐘信號在晶片上建立耦接。因此，阻抗匹配可更準確，信號的反射被降低，由此提高了信號的完整性。 In short, in the termination resistor structure of the present invention, the clock signal and the reverse clock signal are allowed to establish coupling on the wafer. Therefore, impedance matching can be more accurate, and reflection of the signal is reduced, thereby improving signal integrity.

申請專利範圍書中用以修飾元件的“第一”、“第二”等序數詞的使用本身未暗示任何優先權、優先次序、各元件之間的先後次序、或所執行方法的時間次序，而僅用作標識來區分具有相同名稱(具有不同序數詞)的不同元件。 The use of ordinal numbers such as "first," "second," etc., used to modify elements in the scope of the claims is not intended to suggest any priority, prioritization, or It is only used as an identifier to distinguish different components with the same name (with different ordinal numbers).

儘管已經對本發明實施例及其優點進行了詳細說明，但應當理解的 是，在不脫離本發明的精神以及申請專利範圍所定義的範圍內，可以對本發明進行各種改變、替換和變更。所描述的實施例在所有方面僅用於說明的目的而並非用於限制本發明。本發明的保護範圍當視所附的申請專利範圍所界定者為准。所屬領域技術人員皆在不脫離本發明之精神以及範圍內做些許更動與潤飾。 Although the embodiments of the invention and their advantages have been described in detail, it should be understood It is to be understood that various changes, substitutions and changes can be made in the present invention without departing from the spirit and scope of the invention. The described embodiments are to be considered in all respects as illustrative and not limiting. The scope of the invention is defined by the scope of the appended claims. Those skilled in the art will make some modifications and refinements without departing from the spirit and scope of the invention.

Claims (16)

一種記憶體系統，包括：記憶體控制器，用於至少產生第一時鐘信號和反向第一時鐘信號；以及記憶體模組，耦接於該記憶體控制器，用於從該記憶體控制器至少接收該第一時鐘信號和該反向第一時鐘信號；其中，該記憶體模組包括第一終端模組，該第一時鐘信號通過該第一終端模組與該反向第一時鐘信號耦接；該第一終端模組包括：第一終端電阻和第二終端電阻；其中，該第一終端電阻的第一節點用於接收該第一時鐘信號；其中，該第二終端電阻的第一節點用於接收該反向第一時鐘信號；其中，該第一終端電阻的第二節點直接耦接於該第二終端電阻的第二節點。 A memory system includes: a memory controller for generating at least a first clock signal and a reverse first clock signal; and a memory module coupled to the memory controller for controlling from the memory Receiving at least the first clock signal and the reverse first clock signal; wherein the memory module includes a first terminal module, the first clock signal passing the first terminal module and the reverse first clock The first terminal module includes: a first termination resistor and a second termination resistor; wherein the first node of the first termination resistor is configured to receive the first clock signal; wherein, the second termination resistor The first node is configured to receive the reverse first clock signal; wherein the second node of the first termination resistor is directly coupled to the second node of the second termination resistor. 如申請專利範圍第1項的記憶體系統，該記憶體模組通過兩個襯墊分別接收該第一時鐘信號和該反向第一時鐘信號，且在該記憶體模組內部，該第一終端模組包括位於該兩個襯墊之間的電流路徑。 For example, in the memory system of claim 1, the memory module receives the first clock signal and the reverse first clock signal through two pads, and the first in the memory module The terminal module includes a current path between the two pads. 如申請專利範圍第1項的記憶體系統，包括動態隨機訪問記憶體系統。 A memory system as claimed in claim 1 includes a dynamic random access memory system. 如申請專利範圍第3項的記憶體系統，該第一時鐘信號用於在該記憶體模組中鎖存資料信號。 In the memory system of claim 3, the first clock signal is used to latch a data signal in the memory module. 如申請專利範圍第3項的記憶體系統，該第一時鐘信號用於在該記憶體模組中鎖存命令信號。 In the memory system of claim 3, the first clock signal is used to latch a command signal in the memory module. 如申請專利範圍第1項的記憶體系統，該記憶體控制器還用於產生第二時鐘信號和反向第二時鐘信號；該記憶體模組還用於從該記憶體控制器接收該第二時鐘信號和該反向第二 時鐘信號；該記憶體模組還包括第二終端模組；其中，該第二時鐘信號通過該第二終端模組耦接於該反向第二時鐘信號。 For example, in the memory system of claim 1, the memory controller is further configured to generate a second clock signal and a reverse second clock signal; the memory module is further configured to receive the first clock from the memory controller Two clock signals and the second reverse The clock module further includes a second terminal module, wherein the second clock signal is coupled to the reverse second clock signal through the second terminal module. 如申請專利範圍第6項的記憶體系統，包括動態隨機訪問記憶體系統。 A memory system as claimed in claim 6 includes a dynamic random access memory system. 如申請專利範圍第7項的記憶體系統，該第一時鐘信號用於在該記憶體模組中鎖存資料信號，該第二時鐘信號用於在該記憶體模組中鎖存命令信號。 In the memory system of claim 7, the first clock signal is used to latch a data signal in the memory module, and the second clock signal is used to latch a command signal in the memory module. 一種記憶體模組，包括：記憶體介面電路，用於從記憶體控制器至少接收第一時鐘信號和反向第一時鐘信號；以及第一終端模組，耦接於該記憶體介面電路；其中，該第一時鐘信號通過該第一終端模組耦接於該反向第一時鐘信號；該第一終端模組包括：第一終端電阻和第二終端電阻；其中，該第一終端電阻的第一節點用於接收該第一時鐘信號；其中，該第二終端電阻的第一節點用於接收該反向第一時鐘信號；其中，該第一終端電阻的第二節點直接耦接於該第二終端電阻的第二節點。 A memory module includes: a memory interface circuit for receiving at least a first clock signal and a reverse first clock signal from a memory controller; and a first terminal module coupled to the memory interface circuit; The first clock signal is coupled to the reverse first clock signal through the first terminal module; the first terminal module includes: a first terminal resistor and a second terminal resistor; wherein the first terminal resistor The first node is configured to receive the first clock signal, wherein the first node of the second termination resistor is configured to receive the reverse first clock signal; wherein the second node of the first termination resistor is directly coupled to a second node of the second termination resistor. 如申請專利範圍第9項的記憶體模組，該記憶體介面電路包括兩個襯墊用於分別接收該第一時鐘信號和該反向第一時鐘信號，且該第一終端模組在該兩個襯墊之間建立電流路徑。 The memory module of claim 9, wherein the memory interface circuit includes two pads for respectively receiving the first clock signal and the reverse first clock signal, and the first terminal module is in the A current path is established between the two pads. 如申請專利範圍第9項的記憶體模組，該記憶體介面電路還從該記憶體控制器接收第二時鐘信號和反向第二時鐘信號，該記憶體模組還包括第二終端模組； 其中，該第二時鐘信號通過該第二終端模組耦接於該反向第二時鐘信號。 The memory module of claim 9, wherein the memory interface circuit further receives a second clock signal and a reverse second clock signal from the memory controller, the memory module further comprising a second terminal module ; The second clock signal is coupled to the reverse second clock signal through the second terminal module. 如申請專利範圍第11項的記憶體模組，包括動態隨機訪問記憶體模組。 The memory module of claim 11 includes a dynamic random access memory module. 如申請專利範圍第12項的記憶體模組，該第一時鐘信號用於在該記憶體模組中鎖存資料信號，該第二時鐘信號用於在該記憶體模組中鎖存命令信號。 For example, in the memory module of claim 12, the first clock signal is used to latch a data signal in the memory module, and the second clock signal is used to latch a command signal in the memory module. . 一種記憶體模組的控制方法，其中，該記憶體模組包括第一終端模組，該控制方法包括：從記憶體控制器接收第一時鐘信號和反向第一時鐘信號；以及在該記憶體模組內，通過該第一終端模組耦接該第一時鐘信號和該反向第一時鐘信號；該第一終端模組包括第一終端電阻和第二終端電阻，該第一終端電阻的第一節點用於接收該第一時鐘信號，該第二終端電阻的第一節點用於接收該反向第一時鐘信號；該通過該第一終端模組耦接該時鐘信號和該第一反向時鐘信號的步驟，包括：將該第二終端電阻的第二節點直接耦接至該第一終端電阻的第二節點。 A method for controlling a memory module, wherein the memory module includes a first terminal module, the control method comprising: receiving a first clock signal and a reverse first clock signal from a memory controller; and in the memory The first terminal module is coupled to the first clock signal and the reverse first clock signal by the first terminal module; the first terminal module includes a first termination resistor and a second termination resistor, the first termination resistor The first node is configured to receive the first clock signal, the first node of the second termination resistor is configured to receive the reverse first clock signal, and the first terminal module is coupled to the clock signal and the first The step of reversing the clock signal includes: directly coupling the second node of the second termination resistor to the second node of the first termination resistor. 如申請專利範圍第14項的方法，該記憶體模組通過兩個襯墊分別接收該第一時鐘信號和該第一反向時鐘信號；該通過該第一終端模組耦接該第一時鐘信號和該第一反向時鐘信號的步驟，包括：通過該第一終端模組耦接該第一時鐘信號和該第一反向時鐘信號來在該兩個襯墊之間建立電流路徑。 The method of claim 14, wherein the memory module receives the first clock signal and the first reverse clock signal through two pads respectively; the first terminal module is coupled to the first clock The step of the signal and the first reverse clock signal includes coupling a first clock signal and the first reverse clock signal through the first terminal module to establish a current path between the two pads. 如申請專利範圍第14項的方法，該記憶體模組包括動態隨機訪問記憶體模組。 For example, in the method of claim 14, the memory module includes a dynamic random access memory module.
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