TWI634601B - Semiconductor device manufacturing method and semiconductor device - Google Patents

Semiconductor device manufacturing method and semiconductor device Download PDF

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TWI634601B
TWI634601B TW103127900A TW103127900A TWI634601B TW I634601 B TWI634601 B TW I634601B TW 103127900 A TW103127900 A TW 103127900A TW 103127900 A TW103127900 A TW 103127900A TW I634601 B TWI634601 B TW I634601B
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cavity
resin
semiconductor device
substrate
semiconductor element
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TW201515121A (en
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中村朋陽
塩原利夫
秋葉秀樹
関口晋
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信越化學工業股份有限公司
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144Gold (Au) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93Batch processes
    • H01L2224/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • H01L24/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/35Mechanical effects
    • H01L2924/351Thermal stress
    • H01L2924/3511Warping

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  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Moulds For Moulding Plastics Or The Like (AREA)
  • Casting Or Compression Moulding Of Plastics Or The Like (AREA)

Abstract

本發明之課題為提供一種半導體裝置之製造方法,其係無須進行因應於以往因填料所導致的翹曲對策及密封層形成時的不良元件數目之樹脂填充量的調整,而減少繁雜的步驟,同時能夠製造減低翹曲,且耐熱性、耐濕性優異的半導體裝置。 An object of the present invention is to provide a method for producing a semiconductor device, which is capable of reducing complicated steps in accordance with the adjustment of the resin filling amount in accordance with conventional warping measures due to the filler and the number of defective components in the formation of the sealing layer. At the same time, it is possible to manufacture a semiconductor device which is excellent in heat resistance and moisture resistance while reducing warpage.

本發明之解決手段為一種半導體裝置之製造方法,其係具有:於半導體元件非搭載基板上,載置比密封層之形成所需要的量更多量的熱硬化性樹脂之樹脂載置步驟;將第1空腔內從室溫加熱至200℃,將半導體元件搭載基板配置於成形模具之上模具及下模具其中一方的模具,並將半導體元件非搭載基板配置於另一方的模具之配置步驟;將上模具及下模具進行加壓並將多餘的熱硬化性樹脂排出至第1空腔的外部之樹脂排出步驟;以及一邊將上模具及下模具進行加壓一邊使熱硬化性樹脂成形,使半導體元件搭載基板、半導體元件非搭載基板、及密封層一體化之一體化步驟。 The method of the present invention is a method of manufacturing a semiconductor device, comprising: a resin mounting step of placing a thermosetting resin in a larger amount than that required for formation of a sealing layer on a semiconductor element non-mounting substrate; In the first cavity, the semiconductor element mounting substrate is placed on one of the mold upper mold and the lower mold, and the semiconductor element non-mounting substrate is placed in the other mold. a step of discharging the upper mold and the lower mold and discharging the excess thermosetting resin to the outside of the first cavity; and molding the thermosetting resin while pressurizing the upper mold and the lower mold. An integration step of integrating a semiconductor element mounting substrate, a semiconductor element non-mounting substrate, and a sealing layer.

Description

半導體裝置之製造方法及半導體裝置 Semiconductor device manufacturing method and semiconductor device

本發明係關於使用了成形模具的半導體裝置之製造方法、及藉由此方法所製造的半導體裝置。 The present invention relates to a method of manufacturing a semiconductor device using a molding die, and a semiconductor device manufactured by the method.

以往,晶圓級之密封方法、或以熱硬化性環氧樹脂將呈矩陣狀搭載了半導體元件的有機基板予以單面成形之方法已有各種提案並加以探討(專利文獻1-3)。 Conventionally, a method of forming a wafer-level sealing method or a method of forming a single-sided organic substrate in which a semiconductor element is mounted in a matrix with a thermosetting epoxy resin has been proposed and discussed (Patent Documents 1-3).

以上述方式製造半導體裝置時,基板的尺寸小者,係可藉由調整環氧樹脂之線膨脹係數而控制密封後之基板的翹曲。 When the semiconductor device is manufactured in the above manner, the substrate is small in size, and the warpage of the substrate after sealing can be controlled by adjusting the linear expansion coefficient of the epoxy resin.

於使用了直徑8英吋(200mm)左右的小直徑晶圓等之基板或小尺寸之有機基板的情況中,雖目前仍可無大問題地進行密封成形,但由於直徑8英吋以上的晶圓或大型的有機基板在密封後,環氧樹脂等的收縮應力大,因此在經單面成形的晶圓或有機基板會發生大的翹曲或基板的破裂而無法製造半導體裝置。 In the case of using a substrate such as a small-diameter wafer having a diameter of about 8 inches (200 mm) or a small-sized organic substrate, although it is still possible to perform sealing molding without any problem, it is a crystal having a diameter of 8 inches or more. Since the shrinkage stress of the epoxy resin or the like is large after the sealing of the round or large organic substrate, large warpage or cracking of the substrate occurs in the wafer or the organic substrate formed by the single surface, and the semiconductor device cannot be manufactured.

為了解決隨著晶圓或金屬基板的大型化而生之如上所述般的問題,需要將填料填充至95wt%程度, 或以樹脂的低彈性化來縮小硬化時之收縮應力。 In order to solve the problems as described above as the wafer or the metal substrate is enlarged, it is necessary to fill the filler to an extent of 95% by weight. Or the shrinkage stress at the time of hardening is reduced by the low elasticity of the resin.

[先前技術文獻] [Previous Technical Literature] [專利文獻] [Patent Literature]

[專利文獻1]日本特開2001-044324號公報 [Patent Document 1] Japanese Patent Laid-Open Publication No. 2001-044324

[專利文獻2]日本特開2003-213087號公報 [Patent Document 2] Japanese Patent Laid-Open Publication No. 2003-213087

[專利文獻3]日本特開2009-032842號公報 [Patent Document 3] Japanese Patent Laid-Open Publication No. 2009-032842

然而,將填料填充至95wt%程度來維持能夠充分成形的性能之熱硬化性樹脂目前尚無法製造。此外,若低彈性化至不發生翹曲的程度,則會發生耐熱性或耐濕性降低等的缺陷。 However, a thermosetting resin which fills the filler to an extent of about 95% by weight to maintain a sufficiently formed property is currently not manufactured. Further, if the elasticity is low to such an extent that warpage does not occur, defects such as deterioration in heat resistance and moisture resistance occur.

以樹脂密封搭載了複數個半導體元件的基板來形成密封層時,於存在不良的半導體元件之情況中,係將該不良元件排除後再進行密封。於此情況中,密封層之形成所需要的樹脂之量,會變得多於已排除之不良元件的體積量。因此,必須控制密封層之形成所需要的樹脂之體積。 When a substrate in which a plurality of semiconductor elements are mounted is sealed with a resin to form a sealing layer, in the case where a defective semiconductor element is present, the defective element is removed and then sealed. In this case, the amount of resin required for the formation of the sealing layer may become larger than the volume of the defective component that has been excluded. Therefore, it is necessary to control the volume of the resin required for the formation of the sealing layer.

但,如此地算出密封時每次所需要的樹脂量來調整填充量一事會非常煩雜,而產生增加步驟時間的問題,或填充量不足而發生在密封層形成空隙等之缺陷的問題。 However, it is very cumbersome to calculate the amount of resin required for each sealing during the sealing, and there is a problem that the step time is increased, or the filling amount is insufficient to cause defects such as voids in the sealing layer.

本發明係鑑於如前述般之問題而完成者,其目的為提供一種半導體裝置之製造方法,其係無須進行因應於以往因填料所導致的翹曲對策及密封層形成時的不良元件數目之樹脂填充量的調整,而減少繁雜的步驟,同時能夠製造減低翹曲,且耐熱性、耐濕性優異的半導體裝置。 The present invention has been made in view of the problems as described above, and an object of the invention is to provide a method for manufacturing a semiconductor device which does not require a resin which is resistant to warpage caused by a filler and a defective component during formation of a sealing layer. The adjustment of the filling amount reduces the complicated steps, and at the same time, it is possible to manufacture a semiconductor device which is excellent in heat resistance and moisture resistance while reducing warpage.

為了達成上述目的,依據本發明,提供一種半導體裝置之製造方法,其係使用具有上模具及下模具之成形模具來製造半導體裝置的方法,其特徵為具有:準備具有用以使半導體元件搭載基板、半導體元件非搭載基板、與形成於此等基板之間之由熱硬化性樹脂所構成的密封層一體化之第1空腔的前述成形模具之準備步驟;於前述半導體元件非搭載基板上,載置比前述密封層之形成所需要的量更多量的前述熱硬化性樹脂之樹脂載置步驟;將前述第1空腔內從室溫加熱至200℃,將前述半導體元件搭載基板配置於前述成形模具之前述上模具及前述下模具其中一方的模具,並將前述半導體元件非搭載基板配置於另一方的模具之配置步驟;將前述上模具及前述下模具進行加壓,而將多餘的前述熱硬化性樹脂排出至前述第1空腔的外部之樹脂排出步驟;一邊將前述上模具及前述下模具進行加壓一邊使前述熱硬化性樹脂成形,使前述半導體元件搭載基板、前述半導體元件非搭載基板、及前述密封層一體化之一體化步驟;以及將該一體化的基板從前述成 形模具取出,藉由切割予以單片化的步驟。 In order to achieve the above object, according to the present invention, there is provided a method of manufacturing a semiconductor device using a molding die having an upper mold and a lower mold to manufacture a semiconductor device, comprising: preparing a substrate for mounting a semiconductor element a preparation step of the molding die in which the semiconductor element is not mounted on the substrate, and the first cavity in which the sealing layer made of the thermosetting resin is integrated between the substrates; and the semiconductor element non-mounting substrate a resin mounting step of placing the thermosetting resin in an amount larger than the amount required for the formation of the sealing layer; heating the first cavity to room temperature from 200 ° C to 200 ° C to dispose the semiconductor element mounting substrate a step of disposing the semiconductor element non-mounting substrate in the other mold in the mold of the upper mold and the lower mold of the mold, and pressurizing the upper mold and the lower mold to remove excess a step of discharging the thermosetting resin to the outside of the first cavity; And a step of integrating the semiconductor element mounting substrate, the semiconductor element non-mounting substrate, and the sealing layer by molding the thermosetting resin while pressing the lower mold; and integrating the integrated substrate The aforementioned The step of taking out the mold and singulating it by cutting.

依據如此之半導體裝置之製造方法,即使於排除了不良的半導體元件之情況中,亦無須調整每次填充的樹脂量,可無發生空隙而確實地將基板與密封層予以一體化。此外,藉由預先將熱硬化性樹脂形成於半導體非搭載基板上,可減低步驟時之煩雜度,且可防止因使用粉體所造成之生產線的污染。進而,即使密封大型基板亦可抑制密封後之基板的翹曲或破裂,而能夠以晶圓級進行整體密封。 According to such a method of manufacturing a semiconductor device, even in the case where a defective semiconductor element is excluded, it is not necessary to adjust the amount of resin to be filled each time, and the substrate and the sealing layer can be surely integrated without voids. Further, by forming the thermosetting resin on the semiconductor non-mount substrate in advance, the trouble at the time of the step can be reduced, and contamination of the production line due to the use of the powder can be prevented. Further, even if the large substrate is sealed, warping or cracking of the substrate after sealing can be suppressed, and the entire sealing can be performed at the wafer level.

較佳為於前述準備步驟中,準備進一步具有透過澆道(runner)與前述第1空腔連結的第2空腔之前述成形模具,於前述樹脂排出步驟中,將前述多餘的前述熱硬化性樹脂排出至前述第2空腔。 Preferably, in the preparation step, the molding die further having a second cavity through which a runner is coupled to the first cavity is prepared, and the excess thermosetting property is obtained in the resin discharging step. The resin is discharged to the second cavity.

如此一來,可充滿第1空腔內部,同時容易將多餘的熱硬化性樹脂排出至第1空腔的外部。 In this way, the inside of the first cavity can be filled, and the excess thermosetting resin can be easily discharged to the outside of the first cavity.

較佳為於前述樹脂載置步驟中,以比前述密封層之形成所需要的量多0.1~70vol%的方式載置前述熱硬化性樹脂。 In the resin mounting step, the thermosetting resin is preferably placed in an amount of 0.1 to 70 vol% more than the amount required for the formation of the sealing layer.

如此一來,若以比需要的量多0.1vol%的方式載置,則可將第1空腔確實地充滿,若以多70vol%的方式載置,則可抑制多餘的熱硬化性樹脂增加而抑制成本的增加。 When the amount is more than 0.1 vol% more than the required amount, the first cavity can be surely filled, and if it is placed at 70 vol%, the excess thermosetting resin can be suppressed from increasing. And suppress the increase in cost.

較佳為於前述一體化步驟中,將前述第1空腔內或前述第2空腔內進行加壓,而使前述熱硬化性樹脂 成形。 Preferably, in the integration step, the thermosetting resin is pressed in the first cavity or in the second cavity. Forming.

如此一來,可減低密封層的空隙,而可提昇所製造的半導體裝置之性能。 In this way, the gap of the sealing layer can be reduced, and the performance of the manufactured semiconductor device can be improved.

此時,可藉由將空氣或惰性氣體壓入前述第2空腔,以進行前述第1空腔內之加壓。此時,可藉由外部泵或汽缸進行朝前述第2空腔之空氣或惰性氣體的壓入。 At this time, pressurization in the first cavity can be performed by pressing air or an inert gas into the second cavity. At this time, the pressurization of the air or the inert gas into the second cavity can be performed by an external pump or a cylinder.

如此一來,可容易地將第1空腔內進行加壓。 In this way, the inside of the first cavity can be easily pressurized.

亦可於前述配置步驟中,將前述第2空腔內的溫度加熱至比前述第1空腔內的溫度更高之溫度,於前述樹脂排出步驟中,使排出至前述第2空腔的前述多餘之熱硬化性樹脂比前述第1空腔內的前述熱硬化性樹脂更早硬化。此時,可將前述第2空腔內的溫度加熱至100~250℃之範圍內的溫度。 In the arranging step, the temperature in the second cavity may be heated to a temperature higher than a temperature in the first cavity, and the resin may be discharged to the second cavity in the resin discharging step. The excess thermosetting resin is hardened earlier than the thermosetting resin in the first cavity. At this time, the temperature in the second cavity can be heated to a temperature in the range of 100 to 250 °C.

如此一來,無關於第1及第2空腔的容積、所載置之熱硬化性樹脂的量,皆可確實地將第1空腔內密閉而將基板與密封層予以一體化。 In this way, regardless of the volume of the first and second cavities and the amount of the thermosetting resin placed thereon, the first cavity can be surely sealed and the substrate and the sealing layer can be integrated.

亦可於前述一體化步驟中,將前述第1空腔內的環境進行減壓,而使前述熱硬化性樹脂成形。此時,可將前述第1空腔內的環境進行減壓而成為真空度0.01333~13.33KPa。 In the integration step, the environment in the first cavity may be depressurized to form the thermosetting resin. At this time, the environment in the first cavity can be decompressed to have a vacuum of 0.01333 to 13.33 KPa.

如此一來,可更有效地減低密封層的空隙。 In this way, the void of the sealing layer can be more effectively reduced.

本發明之半導體裝置之製造方法,係能夠以壓縮成形進行前述熱硬化性樹脂之成形。 In the method for producing a semiconductor device of the present invention, the thermosetting resin can be formed by compression molding.

此外,可使用環氧樹脂、聚矽氧樹脂、及聚 矽氧/環氧混合(hybrid)樹脂中任一者作為前述熱硬化性樹脂。 In addition, epoxy resin, polyoxyl resin, and poly Any of the oxygen/epoxy hybrid resins is used as the thermosetting resin.

藉由使用如此之樹脂而可製造耐熱性、耐濕性優異的半導體裝置。 By using such a resin, a semiconductor device excellent in heat resistance and moisture resistance can be produced.

進而,提供藉由前述半導體裝置之製造方法所製造的半導體裝置。 Further, a semiconductor device manufactured by the above-described method of manufacturing a semiconductor device is provided.

如此之半導體裝置,係成為耐熱性、耐濕性優異,並且翹曲受到抑制之結果,殘留應變較少者。 Such a semiconductor device is excellent in heat resistance and moisture resistance, and warpage is suppressed, and residual strain is small.

於本發明之半導體裝置之製造方法中,由於在半導體元件非搭載基板上載置比密封層之形成所需要的量更多量的熱硬化性樹脂之後,於模具配置半導體元件搭載基板與半導體元件非搭載基板,將上模具及下模具進行加壓,而將多餘的熱硬化性樹脂排出至第1空腔的外部,因此即使於排除不良的半導體元件之情況中,亦無須進行因應於密封層形成時的不良元件數目之樹脂填充量的調整,可無發生空隙等而確實地將基板與密封層予以一體化,而可減少步驟的煩雜度或生產線的污染等。進而,由於使半導體元件搭載基板、半導體元件非搭載基板、與形成於此等基板之間之由熱硬化性樹脂所構成的密封層一體化,因此即使密封大型基板亦可抑制密封後之基板的翹曲或破裂,此外,亦能夠以晶圓級進行整體密封。 In the method of manufacturing a semiconductor device according to the present invention, after the thermosetting resin is placed on the semiconductor element non-mount substrate in an amount larger than the amount required for the formation of the sealing layer, the semiconductor element mounting substrate and the semiconductor element are disposed in the mold. By mounting the substrate and pressurizing the upper mold and the lower mold to discharge the excess thermosetting resin to the outside of the first cavity, even in the case of eliminating the defective semiconductor element, it is not necessary to form a sealing layer. When the resin filling amount of the number of defective components is adjusted, the substrate and the sealing layer can be surely integrated without voids, and the trouble of the steps or the contamination of the production line can be reduced. Further, since the semiconductor element mounting substrate, the semiconductor element non-mounting substrate, and the sealing layer made of a thermosetting resin between the substrates formed thereon are integrated, the sealing of the substrate can be suppressed even if the large substrate is sealed. Warping or cracking, in addition, it is also possible to seal the wafer at the wafer level.

1‧‧‧上模具 1‧‧‧Upper mold

2‧‧‧下模具 2‧‧‧ Lower mold

3‧‧‧成形模具 3‧‧‧Forming mould

4‧‧‧第1空腔 4‧‧‧1st cavity

5‧‧‧半導體元件搭載基板 5‧‧‧Semiconductor component mounting substrate

6‧‧‧半導體元件非搭載基板 6‧‧‧Semiconductor components are not mounted on the substrate

7‧‧‧半導體元件 7‧‧‧Semiconductor components

8‧‧‧熱硬化性樹脂 8‧‧‧ thermosetting resin

9‧‧‧第2空腔 9‧‧‧2nd cavity

10‧‧‧澆道(runner) 10‧‧‧Runner

11‧‧‧密封層 11‧‧‧ Sealing layer

12‧‧‧切割刀片(dicing blade) 12‧‧‧dicing blade

20‧‧‧半導體裝置 20‧‧‧Semiconductor device

[第1圖]係本發明之半導體裝置之製造方法的流程圖。 [Fig. 1] is a flow chart showing a method of manufacturing a semiconductor device of the present invention.

[第2圖]係顯示本發明之半導體裝置的概略圖。 [Fig. 2] A schematic view showing a semiconductor device of the present invention.

[第3圖]係顯示能夠在本發明之半導體裝置之製造方法中使用的模具之另一例子的圖。 [Fig. 3] Fig. 3 is a view showing another example of a mold which can be used in the method of manufacturing a semiconductor device of the present invention.

以下,雖針對本發明說明實施的形態,但本發明並不限定於此。 Hereinafter, the embodiment of the present invention will be described, but the present invention is not limited thereto.

如前述般,期望有一種半導體裝置之製造方法,其係於樹脂密封時,即使於排除不良的半導體元件之情況中,亦無須算出其每次所需要的樹脂量來調整填充量,而減少煩雜的步驟,同時可將基板與密封層予以一體化。 As described above, there is a need for a method of manufacturing a semiconductor device in which, in the case of resin sealing, even in the case of eliminating a defective semiconductor element, it is not necessary to calculate the amount of resin required each time to adjust the filling amount, thereby reducing cumbersomeness. The steps of the substrate and the sealing layer can be integrated at the same time.

本發明者們,為了達成上述課題屢經努力探討的結果發現以下的見解,因而完成本發明。亦即,在半導體元件非搭載基板上載置比密封層之形成所需要的量更多量的熱硬化性樹脂之後,於模具配置半導體元件搭載基板與半導體元件非搭載基板,將上模具及下模具進行加壓而使多餘的熱硬化性樹脂排出至第1空腔的外部,如此一來則無須進行上述之樹脂的填充量之調整,而減少煩雜的步驟,同時可將基板與密封層確實地一體化。 The present inventors have found the following findings as a result of repeated efforts to achieve the above problems, and have completed the present invention. In other words, after the thermosetting resin having a larger amount than that required for the formation of the sealing layer is placed on the semiconductor element non-mounting substrate, the semiconductor element mounting substrate and the semiconductor element non-mounting substrate are placed on the mold, and the upper mold and the lower mold are placed. By pressurizing and discharging the excess thermosetting resin to the outside of the first cavity, it is not necessary to adjust the filling amount of the resin described above, and the troublesome steps can be reduced, and the substrate and the sealing layer can be surely Integration.

首先,針對藉由本發明之半導體裝置之製造 方法所製造的本發明之半導體裝置進行說明。 First, for the manufacture of a semiconductor device by the present invention The semiconductor device of the present invention produced by the method will be described.

如第2圖所示般,本發明之半導體裝置20,主要由半導體元件7、半導體元件搭載基板5、半導體元件非搭載基板6、及由熱硬化性樹脂所成之密封層11所構成。半導體元件7係搭載於半導體元件搭載基板5上。用以密封此半導體元件7的密封層11,係形成在半導體元件搭載基板5、與半導體元件非搭載基板6之間。半導體裝置20的厚度雖依存於內建之半導體元件7的厚度,但就將半導體裝置安裝於家電等時能夠小型化的觀點而言,以1mm以下較為理想。 As shown in FIG. 2, the semiconductor device 20 of the present invention mainly comprises a semiconductor element 7, a semiconductor element mounting substrate 5, a semiconductor element non-mounting substrate 6, and a sealing layer 11 made of a thermosetting resin. The semiconductor element 7 is mounted on the semiconductor element mounting substrate 5. The sealing layer 11 for sealing the semiconductor element 7 is formed between the semiconductor element mounting substrate 5 and the semiconductor element non-mounting substrate 6. Though the thickness of the semiconductor device 20 depends on the thickness of the built-in semiconductor element 7, it is preferable that the semiconductor device is 1 mm or less from the viewpoint of being able to be downsized when the semiconductor device is mounted on a home appliance or the like.

本發明之半導體裝置,係藉由以下所詳細說明的本發明之半導體裝置之製造方法而製造者。第1圖顯示本發明之半導體裝置之製造方法的流程圖。 The semiconductor device of the present invention is manufactured by the method of manufacturing a semiconductor device of the present invention described in detail below. Fig. 1 is a flow chart showing a method of manufacturing a semiconductor device of the present invention.

[(A)準備步驟] [(A) Preparation Steps]

於準備步驟中,係準備具有用以使半導體元件搭載基板、半導體元件非搭載基板、與形成於此等基板之間之由熱硬化性樹脂所構成的密封層一體化之第1空腔4的成形模具3。成形模具3係由上模具1及下模具2所構成。 In the preparation step, the first cavity 4 having the semiconductor element mounting substrate, the semiconductor element non-mounting substrate, and the sealing layer made of a thermosetting resin formed between the substrates is prepared. Forming the mold 3. The molding die 3 is composed of an upper die 1 and a lower die 2.

此成形模具,亦可為具備如同使用於壓縮成形般之能夠在空腔部分活動的結構者。 The forming mold may also have a structure capable of moving in the cavity portion as used for compression molding.

第1空腔4的尺寸、形狀並無特別限定,可因應所製造的半導體裝置而適當構成。第1空腔4,係可形成於上模具1或下模具2中任一者,亦可形成於兩者。 The size and shape of the first cavity 4 are not particularly limited, and may be appropriately configured in accordance with the semiconductor device to be manufactured. The first cavity 4 may be formed in either the upper mold 1 or the lower mold 2, or may be formed in both.

在此所準備的成形模具3,係可設為進一步具有透過澆道10與第1空腔4連結的第2空腔9者。 The molding die 3 prepared here may be further provided with a second cavity 9 that is connected to the first cavity 4 through the runner 10.

[(B)樹脂載置步驟] [(B) Resin mounting step]

於樹脂載置步驟中,係於半導體元件非搭載基板6上,載置比密封層11之形成所需要的量更多量的熱硬化性樹脂8。 In the resin mounting step, the thermosetting resin 8 is placed on the semiconductor element non-mount substrate 6 in an amount larger than the amount required for the formation of the sealing layer 11.

若如此地載置熱硬化性樹脂8,則即使在將一部分不良的半導體元件從半導體元件搭載基板5排除的情況中,亦無須如以往進行之方式般的因應所排除之半導體元件的個數來算出需要的熱硬化性樹脂之量以調整填充量。此外,可排除將熱硬化性樹脂從外部填充至第1空腔4內之煩雜的步驟。 When the thermosetting resin 8 is placed in this manner, even when a part of defective semiconductor elements are removed from the semiconductor element mounting substrate 5, there is no need to reduce the number of semiconductor elements to be excluded as in the conventional method. The amount of the thermosetting resin required was calculated to adjust the filling amount. Further, the troublesome step of filling the thermosetting resin into the first cavity 4 from the outside can be eliminated.

在此,密封層之形成所需要的樹脂之量,例如,可設為在半導體元件搭載基板5上並無搭載半導體元件時所需要的量。如此一來,無關於不良的半導體元件之個數,皆不形成未填充空隙部而可確實地形成密封層。 Here, the amount of the resin required for the formation of the sealing layer can be, for example, an amount required when the semiconductor element is not mounted on the semiconductor element mounting substrate 5. In this way, the number of defective semiconductor elements is not formed, and the unfilled void portion is not formed, and the sealing layer can be reliably formed.

熱硬化性樹脂8,較佳為以比密封層之形成所需要的量多0.1~70vol%的方式載置。 The thermosetting resin 8 is preferably placed in an amount of 0.1 to 70 vol% more than the amount required for the formation of the sealing layer.

如此一來,若以比需要的量多0.1vol%的方式載置,則可將第1空腔內部確實地充滿,若以多70vol%以下的方式填充,則可抑制多餘的熱硬化性樹脂增加而抑制成本的增加。 In this way, when the amount is more than 0.1 vol% more than the required amount, the inside of the first cavity can be surely filled, and if it is filled at 70 vol% or less, the excess thermosetting resin can be suppressed. Increase and suppress the increase in cost.

[(C)配置步驟] [(C) Configuration Steps]

於配置步驟中,係將第1空腔內從室溫加熱至200℃,將半導體元件搭載基板5配置於成形模具3之上模具1及下模具2其中一方的模具,並將在上述樹脂載置步驟載置有熱硬化性樹脂8的半導體元件非搭載基板6配置於另一方的模具。配置方法,雖無特別限制,但可藉由以吸引方式等將基板吸附於經加熱之上模具1及下模具2的表面而進行。 In the disposing step, the first cavity is heated from room temperature to 200° C., and the semiconductor element mounting substrate 5 is placed on one of the mold 1 and the lower mold 2 of the molding die 3, and the resin is loaded on the resin. The semiconductor element non-mount substrate 6 on which the thermosetting resin 8 is placed is placed in the other mold. Although the arrangement method is not particularly limited, it can be carried out by suctioning the substrate onto the surfaces of the upper mold 1 and the lower mold 2 by suction.

在此,將半導體元件搭載基板5及半導體元件非搭載基板6配置於哪一模具並無特別限定。第1圖(C)係顯示將半導體元件搭載基板5配置於上模具1的例子。 Here, the mold in which the semiconductor element mounting substrate 5 and the semiconductor element non-mounting substrate 6 are disposed is not particularly limited. FIG. 1(C) shows an example in which the semiconductor element mounting substrate 5 is placed on the upper mold 1.

半導體元件搭載基板5及/或半導體元件非搭載基板6,例如,可設為矩形狀的基板或圓盤狀的晶圓,且可使用無機基板、金屬基板、或有機樹脂基板。半導體元件搭載基板5,係於如此之基板載置或形成有半導體元件7者,半導體元件非搭載基板6,係未載置或形成有半導體元件者。尤其,於使用有機樹脂基板的情況中,就控制後述之膨脹係數的觀點而言,亦可使用含有纖維的有機樹脂基板。 The semiconductor element mounting substrate 5 and/or the semiconductor element non-mounting substrate 6 can be, for example, a rectangular substrate or a disk-shaped wafer, and an inorganic substrate, a metal substrate, or an organic resin substrate can be used. The semiconductor element mounting substrate 5 is one in which the semiconductor element 7 is placed or formed on the substrate, and the semiconductor element is not mounted on the substrate 6, and the semiconductor element is not placed or formed. In particular, in the case of using an organic resin substrate, an organic resin substrate containing fibers may be used from the viewpoint of controlling the expansion coefficient described later.

無機基板,係以陶瓷基板、矽晶圓等為代表者,金屬基板,係以表面經絕緣處理的銅或鋁基板等為代表者。有機樹脂基板,係可列舉:BT(雙馬來醯亞胺三嗪)樹脂基板、玻璃環氧基板、FRP(纖維強化塑膠)基板等。 The inorganic substrate is represented by a ceramic substrate, a tantalum wafer, or the like, and the metal substrate is represented by a copper or aluminum substrate having an insulating surface. Examples of the organic resin substrate include a BT (bismaleimide triazine) resin substrate, a glass epoxy substrate, and an FRP (fiber reinforced plastic) substrate.

可適用於含有纖維的有機樹脂基板之纖維,係可列舉:碳纖維、玻璃纖維、石英玻璃纖維、金屬纖維等之無機纖維、芳香族聚醯胺纖維、聚醯亞胺纖維、聚醯胺醯亞胺醯纖維等之有機纖維、進而碳化矽纖維、碳化鈦纖維、硼纖維、氧化鋁纖維等。含有纖維的有機樹脂基板,係可列舉:經此等之纖維補強的環氧樹脂、BT樹脂或聚矽氧樹脂基板。因應製品特性,此種基板以外,只要能夠維持絕緣性,則可使用任何者。最佳之含有纖維的有機樹脂基板,係以經玻璃纖維、石英纖維、碳纖維等補強者較為理想。其中較佳者為使用絕緣性高的玻璃纖維或石英玻璃纖維者。 The fibers which can be applied to the fiber-containing organic resin substrate include inorganic fibers such as carbon fibers, glass fibers, quartz glass fibers, and metal fibers, aromatic polyamide fibers, polyimine fibers, and polyamidoximines. An organic fiber such as an amidoxime fiber, further a tantalum carbide fiber, a titanium carbide fiber, a boron fiber, or an alumina fiber. Examples of the fiber-containing organic resin substrate include a fiber-reinforced epoxy resin, a BT resin, or a polyoxymethylene resin substrate. Any of such substrates can be used as long as the insulating properties can be maintained in accordance with the characteristics of the product. The most preferable organic resin substrate containing fibers is preferably a fiberglass, quartz fiber, carbon fiber or the like. Among them, those which are preferably made of glass fiber or quartz glass fiber having high insulation properties are preferred.

如上述般之補強用纖維的形態,係只要是將長纖維絲在特定方向拉齊的粗紗、布帛、不織布等之薄片狀者,進而切股氈(chopped strand mat)等可形成層合體者即無特別限制。 The form of the reinforcing fiber as described above is a sheet such as a roving, a cloth, or a non-woven fabric in which the long fiber yarn is drawn in a specific direction, and a laminated body such as a chopped strand mat can be formed. There are no special restrictions.

於金屬基板、無機基板、或有機樹脂基板中,任何基板的情況中,其厚度較佳均為20μm~1mm,更佳為30μm~500μm,再更佳為30μm~200μm。若為20μm以上則可防止因過薄所導致的變形,尤其在使用無機基板的情況中,可抑制操作時的破裂。此外,若為1mm以下則可防止半導體裝置變厚。 In the case of any of the metal substrate, the inorganic substrate, or the organic resin substrate, the thickness thereof is preferably 20 μm to 1 mm, more preferably 30 μm to 500 μm, still more preferably 30 μm to 200 μm. When it is 20 μm or more, deformation due to excessively thin can be prevented, and particularly in the case of using an inorganic substrate, cracking during handling can be suppressed. Further, if it is 1 mm or less, it is possible to prevent the semiconductor device from becoming thick.

半導體元件搭載基板與半導體元件非搭載基板,較佳係具有類似的物理特性者,尤其,以使用兩基板之線膨脹係數實質上彼此同等或25ppm/℃以下,特別是 15ppm/℃以下者更佳。尤其,若兩基板間之物理特性類似則可更加抑制以熱硬化性樹脂8成形密封之後的半導體裝置之翹曲的發生。 The semiconductor element mounting substrate and the semiconductor element non-mounting substrate preferably have similar physical properties, and in particular, the linear expansion coefficients of the two substrates are substantially equal to each other or 25 ppm/° C. or less, in particular It is better to be 15 ppm/°C or less. In particular, if the physical properties between the two substrates are similar, the occurrence of warpage of the semiconductor device after the thermosetting resin 8 is formed and sealed can be further suppressed.

此外,使用有機樹脂基板作為半導體元件搭載基板及半導體元件非搭載基板的情況中,其至少一方的有機樹脂基板,較佳為兩者之有機樹脂基板,係於室溫~200℃之線膨脹係數為3~25ppm/℃的有機樹脂基板,此基板係就所製造的半導體裝置之翹曲的減低之觀點而言較為理想。另外,於本發明中,室溫係意味著25℃±10℃(以下,相同)。 In the case where the organic resin substrate is used as the semiconductor element mounting substrate and the semiconductor element non-mounting substrate, at least one of the organic resin substrates is preferably an organic resin substrate of both, which is a linear expansion coefficient at room temperature to 200 ° C. The organic resin substrate of 3 to 25 ppm/° C. is preferable in terms of the reduction in warpage of the manufactured semiconductor device. Further, in the present invention, room temperature means 25 ° C ± 10 ° C (hereinafter, the same).

進而,使用矽晶圓等之無機基板或有機樹脂基板作為半導體元件搭載基板的情況中,搭載有該半導體元件的無機基板或有機樹脂基板之線膨脹係數,係以於室溫~200℃中在X-Y方向為3~15ppm/℃較為理想。 In the case where an inorganic substrate or an organic resin substrate such as a ruthenium wafer is used as the semiconductor element mounting substrate, the linear expansion coefficient of the inorganic substrate or the organic resin substrate on which the semiconductor element is mounted is at room temperature to 200 ° C. The XY direction is preferably 3 to 15 ppm/°C.

此外,使用有機樹脂基板作為半導體元件非搭載基板的情況中,該有機樹脂基板之線膨脹係數,係以於室溫~200℃中在X-Y方向為5~25ppm/℃較為理想。若為如此之範圍的有機樹脂基板,則與半導體元件搭載基板之線膨脹係數的差小,而可更加抑制所製造的半導體裝置之翹曲。另外,有機樹脂基板之膨脹係數,更理想為5~20ppm/℃,再更理想為5~15ppm/℃。 Further, when an organic resin substrate is used as the semiconductor element non-mounting substrate, the linear expansion coefficient of the organic resin substrate is preferably 5 to 25 ppm/° C in the X-Y direction at room temperature to 200 °C. When the organic resin substrate is in such a range, the difference in linear expansion coefficient from the semiconductor element mounting substrate is small, and warpage of the manufactured semiconductor device can be further suppressed. Further, the expansion coefficient of the organic resin substrate is more preferably 5 to 20 ppm/° C., still more preferably 5 to 15 ppm/° C.

就生產性或操作容易度的觀點而言,上述基板的尺寸為縱20~500mm,橫為100~500mm左右者較為理想。此外,就生產性或操作容易度的觀點而言,圓形狀的 基板係直徑為50~400mm左右者較為理想。若為如此之基板,則容易將半導體元件配置於基板上,或以打線接合(Wire bonding)連接金線等。 From the viewpoint of productivity or ease of handling, the size of the substrate is preferably 20 to 500 mm in length and 100 to 500 mm in width. In addition, in terms of productivity or ease of operation, a circular shape It is preferable that the substrate system has a diameter of about 50 to 400 mm. In the case of such a substrate, it is easy to arrange the semiconductor element on the substrate, or to connect a gold wire or the like by wire bonding.

[(D)樹脂排出步驟] [(D) Resin discharge step]

於樹脂排出步驟中,係將上模具1及下模具2進行加壓,而將多餘的熱硬化性樹脂8排出至第1空腔4的外部。 In the resin discharge step, the upper mold 1 and the lower mold 2 are pressurized, and the excess thermosetting resin 8 is discharged to the outside of the first cavity 4.

如第1圖所示般,例如,可於上述準備步驟(A)中,準備進一步具有上述之第2空腔9的成形模具3,於樹脂排出步驟(D)中,將多餘的熱硬化性樹脂8排出至第2空腔9。 As shown in Fig. 1, for example, in the preparation step (A), the molding die 3 further having the second cavity 9 described above can be prepared, and in the resin discharging step (D), excess thermosetting property is obtained. The resin 8 is discharged to the second cavity 9.

第2空腔9及澆道10的尺寸、形狀並無特別限定,可因應所使用之成形模具的尺寸、形狀或所填充之熱硬化性樹脂的量而適當構成。此外,第2空腔9,係可形成於上模具1或下模具2中任一者,亦可形成於兩者。 The size and shape of the second cavity 9 and the runner 10 are not particularly limited, and may be appropriately configured depending on the size and shape of the molding die to be used or the amount of the thermosetting resin to be filled. Further, the second cavity 9 may be formed in either the upper mold 1 or the lower mold 2, or may be formed in both.

例如,可構成為:第1空腔4與第2空腔9的容量之合計大於在樹脂載置步驟(B)中載置的熱硬化性樹脂8之體積。如此一來,可避免多餘的熱硬化性樹脂8從成形模具溢出,或進一步避免形成毛邊(burr)的情況。 For example, the total capacity of the first cavity 4 and the second cavity 9 may be larger than the volume of the thermosetting resin 8 placed in the resin mounting step (B). In this way, it is possible to prevent the excess thermosetting resin 8 from overflowing from the forming mold or to further avoid the formation of a burr.

於此情況中,在後續步驟之一體化步驟中,為了在熱硬化性樹脂成形時使第1空腔4內確實地成為密閉狀態,例如,可於上述之配置步驟(C)中,將第2空腔9內的 溫度加熱至比第1空腔4內的溫度更高的溫度,於樹脂排出步驟(D)中,使排出至第2空腔9後之多餘的熱硬化性樹脂比第1空腔4內的熱硬化性樹脂更早硬化。在此,可將第2空腔9內的溫度加熱至100~250℃之範圍內的溫度。 In this case, in the integration step of the subsequent step, in order to reliably seal the inside of the first cavity 4 during the thermosetting resin molding, for example, in the above-described arrangement step (C), 2 in the cavity 9 The temperature is heated to a temperature higher than the temperature in the first cavity 4, and in the resin discharge step (D), the excess thermosetting resin discharged to the second cavity 9 is made larger than that in the first cavity 4. The thermosetting resin hardens earlier. Here, the temperature in the second cavity 9 can be heated to a temperature in the range of 100 to 250 °C.

或者,亦可如後述般,一邊將第1空腔4內或第2空腔9內進行加壓一邊使熱硬化性樹脂成形。 Alternatively, the thermosetting resin may be molded while pressurizing the inside of the first cavity 4 or the second cavity 9 as will be described later.

[(E)一體化步驟] [(E) Integration Step]

於一體化步驟中,係一邊將上模具1及下模具2進行加壓一邊使熱硬化性樹脂8成形,使半導體元件搭載基板5、半導體元件非搭載基板6、及密封層11一體化。如此一來,藉由使用2片基板作為半導體元件的表背面,並以熱硬化性樹脂將此等基板之間進行成形密封,而可製造幾乎無翹曲發生,且耐熱性、耐濕性優異的半導體裝置。經一體化的半導體元件搭載基板及半導體元件非搭載基板的間隔,亦即密封層11的高度,較佳為20~1000μm。 In the integration step, the thermosetting resin 8 is molded while the upper mold 1 and the lower mold 2 are pressurized, and the semiconductor element mounting substrate 5, the semiconductor element non-mounting substrate 6, and the sealing layer 11 are integrated. In this way, by using two substrates as the front and back surfaces of the semiconductor element and molding and sealing the substrates together with a thermosetting resin, it is possible to produce almost no warpage, and it is excellent in heat resistance and moisture resistance. Semiconductor device. The height of the sealing layer 11 which is the interval between the integrated semiconductor element mounting substrate and the semiconductor element non-mounting substrate is preferably 20 to 1000 μm.

於一體化步驟中,係可利用通常使用的壓縮成形。具體而言,於一體化步驟中,可在室溫下或加熱下將上模具與下模具進行加壓,來將載置於半導體元件非搭載基板6上的熱硬化性樹脂8進行壓縮成形。於此情況中,在上述樹脂排出步驟(D)中,將經加熱的上下模具在加壓下進行模具夾緊(mold clamping),將多餘的熱硬化性樹脂8排出至第1空腔4的外部,在此狀態下使熱硬 化性樹脂8熱硬化。 In the integration step, compression molding which is generally used can be utilized. Specifically, in the integration step, the upper mold and the lower mold can be pressurized at room temperature or under heating to compress-form the thermosetting resin 8 placed on the semiconductor element non-mounting substrate 6. In this case, in the resin discharge step (D), the heated upper and lower molds are subjected to mold clamping under pressure, and the excess thermosetting resin 8 is discharged to the first cavity 4. External, making hot hard in this state The resin 8 is thermally hardened.

於一體化步驟中,係可將第1空腔4內或第2空腔9內進行加壓而將熱硬化性樹脂成形。如此一來,可提昇對間隙的填充性,而可減低密封層11之空隙的發生。 In the integration step, the thermosetting resin can be molded by pressurizing the inside of the first cavity 4 or the second cavity 9. In this way, the filling of the gap can be improved, and the occurrence of the gap of the sealing layer 11 can be reduced.

具體的方法,係可藉由使用例如外部泵或汽缸,來將空氣或惰性氣體壓入第2空腔中,而將第1空腔內進行加壓。 In a specific method, air or an inert gas can be pressed into the second cavity by using, for example, an external pump or a cylinder, and the inside of the first cavity can be pressurized.

或者,由於提昇對間隙之填充性,因此亦可將第1空腔內的環境進行減壓,而使熱硬化性樹脂8成形。減壓度係以盡可能地減壓至接近真空的程度者較佳。例如,可將真空度設為0.01333~13.33KPa(0.1~100Torr)。 Alternatively, since the filling property to the gap is improved, the environment in the first cavity can be depressurized, and the thermosetting resin 8 can be molded. The degree of decompression is preferably as low as possible to a degree close to vacuum. For example, the degree of vacuum can be set to 0.01333 to 13.33 KPa (0.1 to 100 Torr).

一體化步驟所使用的熱硬化性樹脂8,亦可作為包含其他成分之組成物的形態。熱硬化性樹脂,通常適合使用在100℃以下之加熱下進行液狀化的固體之環氧樹脂、聚矽氧樹脂、或者由環氧樹脂與聚矽氧樹脂所構成的聚矽氧/環氧混合樹脂。若使用在加熱下進行液狀化的固體之熱硬化性樹脂,則可避免使用粉體之熱硬化性樹脂時所發生的生產線之污染。 The thermosetting resin 8 used in the integration step may also be in the form of a composition containing other components. The thermosetting resin is generally suitably used as a solid epoxy resin, a polyoxyxylene resin, or a polysiloxane/epoxy resin composed of an epoxy resin and a polyoxyxylene resin, which is liquidified under heating at 100 ° C or lower. Mixed resin. When a solid thermosetting resin which is liquidified under heating is used, contamination of the production line which occurs when a powdery thermosetting resin is used can be avoided.

此環氧樹脂的例子,係可使用如同雙酚A型環氧樹脂、雙酚F型環氧樹脂、3,3’,5,5’-四甲基-4,4’-聯苯酚型環氧樹脂或4,4’-聯苯酚型環氧樹脂般之聯苯酚型環氧樹脂、酚酚醛清漆型環氧樹脂、甲酚酚醛清漆型環氧 樹脂、雙酚A酚醛清漆型環氧樹脂、萘二酚型環氧樹脂、參苯酚基甲烷型環氧樹脂、肆苯酚基乙烷型環氧樹脂、及酚二環戊二烯酚醛清漆型環氧樹脂之將芳香環氫化的環氧樹脂、脂環式環氧樹脂等在室溫為液狀或固體之周知的環氧樹脂。此外,可因應需要,而將上述以外之環氧樹脂在一定量以下進行併用。 As an example of the epoxy resin, a bisphenol A type epoxy resin, a bisphenol F type epoxy resin, a 3,3', 5,5'-tetramethyl-4,4'-biphenol type ring can be used. Oxygen resin or 4,4'-biphenol type epoxy resin biphenol type epoxy resin, phenol novolak type epoxy resin, cresol novolac type epoxy Resin, bisphenol A novolac type epoxy resin, naphthalene diphenol type epoxy resin, phenol-based methane type epoxy resin, decyl phenol ethane type epoxy resin, and phenol dicyclopentadiene novolac type ring An epoxy resin which is a liquid or solid at room temperature, such as an aromatic ring hydrogenated epoxy resin or an alicyclic epoxy resin. Further, the epoxy resin other than the above may be used in combination of a certain amount or less as needed.

另外,就密封半導體元件來看,熱硬化性樹脂中之氯等之鹵素離子,或鈉等之鹼離子,係極力減少者為佳。通常,較理想為在離子交換水50ml中添加試樣10g,進行密封,並於120℃的烘箱中靜置20小時之後,在進行加熱萃取之120℃的萃取下任一離子皆為10ppm以下。 In addition, in the case of sealing the semiconductor element, it is preferable that the halogen ion such as chlorine or the alkali ion such as sodium in the thermosetting resin is extremely reduced. In general, it is preferred to add 10 g of a sample to 50 ml of ion-exchanged water, seal it, and let it stand in an oven at 120 ° C for 20 hours, and then use any of the ions at a temperature of 120 ° C for heating extraction to be 10 ppm or less.

上述環氧樹脂之硬化劑,係可使用使酚酚醛清漆樹脂、各種胺衍生物、酸酐或酸酐基一部分開環而生成羧酸者等。其中,為了確保半導體裝置之可靠性,較理想為酚酚醛清漆樹脂。 As the curing agent for the epoxy resin, a phenol novolac resin, a variety of amine derivatives, an acid anhydride or an acid anhydride group may be partially opened to form a carboxylic acid. Among them, in order to secure the reliability of the semiconductor device, a phenol novolak resin is preferable.

為了促進上述環氧樹脂與硬化劑之反應,亦可使用咪唑衍生物、膦衍生物、胺衍生物、有機鋁化合物等之金屬化合物等。例如,環氧樹脂與酚酚醛清漆樹脂之混合比,較佳為以使環氧基與酚性羥基的比率成為1:0.8~1.3的方式進行混合。 In order to promote the reaction between the epoxy resin and the curing agent, a metal compound such as an imidazole derivative, a phosphine derivative, an amine derivative or an organoaluminum compound may be used. For example, the mixing ratio of the epoxy resin to the phenol novolak resin is preferably such that the ratio of the epoxy group to the phenolic hydroxyl group is 1:0.8 to 1.3.

其他,可進一步因應需要,於環氧樹脂組成物中摻合各種添加劑。例如,可添加摻合各種的熱塑性樹脂、熱塑性彈性體、有機合成橡膠、聚矽氧系等之低應力 劑、蠟類、鹵捕捉劑(halogen trapping agent)等之添加劑,以改善樹脂之性質。 In addition, various additives may be blended in the epoxy resin composition as needed. For example, low stress can be added by blending various thermoplastic resins, thermoplastic elastomers, organic synthetic rubbers, polyfluorene oxides, and the like. Additives such as agents, waxes, halogen trapping agents, etc., to improve the properties of the resin.

此外,上述聚矽氧樹脂,係能夠使用縮合性或熱硬化性的聚矽氧樹脂等。其中,較理想為加成硬化型聚矽氧樹脂之組成物。加成硬化型聚矽氧樹脂組成物,係適合使用將(A)具有非共軛性雙鍵基(例如,乙烯基等之烯基)之有機聚矽氧烷、(B)有機氫聚矽氧烷、及(C)鉑系觸媒作為必須成分之加成硬化型聚矽氧樹脂組成物。 Further, as the polyfluorene oxide resin, a condensed or thermosetting polyoxyxylene resin or the like can be used. Among them, a composition of an addition hardening type polyoxyxylene resin is preferable. The addition-hardening type polyoxymethylene resin composition is preferably an organic polyoxyalkylene having (A) a non-conjugated double bond group (for example, an alkenyl group such as a vinyl group) or (B) an organic hydrogen polycondensate. An addition-type polyoxyxylene resin composition containing an oxane and a (C) platinum-based catalyst as essential components.

進而,上述聚矽氧/環氧混合樹脂,係可列舉:由前述環氧樹脂與前述聚矽氧樹脂所構成的共聚物等。 Further, the polyfluorene/epoxy hybrid resin may be a copolymer composed of the above epoxy resin and the polyfluorene oxide resin.

上述,可於能夠作為熱硬化性樹脂使用的環氧樹脂、聚矽氧樹脂、聚矽氧/環氧混合樹脂之組成物中,摻合無機填充材。所摻合的無機填充材,係可列舉例如:熔融二氧化矽、結晶性二氧化矽等之二氧化矽類、氧化鋁、氮化矽、氮化鋁、鋁矽酸鹽(aluminosilicate)、氮化硼(boron nitride)、玻璃纖維、三氧化二銻等。此等無機填充材的平均粒徑或形狀雖無特別限定,但為了確保對大型基板間之間隙為1mm以下的狹窄部之填充性,最大粒徑以75μm以下,較理想為50μm以下為佳。尤其,基板間為500μm以下時,係以最大30μm以下,且形狀為球狀的粒子為適合。若使用75μm以下之填充材,則局部的流動性之降低會受到抑制,可確保充分的填充性, 而抑制空隙或未填充。 As described above, the inorganic filler can be blended in the composition of the epoxy resin, the polyoxynoxy resin, and the polyoxynoxy/epoxy hybrid resin which can be used as the thermosetting resin. Examples of the inorganic filler to be blended include cerium oxide such as molten cerium oxide and crystalline cerium oxide, alumina, tantalum nitride, aluminum nitride, aluminosilicate, and nitrogen. Boron nitride, glass fiber, antimony trioxide, and the like. The average particle diameter or shape of the inorganic filler is not particularly limited. However, in order to ensure the filling property of the narrow portion having a gap of 1 mm or less between the large substrates, the maximum particle diameter is preferably 75 μm or less, and more preferably 50 μm or less. In particular, when the distance between the substrates is 500 μm or less, particles having a maximum of 30 μm or less and having a spherical shape are suitable. When a filler of 75 μm or less is used, the reduction in local fluidity is suppressed, and sufficient filling property can be ensured. The gap is suppressed or not filled.

尤其,添加於環氧樹脂組成物中之上述無機填充材,亦可為了增強環氧樹脂與無機填充材的結合強度,而摻合預先以矽烷偶合劑、鈦酸酯偶合劑等的偶合劑加以表面處理者。 In particular, the inorganic filler added to the epoxy resin composition may be blended with a coupling agent such as a decane coupling agent or a titanate coupling agent in order to enhance the bonding strength between the epoxy resin and the inorganic filler. Surface processor.

如此之偶合劑,較佳為使用例如:γ-環氧丙氧基丙基三甲氧基矽烷、γ-環氧丙氧基丙基甲基二乙氧基矽烷、β-(3,4-環氧環己基)乙基三甲氧基矽烷等之環氧官能性烷氧基矽烷、N-β(胺基乙基)-γ-胺基丙基三甲氧基矽烷、γ-胺基丙基三乙氧基矽烷、N-苯基-γ-胺基丙基三甲氧基矽烷等之胺基官能性烷氧基矽烷;γ-巰基丙基三甲氧基矽烷等之巰基官能性烷氧基矽烷等。另外,針對表面處理所使用的偶合劑之摻合量及表面處理方法並無特別限制。 As such a coupling agent, for example, γ-glycidoxypropyltrimethoxydecane, γ-glycidoxypropylmethyldiethoxydecane, β-(3,4-ring) is preferably used. Epoxy-functional alkoxydecane such as oxycyclohexyl)ethyltrimethoxydecane, N-β(aminoethyl)-γ-aminopropyltrimethoxydecane, γ-aminopropyltriethyl An amino functional alkoxy decane such as oxy decane or N-phenyl-γ-aminopropyltrimethoxy decane; or a fluorenyl functional alkoxy decane such as γ-mercaptopropyltrimethoxydecane. Further, the blending amount and surface treatment method of the coupling agent used for the surface treatment are not particularly limited.

於聚矽氧樹脂組成物或聚矽氧/環氧混合樹脂組成物的情況中,亦可以如上述般之偶合材來處理無機質填充材表面。 In the case of a polyoxyxylene resin composition or a polyoxyxene/epoxy hybrid resin composition, the surface of the inorganic filler may also be treated as described above.

無機填充材的填充量,相對於環氧樹脂組成物或聚矽氧樹脂、聚矽氧/環氧混合樹脂之組成物中的樹脂之總量100質量份,以20~1300質量份,特別是以50~1000質量份為佳。若為20質量份以上,則可得到充分的強度,若為1300質量份以下,則不易產生因增黏所導致的流動性之降低,且可防止填充性的不良,而可將排列於基板上的半導體元件完全密封。另外,此無機填充 材,係以組成物全體的15~95質量%,特別是以30~90質量%之範圍含有為佳。 The filling amount of the inorganic filler is 20 to 1300 parts by mass, based on 100 parts by mass of the total amount of the resin in the composition of the epoxy resin composition or the polyoxynoxy resin/polyoxymethylene/epoxy mixed resin, in particular It is preferably 50 to 1000 parts by mass. When the amount is 20 parts by mass or more, sufficient strength can be obtained, and if it is 1300 parts by mass or less, the fluidity due to thickening is less likely to occur, and the filling property can be prevented, and the substrate can be arranged on the substrate. The semiconductor components are completely sealed. In addition, this inorganic fill The material is preferably contained in the range of 15 to 95% by mass, particularly in the range of 30 to 90% by mass.

[(F)切割步驟] [(F) cutting step]

藉由上述步驟,可不發生空隙或翹曲地進行搭載有半導體元件之大型基板的密封。將以上述方法一體化後的基板從成形模具取出,通常,可藉由以150~180℃的溫度進行後硬化1~4小時,使電特性或機械特性安定化。 According to the above steps, the sealing of the large substrate on which the semiconductor element is mounted can be performed without voids or warping. The substrate integrated by the above method is taken out from the molding die, and usually, it can be post-hardened at a temperature of 150 to 180 ° C for 1 to 4 hours to stabilize the electrical properties or mechanical properties.

進而,後硬化後可藉由以通常的方法使用切割刀片12將基板切割並予以單片化,而製造半導體裝置20。 Further, after the post-hardening, the semiconductor device 20 can be manufactured by dicing and dicing the substrate using the dicing blade 12 in a usual manner.

藉由上述半導體裝置之製造方法所製造的半導體裝置20,係成為翹曲會受到抑制且殘留應變少的高品質者,且成為耐熱性、耐濕性優異者。 The semiconductor device 20 manufactured by the method for manufacturing a semiconductor device described above has a high quality in which the warpage is suppressed and the residual strain is small, and the heat resistance and the moisture resistance are excellent.

[實施例] [Examples]

以下,雖顯示本發明之實施例及比較例來更具體地說明本發明,但本發明並不限定於此等。 Hereinafter, the present invention will be more specifically described by showing examples and comparative examples of the invention, but the invention is not limited thereto.

(實施例1) (Example 1)

準備具有以下之半導體元件搭載的有機樹脂基板、載置有熱硬化性環氧樹脂之半導體元件非搭載的有機樹脂基板、及如第1圖(A)所示的第1空腔與第2空腔之成形模具。 An organic resin substrate having a semiconductor element mounted on the following semiconductor element, an organic resin substrate on which a semiconductor element on which a thermosetting epoxy resin is mounted, and a first cavity and a second space as shown in FIG. 1(A) are prepared. Forming mold for the cavity.

半導體元件搭載的有機樹脂基板:厚度100μm、長 220mm、寬240mm之BT樹脂基板(線膨脹係數:15ppm/℃)。最多能夠搭載144個厚度300μm、9mm見方的矽晶片。以環氧黏晶材接著,並以金線與基板連接的144個矽晶片當中,排除30個不良晶片者。 Organic resin substrate mounted on a semiconductor element: 100 μm thick and long BT resin substrate of 220 mm and width of 240 mm (linear expansion coefficient: 15 ppm/° C.). A maximum of 144 silicon wafers having a thickness of 300 μm and a thickness of 9 mm can be mounted. Among the 144 bismuth wafers in which the epoxy bonding material was followed by the gold wire and the substrate, 30 defective wafers were excluded.

半導體元件非搭載的有機樹脂基板:厚度100μm、長214mm、寬234mm之BT樹脂基板(線膨脹係數:15ppm/℃) Organic resin substrate on which semiconductor elements are not mounted: BT resin substrate having a thickness of 100 μm, a length of 214 mm, and a width of 234 mm (linear expansion coefficient: 15 ppm/°C)

熱硬化性環氧樹脂:信越化學製KMC-2520、比重(25℃)1.93、64g(33.2cm3) Thermosetting epoxy resin: KMC-2520 manufactured by Shin-Etsu Chemical Co., Ltd., specific gravity (25 ° C) 1.93, 64 g (33.2 cm 3 )

將壓縮成形裝置的成形模具溫度設定為150℃,並藉由吸引而使半導體元件搭載的有機樹脂基板吸附於上模具。另一方面,載置有熱硬化性環氧樹脂之半導體元件非搭載的有機樹脂基板,係相同地吸引吸附於下模具。 The molding die temperature of the compression molding apparatus was set to 150 ° C, and the organic resin substrate mounted on the semiconductor element was attracted to the upper mold by suction. On the other hand, the organic resin substrate on which the semiconductor element on which the thermosetting epoxy resin is mounted is not attracted to the lower mold in the same manner.

其後,將模具的周圍密封,藉由脫氣使其內部成為真空度5kPa之後,關閉上下模具。基板間的間隙係設為600μm。接著,施加20Kg/cm2的壓力,通過澆道使多餘的樹脂以及空隙排出至第2空腔。此時,將空氣導入第2空腔,以避免降低對樹脂之加壓。成形時間係進行3分鐘。 Thereafter, the periphery of the mold was sealed, and after the inside of the mold was degassed to a vacuum of 5 kPa, the upper and lower dies were closed. The gap between the substrates was set to 600 μm. Next, a pressure of 20 Kg/cm 2 was applied, and excess resin and voids were discharged to the second cavity through the runner. At this time, air is introduced into the second cavity to avoid lowering the pressure on the resin. The forming time was carried out for 3 minutes.

成形後,將經一體化的基板從成形模具取出並冷卻至室溫之後,調查密封層的結果,並無樹脂不足或空隙的形成之缺陷發生。此外,測定基板之翹曲的結果,翹曲量在長邊方向為0.1mm,在短邊方向為0.1mm。進 而,以180℃進行後硬化4小時,同樣地測定翹曲的結果,在長邊方向為0.2mm,在短邊方向為0.1mm,係幾乎無翹曲者。 After the molding, the integrated substrate was taken out from the molding die and cooled to room temperature, and then the result of the sealing layer was investigated, and no defects such as insufficient resin or void formation occurred. Further, as a result of measuring the warpage of the substrate, the amount of warpage was 0.1 mm in the longitudinal direction and 0.1 mm in the short side direction. Enter On the other hand, the film was post-hardened at 180 ° C for 4 hours, and the results of warpage were measured in the same manner, and were 0.2 mm in the longitudinal direction and 0.1 mm in the short-side direction, and there was almost no warp.

將此基板貼附於切割膠帶,進行切割並將焊球焊在50個經單片化的半導體裝置之背面,而製造出半導體裝置。電性確認各個半導體裝置的結果,全部皆無問題地發揮功能。 The substrate was attached to a dicing tape, cut, and soldered to the back surface of 50 singulated semiconductor devices to fabricate a semiconductor device. The results of the respective semiconductor devices were electrically confirmed, and all of them functioned without problems.

重複進行100次上述半導體裝置的製造,評估密封層的結果,缺陷發生率為0%。 The production of the above semiconductor device was repeated 100 times, and the result of the sealing layer was evaluated, and the defect occurrence rate was 0%.

如上所述,本發明之半導體裝置之製造方法,即使於排除不良的半導體元件之情況中,亦無須進行因應密封層形成時之不良元件數目的樹脂填充量之調整,而可確實地將基板與密封層予以一體化,即使密封大型基板亦可抑制密封後之基板的翹曲或破裂。藉由預先將熱硬化性樹脂形成於半導體非搭載基板上,而可減低步驟時之煩雜度,且可防止因使用粉體所造成之生產線的污染。 As described above, in the method of manufacturing a semiconductor device of the present invention, even in the case of eliminating a defective semiconductor element, it is not necessary to adjust the amount of resin filling in accordance with the number of defective elements in the formation of the sealing layer, and the substrate can be surely The sealing layer is integrated, and even if the large substrate is sealed, warpage or cracking of the sealed substrate can be suppressed. By forming the thermosetting resin on the semiconductor non-mount substrate in advance, the trouble at the time of the step can be reduced, and contamination of the production line due to the use of the powder can be prevented.

(實施例2) (Example 2)

準備如第3圖所示之分別在不同區塊形成第1空腔與第2空腔的成形模具。此模具,係可分別控制第1空腔內或第2空腔內的溫度。將上模具及下模具之第1空腔內的溫度設為150℃,將下模具之第2空腔內的溫度設定為180℃。 A molding die in which the first cavity and the second cavity are formed in different blocks as shown in Fig. 3 is prepared. The mold can control the temperature in the first cavity or in the second cavity, respectively. The temperature in the first cavity of the upper mold and the lower mold was set to 150 ° C, and the temperature in the second cavity of the lower mold was set to 180 ° C.

除對樹脂加壓時不輸送空氣至第2空腔以外,藉由與 實施例1相同的成形步驟進行成形。結果,無樹脂不足或空隙之形成的缺陷發生。此外,測定基板之翹曲的結果,翹曲量在長邊方向為0.1mm,在短邊方向為0.1mm。進而,以180℃進行後硬化4小時,同樣地測定翹曲的結果,在長邊方向為0.2mm,在短邊方向為0.1mm,係幾乎無翹曲者。 Except when the resin is pressurized, air is not supplied to the second cavity, The same molding step of Example 1 was carried out. As a result, defects such as lack of resin or formation of voids occur. Further, as a result of measuring the warpage of the substrate, the amount of warpage was 0.1 mm in the longitudinal direction and 0.1 mm in the short side direction. Further, post-hardening was carried out at 180 ° C for 4 hours, and as a result of warping, the result was 0.2 mm in the longitudinal direction and 0.1 mm in the short-side direction, and there was almost no warpage.

將此基板貼附於切割膠帶,進行切割並將焊球焊在50個經單片化的半導體裝置之背面,而製造出半導體裝置。電性確認各個半導體裝置的結果,全部皆無問題地發揮功能。 The substrate was attached to a dicing tape, cut, and soldered to the back surface of 50 singulated semiconductor devices to fabricate a semiconductor device. The results of the respective semiconductor devices were electrically confirmed, and all of them functioned without problems.

重複進行100次上述半導體裝置的製造,評估密封層的結果,缺陷發生率為0%。 The production of the above semiconductor device was repeated 100 times, and the result of the sealing layer was evaluated, and the defect occurrence rate was 0%.

(比較例1) (Comparative Example 1)

準備與實施例1相同之半導體元件搭載的有機樹脂基板、半導體元件非搭載的有機樹脂基板、熱硬化性樹脂、成形模具。不將熱硬化性樹脂載置於半導體元件非搭載基板,而將半導體元件非搭載基板及半導體元件搭載基板配置於模具。具體而言,將壓縮成形裝置的成形模具溫度設定為150℃,並藉由吸引而使半導體元件搭載的有機樹脂基板吸附於上模具,半導體元件非搭載基板的有機樹脂基板係同樣地吸引吸附於下模具。其後,將比密封層之形成所需要的量更多量的粉體之熱硬化性環氧樹脂(信越化學製KMC-2520比重1.93),具體而言為64g層合於下基 板上,在與實施例1相同的條件下,製造半導體裝置,進行相同地評估。 An organic resin substrate mounted on a semiconductor element similar to that of the first embodiment, an organic resin substrate on which a semiconductor element is not mounted, a thermosetting resin, and a molding die are prepared. The semiconductor element non-mounting substrate and the semiconductor element mounting substrate are placed in a mold without placing the thermosetting resin on the semiconductor element non-mounting substrate. Specifically, the temperature of the molding die of the compression molding apparatus is set to 150° C., and the organic resin substrate on which the semiconductor element is mounted is attracted to the upper mold by suction, and the organic resin substrate on which the semiconductor element is not mounted is similarly attracted and adsorbed. Lower mold. Thereafter, a powder of a thermosetting epoxy resin (KMC-2520 specific gravity: 1.93) manufactured by Shin-Etsu Chemical Co., Ltd., specifically 64 g, is laminated to the lower base than the amount required for the formation of the sealing layer. On the board, under the same conditions as in Example 1, a semiconductor device was fabricated and evaluated in the same manner.

調查製造後之半導體裝置的密封層的結果,並無樹脂不足或空隙之形成的缺陷發生。與實施例1相同地重複進行100次上述半導體裝置的製造,評估密封層的結果,缺陷發生率為0%。但,如上述般地將半導體元件非搭載基板配置於模具之後再將熱硬化性樹脂進行層合的方式為非常煩雜的作業,再者,由於使用粉體之熱硬化性樹脂,因此發生生產線的污染,故生產性方面並非有效率。 As a result of investigating the sealing layer of the semiconductor device after the production, no defects such as insufficient resin or void formation occurred. The production of the above semiconductor device was repeated 100 times in the same manner as in Example 1, and as a result of evaluation of the sealing layer, the defect occurrence rate was 0%. However, the method of laminating the thermosetting resin after disposing the semiconductor element non-mounting substrate in the mold as described above is a very complicated operation, and further, since the powder is made of a thermosetting resin, the production line is generated. Pollution is not efficient in terms of productivity.

(比較例2) (Comparative Example 2)

準備未具備第2空腔,僅將第1空腔進行模具夾緊的壓縮成形用之上下模具。與實施例1相同地使用排除不良晶片30個之半導體元件搭載的有機樹脂基板,將52.64g之粉體的熱硬化性環氧樹脂(信越化學製KMC-2520比重1.93)層合於下基板上。此樹脂的秤量步驟係非常煩雜,故成為妨礙生產者。 An upper and lower mold for compression molding in which the second cavity is not provided and the first cavity is clamped by the mold is prepared. In the same manner as in the first embodiment, an organic resin substrate mounted on a semiconductor element in which 30 defective wafers were removed was used, and 52.64 g of a powder of a thermosetting epoxy resin (KMC-2520 specific gravity: 1.93 manufactured by Shin-Etsu Chemical Co., Ltd.) was laminated on the lower substrate. . This weighing step of the resin is very cumbersome and therefore hinders the producer.

在與實施例1相同的條件下製造半導體裝置,並進行相同的評估。 A semiconductor device was fabricated under the same conditions as in Example 1, and the same evaluation was performed.

調查製造後之半導體裝置的密封層之結果,確認出空隙的發生。與實施例1相同地重複進行100次上述半導體裝置的製造,評估密封層的結果,其發生率為30%。 As a result of investigating the sealing layer of the manufactured semiconductor device, the occurrence of voids was confirmed. The production of the above-described semiconductor device was repeated 100 times in the same manner as in Example 1, and the result of evaluation of the sealing layer was 30%.

此外,由於使用粉體作為熱硬化性樹脂,因此步驟變 得比實施例更煩雜,再者,由於發生生產線的污染,故生產性方面並非有效率。 In addition, since the powder is used as the thermosetting resin, the step is changed. It is more complicated than the embodiment, and further, productivity is not efficient due to contamination of the production line.

另外,本發明並不限定於上述實施形態。上述實施形態係為例示,具有與本發明之申請專利範圍所記載之技術思想實質上相同的構造,且發揮相同的作用效果者,皆包含於本發明之技術性範圍中。 Further, the present invention is not limited to the above embodiment. The above-described embodiments are exemplified, and have substantially the same structure as the technical idea described in the patent application scope of the present invention, and all of the same effects are included in the technical scope of the present invention.

Claims (11)

一種半導體裝置之製造方法,其係使用具有上模具及下模具之成形模具來製造半導體裝置的方法,其特徵為具有:準備具有用以使半導體元件搭載基板、半導體元件非搭載基板、與形成於此等基板之間之由熱硬化性樹脂所構成的密封層一體化之第1空腔,及透過澆道與前述第1空腔連結的第2空腔的前述成形模具之準備步驟;於前述半導體元件非搭載基板上,載置比前述密封層之形成所需要的量更多量的前述熱硬化性樹脂之樹脂載置步驟;將前述第1空腔內從室溫加熱至200℃,將前述第2空腔內的溫度加熱至比前述第1空腔內的溫度更高之溫度,將前述半導體元件搭載基板配置於前述成形模具之前述上模具及前述下模具其中一方的模具,並將前述半導體元件非搭載基板配置於另一方的模具之配置步驟;將前述上模具及前述下模具進行加壓,而將多餘的前述熱硬化性樹脂排出至前述第2空腔,且使排出至前述第2空腔的前述多餘之熱硬化性樹脂比前述第1空腔內的前述熱硬化性樹脂更早硬化之樹脂排出步驟;一邊將前述上模具及前述下模具進行加壓一邊使前述熱硬化性樹脂成形,使前述半導體元件搭載基板、前述半導體元件非搭載基板、及前述密封層一體化之一體化步驟;以及 將該一體化的基板從前述成形模具取出,藉由切割予以單片化的步驟。 A method of manufacturing a semiconductor device using a molding die having an upper mold and a lower mold to manufacture a semiconductor device, comprising: preparing a substrate for mounting a semiconductor element, mounting a substrate for a semiconductor element, and forming the semiconductor device a step of preparing a first cavity in which a sealing layer composed of a thermosetting resin is integrated between the substrates, and a molding die in which a second cavity that is connected to the first cavity is connected to the first cavity; a resin mounting step of placing the thermosetting resin in a larger amount than that required for formation of the sealing layer on the semiconductor element non-mounting substrate; heating the inside of the first cavity from room temperature to 200 ° C The temperature in the second cavity is heated to a temperature higher than a temperature in the first cavity, and the semiconductor element mounting substrate is placed on one of the upper mold and the lower mold of the molding die, and a step of disposing the semiconductor element non-mount substrate on the other mold; pressurizing the upper mold and the lower mold to add excess a resin discharge step of discharging the curable resin to the second cavity and curing the excess thermosetting resin discharged to the second cavity earlier than the thermosetting resin in the first cavity; a step of integrating the semiconductor element mounting substrate, the semiconductor element non-mounting substrate, and the sealing layer by molding the thermosetting resin while pressurizing the upper mold and the lower mold; and The integrated substrate is taken out from the molding die and diced by dicing. 如請求項1之半導體裝置之製造方法,其中於前述樹脂載置步驟中,以比前述密封層之形成所需要的量更多0.1~70vol%的方式載置前述熱硬化性樹脂。 The method of manufacturing a semiconductor device according to claim 1, wherein the thermosetting resin is placed in an amount of 0.1 to 70 vol% more than the amount required for formation of the sealing layer in the resin mounting step. 如請求項1之半導體裝置之製造方法,其中於前述一體化步驟中,將前述第1空腔內或前述第2空腔內進行加壓,而使前述熱硬化性樹脂成形。 The method of manufacturing a semiconductor device according to claim 1, wherein in the integrating step, the thermosetting resin is molded by pressurizing the inside of the first cavity or the second cavity. 如請求項3之半導體裝置之製造方法,其中藉由將空氣或惰性氣體壓入前述第2空腔,以進行前述第1空腔內之加壓。 The method of manufacturing a semiconductor device according to claim 3, wherein the pressurization in the first cavity is performed by pressing air or an inert gas into the second cavity. 如請求項4之半導體裝置之製造方法,其中藉由外部泵或汽缸進行朝前述第2空腔之空氣或惰性氣體的壓入。 The method of manufacturing a semiconductor device according to claim 4, wherein the pressurization of the air or the inert gas toward the second cavity is performed by an external pump or a cylinder. 如請求項1之半導體裝置之製造方法,其中將前述第2空腔內的溫度加熱至100~250℃之範圍內的溫度。 The method of manufacturing a semiconductor device according to claim 1, wherein the temperature in the second cavity is heated to a temperature in a range of 100 to 250 °C. 如請求項1或6之半導體裝置之製造方法,其中於前述一體化步驟中,將前述第1空腔內的環境進行減壓,而使前述熱硬化性樹脂成形。 The method of manufacturing a semiconductor device according to claim 1 or 6, wherein in the integrating step, the environment in the first cavity is decompressed to form the thermosetting resin. 如請求項7之半導體裝置之製造方法,其中將前述第1空腔內的環境進行減壓而成為真空度0.01333~13.33KPa。 The method of manufacturing a semiconductor device according to claim 7, wherein the environment in the first cavity is depressurized to have a degree of vacuum of 0.01333 to 13.33 KPa. 如請求項1之半導體裝置之製造方法,其中以壓縮成形進行前述熱硬化性樹脂之成形。 The method of manufacturing a semiconductor device according to claim 1, wherein the molding of the thermosetting resin is performed by compression molding. 如請求項1之半導體裝置之製造方法,其中使用環氧樹脂、聚矽氧樹脂、及聚矽氧/環氧混合樹脂中任一者作為前述熱硬化性樹脂。 A method of producing a semiconductor device according to claim 1, wherein any one of an epoxy resin, a polyoxynoxy resin, and a polyoxymethylene/epoxy hybrid resin is used as the thermosetting resin. 一種半導體裝置,其特徵為藉由如請求項1~10中任一項之半導體裝置之製造方法所製造。 A semiconductor device manufactured by the method of manufacturing a semiconductor device according to any one of claims 1 to 10.
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