JP5317548B2 - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof Download PDF

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JP5317548B2
JP5317548B2 JP2008162649A JP2008162649A JP5317548B2 JP 5317548 B2 JP5317548 B2 JP 5317548B2 JP 2008162649 A JP2008162649 A JP 2008162649A JP 2008162649 A JP2008162649 A JP 2008162649A JP 5317548 B2 JP5317548 B2 JP 5317548B2
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直実 舛田
淳二 田中
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スパンション エルエルシー
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H—ELECTRICITY
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Microelectronics & Electronic Packaging (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device that can reduce warpage and also can control the amount of the warpage. <P>SOLUTION: The semiconductor device has a substrate 2, a semiconductor chip 6 mounted on the substrate 2, and a resin 4 to which a needlelike filler is added and which seals the substrate 2 and semiconductor chip 6 such that the surface of the substrate 2 on the opposite side from the surface where the semiconductor chip 6 is mounted is exposed. The difference in contraction rate between the substrate 2 and resin 4 can be made small, so the warpage of the substrate 2 is reduced and the amount of the warpage can be controlled. <P>COPYRIGHT: (C)2010,JPO&amp;INPIT

Description

本発明は、半導体装置及びその製造方法に関し、特に樹脂封止型の半導体装置及びその製造方法に関する。   The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a resin-encapsulated semiconductor device and a manufacturing method thereof.

半導体装置では、基板に実装された半導体チップを保護するため基板と半導体チップとは樹脂等で封止される。その中に、ＢＧＡ（Ｂａｌｌ Ｇｒｉｄ Ａｒｒａｙ）型のように、基板の半導体チップが実装された面のみを封止する片面封止型のパッケージがある。   In a semiconductor device, the substrate and the semiconductor chip are sealed with a resin or the like in order to protect the semiconductor chip mounted on the substrate. Among them, there is a single-side sealed package that seals only a surface of a substrate on which a semiconductor chip is mounted, such as a BGA (Ball Grid Array) type.

特許文献１には、樹脂の表面を金属で覆い耐久性を高めた半導体装置を、簡単な工程により高歩留まりで生産する技術が開示されている。特許文献２及び特許文献３には、異なる物性を有する複数の樹脂を用いて半導体装置を封止する技術が開示されている。特許文献４には、樹脂の上面にガラスエポキシ板を設ける技術が開示されている。
特開平９−２３２４７７号公報 特開平９−１４８３５２号公報 特開平４−１７１９７０号公報 特開２０００−１２４３６３号公報 Patent Document 1 discloses a technique for producing a semiconductor device with high durability by covering a resin surface with metal by a simple process. Patent Documents 2 and 3 disclose techniques for sealing a semiconductor device using a plurality of resins having different physical properties. Patent Document 4 discloses a technique of providing a glass epoxy plate on the upper surface of a resin.
Japanese Patent Laid-Open No. 9-232477 JP-A-9-148352 JP-A-4-171970 JP 2000-124363 A

片面封止型パッケージでは、封止後の半導体装置が基板と樹脂の二層構造になる。基板と樹脂とでは収縮率に差異があるため、半導体装置を実装する工程等において加熱されると、基板に反りが発生する場合がある。このことは、基板と半導体チップとの接続不良が起きるなど、半導体装置の信頼性が低下する原因となる恐れがあった。   In the single-side sealed package, the semiconductor device after sealing has a two-layer structure of a substrate and a resin. Since there is a difference in shrinkage between the substrate and the resin, the substrate may be warped when heated in a process of mounting a semiconductor device or the like. This may cause a decrease in the reliability of the semiconductor device, such as a connection failure between the substrate and the semiconductor chip.

特許文献４の技術によれば、基板とガラスエポキシ板との収縮率の差異が小さいため、反りを低減することができるが、一定量の反り低減効果しか期待できない。   According to the technique of Patent Document 4, since the difference in shrinkage between the substrate and the glass epoxy plate is small, the warpage can be reduced, but only a certain amount of warpage reduction effect can be expected.

そこで本発明は、上記課題に鑑み、反りを低減することができ、かつ反りの量を制御することが可能な半導体装置の提供を目的とする。   In view of the above problems, an object of the present invention is to provide a semiconductor device capable of reducing warpage and controlling the amount of warpage.

本発明は、基板と、前記基板に実装された半導体チップと、針状フィラーが添加され、前記基板の前記半導体チップが実装された面と反対側の面が露出するように、前記基板と前記半導体チップとを封止する樹脂と、を具備することを特徴とする半導体装置である。本発明によれば、基板の反りを低減することができ、かつ反りの量を制御することが可能となる。   The present invention includes a substrate, a semiconductor chip mounted on the substrate, and a needle-like filler, so that the surface of the substrate opposite to the surface on which the semiconductor chip is mounted is exposed. A semiconductor device comprising: a resin for sealing the semiconductor chip. According to the present invention, the warpage of the substrate can be reduced, and the amount of warpage can be controlled.

上記構成において、前記針状フィラーは前記基板の前記半導体チップが実装された面と平行な方向に配向している構成とすることができる。この構成によれば、基板の半導体チップが実装された面と平行な方向における樹脂の収縮率を小さくすることができるため、反りを低減することが可能となる。   The said structure WHEREIN: The said acicular filler can be set as the structure orientated in the direction parallel to the surface in which the said semiconductor chip of the said board | substrate was mounted. According to this configuration, the shrinkage rate of the resin in the direction parallel to the surface of the substrate on which the semiconductor chip is mounted can be reduced, so that the warpage can be reduced.

上記構成において、前記樹脂の表面では前記樹脂の表面以外の領域よりも、前記針状フィラーの密度が高い構成とすることができる。この構成によれば、樹脂の表面の収縮率を小さくすることができるため、反りを低減することが可能となる。   The said structure WHEREIN: It can be set as the structure where the density of the said acicular filler is higher than the area | regions other than the surface of the said resin on the surface of the said resin. According to this configuration, the shrinkage rate on the surface of the resin can be reduced, so that warpage can be reduced.

上記構成において、前記針状フィラーは溶融シリカからなる構成とすることができる。この構成によれば、溶融シリカの収縮率が結晶性シリカよりも小さいため、反りをより低減することが可能となる。   The said structure WHEREIN: The said acicular filler can be set as the structure which consists of fused silica. According to this configuration, since the shrinkage rate of the fused silica is smaller than that of the crystalline silica, it is possible to further reduce the warpage.

本発明は、基板に半導体チップを実装する工程と、前記基板の前記半導体チップが実装された面とは反対の面が露出し、樹脂に針状フィラーが添加されるように、前記基板と前記半導体チップとを前記樹脂で封止する工程と、を有することを特徴とする半導体装置の製造方法である。本発明によれば、基板の反りを低減することができ、かつ反りの量を制御することが可能となる。   The present invention includes a step of mounting a semiconductor chip on a substrate, and exposing the surface of the substrate opposite to the surface on which the semiconductor chip is mounted, so that a needle-like filler is added to a resin. A method of manufacturing a semiconductor device, comprising: sealing a semiconductor chip with the resin. According to the present invention, the warpage of the substrate can be reduced, and the amount of warpage can be controlled.

上記構成において、前記封止する工程は、前記針状フィラーが前記基板の前記半導体チップが実装された面と平行な方向に配向するように封止する工程とすることができる。この構成によれば、基板の半導体チップが実装された面と平行な方向における樹脂の収縮率を小さくすることができるため、反りを低減することが可能となる。   In the above configuration, the sealing step may be a step of sealing so that the needle-like filler is oriented in a direction parallel to a surface of the substrate on which the semiconductor chip is mounted. According to this configuration, the shrinkage rate of the resin in the direction parallel to the surface of the substrate on which the semiconductor chip is mounted can be reduced, so that the warpage can be reduced.

上記構成において、前記封止する工程は、金型の上に前記樹脂を配置し、前記基板と前記半導体チップとを前記樹脂に押し付けて、封止する工程とすることができる。この構成によれば、ワイヤ流れを防止することができる。また、針状フィラーを基板の半導体チップが実装された面と平行な方向に配向させることができる。   In the above configuration, the sealing step may be a step of sealing the resin by placing the resin on a mold and pressing the substrate and the semiconductor chip against the resin. According to this configuration, wire flow can be prevented. Further, the needle-like filler can be oriented in a direction parallel to the surface of the substrate on which the semiconductor chip is mounted.

上記構成において、前記封止する工程で、前記樹脂は前記金型の上に配置された前記針状フィラーの上に配置される構成とすることができる。この構成によれば、基板の反りを低減することができ、かつ反りの量を制御することが可能となる。   The said structure WHEREIN: In the said sealing process, the said resin can be set as the structure arrange | positioned on the said acicular filler arrange | positioned on the said metal mold | die. According to this configuration, the warpage of the substrate can be reduced and the amount of warpage can be controlled.

上記構成において、前記封止する工程で、前記樹脂は、前記金型の上に配置され、前記針状フィラーが配向された、前記樹脂と同じ材質からなる樹脂板の上に配置される構成とすることができる。この構成によれば、針状フィラーの飛散を防止することができる。   In the above configuration, in the sealing step, the resin is disposed on the mold, and is disposed on a resin plate made of the same material as the resin, in which the needle-like filler is oriented. can do. According to this configuration, the acicular filler can be prevented from scattering.

上記構成において、前記封止する工程で、前記樹脂は、前記金型の上に配置され、上面に前記針状フィラーが配向されたフィルムの上に配置される構成とすることができる。この構成によれば、製造工程における樹脂の流出を防止することができる。また、樹脂と金型との接着を防止することができる。   The said structure WHEREIN: In the said sealing process, the said resin can be set as the structure arrange | positioned on the said metal mold | die, and is arrange | positioned on the film by which the said acicular filler was orientated on the upper surface. According to this configuration, it is possible to prevent the resin from flowing out in the manufacturing process. In addition, adhesion between the resin and the mold can be prevented.

本発明によれば、基板の反りを低減することができ、かつ反りの量を制御することが可能な半導体装置を提供することが可能となる。   ADVANTAGE OF THE INVENTION According to this invention, it becomes possible to provide the semiconductor device which can reduce the curvature of a board | substrate and can control the quantity of curvature.

図面を用いて、従来技術について説明する。   The prior art will be described with reference to the drawings.

比較例１は、従来から用いられている片面封止型の半導体装置である。図１（ａ）は比較例１に係る半導体装置１００の個片化前の状態を示す断面図であり、図１（ｂ）から図１（ｄ）は半導体装置１００の封止工程を示す断面図である。   Comparative Example 1 is a single-side sealed semiconductor device that has been conventionally used. FIG. 1A is a cross-sectional view illustrating a state before the semiconductor device 100 according to the comparative example 1 is singulated, and FIGS. 1B to 1D are cross-sectional views illustrating a sealing process of the semiconductor device 100. FIG.

図１（ａ）に示すように、例えばガラスエポキシからなる基板２の上に、例えばシリコンからなる半導体チップ６が接着剤８を用いて搭載されている。また、図１（ｂ）から図１（ｄ）に示すように、基板２と半導体チップ６とは、例えばＡｌ等の金属からなるワイヤ１２により電気的に接続されている（図１（ａ）においては省略）。すなわち、半導体チップ６は基板２に実装されている。基板２と半導体チップ６とは、基板２の半導体チップ６が実装された面とは反対の面が露出するように、例えばエポキシからなる樹脂４により封止されている。   As shown in FIG. 1A, a semiconductor chip 6 made of, for example, silicon is mounted on a substrate 2 made of, for example, glass epoxy using an adhesive 8. Further, as shown in FIGS. 1B to 1D, the substrate 2 and the semiconductor chip 6 are electrically connected by a wire 12 made of a metal such as Al (FIG. 1A). Omitted). That is, the semiconductor chip 6 is mounted on the substrate 2. The substrate 2 and the semiconductor chip 6 are sealed with a resin 4 made of, for example, epoxy so that the surface opposite to the surface of the substrate 2 on which the semiconductor chip 6 is mounted is exposed.

図１（ｂ）に示すように、溶解した状態の樹脂４を配置した金型１０を準備し、基板２の半導体チップ６が実装された面と樹脂４とが対向するように、基板２の位置合わせを行う。   As shown in FIG. 1B, a mold 10 having a resin 4 in a melted state is prepared, and the surface of the substrate 2 so that the surface of the substrate 2 on which the semiconductor chip 6 is mounted and the resin 4 face each other. Perform alignment.

図１（ｃ）に示すように、基板２と半導体チップ６とを樹脂４に押し付け、基板２の半導体チップ６が実装された面を樹脂４で封止する。   As shown in FIG. 1C, the substrate 2 and the semiconductor chip 6 are pressed against the resin 4, and the surface of the substrate 2 on which the semiconductor chip 6 is mounted is sealed with the resin 4.

図１（ｄ）に示すように、樹脂４が硬化し、半導体装置１００が形成される。このように、封止工程には、圧縮成形法を用いることができる。   As shown in FIG. 1D, the resin 4 is cured, and the semiconductor device 100 is formed. Thus, the compression molding method can be used for the sealing step.

比較例１によれば、半導体装置１００は基板２と樹脂４との二層構造となっている。基板２と樹脂４とでは収縮率に差異があるため、半導体装置１００を加熱すると、基板２に反りが発生し半導体装置の信頼性が低下する恐れがある。   According to Comparative Example 1, the semiconductor device 100 has a two-layer structure of the substrate 2 and the resin 4. Since there is a difference in shrinkage between the substrate 2 and the resin 4, when the semiconductor device 100 is heated, the substrate 2 may be warped and the reliability of the semiconductor device may be reduced.

比較例２は、特許文献４に係る半導体装置１１０である。   Comparative Example 2 is a semiconductor device 110 according to Patent Document 4.

図２に示すように、樹脂４の上面にガラスエポキシ板１４が設けられている。比較例２によれば、樹脂４とガラスエポキシ板１４とでは、収縮率の差異が小さいため、反りを低減することができる。   As shown in FIG. 2, a glass epoxy plate 14 is provided on the upper surface of the resin 4. According to the comparative example 2, since the difference in shrinkage is small between the resin 4 and the glass epoxy plate 14, warpage can be reduced.

しかし、比較例２では、ガラスエポキシ板１４の厚さが一定であるため、一定量の反り低減効果しか期待できない。   However, in Comparative Example 2, since the thickness of the glass epoxy plate 14 is constant, only a certain amount of warpage reduction effect can be expected.

本発明は、反りを低減することができ、かつ反りの量を制御することが可能な半導体装置の提供を目的とする。   An object of the present invention is to provide a semiconductor device capable of reducing warpage and controlling the amount of warpage.

図面を用いて、本発明の実施例について説明する。   Embodiments of the present invention will be described with reference to the drawings.

図３（ａ）は、実施例１に係る半導体装置２００を示す断面図であり、図３（ｂ）から図３（ｄ）は製造方法を示す断面図である。既述したものと同じ構成については、説明を省略する。   FIG. 3A is a cross-sectional view illustrating the semiconductor device 200 according to the first embodiment, and FIGS. 3B to 3D are cross-sectional views illustrating the manufacturing method. The description of the same configuration as described above is omitted.

図３（ａ）に示すように、例えばエポキシからなり、球状フィラーが添加された樹脂４の表面に、針状フィラー層１６が形成されている。すなわち、樹脂４の表面では、樹脂４の表面以外の部分よりも針状フィラーの密度が高くなっている。また、樹脂４中では針状フィラーは、基板２の半導体チップ６が実装された面２ａと平行な方向（Ｘ−Ｙ方向とする）に配向している。すなわち、図中の左右方向及び紙面に垂直な方向に配向している。針状フィラー層１６を含めた樹脂４全体の厚さは例えば３００μｍであり、針状フィラー層１６の厚さは例えば数十μｍである。また、個々の針状フィラーの直径は例えば１０μｍ、長さは例えば１００μｍである。   As shown in FIG. 3A, a needle-like filler layer 16 is formed on the surface of a resin 4 made of, for example, epoxy and added with a spherical filler. That is, the density of the needle-like filler is higher on the surface of the resin 4 than on portions other than the surface of the resin 4. In the resin 4, the needle-like filler is oriented in a direction parallel to the surface 2 a on which the semiconductor chip 6 of the substrate 2 is mounted (X-Y direction). That is, it is oriented in the horizontal direction in the figure and in the direction perpendicular to the paper surface. The total thickness of the resin 4 including the needle filler layer 16 is, for example, 300 μm, and the thickness of the needle filler layer 16 is, for example, several tens of μm. The diameter of each needle-like filler is, for example, 10 μm, and the length is, for example, 100 μm.

半導体装置２００の製造方法について説明する。   A method for manufacturing the semiconductor device 200 will be described.

図３（ｂ）に示すように、金型１０の上に針状フィラー１８を配置し、その上に樹脂４を配置する。   As shown in FIG.3 (b), the acicular filler 18 is arrange | positioned on the metal mold | die 10, and the resin 4 is arrange | positioned on it.

図３（ｃ）に示すように、金型１０を加熱し、樹脂４を溶解させる。基板２と半導体チップ６とを溶解した樹脂４に押し付ける。このとき樹脂４が流動するため、針状フィラー１８は樹脂４の表面において、基板２の面２ａと平行な方向に配向する。これにより、樹脂４の表面に針状フィラー層１６が形成される。   As shown in FIG.3 (c), the metal mold | die 10 is heated and the resin 4 is melt | dissolved. The substrate 2 and the semiconductor chip 6 are pressed against the dissolved resin 4. At this time, since the resin 4 flows, the acicular filler 18 is oriented in a direction parallel to the surface 2 a of the substrate 2 on the surface of the resin 4. Thereby, the acicular filler layer 16 is formed on the surface of the resin 4.

図３（ｄ）に示すように、以上の工程により、実施例１に係る半導体装置２００が完成する。   As shown in FIG. 3D, the semiconductor device 200 according to the first embodiment is completed through the above steps.

実施例１によれば、樹脂４に針状フィラー１８を添加することで、表面に針状フィラー層１６が形成することができる。針状フィラー１８はＸ−Ｙ方向に配向しているため、針状フィラー層１６のＸ−Ｙ方向の収縮率を小さくすることができる。これにより、基板２と、樹脂４の針状フィラー層１６との収縮率の差異が小さくなる。従って、基板２の反りを低減することができ、半導体装置２００の信頼性を向上させることが可能となる。   According to Example 1, the needle-like filler layer 16 can be formed on the surface by adding the needle-like filler 18 to the resin 4. Since the acicular filler 18 is oriented in the XY direction, the shrinkage rate of the acicular filler layer 16 in the XY direction can be reduced. Thereby, the difference in shrinkage between the substrate 2 and the needle-like filler layer 16 of the resin 4 is reduced. Therefore, the warpage of the substrate 2 can be reduced, and the reliability of the semiconductor device 200 can be improved.

針状フィラーを用いるため、比較例２のようにガラスエポキシ板１４を樹脂４の上面に設ける場合よりも、材料費及び工程を削減することができる。従って、半導体装置のコストダウンが可能となる。また、金型１０に配置する針状フィラー１８の添加量を調節することで、針状フィラー層１６の収縮率を調節することができる。このため、基板２や樹脂４の材質、大きさ等を変更した場合でも、反りの量を制御することが可能となる。   Since the needle filler is used, the material cost and the process can be reduced as compared with the case where the glass epoxy plate 14 is provided on the upper surface of the resin 4 as in Comparative Example 2. Therefore, the cost of the semiconductor device can be reduced. Moreover, the shrinkage rate of the acicular filler layer 16 can be adjusted by adjusting the addition amount of the acicular filler 18 arranged in the mold 10. For this reason, even when the material and size of the substrate 2 and the resin 4 are changed, the amount of warpage can be controlled.

図４は、基板と樹脂とにおいて、温度と伸び量との関係を例示した図である。横軸は温度、縦軸は伸び量を各々表す。樹脂が溶解する温度をＴ１、樹脂の収縮率が変化する温度をＴ２、基板と樹脂とで伸び量が等しくなる温度をＴ３とし、Ｔ３＜Ｔ２＜Ｔ１であるものとする。点線は基板、実線は樹脂の伸び量を各々表す。温度Ｔ１で基板を樹脂により封止し、温度を下げる場合を考える。   FIG. 4 is a diagram illustrating the relationship between the temperature and the amount of elongation in the substrate and the resin. The horizontal axis represents temperature, and the vertical axis represents elongation. The temperature at which the resin melts is T1, the temperature at which the shrinkage rate of the resin changes is T2, the temperature at which the amount of elongation between the substrate and the resin is equal is T3, and T3 <T2 <T1. The dotted line represents the substrate, and the solid line represents the amount of elongation of the resin. Consider a case where the substrate is sealed with resin at temperature T1 and the temperature is lowered.

基板の収縮率は例えば１４ｐｐｍ／℃であるため、図４中の破線の傾きは１４である。これに対し、樹脂は硬化する際に収縮し、その収縮率は例えば３０００ｐｐｍである。また、樹脂の温度変化による収縮率は、Ｔ２以下の温度においては例えば９ｐｐｍ／℃、Ｔ１からＴ２の温度においては例えば３０ｐｐｍ／℃である。このため、図４において樹脂の伸び量は、傾き３０の実線と傾き９の実線とが連結された実線として表される。   Since the shrinkage rate of the substrate is 14 ppm / ° C., for example, the slope of the broken line in FIG. On the other hand, the resin shrinks when cured, and the shrinkage rate is, for example, 3000 ppm. Further, the shrinkage rate due to the temperature change of the resin is, for example, 9 ppm / ° C. at a temperature of T2 or lower, and 30 ppm / ° C. at a temperature from T1 to T2. Therefore, in FIG. 4, the amount of elongation of the resin is represented as a solid line in which a solid line with an inclination 30 and a solid line with an inclination 9 are connected.

基板と樹脂とで伸び量が等しくなるとき、すなわち図４の点線と実線が交わるときに反りがゼロとなる。このときの温度Ｔ３が室温でなければ、反りが発生することとなる。実施例１によれば、針状フィラー１８の添加量を調節することで、樹脂４の表面に形成された針状フィラー層１６の収縮率を調節することができる（図３（ｄ）参照）。すなわち、図４の実線の傾きを調節することができる。これにより、Ｔ３を室温と等しくすることができる。   When the amount of elongation is the same between the substrate and the resin, that is, when the dotted line and the solid line in FIG. 4 intersect, the warpage becomes zero. If temperature T3 at this time is not room temperature, curvature will occur. According to Example 1, the shrinkage rate of the acicular filler layer 16 formed on the surface of the resin 4 can be adjusted by adjusting the addition amount of the acicular filler 18 (see FIG. 3D). . That is, the inclination of the solid line in FIG. 4 can be adjusted. Thereby, T3 can be made equal to room temperature.

針状フィラー層１６は樹脂４の表面、すなわちワイヤ１２と接触しない領域に形成される。このため、ワイヤ１２及び半導体チップ６に損傷を与えることを抑制することができる。   The acicular filler layer 16 is formed on the surface of the resin 4, that is, in a region not in contact with the wire 12. For this reason, it can suppress that the wire 12 and the semiconductor chip 6 are damaged.

圧縮成形法は、トランスファ成形に比べて樹脂の流動が少ない。このため、樹脂の流動によるワイヤ１２の変形（ワイヤ流れ）を抑制することができ、半導体装置の信頼性を向上させることが可能となる。また、金型１０に針状フィラー１８を配置して圧縮成形を行うことで、樹脂４の流れにより針状フィラー１８をＸ−Ｙ方向に配向させることができる。   The compression molding method has less resin flow than transfer molding. For this reason, deformation (wire flow) of the wire 12 due to resin flow can be suppressed, and the reliability of the semiconductor device can be improved. Moreover, the needle-like filler 18 can be oriented in the XY direction by the flow of the resin 4 by arranging the needle-like filler 18 in the mold 10 and performing compression molding.

針状フィラー１８の材質は溶融シリカに限定されず、例えば結晶性シリカからなっていてもよい。しかし、溶融シリカは結晶性シリカよりも収縮率が小さいため、反りをより低減することができる。このことから、針状フィラー１８は溶融シリカであることが好ましい。   The material of the acicular filler 18 is not limited to fused silica, and may be made of, for example, crystalline silica. However, since fused silica has a smaller shrinkage rate than crystalline silica, warpage can be further reduced. From this, it is preferable that the acicular filler 18 is a fused silica.

樹脂４には球状フィラーが添加されていなくてもよい。しかし、樹脂４全体に球状フィラーが添加されることで、樹脂４の硬度を高め、また樹脂４の収縮率を小さくすることができる。このため、球状フィラーが添加されていることが好ましい。   A spherical filler may not be added to the resin 4. However, by adding a spherical filler to the entire resin 4, the hardness of the resin 4 can be increased and the shrinkage rate of the resin 4 can be reduced. For this reason, it is preferable that a spherical filler is added.

実施例２は、針状フィラーをあらかじめ配向させた樹脂板を金型に配置して圧縮成形を行う、半導体装置の製造方法である。図５（ａ）は樹脂板２０を示す断面図であり、図５（ｂ）から図５（ｄ）は実施例２に係る半導体装置３００の製造方法を示す断面図である。   Example 2 is a method for manufacturing a semiconductor device, in which a resin plate having needle-shaped fillers previously oriented is placed in a mold and compression molding is performed. FIG. 5A is a cross-sectional view illustrating the resin plate 20, and FIGS. 5B to 5D are cross-sectional views illustrating a method for manufacturing the semiconductor device 300 according to the second embodiment.

図５（ａ）に示すように、針状フィラーを添加した樹脂板２０を準備する。樹脂板２０は、樹脂４と同じ樹脂からなる。また、樹脂板２０の中で、針状フィラーはＸ−Ｙ方向に配向している。   As shown to Fig.5 (a), the resin board 20 which added the acicular filler is prepared. The resin plate 20 is made of the same resin as the resin 4. Moreover, in the resin board 20, the acicular filler is orientated in the XY direction.

図５（ｂ）に示すように、金型１０の上に樹脂板２０を配置し、その上に樹脂４を配置する。   As shown in FIG.5 (b), the resin board 20 is arrange | positioned on the metal mold | die 10, and the resin 4 is arrange | positioned on it.

図５（ｃ）に示すように、金型１０を加熱し、樹脂板２０と樹脂４とを各々溶解させる。溶解された樹脂板２０と樹脂４とは、混じり合う。基板２と半導体チップ６とを樹脂４に押し付ける。樹脂板２０に添加され、配向していた針状フィラーは、樹脂４の表面に針状フィラー層１６を形成する。   As shown in FIG.5 (c), the metal mold | die 10 is heated and the resin board 20 and the resin 4 are each melt | dissolved. The dissolved resin plate 20 and the resin 4 are mixed. The substrate 2 and the semiconductor chip 6 are pressed against the resin 4. The needle-like filler added to the resin plate 20 and oriented forms a needle-like filler layer 16 on the surface of the resin 4.

図５（ｄ）に示すように、以上の工程により、実施例２に係る半導体装置３００が完成する。   As shown in FIG. 5D, the semiconductor device 300 according to the second embodiment is completed through the above steps.

実施例２によれば、実施例１と同様、図５（ｄ）に示すように、樹脂４の表面に針状フィラー層１６が形成されるため、半導体装置の反りを低減することができる。   According to the second embodiment, as in the first embodiment, as shown in FIG. 5D, since the needle-like filler layer 16 is formed on the surface of the resin 4, the warp of the semiconductor device can be reduced.

また、樹脂板２０の材質には、樹脂４と同じ樹脂を用いるため、樹脂板２０と樹脂４とが一体となり、基板２と半導体チップ６とを封止することができる。あらかじめ針状フィラーを配向させた樹脂板２０を金型１０に配置するため、針状フィラーが飛散することを抑制することができる。   Moreover, since the same resin as the resin 4 is used as the material of the resin plate 20, the resin plate 20 and the resin 4 are integrated, and the substrate 2 and the semiconductor chip 6 can be sealed. Since the resin plate 20 in which the needle filler is oriented in advance is arranged in the mold 10, the needle filler can be prevented from being scattered.

実施例３は、上面に針状フィラーが配向されたフィルムを金型に配置して圧縮成形を行う、半導体装置の製造方法である。図６（ａ）はフィルム２２と樹脂層２４との断面図であり、図６（ｂ）から図６（ｄ）は、実施例３に係る半導体装置４００の製造方法を示す断面図である。   Example 3 is a method for manufacturing a semiconductor device, in which a film having needle-like fillers oriented on the upper surface is placed in a mold and compression molding is performed. 6A is a cross-sectional view of the film 22 and the resin layer 24, and FIGS. 6B to 6D are cross-sectional views illustrating a method for manufacturing the semiconductor device 400 according to the third embodiment.

図６（ａ）に示すように、フィルム２２の上には樹脂層２４が形成されており、樹脂層２４の中では針状フィラーがＸ−Ｙ方向に配向されている。フィルム２２は、例えばＰＴＦＥ（ポリテトラフルオロエチレン）等の樹脂からなる。樹脂層２４は、樹脂４と同じ材質からなる。   As shown in FIG. 6A, a resin layer 24 is formed on the film 22, and the needle filler is oriented in the XY direction in the resin layer 24. The film 22 is made of a resin such as PTFE (polytetrafluoroethylene). The resin layer 24 is made of the same material as the resin 4.

図６（ｂ）に示すように、金型１０の上にフィルム２２を配置する。フィルム２２の上に、樹脂層２４と接するように樹脂４を配置する。   As shown in FIG. 6B, the film 22 is placed on the mold 10. The resin 4 is arranged on the film 22 so as to be in contact with the resin layer 24.

図６（ｃ）に示すように、金型１０を加熱し、樹脂層２４と樹脂４とを各々溶解させる。溶解した樹脂層２４と樹脂４とは混じり合う。基板２と半導体チップ６とを樹脂４に押し付ける。樹脂層２４に添加され、配向していた針状フィラーは、樹脂４の表面に針状フィラー層１６を形成する。   As shown in FIG.6 (c), the metal mold | die 10 is heated and the resin layer 24 and the resin 4 are each melt | dissolved. The dissolved resin layer 24 and the resin 4 are mixed. The substrate 2 and the semiconductor chip 6 are pressed against the resin 4. The needle-like filler added to the resin layer 24 and oriented forms the needle-like filler layer 16 on the surface of the resin 4.

図６（ｄ）に示すように、以上の工程により、実施例３に係る半導体装置４００が完成する。   As shown in FIG. 6D, the semiconductor device 400 according to the third embodiment is completed through the above steps.

実施例３によれば、実施例１と同様、図６（ｄ）に示すように、樹脂４の表面に針状フィラー層１６が形成されるため、半導体装置の反りを低減することができる。   According to the third embodiment, similar to the first embodiment, as shown in FIG. 6D, the needle-like filler layer 16 is formed on the surface of the resin 4, so that the warpage of the semiconductor device can be reduced.

図６（ｃ）に示すように、フィルム２２により基板２と金型１０との間の隙間を埋めることができる。このため、圧縮成形を行う際に樹脂４が金型１０の外部へ流出することを防止することができる。また、図６（ｂ）及び図６（ｃ）に示すように、樹脂４と金型１０との間にフィルム２２が配置されることとなる。このため、樹脂４と金型１０との接着を防止することができ、半導体装置４００の金型１０からの取り出しを容易に行うことができる。   As shown in FIG. 6C, the gap between the substrate 2 and the mold 10 can be filled with the film 22. For this reason, it is possible to prevent the resin 4 from flowing out of the mold 10 when performing compression molding. Further, as shown in FIGS. 6B and 6C, the film 22 is disposed between the resin 4 and the mold 10. For this reason, adhesion between the resin 4 and the mold 10 can be prevented, and the semiconductor device 400 can be easily taken out from the mold 10.

以上、本発明の実施例について詳述したが、本発明は係る特定の実施例に限定されるものではなく、特許請求の範囲に記載された本発明の要旨の範囲内において、種々の変形・変更が可能である。   Although the embodiments of the present invention have been described in detail above, the present invention is not limited to such specific embodiments, and various modifications and changes can be made within the scope of the gist of the present invention described in the claims. It can be changed.

図１（ａ）は比較例１に係る半導体装置１００を示す断面図であり、図１（ｂ）から図１（ｄ）は半導体装置１００の製造方法を示す断面図である。FIG. 1A is a cross-sectional view showing a semiconductor device 100 according to Comparative Example 1, and FIGS. 1B to 1D are cross-sectional views showing a method for manufacturing the semiconductor device 100. 図２は比較例２に係る半導体装置１１０を示す断面図である。FIG. 2 is a cross-sectional view showing a semiconductor device 110 according to Comparative Example 2. 図３（ａ）は実施例１に係る半導体装置２００を示す断面図であり、図３（ｂ）から図３（ｄ）は半導体装置２００の製造方法を示す断面図である。FIG. 3A is a cross-sectional view illustrating the semiconductor device 200 according to the first embodiment, and FIGS. 3B to 3D are cross-sectional views illustrating a method for manufacturing the semiconductor device 200. 図４は温度と伸び量との関係を例示した図である。FIG. 4 is a diagram illustrating the relationship between temperature and elongation. 図５（ａ）は樹脂板２０を示す断面図であり、図５（ｂ）から図５（ｄ）は実施例２に係る半導体装置３００の製造方法を示す断面図である。FIG. 5A is a cross-sectional view illustrating the resin plate 20, and FIGS. 5B to 5D are cross-sectional views illustrating a method for manufacturing the semiconductor device 300 according to the second embodiment. 図６（ａ）はフィルム２２と樹脂層２４とを示す断面図であり、図６（ｂ）から図６（ｄ）は実施例３に係る半導体装置４００の製造方法を示す断面図である。FIG. 6A is a cross-sectional view showing the film 22 and the resin layer 24, and FIGS. 6B to 6D are cross-sectional views showing a method for manufacturing the semiconductor device 400 according to the third embodiment.

符号の説明Explanation of symbols

基板 ２
樹脂 ４
半導体チップ ６
接着剤 ８
金型 １０
ワイヤ １２
針状フィラー層 １６
針状フィラー １８
樹脂板 ２０
フィルム ２２
樹脂層 ２４
半導体装置 １００、２００、３００、４００ Board 2
Resin 4
Semiconductor chip 6
Adhesive 8
Mold 10
Wire 12
Needle-shaped filler layer 16
Needle-shaped filler 18
Resin plate 20
Film 22
Resin layer 24
Semiconductor device 100, 200, 300, 400

Claims (8)

基板と、
前記基板に実装された半導体チップと、
前記基板の前記半導体チップが実装された面と反対側の面が露出するように、前記基板と前記半導体チップとを封止する樹脂と、
前記樹脂に針状フィラーを添加し、前記樹脂上に針状フィラー層を形成するように硬化することにより形成された針状フィラー層と、を備え、
前記針状フィラーは、前記基板の前記半導体チップが実装された面と平行な方向に配向している、ことを特徴とする半導体装置。 A substrate,
A semiconductor chip mounted on the substrate;
As the semiconductor chip opposite to the surface and is implemented surface before Symbol substrate is exposed, a resin for sealing the substrate and the semiconductor chip,
A needle-like filler layer formed by adding a needle-like filler to the resin and curing to form a needle-like filler layer on the resin ,
The acicular filler is oriented in a direction parallel to a surface of the substrate on which the semiconductor chip is mounted . 前記樹脂の表面では前記樹脂の表面以外の領域よりも、前記針状フィラーの密度が高いことを特徴とする請求項１記載の半導体装置。 Than in the region other than the surface of the resin on the surface of the resin, according to claim 1 Symbol mounting semiconductor device, wherein the density of the needle-like filler is high. 前記針状フィラーは溶融シリカからなることを特徴とする請求項１又は２に記載の半導体装置。 The semiconductor device according to claim 1 or 2 wherein the needle-like filler is characterized in that it consists of fused silica. 基板に半導体チップを実装する工程と、
前記基板の前記半導体チップが実装された面とは反対の面が露出し、樹脂に針状フィラーが添加されるように、前記基板と前記半導体チップとを前記樹脂で封止する工程と、を有し、
前記樹脂に前記針状フィラーを添加し、前記針状フィラーが前記基板の前記半導体チップが実装された面と平行な方向に配向するように前記樹脂上に針状フィラー層を形成するように硬化することにより、針状フィラー層が形成される、ことを特徴とする半導体装置の製造方法。 Mounting a semiconductor chip on a substrate;
Sealing the substrate and the semiconductor chip with the resin so that a surface opposite to the surface on which the semiconductor chip is mounted of the substrate is exposed and a needle-like filler is added to the resin. Yes, and
The needle-like filler is added to the resin, and cured to form a needle-like filler layer on the resin so that the needle-like filler is oriented in a direction parallel to the surface of the substrate on which the semiconductor chip is mounted. By doing so, a needle-like filler layer is formed , The manufacturing method of the semiconductor device characterized by the above-mentioned. 前記封止する工程は、金型の上に前記樹脂を配置し、前記基板と前記半導体チップとを前記樹脂に押し付けて、封止する工程であることを特徴とする請求項４に記載の半導体装置の製造方法。 5. The semiconductor according to claim 4, wherein the sealing step is a step of sealing the resin by disposing the resin on a mold and pressing the substrate and the semiconductor chip against the resin. Device manufacturing method. 前記封止する工程において、前記樹脂は前記金型の上に配置された前記針状フィラーの上に配置されることを特徴とする請求項５に記載の半導体装置の製造方法。 6. The method of manufacturing a semiconductor device according to claim 5, wherein, in the sealing step, the resin is disposed on the needle-shaped filler disposed on the mold. 前記封止する工程において、前記樹脂は、前記金型の上に配置され、前記針状フィラーが配向された前記樹脂と同じ材質からなる樹脂板の上に配置されることを特徴とする請求項５に記載の半導体装置の製造方法。 In the sealing step, the resin is disposed on the mold, and is disposed on a resin plate made of the same material as the resin in which the needle filler is oriented. 6. A method for manufacturing a semiconductor device according to 5 . 前記封止する工程において、前記樹脂は、前記金型の上に配置され、上面に前記針状フィラーが配向されたフィルムの上に配置されることを特徴とする請求項５に記載の半導体装置の製造方法。 6. The semiconductor device according to claim 5, wherein, in the sealing step, the resin is disposed on the mold, and is disposed on a film in which the needle-like filler is oriented on an upper surface. Manufacturing method.
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