TWI634590B - Methods for fabricating semiconductor structures - Google Patents

Abstract

A method of fabricating a semiconductor structure includes coating a photoresist layer on a dielectric layer on a substrate, and performing a lithography process on the photoresist layer. The lithography process includes measuring the focus position of the photoresist layer, setting the focus of the lens to a defocus position directly below the focus position, exposing the photoresist layer, and exposing the exposure if the focus of the lens is set at the defocus position The subsequent photoresist layer is developed to form an opening in the photoresist layer, the width of the opening decreasing from the top of the opening toward the bottom of the opening. The method also includes etching the dielectric layer through the opening to form a via, and filling the via with a conductive material to form the via.

Description

Semiconductor structure manufacturing method

Embodiments of the present invention relate to semiconductor fabrication techniques, and in particular to methods of fabricating vias having tapered sidewalls for semiconductor structures.

The semiconductor integrated circuit industry has experienced rapid growth over the past few decades. Advances in semiconductor materials and manufacturing technology have made components smaller and smaller, and their manufacturing has become more complex. Advances in semiconductor device miniaturization and performance improvement have been realized due to advances in semiconductor process technology. In the course of the development of semiconductor manufacturing, the number of components that can be interconnected per unit area is increasing due to the smaller and smaller size of the smallest components that can be reliably manufactured.

The semiconductor integrated circuit industry transfers the mask pattern to the photoresist layer of the wafer by lithography, and then forms various functional components or circuit components on the wafer by processes such as etching process, deposition process and ion implantation. . The steps of lithography generally involve photoresist coating, baking, alignment, exposure, and development. In order to accurately define the position and size of individual semiconductor components and the overlapping relationship between different material layers, complex process parameters are required to control the implementation of these lithography steps.

Although the semiconductor integrated circuit industry has made many developments in order to reduce the size of components, many challenges have arisen as the size of the smallest components continues to shrink. For example, as the aspect ratio of trenches and/or vias increases, defects such as voids or pipelines may This may be formed in the material in the trenches and/or vias, which results in a decrease in the reliability of the semiconductor device. Therefore, there is still a need in the industry to improve the manufacturing method of a semiconductor device to overcome the problems caused by the downsizing of components.

Some embodiments of the present invention provide a method of fabricating a semiconductor structure, the method comprising forming a dielectric layer on a substrate, coating a photoresist layer on the dielectric layer, and performing a lithography process on the photoresist layer. The lithography process includes placing a substrate under the lens, measuring a focus position of the photoresist layer, wherein the lens has a first focus length between the focus position and the focus position of the lens is set at a defocus position directly below the focus position, wherein Between the lens and the defocusing position, having a second focusing length greater than the first focusing length, after setting the focus of the lens to the defocusing position, exposing the photoresist layer, and developing the exposed photoresist layer to form an opening In the photoresist layer, wherein the width of the opening tapers from the top of the opening toward the bottom of the opening. The method further includes etching the dielectric layer through the opening to form a via hole, and filling the via hole with a conductive material to form the via hole.

Further embodiments of the present invention provide a method of fabricating a semiconductor structure, the method comprising applying a photoresist layer on a semiconductor substrate, and performing a lithography process on the photoresist layer, the lithography process comprising placing the semiconductor substrate under the lens, measuring a focus position of the photoresist layer, wherein the lens has a first focus length between the focus position and the focus position, and the focus of the lens is set at a defocus position directly below the focus position, wherein the lens and the defocus position have a greater than the first focus length a second focus length, after the focus of the lens is set at the defocus position, exposing the photoresist layer, and developing the exposed photoresist layer to form an opening in the photoresist layer, wherein the width of the opening is from the opening The top gradually decreases toward the bottom of the opening. This method is more included by opening The semiconductor substrate is etched to form a trench, and a layer of material is filled in the trench.

90, 201‧‧‧ semiconductor substrate

91‧‧‧ source area

92‧‧‧Bungee Area

93‧‧‧gate electrode

94‧‧‧Contacts

95‧‧‧First dielectric layer

96‧‧‧metal layer

100, 200‧‧‧ semiconductor structure

101‧‧‧Base

102‧‧‧Second dielectric layer

104, 204 ₁ , 204 ₂ ‧‧‧ photoresist layer

104’‧‧‧Exposure section

106, 206 ₁ , 206 ₂ ‧ ‧ openings

108‧‧‧through hole

110‧‧‧Guide

208 ₁ ‧‧‧First groove

208 ₂ ‧‧‧Second trench

210‧‧‧Isolation structure

212‧‧‧gate electrode

300‧‧‧Exposure steps

301, 303‧‧‧ lithography process

302‧‧‧Exposure equipment

304‧‧‧Light source

306‧‧‧Photomask

306A‧‧‧Lighting area

306B‧‧‧ Non-transparent area

308‧‧‧ lens

308A‧‧‧ horizontal plane

308B‧‧‧ optical axis

310‧‧‧ Wafer stage

312‧‧‧Light

400‧‧‧Development steps

500, 501, 502‧ ‧ etching process

D1, D2, D3‧‧‧ Depth

DOF1, DOF2‧‧‧ Depth of focus

F1‧‧‧first focus length

F1‧‧‧ Focus position

F2‧‧‧second focus length

F2‧‧‧ defocusing position

T1, T2‧‧‧ thickness

W1, W2, W3, W4, W5, W6, W7, W8, W9, W10‧‧‧ width

Θ1, θ2, θ3‧‧‧ angle

The views of the embodiments of the present invention can be more fully understood from the following detailed description. It is worth noting that, depending on the standard practice of the industry, various features are not necessarily drawn to scale. In fact, the dimensions of the various components may be arbitrarily increased or decreased for clarity of discussion.

1A through 1G are cross-sectional schematic views illustrating various intermediate stages of a method of forming a semiconductor structure in accordance with some embodiments of the present invention.

2A through 2H are cross-sectional schematic views illustrating various intermediate stages of a method of forming a semiconductor structure in accordance with further embodiments of the present invention.

The following description provides many different embodiments or examples for implementing the various components of the embodiments of the invention. Specific examples of components and configurations are described below to simplify embodiments of the present invention. Of course, these are merely examples and are not intended to limit the embodiments of the invention. For example, reference to a first component formed on a second component in the description may include forming an embodiment in which the first and second components are in direct contact, and may also include additional components formed in the first and second components. An embodiment in which the first and second components are not in direct contact. In addition, the embodiments of the present invention may repeat reference numerals and/or letters in many examples. The purpose of these repetitions is for simplicity and clarity, and is not intended to represent the relationship between the various embodiments and/or the configurations discussed.

Furthermore, spatially relevant terms can be used in the following descriptions, such as "under", "below", "below", "at..... "above", "above" and other similar terms to simplify a component or component and other elements A statement of the relationship between a piece or other component as shown. This spatially relevant wording encompasses different orientations of the device in use or operation, in addition to the orientation depicted in the drawings. The device can be positioned in other directions (rotated 90 degrees or in other directions), and the spatially related descriptions used herein can be interpreted accordingly accordingly.

1A through 1G are cross-sectional views illustrating various intermediate stages of a method of forming the semiconductor structure 100 shown in Fig. 1G, in accordance with some embodiments of the present invention. Referring to Figure 1A, a substrate 101 is provided. In some embodiments, substrate 101 is part of a semiconductor structure that has completed a front-end process, substrate 101 includes a semiconductor substrate 90, and a source region 91 and a drain region 92 formed in semiconductor substrate 90. The substrate 101 further includes a gate electrode 93 and a first dielectric layer 95 formed on the semiconductor substrate 90, and a contact 94 and a metal layer 96 in the first dielectric layer 95, wherein the gate electrode 93 is transparent. The contact member 94 is electrically connected to the metal layer 96. In some embodiments of the invention, substrate 101 further includes other components not shown in FIG. 1A, such as shallow trench isolation structures in semiconductor substrate 90, gates between gate electrodes 93 and semiconductor substrate 90. A very dielectric layer, as well as other metal layers located in the first dielectric layer 95. For the sake of simplicity of the drawing, the substrate 101 is represented by only simple squares in the 1B to 1F drawings.

Referring to FIG. 1A, a second dielectric layer 102 is formed on the substrate 101. In some embodiments, the second dielectric layer 102 can be an inter-layer dielectric layer (ILD layer). In some embodiments, the material of the second dielectric layer 102 may be tantalum oxide, tantalum nitride, hafnium oxynitride, SiCON, SiC, SiOC, combinations of the foregoing, or the like. The second dielectric layer 102 may be formed by chemical vapor deposition (CVD), such as plasma enhanced CVD (PECVD) or low pressure chemistry. Low pressure CVD (LPCVD). In some embodiments, the thickness T1 of the second dielectric layer 102 may be between about 0.5 micrometers and about 10 micrometers, depending on the electrical requirements of the subsequently formed semiconductor component, such as the breakdown voltage of the semiconductor component. And set.

With continued reference to FIG. 1A, a photoresist layer 104 is applied over the second dielectric layer 102. In some embodiments, the photoresist layer 104 can be formed by a spin-on coating process. The thickness T2 of the photoresist layer 104 can be between about 0.1 micrometers and about 5 micrometers, and can be adjusted by the thickness T1 of the second dielectric layer 102. For example, as the thickness T1 of the second dielectric layer 102 increases, the thickness T2 of the photoresist layer 104 may be increased. In addition, a bottom anti-reflective coating (BARC) may be selectively formed on the second dielectric layer 102 before the photoresist layer 104 is coated on the second dielectric layer 102 to reduce the subsequent In the exposure step 300 (Fig. 1C), the incident light and the reflected light interfere with each other. After the photoresist layer 104 is coated on the second dielectric layer 102, the photoresist layer 104 can be cured and/or baked.

After the photoresist layer 104 is formed on the second dielectric layer 102, the photoresist layer 104 is subjected to a lithography process. As shown in FIGS. 1B and 1C, in the embodiment of the present invention, the step of the lithography process includes measuring the focus position F1 of the photoresist layer 104, and setting the focus of the lens 308 of the exposure device 302 to the defocus position F2 for exposure. And developing the photoresist layer 104, these steps will be described in detail with reference to FIGS. 1B, 1C and 1D, respectively. Referring to FIG. 1B, substrate 101 is placed on exposure apparatus 302, which includes light source 304, reticle 306, lens 308, and wafer stage 310.

The light source 304 of the exposure device 302 can use a mercury lamp to excite the laser Or a visible light, ultraviolet (UV) or deep ultraviolet (DUV) light source or the like generated by a light source, depending on the size of the critical dimension (CD) transferred to the pattern of the photoresist layer 104. The wavelength range of light source 304 is selected.

The reticle 306 of the exposure device 302 can use a mask or a reticle (also known as a reticle). In some embodiments of the invention, the reticle 306 may employ a reticle that is 5 times the microcosm ratio. However, embodiments of the present invention may also use other reticle scales, such as 4 or 10 times, or a mask may be used. The mask 306 includes a light transmitting region 306A and a non-light transmitting region 306B. During the subsequent exposure, transferring the pattern of the mask 306 to the photoresist layer 104 is to shield the undesired portion of the photoresist layer 104 from the non-transmissive region 306B, and let the light emitted by the light source 304 pass through the light. Region 306A illuminates the portion of the photoresist layer 104 that is expected to be exposed.

The lens 308 of the exposure device 302 can be a convex lens or a combination of a series of lenses. In the embodiment of the present invention, the lens 308 is a focusing lens, and the light emitted by the light source 304 is focused by the lens 308 through a light transmitting area 306A on a focal point on the optical axis 308B. In some embodiments of the present invention, the focal length of the lens 308 is adjustable, so that the light emitted by the light source 304 can be adjusted by the lens 308 on the optical axis 308B by adjusting the focus length of the lens 308. position. In some embodiments of the invention, the distance between the lens 308 and the photoresist layer 104 can be adjusted by adjusting the height of the horizontal plane 308A of the lens 308 to achieve the purpose of adjusting the focus length of the lens 308.

The wafer stage 310 of the exposure apparatus 302 is used to carry the substrate 101. In some embodiments of the invention, the level of wafer stage 310 can be adjusted The height is adjusted to adjust the distance between the lens 308 and the photoresist layer 104 for the purpose of adjusting the focus length of the lens 308.

Continuing with reference to FIG. 1B, the substrate 101 is placed under the lens 308 and is fixed to the wafer stage 310. In order to allow the pattern of the reticle 306 to be accurately transferred to the photoresist layer 104, the reticle 306 can be aligned with the substrate 101 through an alignment assembly (not shown) of the exposure device 302 to achieve an optimal overlay (overlay). ). Next, the focus position F1 of the photoresist layer 104 is measured by the autofocus assembly of the exposure device 302, and the first focus length f1 is between the focus position F1 and the horizontal plane 308A of the lens 308.

If the focus length of the lens 308 is set to the first focus length f1, the lens 308 can focus the light emitted by the light source 304 to the focus position F1, and the lens 308 can have a thickness T2 greater than the photoresist layer 104 and completely cover the photoresist layer 104. The depth of focus (DOF, also known as depth of field) DOF1. The focus position F1 is located at the center of the depth of focus DOF1, and the focus position F1 is substantially at a position half the thickness of the photoresist layer 104. The depth of focus DOF1 covering the full thickness of the photoresist layer 104 allows the portion of the photoresist layer 104 to be exposed to have a uniform exposure energy and size in depth.

In some embodiments of the present invention, when the focus position F1 of the photoresist layer 104 is measured by the autofocus assembly of the exposure device 302, the focus length of the lens 308 may be automatically adjusted to the first focus length f1. In other embodiments, when the focus position of the photoresist layer 104 is measured with the autofocus assembly, the focus length of the lens 308 may not be automatically adjusted to the first focus length f1 while maintaining a predetermined value of the focus length of the lens 308. In addition, it should be noted that the subsequent exposure step 300 does not employ the lens 308 having the first focus length f1 for exposure, but Exposure is performed using a lens 308 having a second focus length f2 (shown in FIG. 1C) greater than the first focus length f1, the details of which will be described later.

Referring to FIG. 1C, after measuring F1 of the focus position of the photoresist layer 104, the focus of the lens 308 is set at a defocus position F2 directly below the focus position F1, wherein between the horizontal plane 308A and the defocus position F2 of the lens 308. There is a second focus length f2 that is greater than the first focus length f1. In other words, at this time, the lens 308 has a second focus length f2 that is larger than the first focus length f1. In some embodiments of the invention, the second focus length f2 may be 1.1 to 1.3 times the first focus length f1. In some embodiments, setting the focus of the lens 308 at the defocus position F2 can be achieved by reducing the distance between the lens 308 and the photoresist layer 104, for example, without changing the level of the wafer stage 310. The level of the lens 308 can be lowered; or the level of the wafer stage 310 can be raised without changing the level of the lens 308. The lithography process of the embodiment of the present invention sets the focus of the lens 308 to the defocus position F2 directly below the focus position F1, and causes the photoresist layer 104 to be in a defocused state during exposure.

Next, as shown in FIG. 1C, an exposure step 300 of the lithography process is performed on the photoresist layer 104. Light ray 312 from source 304 passes through light transmissive region 306A of reticle 306 and exposes photoresist layer 104 through lens 308. After the light ray 312 passes through the light transmissive region 306A of the reticle 306, a diffraction occurs to become divergent, and then the light ray 312 is focused to the defocus position F2 via the lens 308. Since the light ray 340 is focused on the defocusing position F2 directly below the focus position F1, the area illuminated by the light ray 312 is gradually decreased in the depth direction of the photoresist layer 104 instead of being uniform. of. In addition, in the embodiment of the present invention, the depth of focus DOF2 of the lens 308 having the second focus length f2 is lower than the depth of focus DOF1, The focal depth DOF2 may not cover the full thickness of the photoresist layer 104. In order to achieve sufficient exposure of the exposed portion of the photoresist layer 104 in depth, the exposure portion of the photoresist layer 104 can be completely removed by the subsequent development step 400 (Fig. 1D) by compensating for the exposure energy of the light source 304.

Referring to Fig. 1D, the width of the exposed portion 104' of the photoresist layer 104 is gradually decreased in the depth direction of the photoresist layer 104. After the exposure step 300 of FIG. 1C is performed on the photoresist layer 104, the photoresist layer 104 may be baked (not shown), and then the development step 400 is performed to develop the exposed photoresist layer 104 to remove the light. The exposed portion 104' of the resist layer 104.

Referring to FIG. 1E, after the exposed photoresist layer 104 is developed, an opening 106 is formed in the photoresist layer 104. The width of the opening 106 tapers from the top of the opening 106 toward the bottom of the opening 106. In some embodiments of the invention, the top of the opening 106 has a width W1 that may be between about 0.5 microns and about 5 microns, and the bottom of the opening 106 has a width W2 that may be between about 0.2 microns and about 2 microns. Where width W1 is greater than width W2.

In an embodiment of the invention, the top of the opening 106 and the bottom of the opening 106 have a pattern of the same shape but different sizes. In some embodiments, the bottom and top of the opening 106 are both circular from a top view. However, embodiments of the invention are not limited thereto, and the bottom and top of the opening 106 may be any other shape, such as an elliptical, square, strip, ring, or other shape.

Continuing with reference to FIG. 1E, after forming the opening 106 in the photoresist layer 104, an etching process 500 is performed. The second dielectric layer 102 is etched through the opening 106 to form a via 108 (shown in FIG. 1F) in the second dielectric layer 102. Etch process 500 can be dry etch, wet etch, or a combination of the foregoing. In some embodiments The etching process 500 is a dry etching process, such as reactive ion etching (RIE) or a similar dry etching process.

Referring to FIG. 1F, after the etching process 500, vias 108 are formed in the second dielectric layer 102, and the vias 108 extend from the top surface of the second dielectric layer 102 to the bottom surface of the second dielectric layer 102. It is noted that the etchant of the etch process 500 not only etches the second dielectric layer 102, but also etches the photoresist layer 106. As shown in FIG. 1F, because the lithography process according to an embodiment of the present invention, the thinner the portion of the photoresist layer 104 around the opening 106 is closer to the bottom of the opening 106, the photoresist is resisted during the etching process 500. The closer the portion of layer 104 around opening 106 is to the bottom of opening 106, the more etchant is depleted. As the etching process 500 continues, the opening 106 gradually expands outward and the size of the opening 106 gradually becomes larger. Therefore, the through hole 108 formed by etching the second dielectric layer 102 through the opening 106 having a gradually increasing size may have It is inclined to the side wall of the upper surface of the substrate 101.

Further, in the embodiment of the present invention, within the adjustable range of the second focus length f2 of the lens 308 (refer to FIG. 1C), for example, the second focus length f2 can be adjusted to 1.1 times the first focus length f1. Between 1.3 times, as the value of the second focus length f2 increases, the top of the formed opening 106 has a larger width W1, and the width W1 of the top of the opening 106 and the width W2 of the bottom of the opening 106 The larger the ratio, the angle at which the side walls of the through holes 108 are inclined can be adjusted.

As shown in FIG. 1F, the top of the opening 106 after the etching process 500 has a width W3 that is greater than the top width W1 of the opening 106 before the etching process 500. The bottom of the opening 106 after the etching process 500 has a width W4 that is greater than the bottom width W2 of the opening 106 before the etching process 500, and the width W3 is greater than the width W4.

As shown in FIG. 1F, the width of the through hole 108 gradually decreases from the top of the through hole 108 toward the depth of the bottom of the through hole 108. In some embodiments, the top of the via 108 can have a width W5 of between about 1 micron and about 10 microns, and the bottom of the via 108 can have a width W6 of between about 0.5 microns and about 5 microns, and the width. W5 is greater than the width W6. The depth D1 of the via 108 is substantially the same as the thickness T1 of the second dielectric layer 102, which may be between about 1 micrometer and about 10 micrometers. In some embodiments, the aspect ratio of the vias 108 can be between about 0.2 and about 20. In some embodiments, the sidewalls of the vias 108 intersect the bottom surface at an angle θ1 that is greater than 90° and less than 110°.

Thereafter, an ash process (not shown) may be performed, the photoresist layer 104 on the second dielectric layer 102 is removed, and a polymer on the sidewalls of the vias 108 is removed (not shown). This polymer is a mixture of the photoresist layer 104 and the etch by-products that are consumed in the etching process 500.

Referring to FIG. 1G, a conductive material is filled in the via hole 108 as a via hole 110 to form the semiconductor structure 100. In some embodiments of the present invention, as shown in FIG. 1G, the vias 110 may be electrically connected to the metal layer 96 in the substrate 101. In some embodiments, the conductive material forming the vias 108 may be a metal having good electrical conductivity, such as aluminum, copper, tungsten, alloys of the foregoing, combinations of the foregoing, or the like, and may be sputtered, A chemical vapor deposition (CVD), physical vapor deposition (PVD), electroplating, electroless plating or the like is performed to fill the conductive material in the via hole 108. In some embodiments, an adhesive layer or barrier layer can be formed on the sidewalls and bottom of the via 108 prior to filling the conductive material. The material of the adhesive layer or barrier layer may be titanium, titanium nitride, tantalum, tantalum nitride, a combination of the foregoing or a multilayer structure as described above.

In the embodiment of the present invention, by forming the conductive material into the through hole 108 having the inclined side wall to form the via hole 110, the problem caused by the void or the via hole formed in the via hole 110 can be avoided. Therefore, the reliability of the semiconductor device including the semiconductor structure can be improved by the method of fabricating the semiconductor structure having the via holes of the inclined sidewalls according to the embodiment of the present invention.

Further, in the embodiment of the present invention, the inclination angle θ1 of the side wall of the through hole 108 can be adjusted by setting the focus of the lens 308 at a different defocus position F2 (refer to FIG. 1C). For example, when the conductive material filled in the via hole 108 has a lower step coverage ratio, or the predetermined via hole 108 has a large aspect ratio, the focus of the lens 308 is set by The through hole 108 having a larger angle θ1 can be formed than the lower defocus position F2. In an embodiment of the invention, when the conductive material is tungsten (step coverage is about 70%) and the aspect ratio of the via 108 is about 7, a via hole 108 having an angle θ1 of 98° can be formed.

It should be noted that the embodiment shown in FIG. 1A-1G is only an example, and the scope of the embodiment of the present invention is not limited thereto. The method of the embodiments of the present invention can be applied to other semiconductor structures in addition to the embodiments shown in the above FIGS. 1A-1G.

2A-2H is a schematic cross-sectional view showing various intermediate stages of a method of forming a semiconductor structure 200 as shown in FIG. 2H, in accordance with further embodiments of the present invention. Referring to FIG. 2A, a semiconductor substrate 201 is provided. In some embodiments, the semiconductor substrate 201 can be a germanium substrate, a germanium substrate, a semiconductor-on-insulator (SOI) substrate, or a similar semiconductor substrate. In some embodiments, the semiconductor substrate 201 can also be a doped semiconductor substrate, such as a p-type semiconductor substrate or an n-type semiconductor substrate.

A photoresist layer 204 ₁ is coated on the semiconductor substrate 201. Next, a lithography process 301 is performed on the photoresist layer 204 ₁ . The lithography process 301 can be similar to the lithography process shown in the above FIG. 1B-1D. The step of the lithography process 301 includes measuring the focus position of the photoresist layer 204 ₁ and setting the focus of the lens of the exposure device (not shown) at Exposure is performed after the defocus position directly below the focus position, and the photoresist layer 204 _{1 is} developed.

Referring first to FIG 2B, in the embodiment lithography process 301, an opening is formed in photoresist layer 204 _{2,061 1,} wherein the width of the opening ₂₀₆₁ from the top opening toward the bottom of the opening ₂₀₆₁ to ₂₀₆₁ decreasing. Next, an etching process 501 is performed to etch the semiconductor substrate 201 through the opening 206 ₁ to form a first trench 208 ₁ (shown in FIG. 2C) in the semiconductor substrate 201.

Referring first to FIG 2C, after the etch process 501, forming a first trench having inclined sidewalls in the semiconductor substrate 201 _2081, wherein the width of the first trench ₂₀₈₁ from the top of the first trench ₂₀₈₁ towards the first The depth direction of the bottom of the trench 208 ₁ is gradually reduced. In some embodiments, the top of the first trench 208 ₁ has a width W7, and the bottom of the first trench 208 ₁ has a width W8, wherein the width W7 is greater than the width W8. The first trench 208 ₁ has a depth D2, and the sidewall of the first trench 208 ₁ intersects the bottom surface at an angle θ2, and the angle θ2 is greater than 90° and less than 110°.

Referring to FIG. 2D, in some embodiments, an insulating material is filled in the first trench 208 ₁ as the isolation structure 210. In some embodiments of the invention, the insulating material may be yttria, tantalum nitride, ytterbium oxynitride, combinations of the foregoing, or similar insulating materials. The isolation structure 210 can be formed by chemical vapor deposition (CVD), atomic layer deposition (ALD), or any other suitable method.

Referring to FIG. 2E, a photoresist layer 204 ₂ is coated on the semiconductor substrate 201. Next, a lithography process 303 is performed on the photoresist layer 204 ₂ . The lithography process 303 can be similar to the lithography process of the first B-1D image. The step of the lithography process 303 includes measuring the focus position of the photoresist layer 204 ₂ and setting the focus of the lens of the exposure device (not shown) to the focus position. Exposure is performed immediately below the defocus position, and the photoresist layer 204 _{2 is} developed.

Referring first to FIG 2F, after the lithography process embodiment 303, is formed on the photoresist layer ₂₀₆₂ in the opening _2042, opening ₂₀₆₂ where the width of the opening 206 from the top toward the bottom of the opening ₂ of the ₂₀₆₁ decreasing. Next, an etching process 502 is performed to etch the semiconductor substrate 201 through the opening 206 ₂ to form a second trench 208 ₂ (shown in FIG. 2G) in the semiconductor substrate 201.

Referring first to FIG 2G, after the etch process 502 to form a second trench having inclined sidewalls ₂₀₈₂ in the semiconductor substrate 201, wherein the width of the second trench ₂₀₈₂ from the top of the second trench ₂₀₈₂ toward the second The depth direction of the bottom of the trench 208 ₂ is gradually reduced. In the embodiment of the present invention, the top of the second trench 208 ₂ has a width W9, and the bottom of the second trench 208 ₂ has a width W10, wherein the width W9 is greater than the width W10. The second trench 208 ₂ has a depth D3. Although the 2G diagram shows that the depth D3 of the second trench 208 ₂ is smaller than the depth D2 of the first trench 208 ₁ , the depth D3 of the second trench 208 ₂ may also be greater than or equal to the depth D2 of the first trench 208 ₁ . . The sidewalls of the second trench 208 ₂ intersect the bottom surface at an angle θ3, and the angle θ3 is greater than 90° and less than 110°.

Referring to FIG. 2H, after the second trench 208 ₁ is formed, a dielectric can be deposited in the second trench 208 ₂ as a gate dielectric layer (not shown). The gate dielectric layer can conformally extend to the sidewalls and bottom surface of the second trench 208 ₂ . Next, a conductive material is filled as a gate electrode 212 in the remaining portion of the second trench 208 ₂ and on the gate dielectric layer to form the semiconductor structure 200. In some embodiments of the present invention, the conductive material filled in the second trench 208 ₂ may be a semiconductor material such as doped polysilicon, or a metal material such as TiN, TaN, TaC, Co, Ru, Al, a combination of the foregoing or a similar material. The conductive material may be filled by chemical vapor deposition (CVD), atomic layer deposition (ALD), or any other suitable method to form the gate electrode 212.

In the embodiment of the present invention, the void or the tube is formed in the isolation by filling the insulating material with the first trench 208 ₁ having the inclined sidewall and filling the conductive material into the second trench 208 ₂ having the inclined sidewall. Problems posed in structure 210 and gate electrode 212. Therefore, the reliability of the semiconductor device including the semiconductor structure can be improved by the method of fabricating the semiconductor structure having the trenches with the inclined sidewalls of the embodiment of the present invention.

In summary, the embodiment of the present invention exposes the photoresist layer by setting the focus of the lens of the exposure device to a defocus position directly below the focus position to form an opening in the photoresist layer, the width of the opening being from the top toward The bottom is decreasing. The embodiment of the present invention further performs an etching process using the above openings to form via holes or trenches having inclined sidewalls. Thereby, problems caused by voids or tubes formed in the material in the via holes or trenches are avoided, thereby improving the reliability of the semiconductor device.

The foregoing has outlined some of the embodiments of the embodiments of the invention in the embodiments of the invention. It should be understood by those of ordinary skill in the art that they can readily use the embodiments of the present invention as a basis for designing or modifying other processes or structures to achieve the same objectives and/or embodiments as those described herein. advantage. It is also to be understood by those skilled in the art that the present invention is not to be construed as limited to the spirit and scope of the invention. Changes, substitutions and substitutions. Accordingly, the scope of the invention is defined by the scope of the appended claims.

Claims (13)

A method of fabricating a semiconductor structure, comprising: forming a dielectric layer on a substrate; coating a photoresist layer on the dielectric layer; performing a lithography process on the photoresist layer, wherein the lithography process comprises: Placing the substrate under a lens; measuring a focus position of the photoresist layer, wherein the lens has a first focus length between the focus position; and setting a focus of the lens directly below the focus position a defocusing position, wherein the lens and the defocusing position have a second focusing length greater than the first focusing length; after the focus of the lens is set at the defocusing position, exposing the photoresist layer The exposure of the photoresist layer is not performed by the lens being set at the focus position; and the exposed photoresist layer is developed to form an opening in the photoresist layer, wherein the width of the opening is from the opening The top portion is tapered toward the bottom of the opening; the dielectric layer is etched through the opening to form a via hole; and a conductive material is filled in the via hole to form a via hole. The method of fabricating a semiconductor structure according to claim 1, wherein the second focus length is 1.1 times to 1.3 times the first focus length. The method of fabricating a semiconductor structure according to claim 1, wherein setting the focus of the lens at the defocus position transmits a distance between the lens and the photoresist layer. The method of manufacturing a semiconductor structure according to claim 1, wherein The width of the through hole gradually decreases from the top of the through hole toward the bottom of the through hole. The method of fabricating a semiconductor structure according to claim 1, wherein an angle at which the sidewall of the through hole intersects the bottom surface is greater than 90 degrees and less than 110 degrees. The method of fabricating a semiconductor structure according to claim 1, wherein the through hole has a depth of between 2 micrometers and 10 micrometers. The method of fabricating a semiconductor structure according to claim 1, wherein the through hole has an aspect ratio of between 0.2 and 20. A method of fabricating a semiconductor structure, comprising: coating a photoresist layer on a semiconductor substrate; performing a lithography process on the photoresist layer, wherein the lithography process comprises: placing the semiconductor substrate under a lens; measuring a focus position of the photoresist layer, wherein the lens and the focus position have a first focus length; a focus of the lens is set at a defocus position directly below the focus position, wherein the lens and the lens Having a second focus length greater than the first focus length between the defocus positions; after the focus of the lens is set at the defocus position, the photoresist layer is exposed, wherein the exposure of the photoresist layer is not Performing at the focus position through the lens; and developing the exposed photoresist layer to form an opening in the photoresist layer, wherein a width of the opening gradually decreases from a top of the opening toward a bottom of the opening; Etching the semiconductor substrate through the opening to form a trench; and filling a trench in the material layer. A method of fabricating a semiconductor structure according to claim 8 wherein The second focus length is 1.1 times to 1.3 times the first focus length. A method of fabricating a semiconductor structure according to claim 8 wherein the width of the trench decreases from the top of the trench toward the bottom of the trench. The method of fabricating a semiconductor structure according to claim 8, wherein an angle at which the sidewall of the trench intersects the bottom surface is greater than 90 degrees and less than 110 degrees. The method of fabricating a semiconductor structure according to claim 8, wherein the material layer is an insulating material, and wherein the insulating material is filled in the trench as an isolation structure. The method of fabricating a semiconductor structure according to claim 8, wherein the material layer is a conductive material, and wherein the conductive material is filled in the trench as a gate electrode.