TWI632678B - High electron mobility transistor - Google Patents

Abstract

Embodiments of the present invention provide a high electron mobility transistor, comprising: a buffer layer on a substrate; a barrier layer on the buffer layer; and a channel layer in the buffer layer adjacent to the interface between the buffer layer and the barrier layer; a gate electrode on the barrier layer; a drain electrode on the barrier layer and on the first side of the gate electrode; and a source electrode on the barrier layer and on the second side of the gate electrode The first side and the second side are opposite sides of each other; and the first reinforcing layer is located on the barrier layer and the channel layer, and is located between the gate electrode and the drain electrode, and is not connected to the gate electrode and the source electrode, And the drain electrode is in direct contact; wherein the first enhancement layer is an N-type doped tri-five semiconductor.

Description

High electron mobility transistor

Embodiments of the present invention relate to a high electron mobility transistor, and more particularly to a high electron mobility transistor that enhances the on current.

High Electron Mobility Transistor (HEMT) is widely used in high-power semiconductor devices due to its high breakdown voltage and high output voltage.

Traditionally, in order to enhance the two-dimensional electron gas (2DEG) concentration, the concentration of the high electron mobility transistor material can be changed, or the spacer structure can be increased, and the two-dimensional electron gas can be enhanced by band change. . However, the above method also enhances the Coulomb scattering, so that the electron mobility is lowered, and the overall current does not necessarily rise. In addition, process uniformity control is also a major challenge.

Although the existing high electron mobility transistor generally meets the requirements, it is not satisfactory in all aspects, and in particular, the conduction current of the high electron mobility transistor needs to be further improved.

Embodiments of the present invention provide a high electron mobility transistor, comprising: a buffer layer on a substrate; a barrier layer on the buffer layer; and a channel layer in the buffer layer adjacent to the interface between the buffer layer and the barrier layer; a gate electrode on the barrier layer; a drain electrode on the barrier layer and located at the gate electrode a source electrode, located on the barrier layer, on the second side of the gate electrode, the first side and the second side are opposite sides of each other; and the first reinforcement layer is located on the barrier layer and the channel layer And located between the gate electrode and the drain electrode, and is not in direct contact with the gate electrode, the source electrode, and the drain electrode; wherein the first enhancement layer is an N-type doped tri-five semiconductor.

The above described objects, features and advantages of the present invention will become more apparent and understood.

100, 200, 300, 400‧‧‧ high electron mobility transistor

102‧‧‧Substrate

104‧‧‧buffer layer

106‧‧‧Barrier layer

108‧‧‧Channel layer

110‧‧‧gate electrode

112‧‧‧Source electrode

114‧‧‧汲electrode

116, 116a‧‧‧ reinforcement layer

118C, 218C‧‧‧ Guide belt

118V, 218V‧‧ ‧ price belt

118F, 218F‧‧‧ Fermi level

120‧‧‧Interconnected structure

122‧‧‧Interlayer dielectric layer/metal interlayer dielectric layer

210‧‧‧With adjustment layer

310‧‧‧gate electrode

312‧‧‧ dielectric layer

410‧‧‧Doped layer

AA’, BB’‧‧‧ segments

T‧‧‧ thickness

The embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various features are not drawn to scale and are merely illustrative. In fact, the dimensions of the elements may be arbitrarily enlarged or reduced to clearly show the features of the embodiments of the invention.

1 is a schematic cross-sectional view of a high electron mobility transistor, in accordance with some embodiments.

Figure 2 illustrates an energy band diagram of a high electron mobility transistor in accordance with some embodiments.

Figure 3 is a schematic cross-sectional view of a high electron mobility transistor, in accordance with some embodiments.

Figure 4 illustrates an energy band diagram of a high electron mobility transistor in accordance with some embodiments.

Figure 5 is a schematic cross-sectional view of a high electron mobility transistor, in accordance with some embodiments.

Figure 6 is a cross-sectional view showing a high electron mobility transistor according to some embodiments. Schematic diagram.

Figure 7 is a schematic cross-sectional view of a high electron mobility transistor, in accordance with some embodiments.

The various features of the embodiments of the invention are set forth in the description of the invention. The embodiments are for illustrative purposes only, and are not intended to limit the scope of the embodiments of the invention. For example, it is mentioned in the specification that the first feature is formed on the second feature, including an embodiment in which the first feature is in direct contact with the second feature, and additionally includes another feature between the first feature and the second feature. An embodiment of the feature, that is, the first feature is not in direct contact with the second feature. In addition, the various embodiments may be used in the various embodiments of the present invention, and are not to be construed as a limitation of the various embodiments and/or structures discussed.

In addition, space-related terms such as "below", "below", "lower", "above", "higher" and similar terms may be used. Words used to describe the relationship between one element or feature(s) in the drawing and another element or feature(s), such spatially related terms include different orientations of the device in operation or operation, and in the drawings The orientation described. When the device is turned to a different orientation (rotated 90 degrees or other orientation), the spatially related adjectives used therein will also be interpreted in terms of the orientation after the turn.

Here, the terms "about", "about" and "major" generally mean within 20% of a given value or range, preferably within 10%, and more preferably within 5%, or 3 Within %, or within 2%, or within 1%, or within 0.5%. Should pay attention The quantity provided in the description is approximate, that is, in the absence of specific descriptions of "about", "about" and "major", "about", "about" and "major" may still be implied. The meaning.

Embodiments of the present invention provide a high electron mobility transistor (HEMT) that forms a reinforcement layer between a gate electrode and a drain electrode, and deepens the energy band of the quantum well. Increase the concentration of two-dimensional electron gas (2DEG) in the channel layer to increase the on-current.

1 is a cross-sectional view of a high electron mobility transistor 100 in accordance with some embodiments of the present invention. As shown in FIG. 1, a substrate 102 is provided. The substrate 102 may comprise Si, SiC, or Al ₂ O ₃ (sapphire), and may be a single layer substrate, a multilayer substrate, a gradient substrate, other suitable substrates, or a combination thereof. In some embodiments, the substrate 102 may further include a semiconductor-on-insulator (SOI) substrate, and the insulating layer-covered semiconductor substrate may include a bottom plate, a buried oxide layer disposed on the substrate, or disposed on the buried oxide layer. The semiconductor layer.

Next, a buffer layer 104 is formed on the substrate 102. In some embodiments, buffer layer 104 includes an undoped III-V semiconductor, such as undoped GaN. In some embodiments, the buffer layer 104 has a thickness between 1 μm and 20 μm. In some embodiments, molecular-beam epitaxy (MBE), metalorganic chemical vapor deposition (MOCVD), chemical vapor deposition (CVD), Hydride vapor phase epitaxy (HVPE), other suitable methods, or combinations thereof, on substrate 102 A buffer layer 104 is formed thereon.

Next, a barrier layer 106 is formed on the buffer layer 104. In some embodiments, barrier layer 106 comprises an undoped III-V semiconductor, such as undoped AlGaN. In some embodiments, the barrier layer 106 has a thickness between 0.1 μm and 5 μm. In some embodiments, molecular-beam epitaxy (MBE), metalorganic chemical vapor deposition (MOCVD), chemical vapor deposition (CVD), A barrier layer 106 is formed on the buffer layer 104 by a hydride vapor phase epitaxy (HVPE), other suitable methods, or a combination thereof.

Since the buffer layer 104 and the barrier layer 106 have different material band gaps, a heterojunction is formed at the interface between the buffer layer 104 and the barrier layer 106, because the energy band at the heterojunction is curved. A quantum well is formed deep in the bending of the conduction band, and electrons generated by the piezoelectric effect are confined in the quantum well, thereby forming a two-dimensional electron gas at the interface between the buffer layer 104 and the barrier layer 106. (two-dimensional electron gas, 2DEG), which in turn forms an on current. As shown in FIG. 1, a channel layer 108 is formed at the interface of the buffer layer 104 and the barrier layer 106, and the channel layer 108 is where the two-dimensional electron gas forms an on current. The channel layer 108 has a thickness between 0.1 μm and 1 μm.

Next, a gate electrode 110, a source electrode 112, and a drain electrode 114 are formed on the barrier layer 106. The source electrode 112 and the drain electrode 114 are located on opposite sides of the gate electrode 110, respectively. In some embodiments, the gate electrode 110 can comprise a metal material, a polysilicon, a metal halide, other suitable conductive material, or The combination described. In some embodiments, source electrode 112 and drain electrode 114 can each comprise Ti, Al, Au, Pd, other suitable metallic materials, alloys thereof, or combinations thereof. In some embodiments, the electroplating method, the sputtering method, the resistance heating evaporation method, the electron beam evaporation method, the physical vapor deposition (PVD), and the chemical vapor deposition (chemical vapor deposition, CVD), atomic layer deposition (ALD), other suitable methods, or combinations thereof, are formed on the barrier layer 106 to form an electrode material, and then patterned by a photolithography and etching process to form the gate electrode 110. The source electrode 112 and the drain electrode 114.

Next, an enhancement layer 116 is formed between the gate electrode 110 and the drain electrode 114 on the barrier layer 106. In some embodiments, the enhancement layer 116 is an N-type doped Group III semiconductor, including N-doped GaN, AlGaN, AlN, GaAs, AlGaAs, InP, InAlAs, or InGaAs, the N-type doping concentration is between 1e17/cm ³ to 1e20/cm ³ . The reinforcing layer 116 has a thickness of between 0.1 μm and 1 μm. In some embodiments, molecular-beam epitaxy (MBE), metalorganic chemical vapor deposition (MOCVD), chemical vapor deposition (CVD), A hydride vapor phase epitaxy (HVPE) forms an N-type doped Group III semiconductor on the barrier layer 106, and then passes through a patterning process (eg, a lithography process, an etching process, or a combination thereof) An enhancement layer 116 is defined between the gate electrode 110 and the drain electrode 114.

It should be noted that in this embodiment, the gate electrode 110, the source electrode 112, and the drain electrode 114 are formed first to form the enhancement layer 116, however, The order of formation in this embodiment is not limited, and the enhancement layer 116 may be formed first to form the gate electrode 110, the source electrode 112, and the drain electrode 114.

Fig. 2 is an energy band diagram in the cross-sectional direction along the line AA' in Fig. 1, including a conduction band 118C, a valence band 118V, and a fermi level 118F. Since the enhancement layer 116 is an N-type doped Group III semiconductor, the N-type doping causes the conduction band 118C to deepen the depth of the quantum well at the interface between the buffer layer 104 and the barrier layer 106, and thus the fee in the channel layer 108 The two-dimensional electron gas concentration at a fermi level of 118 F or less becomes higher, and the on-current is further increased.

In the above embodiment, since the buffer layer 104 and the barrier layer 106 have different material band gaps, a two-dimensional electron gas is formed at the interface thereof to form an on current in the channel layer 108. At this time, the gate voltage is not required to be applied, and the high electron mobility transistor 100 is turned on. Therefore, the high electron mobility transistor 100 is a depletion mode (D-mode) high electron mobility transistor.

As described above, the present invention provides a reinforcing layer on the barrier layer of the high electron mobility transistor. Since the N-type doping changes the band difference, the quantum well depth can be deepened, and the two-dimensional electron gas concentration is changed. High, further increasing the conduction current in the channel layer.

3 is a cross-sectional view of a high electron mobility transistor 200 in accordance with further embodiments of the present invention. Processes or elements that are the same as or similar to the previous embodiments will be given the same reference numerals, and the detailed description thereof will not be repeated. The difference from the foregoing embodiment is that a band adjustment layer 210 is further disposed on the barrier layer 106 and electrically connected to the gate electrode 110. The energy band adjustment layer 210 is a P-type doped tri-five semiconductor, including P-doped GaN, AlGaN, AlN, GaAs, AlGaAs, InP, InAlAs, or InGaAs, and has a P-type doping concentration of 1e17/cm ^{3 .} It is between 1e20/cm ³ . The band adjustment layer 210 has a thickness of between 0.1 μm and 1 μm. In some embodiments, before the formation of the gate electrode 110, the source electrode 112, and the drain electrode 114, molecular-beam epitaxy (MBE), metalorganic chemical (metalorganic chemical) may be used. Vapor deposition (MOCVD), chemical vapor deposition (CVD), hydride vapor phase epitaxy (HVPE), deposition of P-type doping via, for example, lithography process and etching process The Group 5 semiconductor is then patterned to form an energy band adjustment layer 210. After the energy band adjustment layer 210 is formed, the gate electrode 110, the source electrode 112, and the drain electrode 114 are formed in the above-described embodiment, and the band adjustment layer 210 is electrically connected to the gate electrode 110.

Fig. 4 is an energy band diagram in the cross-sectional direction of the line segment BB' in Fig. 3, including a conduction band 218C, a valence band 218V, and a fermi level 218F. Since the band adjustment layer 210 is a P-type doped Group III semiconductor, the P-type doping causes an energy band to be increased, and the quantum well energy at the interface between the buffer layer 104 and the barrier layer 106 is higher than the Fermi level 218F. As a result, no two-dimensional electron gas is generated in the channel layer 108, and thus there is no conduction current.

In the above embodiment, since the energy band adjustment layer 210 pulls up the energy band, when the gate voltage is not applied, the high electron mobility transistor 200 is in an off state, so the high electron mobility transistor 200 is an enhancement mode (E- Mode) High electron mobility transistor.

Compared with the D-mode high electron mobility transistor, the enhanced (E-mode) high electron mobility transistor is safer, and the standby power dissipation is lower, since no supply is required. Negative bias, too Reduce circuit complexity and manufacturing costs.

In the embodiment shown in FIG. 3, the energy band adjustment layer 210 and the enhancement layer 116 are simultaneously provided, and the heterojunction is formed by using different semiconductor materials, and the energy band structure is adjusted, and the enhancement mode (E-mode) high electrons are used. When the mobility transistor 200 is turned on, the on current can be effectively increased.

Figure 5 is a cross-sectional view of a high electron mobility transistor 300 in accordance with yet another embodiment of the present invention. Processes or elements that are the same as or similar to the previous embodiments will be given the same reference numerals, and the detailed description thereof will not be repeated. The difference from the foregoing embodiment is that the gate electrode 310 is embedded in the barrier layer 106. Before the gate electrode 310 is formed, one or more etching processes may be performed to form a trench in the barrier layer 106, followed by sputtering, resistance heating evaporation, electron beam evaporation, and physical vapor deposition ( Physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), other suitable methods, or combinations thereof, filled with a conductive material in the trench, And patterned to form a gate electrode 310 embedded in the barrier layer 106.

As shown in FIG. 5, a dielectric layer 312 may be disposed between the gate electrode 310 and the barrier layer 106. The dielectric layer 312 has a thickness between 0.1 μm and 1 μm. The dielectric layer 312 includes hafnium oxide, HfO ₂ , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, LaO, ZrO, Ta ₂ O ₅ , a combination of the above, or the like. In some embodiments, chemical vapor deposition (CVD), metalorganic chemical vapor deposition (MOCVD), plasma enhanced CVD (PECVD) may be used. A high density plasma CVD (HDPCVD), atomic layer deposition (ALD), and/or other suitable technique forms a dielectric layer 312 prior to forming the gate electrode 310. The dielectric layer 312 can reduce the gate leakage current. If the thickness of the dielectric layer 312 is too thick, the component speed may be affected. If the thickness of the dielectric layer 312 is too thin, the gate leakage current may be increased.

As shown in FIG. 5, since the gate electrode 310 is embedded in the barrier layer 106, the barrier layer 106 under the gate electrode 310 is compared with the embodiment shown in FIG. The other portions are thinner, the piezoelectric effect becomes smaller, and the energy band structure of the heterojunction of the barrier layer 106 and the buffer layer 104 is changed, so that the two-dimensional electron gas in the channel layer 108 is reduced. Under the material selection of the appropriate gate electrode 310, the high electron mobility transistor 300 can be turned off when no gate voltage is applied, so the high electron mobility transistor 300 is enhanced (enhancement mode, E-mode). High electron mobility transistor. In one embodiment, the barrier layer 106 under the gate electrode 310 has a thickness T and a thickness T between 0.1 μm and 5 μm. If the thickness T is too thick, the two-dimensional electron gas in the channel layer 108 cannot be effectively reduced, and an enhanced (E-mode) high electron mobility transistor cannot be formed. If the thickness T is too thin, the band structure is susceptible to uniform thickness. Degree impact.

In the embodiment shown in FIG. 5, in addition to the enhancement layer 116, the gate electrode 310 is embedded in the barrier layer 106 at the same time, so that the energy band structure is adjusted, so that the enhancement mode (E-mode) is high. When the electron mobility transistor 300 is turned on, the on current can be effectively increased.

Figure 6 is a cross-sectional view of a high electron mobility transistor 400 of still other embodiments of the present invention. Processes or elements that are the same as or similar to the previous embodiments will be given the same reference numerals, and the detailed description thereof will not be repeated. The difference from the foregoing embodiment is that a doping layer 410 is further disposed in the barrier layer 106 under the gate electrode 110. In some embodiments, the doped layer 410 can be formed by an ion implantation step. For example, F ₂ , CF ₄ , or other fluorine-based ions may be implanted in the barrier layer 106 below the predetermined region of the gate electrode 110 using a patterned mask (not shown) prior to forming the gate electrode 110. The doping layer 410 has a doping concentration of between 1e18/cm ³ and 1e20/cm ³ .

As shown in FIG. 6, the doping layer 410 is disposed in the barrier layer 106 under the gate electrode 110, so that the energy band structure of the heterojunction of the barrier layer 106 and the buffer layer 104 can be improved, thereby reducing The two-dimensional electron gas of the channel layer 108. In some embodiments, the high electron mobility transistor 400 is in an off state when no gate voltage is applied, and thus the high electron mobility transistor 400 is an enhancement mode (E-mode) high electron mobility transistor.

In the embodiment shown in FIG. 6, in addition to the enhancement layer 116, a doping layer 410 is disposed in the barrier layer 106 under the gate electrode 110, so that the energy band structure is adjusted to enhance the enhancement mode (E). -mode) When the high electron mobility transistor 400 is turned on, the on current can be effectively increased.

In accordance with some embodiments, FIG. 7 depicts a cross-sectional view of high electron mobility transistor 500. Processes or elements that are the same as or similar to the previous embodiments will be given the same reference numerals, and the detailed description thereof will not be repeated. The difference from the foregoing embodiment is that, in addition to the enhancement layer 116 between the gate electrode 110 and the gate electrode 114, an additional enhancement layer may be formed on the barrier layer 106 in the same process step when the enhancement layer 116 is formed. 116a, followed by an interconnect process to form an inter-layer dielectric (ILD)/intermetal dielectric layer An inter-metal dielectric (IMD) 122 and an interconnect structure 120 formed thereon/and electrically connected to the drain electrode 114 by the interconnect structure 120. The interconnect structure 120 can be formed via a patterned mask (not shown) in conjunction with an etch and deposition process. The etching process can include selective wet etching, selective dry etching, and/or combinations thereof. The deposition process may include sputtering, resistance heating evaporation, electron beam evaporation, physical vapor deposition (PVD), or other suitable deposition methods, and/or combinations thereof. The material of the interconnect structure 120 may be Al, Ag, Cu, AlCu, Pt, W, Ru, Ni, TaN, TiN, TiAlN, TiW, and/or combinations thereof. The interconnect structure 120 includes various metal lines, contacts, vias, and/or combinations thereof.

It is to be noted that the seventh embodiment is only an exemplary cross-sectional view. The embodiment of the present invention is not limited to the electrical connection between the enhancement layer 116a and the drain electrode 114, and the enhancement layer 116a and the gate electrode 110 may also be required according to circuit design requirements. Or the source electrode 112 is electrically connected, or any electrical connection method in which the reinforcing layer 116a is used as a resistor.

In some embodiments, the enhancement layer 116a is electrically coupled to the gate electrode 110, or the drain electrode 114, or the source electrode 112, at which point the enhancement layer 116a is used as a resistor. In the D-mode high electron mobility transistor 500, the enhancement layer 116 that enhances the on current and the enhancement layer 116a that acts as a resistor are formed by the same process. In this way, process cost and time can be saved.

It should be noted that the enhancement layer 116a may also be formed in the enhanced (E-mode) high electron mobility transistors 200, 300, 400 as shown in FIGS. 3, 5, and 6 to enhance the on current. The enhancement layer 116 and the enhancement layer 116a as a resistor are formed by the same process. In this way, process cost and time can be saved.

In summary, the embodiment of the present invention provides a high electron mobility transistor (HEMT) structure, forming a reinforcement layer above the channel layer, and improving the two-dimensional electron gas by changing the energy band structure (two- Dimensional electron gas (2DEG) concentration, which in turn increases the on-current of the D-mode high electron mobility transistor and the enhanced (E-mode) high electron mobility transistor, and can form a resistor for the same process. Circuit design is used.

The above summary is a summary of the features of the various embodiments, and thus, the various aspects of the embodiments of the invention may be understood. Other processes and structures may be designed or modified based on the embodiments of the present invention without departing from the scope of the present invention to achieve the same objectives and/or the same advantages as the embodiments of the present invention. It is to be understood by those skilled in the art that the present invention is not limited to the spirit and scope of the embodiments of the present invention without departing from the spirit and scope of the invention.

Claims (13)

A high electron mobility transistor (HEMT) includes: a buffer layer on a substrate; a barrier layer on the buffer layer; and a channel layer in the buffer layer adjacent to the buffer layer a buffer layer and one of the barrier layers; a gate electrode on the barrier layer; a drain electrode on the barrier layer and located on a first side of the gate electrode; a source An electrode, located on the barrier layer, on a second side of the gate electrode, the first side and the second side are opposite sides of each other; and a first enhancement layer located at the barrier a layer and the channel layer, and between the gate electrode and the drain electrode, are not in direct contact with the gate electrode, the source electrode, and the drain electrode; wherein the first enhancement layer is N Type doped tri-five semiconductors. The high electron mobility transistor according to claim 1, wherein the first enhancement layer comprises N-type doped GaN, AlGaN, AlN, GaAs, AlGaAs, InP, InAlAs, or InGaAs. The high electron mobility transistor according to claim 1, wherein the first enhancement layer has an N-type doping concentration of between 1e17/cm3 and 1e20/cm3. For example, the high electron mobility transistor described in claim 1 further includes: A band adjustment layer is disposed on the barrier layer and electrically connected to the gate electrode; wherein the band adjustment layer is a P-type doped tri-five semiconductor. The high electron mobility transistor according to claim 4, wherein the band adjustment layer comprises P-type doped GaN, AlGaN, AlN, GaAs, AlGaAs, InP, InAlAs, or InGaAs. The high electron mobility transistor according to claim 4, wherein the band adjustment layer has a P-type doping concentration of between 1e17/cm3 and 1e20/cm3. The high electron mobility transistor of claim 1, wherein the gate electrode is embedded in the barrier layer. The high electron mobility transistor according to claim 7, wherein the barrier layer has a thickness under the gate electrode of between 0.1 μm and 1 μm. The high electron mobility transistor according to claim 7, further comprising: a dielectric layer between the gate electrode and the barrier layer. The high electron mobility transistor according to claim 1, further comprising: a doped layer in the barrier layer under the gate electrode; wherein the doped layer comprises fluorine (F). The high electron mobility transistor according to claim 10, wherein the doping layer has a doping concentration of between 1e18/cm3 and 1e20/cm3. Such as the high electron mobility transistor described in claim 1 of the patent scope, Included: a second enhancement layer on the barrier layer; and an interconnect structure connecting the second enhancement layer and the gate electrode, or the gate electrode, or the source electrode. The high electron mobility transistor according to claim 1, wherein the substrate comprises Si, SiC, or Al 2 O 3 (Sapphire).