TWI629762B - Semiconductor package assembly with through silicon via interconnect - Google Patents

Abstract

The present invention provides a semiconductor package component having a TSV interconnect. The semiconductor package component includes a first semiconductor die mounted on a substrate. The first semiconductor die includes a semiconductor substrate. A first array of TSV interconnects and a second array of TSV interconnects are formed from a semiconductor substrate, wherein the first array and the second array of TSV interconnects are separated by a spacer region. The first grounded TSV interconnect is located within the spaced region. The second semiconductor die is mounted on the first semiconductor die with a ground pad thereon. A first ground TSV interconnect of the first semiconductor die has a first terminal coupled to a ground pad of the second semiconductor die and a second terminal coupled to the interconnect structure on a front side of the semiconductor substrate . The invention can effectively increase the integration degree by the above technical solutions.

Description

Semiconductor package component with TSV interconnect

The present invention relates to a semiconductor package component, and more particularly to a semiconductor package component having a TSV interconnect.

In electronic engineering, Through Silicon Via (TSV) is a vertical electrical connection that passes completely through a silicon wafer or die. TSVs are made up of high performance technologies compared to alternatives such as stacked packages. TSV is used to create three-dimensional (3D) semiconductor packages and 3D integrated circuits. Due to the shorter connection length, the density through the TSV is significantly higher than the density of the alternative.

For memory applications that increase the level of integration and increase performance, bandwidth, latency, power, weight, and form factor, the ratio of signal pads to ground pads becomes important to improve coupling.

Therefore, there is a need for a new 3D semiconductor package.

In view of this, the present invention provides the following technical solution: A semiconductor package component interconnected by a via via technology (TSV) is provided. A typical embodiment of a semiconductor package component interconnected with TSVs includes a first semiconductor die mounted on a substrate. The first semiconductor die includes a semiconductor substrate. The first array of TSV interconnects and the second array of TSV interconnects are made of a semiconductor substrate Formed wherein the first array and the second array of TSV interconnects are separated by a spacer region. The first grounded TSV interconnect is located within the spaced region. A second semiconductor die is mounted on the first semiconductor die, the second semiconductor die having a ground pad thereon. The first ground TSV interconnect of the first semiconductor die has a first terminal coupled to the ground pad of the second semiconductor die and a second terminal coupled to the interconnect structure on the front side of the semiconductor substrate.

Another embodiment of a semiconductor package component interconnected with TSVs includes a first semiconductor die mounted on a substrate. The first semiconductor die includes a semiconductor substrate. A first array of TSV interconnects and a second array of TSV interconnects are formed from a semiconductor substrate. The first array and the second array of TSV interconnects are separated by a spacer region. A first ground TSV interconnect is disposed within the spacer region, the first ground TSV interconnect being coupled to an interconnect structure disposed on a front side of the semiconductor substrate. a conductive layer pattern disposed on a back side of the semiconductor substrate, connected to the first ground TSV interconnect and the second ground TSV interconnect of the first array of TSV interconnects to the first semiconductor die, or to the first semiconductor die The first ground TSV interconnect of the second array of TSV interconnects is connected to the second ground TSV interconnect.

Another exemplary embodiment of a semiconductor package component interconnected with TSVs includes a first semiconductor die mounted on a substrate. The first semiconductor die includes a semiconductor substrate. A first array of TSV interconnects and a second array of TSV interconnects are formed from a semiconductor substrate. Wherein the first array and the second array of TSV interconnects are separated by a spacer region. The first ground TSV interconnect is disposed within the spaced region. A first grounded TSV interconnect of the first semiconductor die has a second array of second interconnected TSV interconnects coupled to the first array of TSV interconnects or coupled to a second array of TSV interconnects of the first semiconductor die a terminal and a second end coupled to the input signal ground (Vss) child. The first ground TSV interconnect is separated from the first array of TSV interconnects by a first distance that is greater than a pitch of the first array of TSV interconnects.

The invention can effectively increase the integration degree by the above technical solutions.

500‧‧‧Semiconductor package components

200‧‧‧Base

300‧‧‧First semiconductor die

400‧‧‧Second semiconductor die

302‧‧‧Semiconductor substrate

306‧‧‧ positive

308‧‧‧ back

304‧‧‧Dielectric layer stack structure

318, 320, 322, 324‧‧‧ interconnection structure

310a, 310b, 314, 316, 414‧‧‧TSV interconnection

346‧‧‧ interval area

309a, 311a, 309b, 311b, 317, 319, 313, 315‧‧‧ terminals

334a, 334b, 336, 338, 330, 326a, 326b, 328‧‧‧ conductive bumps

342‧‧‧ Conductive layer pattern

402, 406, 404‧‧‧ pads

346‧‧‧ interval area

410, 420‧‧ Directions

360‧‧‧Area

344-A, 344-B, 344-C, 344D‧‧‧TSV array area

416a, 416b, 418a, 418b, 418c, 418d, 420a, 420b, 420c, 420d, 420e, 420f, 422a1, 422a2, 422b1, 422b2, 424c1, 424c2, 422d1, 422d2, 422a1, 422a2, 422b1, 422b2, 42c1 42c2, 422d1, 422d2, 422e, 422f, 426a, 426b‧‧‧ Grounded TSV Interconnect

1 is a cross-sectional view of a semiconductor package component interconnected by a via via technique in accordance with some embodiments of the present invention.

2 is a bottom plan view of a semiconductor die of a semiconductor package component interconnected by a via via technology, showing the placement of a TSV array region of a semiconductor package, in accordance with some embodiments of the present invention.

3A through 3G are enlarged views of Fig. 2, showing the arrangement of grounded TSV interconnects in spaced regions between TSV arrays, in accordance with some embodiments of the present invention.

The following description is the best mode of operation for carrying out the invention. This description is made to illustrate the general principles of the invention and is not to be construed as limiting. The scope of the invention is determined by reference to the appended claims.

The invention will be described with respect to several specific embodiments in conjunction with the specific drawings, but the invention is not limited thereto but only by the claims. The drawings described are only schematic and are non-limiting. In the figures, the size of some of the elements may be exaggerated and not drawn to scale. The dimensions and relative dimensions do not correspond to the actual dimensions in the practice of the invention.

Figure 1 is a diagram showing a TSV interconnect in accordance with some embodiments of the present invention. A cross-sectional view of a semiconductor package component 500. In some embodiments, semiconductor package component 500 can function as a three-dimensional (3D) semiconductor package component 500. In some embodiments, the 3D semiconductor package component 500 includes at least two vertically stacked semiconductor dies. In this embodiment, the 3D semiconductor package component 500 includes system-on-a-chip (SOC) die, such as logic die, memory die directly stacked on the SOC die, such as a dynamic random access memory. Body (DRAM) package. As shown in FIG. 1, the 3D semiconductor package component 500 includes a first semiconductor die 300 mounted on a substrate 200, and a second semiconductor die 400 stacked on the first semiconductor die 300. In some embodiments, the first semiconductor die 300 is fabricated by TSV technology. The second semiconductor die 400 directly stacked on the first semiconductor die 300 and coupled thereto forms a plurality of TSV interconnects adjacent to the back surface of the first semiconductor die 300. A plurality of conductive bumps are formed adjacent to the front surface of the first semiconductor die 300 bonded to the substrate 200.

As shown in FIG. 1, the first semiconductor die 300 can include a semiconductor substrate 302 having a front side 306 and a back side 308 opposite the front side 306, in accordance with some embodiments of the present invention. In one embodiment, the semiconductor substrate 302 can comprise germanium. In alternative embodiments, germanium germanium, bulk semiconductors, strained semiconductors, composite semiconductors, silicon germanium (SOI), and other general purpose semiconductor substrates can be used as the semiconductor substrate 302. By implanting p-type or n-type impurities in the semiconductor substrate 302, it is possible to have a desired conductivity type. In some embodiments, an integrated circuit device (not shown), such as a transistor, is formed on the front side 306 of the semiconductor substrate 302. A plurality of interconnect structures (including interconnect structures 318, 320, 322, and 324) are formed in dielectric layer stack structure 304 on front side 306 of semiconductor substrate 302. In one embodiment, the interconnect structure 322 can be formed by a contact, a via And a metal layer pattern is formed, and the metal layer pattern is vertically disposed between the contact body and the through hole and/or the plurality of through holes in different levels. The number of metal layer patterns depends on the design of the first semiconductor die 300, and the scope of the present invention is not limited thereto.

In some embodiments as shown in FIG. 1, the first semiconductor die 300 may further include TSV interconnects 310a, 310b, 314, and 316 shaped to pass through the semiconductor substrate 302 from the back side 308 of the semiconductor substrate 302. As shown in FIG. 1, the TSV interconnect 310a is set to have a first array having a pitch P1. Moreover, the TSV interconnect 310b is arranged to have a second array of pitches P2. In some embodiments, the pitch P1 of the first array can be designed to be equal to the pitch P2 of the second array. In some embodiments, the first array of TSV interconnects 310a and the second array of TSV interconnects 310b are used to transfer input/output (I/O), ground, or power signals from the second semiconductor die 400 to the substrate 200. . In some embodiments, the first array of TSV interconnects 310a and the second array of TSV interconnects 310b are separated by a spacer region 346 to follow the pin assignment rules of the second semiconductor die 400 mounted thereon (eg, JEDECWide I/O memory specifications). In some embodiments, the spacer region 346 can have a width W that is greater than a pitch P1 of the first array of TSV interconnects 310a and a pitch P2 of the second array of TSV interconnects 310b. It should be noted that the number of TSV interconnections in the array is defined by the design of the first semiconductor die 300 and the second semiconductor die 400 mounted thereon, and the scope of the present invention is not limited thereto. . Moreover, the number of TSV interconnects of the first array and the second array of TSV interconnects is defined by the design of the first semiconductor die 300 and the second semiconductor die 400 mounted thereon, and the scope of the present invention Not limited to this.

In some embodiments as shown in Figure 1, the first of the TSV interconnections Each TSV interconnect 310a of the array has two terminals 309a and 311a. Terminal 309a is aligned with back side 308 of semiconductor substrate 302, while terminal 311a is adjacent (or aligned) to front side 306 of semiconductor substrate 302. Similarly, in accordance with some embodiments of the present invention, each TSV interconnect 310b of the second array of TSV interconnects has two terminals 309b and 311b. Terminal 309b is aligned with back side 308 of semiconductor substrate 302, while terminal 311b is adjacent (or aligned) to front side 306 of semiconductor substrate 302. In some embodiments as shown in FIG. 1, the terminals 311a of each TSV interconnect 310a of the first array of TSV interconnects may be connected to the first layer metal pattern (M1) of the interconnect structure 318. Moreover, interconnect structures 318 correspond to each TSV interconnect 310a of the first array of TSV interconnects, respectively. In some embodiments as shown in FIG. 1, the terminals 311b of each TSV interconnect 310b of the second array of TSV interconnects may be connected to the first layer metal pattern (M1) of the interconnect structure 322. Moreover, interconnect structures 322 correspond to TSV interconnects 310b of the second array of TSV interconnects, respectively.

In some embodiments as shown in FIG. 1, conductive bumps 334a, 334b, 336, 338 are located on interconnect structures 318, 320, and 324 of first semiconductor die 300 and are in contact with substrate 200. Conductive bumps 334a, 334b, 336, 338 may be coupled to interconnect structures 318, 320, 322, and 324 by a redistribution layer (RDL) pattern formed over dielectric layer stack 304. Conductive bumps 334a are disposed to correspond to an array of first arrays of TSV interconnects 310a and to respective TSV interconnects 310a. Moreover, conductive bumps 334b are disposed to correspond to an array of second arrays of conductive bumps 326b.

In some embodiments as shown in FIG. 1, the second semiconductor die 400 is mounted on the first semiconductor die 300. In some embodiments, the second semiconductor die 400 can include a memory die, such as a dynamic random access memory. (DRAM) die with a plurality of pads 402, 404 and 406 on the second semiconductor die 400 for transmitting input/output, ground or power signals generated by the integrated circuit device and/or circuitry therein. As shown in FIG. 1, the pads 402 of the second semiconductor die 400 are disposed on the array, and the pads 406 are also disposed on the other array. The array of pads 402 and the array of pads 406 are separated from each other by spaced regions (corresponding to the spacer regions 346) to follow stitch assignment rules (eg, JEDECWide I/O memory specifications). As shown in FIG. 1, the first array of TSV interconnects 310a of the first semiconductor die 300 corresponds to an array arrangement of pads 402. Moreover, the second array of TSV interconnects 310b of the first semiconductor die 300 corresponds to an array arrangement of pads 406. The pad 402 of the second semiconductor die 400 is coupled to the TSV interconnect 310a of the first semiconductor die 300 by conductive bumps 326a disposed on the terminals 309a of the TSV interconnect 310a. The conductive bumps 326a are in contact with the pads 402 of the second semiconductor die 400 and the TSV interconnects 310a of the first semiconductor die 300. The pad 406 of the second semiconductor die 400 is coupled to the TSV interconnect 310b of the first semiconductor die 300 by conductive bumps 326b on the terminals 309b of the TSV interconnect 310b. The conductive bumps 326b are in contact with the pads 406 of the second semiconductor die 400 and the TSV interconnects 310b of the first semiconductor die 300. It should be noted that the dimensions (e.g., width) of the conductive bumps 326a and 326b are designed to be smaller than the dimensions (e.g., width) of the conductive bumps 334a, 334b, 336, and 338.

2 is a bottom view of the first semiconductor die 300 of the semiconductor package component 500 as shown in FIG. 1. FIG. 2 shows the arrangement of the TSV array regions from the back side 308 of the semiconductor substrate 302. To describe the coupling effects between the TSV array regions 344-A, 344-B, 344-C, and 344-D, the TSV interconnects 314 and 316 are not described herein. In some embodiments, four array regions, for example The TVS array regions 344-A, 344-B, 344-C, and 344-D are disposed within the semiconductor substrate 302 of the first semiconductor die 300. Each of the array regions 344-A, 344-B, 344-C, and 344-D provides a TSV interconnect array located therein (eg, a first array or TSV of TSV interconnects 310a as shown in FIG. 1) A second array of interconnects 310b). TSV interconnect arrays located within TSV array regions 344-A, 344-B, 344-C, and 344-D are used to input/output (I/O), ground, or power signals from memory die (eg, The second semiconductor die 400) is transferred to the substrate 200. Moreover, the TSV array regions 344-A, 344-B, 344-C, and 344-D are separated from each other by a spacer region 346. In some embodiments, the spacing regions 346 are cruciform and extend in mutually perpendicular directions 410 and 420. It should be noted that the number of TSV interconnect arrays is defined by the design of the first semiconductor die 300 and the second semiconductor die 400 mounted thereon, and the scope of the present invention is not limited thereto. Accordingly, the spacing region 346 may have various shapes disposed corresponding to the TSV array region, and the scope of the present invention is not limited thereto.

As shown in FIG. 2, the proportions of grounded TSV signals interconnected to the spaced regions 346 disposed within the TSV array regions 344-A, 344-B, 344-C, and 344-D and adjacent to the direction 410 may be different. The proportion of grounded TSV signal interconnections to the spacing region 346 near the direction 420. For example, to follow the JEDECWide I/O memory specification, the proportion of ground TSV signal interconnections to the spacing area 346 near the direction 410 is less than the proportion of grounded TSV signal interconnections to the spacing area 346 near the direction 420. Therefore, the coupling effect between the TSV array regions 344-A and 344-B can be different from the coupling effect between the TSV array regions 344-A and 344-D (or the interior of the TSV array region 344-A). For example, the coupling between TSV array regions 344-A and 344-B is much smaller than the TSV array region. Coupling between 344-A and 344-D (or inside TSV array region 344-A).

In some embodiments as shown in FIG. 1, the first semiconductor die 300 of the semiconductor package component 500 can have one or more ground TSV interconnects, such as ground TSV interconnects 314 and/or 316, disposed in Within the spacing area 346. Grounded TSV interconnects 314 and/or 316 are designed to provide additional ground vias to balance between multiple TSV array regions (344-A through 344-D) along different directions (eg, directions 410 and 420) Coupling effect. In some embodiments, the ground TSV interconnect 314 has a first terminal 313 aligned with the back side 308 of the semiconductor substrate 302 and a second terminal 315 opposite the first terminal 313. The first terminal 313 of the TSV ground structure 314 is designed to be coupled to an additional ground pad 404 of the second semiconductor die 400. In some embodiments, the additional ground pad 404 of the second semiconductor die 400 also provides an additional ground via to balance the coupling effects between the array regions of the pads (eg, pads 402 and 406). Moreover, the second terminal 315 of the ground TSV interconnect 314 is designed to be coupled to an additional interconnect structure 324 located on the front side 306 of the semiconductor substrate 300. In some embodiments, the second terminal 315 of the ground TSV interconnect 314 can be coupled to the input signal ground (Vss) through the interconnect structure 324. Moreover, interconnect structure 324 is coupled to substrate 200 by conductive bumps 336. As shown in FIG. 1, the ground TSV interconnect 314 is separated from the first array of TSV interconnects 310a and the second array of TSV interconnects 310b by a first distance A1 and a second distance A2, respectively. In some embodiments, at least one of the first distance A1 and the second distance A2 is designed to be larger than the pitch P1 of the first array of TSV interconnects 310a or the pitch P2 of the second array of TSV interconnects 310b.

As shown in FIG. 1, the ground TSV interconnect 316 has a first terminal 317 aligned with the back surface 308 of the semiconductor substrate 302 and a first electrode 317 opposite the first terminal 317 Two terminals 319. In some embodiments, a conductive layer pattern 342, such as a redistribution layer (RDL) pattern 342, is designed to be located on the back side 308 of the semiconductor substrate 302. Conductive layer pattern 342 is coupled to first terminal 317 of ground TSV interconnect 316 and to a grounded TSV interconnect of a first array of TSV interconnects or a second array of TSV interconnects of first semiconductor die 300. For example, as shown in FIG. 1, the conductive layer pattern 342 is connected to the first terminal 317 of the ground TSV interconnect 316 and the first terminal 309b of the ground TSV interconnect, the first terminal 309b belonging to the second of the TSV interconnect 310b. Array. The grounded TSV interconnect 316 can also be coupled to the ground pad (one of the pads 406) of the second semiconductor die 400 by conductive bumps 330 on the grounded TSV interconnects belonging to the second array of interconnects 310b. . In some embodiments, the second terminal 319 of the ground TSV interconnect 316 can be coupled to the input signal ground (Vss) via an interconnect structure 320 located on the front side 306 of the semiconductor substrate 300. Moreover, the interconnect structure 320 is coupled to the substrate 200 by conductive bumps 338. As shown in FIG. 1, the grounded TSV interconnect 316 is separated from the first array of TSV interconnects 310a and the second array of TSV interconnects 310b by a first distance B1 and a second distance B2, respectively. In some embodiments, at least one of the first distance B1 and the second distance B2 is designed to be larger than the pitch P1 of the first array of TSV interconnects 310a or the pitch P2 of the second array of TSV interconnects 310b. Thus, the additional ground TSV interconnects 314 and/or 316 of the first semiconductor die 300 can be used to balance the array of pads 402 and 406 of the second semiconductor die 400 in different directions (eg, directions 410 and 420). The coupling effect between.

3A through 3G are enlarged views of area 360 in FIG. 2 showing grounded TSVs located within spaced regions 346 between TSV array regions 344-A through 344-D, in accordance with some embodiments of the present invention. Interconnected devices Set. As shown in Figures 3A through 3G, element G acts as a grounded TSV interconnect with TSV array regions 344-A through 344-D. Element S/P acts as a signal or power TSV interconnect in TSV array regions 344-A through 344-D. In some embodiments, as shown in FIG. 3A, only one grounded TSV interconnect 414 can be located within the bay region 346. The grounded TSV interconnect 414 can be configured to be close to portions along the direction 420 for balancing coupling effects between the TSV array regions 344-A through 344-D along different directions (eg, directions 410 and 420). Figures 3B through 3G show dual grounded TSV interconnects (grounded TSV interconnects 416a and 416b) disposed within bay area 346, four TSV interconnects (grounded TSV interconnects 418a through 418b), six TSV interconnects (grounded TSVs) Interconnects 420a through 420f), eight TSV interconnects (grounded TSV interconnects 422a1, 422a2, 422b1, 422b2, 42c1, 42c2, 422d1, and 422d2), ten TSV interconnects (grounded TSV interconnects 422a1, 422a2, 422b1, 422b2) 424c1, 424c2, 422d1, 422d2, 422e, and 422f), and twenty grounded TSV interconnects (eg, ten grounded TSV interconnects 426a and another ten grounded TSV interconnects 426b arranged in a row along 420) . Similarly, the ground TSV interconnects illustrated in Figures 3B through 3G can be disposed within the spacer region 346. The grounded TSV interconnect 414 can be configured to be close to portions along the direction 420 for balancing coupling effects between the TSV array regions 344-A through 344-D along different directions (eg, directions 410 and 420).

The embodiments as shown in Figures 1 through 3G provide various grounded TSV interconnect arrangements for three-dimensional (3D) semiconductor package components 500. The 3D semiconductor package component 500 includes a first semiconductor die 300, such as a logic die, on a substrate 200 and provided to a second semiconductor die 400, such as a directly stacked DRAM die. At least one grounded TSV interconnect 314 and/or 316 is designed to be spaced apart for separating the TSV array regions 344-A through 344-D of the semiconductor die 300. Within the compartment. Additional ground TSV interconnects 314 and/or 316 are designed to provide additional ground vias for balancing coupling effects between TSV array regions 344-A through 344-D along different directions (eg, directions 410 and 420). An additional grounded TSV interconnect located within the spacing region 346 has a first terminal and a second terminal. The first terminal and the second terminal are coupled to a ground pad of the second semiconductor die 400 and an interconnect structure on the front side 306 of the semiconductor substrate 300, respectively. In some embodiments, the first terminal is aligned with the back side of the first semiconductor die 300 and is coupled to the ground pad of the second semiconductor die 400 by conductive bumps thereon. In some other embodiments, the first terminal aligned with the back side of the first semiconductor die 300 is coupled to at least one of the first array of TSV interconnects 310a by a conductive layer pattern 342, such as a redistribution layer (RDL) pattern. A ground TSV interconnect is coupled to or coupled to a second array of TSV interconnects 310b of the first semiconductor die 300. In some embodiments, the second terminal of the additional ground TSV interconnect can be coupled to the input signal ground (Vss) via an interconnect structure located thereon. Thus, the additional ground TSV interconnect of the first semiconductor die 300 can be used to balance the coupling effects between the pads 402 and 406 arrays of the second semiconductor die 400 along different directions (eg, directions 410 and 420).

The invention is described by way of example and with reference to the preferred embodiments thereof Rather, it is suitable for covering a wide variety of variations and similar arrangements (as will be apparent to those skilled in the art). Accordingly, the scope of the appended claims should be accorded

Claims (18)

A semiconductor package component having a TSV interconnect, comprising: a first semiconductor die mounted on a substrate, the first semiconductor die comprising: a semiconductor substrate; and a conductive on a back surface of the semiconductor substrate a layer pattern; a first array of TSV interconnects formed by the semiconductor substrate and a second array of TSV interconnects, wherein the first array and the second array of the TSV interconnects are separated by a spacer region; a first ground TSV interconnect in the spacer region; and a second semiconductor die mounted on the first semiconductor die, the second semiconductor die having a ground pad, the ground pad corresponding to The first array of TSV interconnects or the second ground TSV of the second array of TSV interconnects, wherein the first grounded TSV interconnect of the first semiconductor die has a second coupled to the second a first terminal on the ground pad of the semiconductor die and a second terminal coupled to the interconnect structure on a front side of the semiconductor substrate, and wherein the conductive layer pattern and the first ground TSV are mutually And the second ground T The first terminals of the SV interconnect are connected. The TSV interconnected semiconductor package component of claim 1, wherein the first terminal is adjacent to a back surface of the semiconductor substrate opposite the front surface. A TSV interconnected semiconductor package component as described in claim 1 Characterized in that the second terminal is aligned with the front side of the semiconductor substrate. The TSV interconnected semiconductor package component of claim 1, wherein the second terminal is connected to the first layer metal pattern of the interconnect structure. The TSV interconnected semiconductor package component of claim 1, wherein the spacer region has a pitch that interconnects the first array with the TSV and a second array of the TSV interconnect. The width is large. The TSV interconnected semiconductor package component of claim 1, wherein the second terminal is coupled to the input signal ground. The TSV interconnected semiconductor package component of claim 1, wherein the first semiconductor die further comprises: a conductive bump on the first semiconductor die and connected to the substrate a first array and a second array of blocks, wherein a first array of conductive bumps corresponds to a first array of the TSV interconnects, and a second array of conductive bumps corresponds to a first of the TSV interconnects Two arrays. The TSV interconnected semiconductor package component of claim 7, wherein the first semiconductor die further comprises: the spacer region on the first semiconductor die and a first ground conductive bump connected to the substrate, wherein the first ground conductive bump is coupled to the first ground TSV interconnect. A semiconductor package component having a TSV interconnect, comprising: a first semiconductor die on a substrate, the first semiconductor die comprising: a semiconductor substrate; a first array of TSV interconnects formed by the semiconductor substrate and a second array of TSV interconnects, wherein the first array and the second array of the TSV interconnects are separated by a spacer region; and at the interval a first ground TSV interconnect in the region coupled to the interconnect structure on the front side of the semiconductor substrate; and a conductive layer pattern on the back side of the semiconductor substrate, the same as the first semiconductor die The first grounded TSV interconnect of the first or second array of TSV interconnects is connected to the second grounded TSV interconnect. The TSV interconnected semiconductor package component of claim 9, further comprising: a second semiconductor die mounted on the first semiconductor die, the second semiconductor die There is a ground pad thereon, wherein the conductive layer pattern of the first semiconductor die is coupled to the ground pad of the second semiconductor die. The TSV interconnected semiconductor package component of claim 9, wherein the spacer region has a pitch that interconnects the first array with the TSV and a second array of the TSV interconnect. The width is large. The TSV interconnected semiconductor package component of claim 9, wherein the first semiconductor die further comprises: a conductive bump on the first semiconductor die and connected to the substrate a first array and a second array of blocks, wherein a first array of conductive bumps corresponds to a first array of the TSV interconnects, and a second array of conductive bumps corresponds to a first of the TSV interconnects Two arrays. A semiconductor package component interconnected by TSV as described in claim 12, The first semiconductor die further includes: a first ground-pair conductive bump located in the spacer region on the first semiconductor die and connected to the substrate, wherein the first ground conductive A bump is coupled to the first ground TSV interconnect. A semiconductor package component having a TSV interconnect, comprising: a first semiconductor die mounted on a substrate, the first semiconductor die comprising: a semiconductor substrate; TSVs formed by the semiconductor substrate a first array of connected and a second array of TSV interconnects, wherein the first array and the second array of the TSV interconnect are separated by a spacer region; and the first ground TSVs located within the spacer region are interconnected, Wherein the first ground TSV interconnect of the first semiconductor die has a second ground TSV interconnect coupled to the first array or the second array of the TSV interconnect of the first semiconductor die a first terminal and a second terminal coupled to the input signal ground, and wherein the first ground TSV interconnect is separated from the first array of the TSV interconnect by a first distance, the first distance Greater than the pitch of the first array of TSV interconnects. The semiconductor package component with a TSV interconnect according to claim 14, wherein the first semiconductor die further comprises: a conductive layer pattern on a back surface of the semiconductor substrate, A ground TSV interconnect is coupled to the first terminal of the second ground TSV interconnect. The semiconductor package component interconnected by the TSV according to claim 15, wherein the method further comprises: a second semiconductor die mounted on the first semiconductor die, the second semiconductor die having a ground pad thereon, wherein the conductive layer pattern of the first semiconductor die is coupled to the first On the ground pad of the second semiconductor die. The TSV interconnected semiconductor package component of claim 14, wherein the first semiconductor die further comprises: a conductive bump on the first semiconductor die and connected to the substrate a first array and a second array of blocks, wherein a first array of conductive bumps corresponds to a first array of the TSV interconnects, and a second array of conductive bumps corresponds to a first of the TSV interconnects Two arrays. The TSV interconnected semiconductor package component of claim 14, wherein the first semiconductor die further comprises: the spacer region on the first semiconductor die and a first ground conductive bump connected to the substrate, wherein the first ground conductive bump is coupled to the first ground TSV interconnect.