TWI628734B - Susceptor for improved epitaxial wafer flatness and methods for fabricating a semiconductor wafer processing device - Google Patents

Abstract

A susceptor for supporting a semiconductor wafer during an epitaxial chemical vapor deposition process, the susceptor defining a wafer diameter, the pedestal comprising a substantially cylindrical surface having an opposite upper surface and a lower surface Shaped body part. The body portion has a diameter that is greater than one of the diameters of the wafer. The base includes a plurality of sets of apertures circumferentially disposed along a first pedestal diameter, the set of apertures being evenly spaced relative to adjacent apertures and extending through the upper surface and the lower surface in a region. The first pedestal has a diameter greater than the diameter of the wafer and omits a hole along the first diameter in a predetermined orientation.

Description

Base for improved epitaxial wafer flatness and method for manufacturing semiconductor wafer processing apparatus

The field of the invention relates generally to semiconductor wafer processing, and more particularly to susceptors and related methods for epitaxial processing.

Epitaxial chemical vapor deposition is a procedure used to grow a thin layer of material on a semiconductor wafer such that the lattice structure is identical to the lattice structure of the wafer. Using this procedure, one layer having a different conductivity type, dopant species, or dopant concentration can be applied to a semiconductor wafer to achieve the necessary electrical characteristics. Epitaxial chemical vapor deposition is widely used in semiconductor wafer fabrication to build epitaxial layers so that the device can be fabricated directly on the epitaxial layer. For example, a lightly doped epitaxial layer deposited over a heavily doped substrate allows a CMOS device to be optimized for latch-up immunity due to the low resistivity of the substrate. Other advantages are also achieved, such as precise control of dopant concentration distribution and oxidation resistance.

Prior to epitaxial deposition, the semiconductor wafer is typically mounted on one of the susceptors in a deposition chamber. The epitaxial deposition process begins by preheating and cleaning the front surface of the wafer by introducing a cleaning gas such as hydrogen or a mixture of hydrogen and hydrogen chloride to one of the front surfaces of the wafer (i.e., facing away from one of the surfaces of the susceptor). The purge gas removes the native oxide from the front surface, allowing the epitaxial layer to continuously and uniformly grow on the surface during one subsequent step of the deposition process. Epitaxial The accumulation process continues by introducing a gaseous helium source gas (such as decane or decane) to the front surface of the wafer to deposit on the front surface and to grow an epitaxial layer. One of the back surfaces of the pedestal opposite the front surface can simultaneously be subjected to hydrogen gas. The susceptor supporting the semiconductor wafer in the deposition chamber during epitaxial deposition is rotated during the process to ensure uniform growth of the epitaxial layer.

The epitaxial delta edge drop (DERO) is often an undesirable effect of epitaxial deposition because it can negatively affect flatness. In conventional single crystal germanium wafers, DERO varies in orientation depending on the orientation of the crystal lattice. The flatness of the wafer can usually be measured by an amount called SFQR, SBIR, ROA, ERO, ESFQR, ESFQD, and the like. In a conventional (100) oriented germanium wafer, there are four equidistant points around the circumference of the wafer that correspond to the <110> equivalent direction. In conventional wafers, DERO can be maximized in a particular direction (specifically, <110> direction). On the edge profile (including the edge bevel and one of the beveled faces between the edge bevel and the side surface of the wafer), there is typically an exposed surface near the (311) orientation. The epitaxial growth on the surface of the wafer (311) is hindered by the large density of surface atoms on the (311) plane of the wafer. Thus, during processing, the gas flow passes through the (311) surface of the wafer to the front and back surfaces of the near edge of the wafer, causing the ruthenium precursor to be depleted to a lesser extent. The result is an increase in the growth rate near the (311) surface, which can result in one of the large DEROs in these regions. The epitaxial DERO on the germanium wafer undesirably affects the flatness of the wafer, especially near the edge of the wafer. Therefore, there is still a need for a system and method for processing a wafer to reduce variations in DERO.

One aspect relates to a susceptor for supporting a semiconductor wafer during an epitaxial chemical vapor deposition process. The pedestal defines a wafer diameter. The pedestal includes a substantially cylindrical body portion having an opposing upper surface and a lower surface, the body portion having a diameter greater than one of the diameters of the wafer. A set of holes in the body portion are circumferentially arranged along a first diameter. The set of apertures are evenly spaced relative to adjacent apertures and extend through the upper surface and the lower surface. The first diameter is greater than the diameter of the wafer and there is no along the first diameter in a predetermined set of orientations hole.

Another aspect relates to a susceptor that defines the diameter of a wafer. The pedestal includes a substantially cylindrical body portion having an opposing upper surface and a lower surface, the body portion having a diameter greater than one of the diameters of the wafer. A set of apertures extends through the upper surface and the lower surface a given diameter of the base other than radially outside the diameter of the wafer. One of the sets of holes has a density that varies circumferentially around the given diameter.

In still another aspect, a method of fabricating a semiconductor processing apparatus includes providing a pedestal comprising a substantially cylindrical body portion having opposing upper and lower surfaces, the body portion having greater than one wafer One diameter of the diameter. The method also includes providing a set of apertures circumferentially disposed along a first pedestal diameter, the set of apertures being evenly spaced relative to adjacent apertures and extending through the upper surface and the lower surface in a region. The first pedestal has a diameter greater than the diameter of the wafer and omits apertures along the first diameter in a predetermined set of orientations.

In still another aspect, a method of processing a wafer in an epitaxial chemical vapor deposition process includes providing a pedestal having a plurality of holes, the plurality of holes being larger than one of the wafers to be processed One of the diameters is arranged circumferentially. The method also includes placing the unprocessed wafer on the susceptor in a predetermined orientation such that the <110> direction of the wafer is aligned with the portion of the pedestal without the diameter of the unprocessed wafer and chemically treated The wafer.

1A‧‧‧ position

1B‧‧‧Location

1C‧‧‧ position

1D‧‧‧ position

3A‧‧‧Area

3B‧‧‧Area

10‧‧‧Test base

20‧‧‧Base/base of the base

30‧‧‧through hole

35‧‧‧ hole/edge difference (DERO) hole

40‧‧‧ Center

50‧‧‧<110>Location

AA‧‧Azimuth

C‧‧‧ benchmark

DV‧‧‧ edge difference (DERO) value

H‧‧‧Horizontal/horizontal axis

RH‧‧‧radial distance/outer hole radius/hole radius

RS‧‧‧ base radius

RW‧‧‧ wafer radius

T‧‧‧ thickness

1 is a top plan view of a test susceptor in accordance with one embodiment of the present invention.

1A through 1D are detailed views of the base of Fig. 1.

2 is a graph showing a change in the orientation of the DERO of one of the wafers processed on the susceptor of FIG.

3 is a top plan view of one embodiment of a susceptor in accordance with the present invention.

3A and 3B are detailed views of the base of Fig. 3.

4 is a top plan view of another embodiment of a pedestal.

4A and 4B are detailed views of the base of Fig. 4.

Figure 5 is a cross section of the base of Figure 4.

Figure 5A is a detailed view of one of the bases of Figure 5.

Referring now to the drawings, and in particular to FIG. 1, a test pedestal is generally indicated at 10. The shape of the base 10 of this embodiment is substantially circular, but other shapes are also contemplated. The susceptor is adapted to support a semiconductor wafer (not shown) in a deposition chamber, such as a chemical vapor deposition (CVD) chamber, during a CVD process. In this embodiment, the semiconductor wafer has a wafer radius RW that is less than one of the pedestal radii RS of the susceptor 20. In this embodiment, the wafer radius is about 150 mm, but may be other radii between about 25 mm and about 300 mm, such as about 25.5 mm, 50 mm, 75 mm, 100 mm, 150 mm, 200. Mm, 225 mm, 300 mm, etc. However, the wafer radius RW and the pedestal radius RS of the susceptor 20 may be any radius that allows the pedestal to operate as described herein.

In this embodiment, the base 10 has a dish-like body 20 having a center 40. The body 20 is substantially planar and includes a plurality of through holes 30. The through hole 30 is configured in a pattern such as a grid pattern or the like, and may include a through hole positioned at one of the centers 40. In this example, each of the through holes is positioned a predetermined distance from the center 40 and at a predetermined angle to the center 40. The angle is measured with reference to the horizontal line H, wherein the positive angle increases toward a counterclockwise direction.

Without being bound by a particular theory, a CVD process tends to deposit a small amount of germanium on the back side of the wafer and can be relative to the area within the edge (within a few millimeters, for example, 5 mm to the edge of the wafer) Thicken the near edge region of the wafer within 6 mm, within 3 mm to 4 mm, or within 1 mm to 2 mm. This thickening can increase the DERO.

In this embodiment, the particular vias 35 in the pedestal are arranged at a radial distance RH just outside the radius of the wafer to reduce azimuthal DERO variations. The aperture 35 outside the radius of the wafer may tend to increase the DERO near the aperture. In one embodiment, to reduce the variation of DERO by angle, a hole 35 is added where DEO is the smallest. For example, near the <110> direction The point has a DERO that is higher than other points typical on the wafer, and the point near the outside of the hole has a DERO that is higher than other points typical on the wafer. Therefore, in this embodiment, the hole 35 is added outside the wafer radius RW according to the hole radius RH such that the DERO between the <110> directions substantially matches the DERO in the <110> direction, thereby reducing the DERO fluctuation. In this embodiment, the average total DERO of the entire wafer edge is increased compared to one of the wafers fabricated on one of the pedestals that are not added outside the wafer radius 35. There is a reduction in DERO variation around the edge of the wafer to achieve a better match between the epi-dee (epi) DERO and the incoming wafer ERO, resulting in good flatness. The azimuthal DERO variation is reduced by including holes 35 just outside the radius of the wafer (except in the vicinity of the <110> direction).

To test the effect of changing the angular position of the apertures 35, a different number of apertures are added at positions 1A, 1B, 1C and 1D shown in Figure 1 according to an external aperture radius RH. When angle measurement is referred to herein, a convention in which 0 degrees is on the right side of the horizontal axis H and the angle is increased counterclockwise is used.

In the embodiment of FIG. 1, the susceptor 20 has a <110> notched wafer disposed at 150.6 mm and spaced at approximately 90 degrees (the recess is positioned at a reference C (ie, 270 degrees)). 100> Align the DEO hole 35 (added outside the wafer radius). Holes 35 are added to locally increase the DERO for the holes. At the <110> position, DERO is the largest. A detail view of each of positions 1A to 1D is shown in FIG. 1 as FIGS. 1A, 1B, 1C, and 1D. At position 1B, five holes are added over a 6 degree span corresponding to a 45 degree angle (measured according to the angle convention used by the KLA-Tencor WaferSight (WS) tool). Each of the holes has a diameter of 0.9 mm and a variation of one or more of 0.05 mm. At position 1A, eleven holes are added over a 15 degree span corresponding to a 135 degree angle. Each of the holes has a diameter of 0.9 mm and a variation of one or more of 0.05 mm. At position 1C, seven holes are added within a 9 degree span corresponding to a 225 degree angle. Each of the holes has a diameter of 0.9 mm and a variation of one or more of 0.05 mm. At position 1D, fifteen holes are added over a 21 degree span corresponding to a 315 degree angle. Each of the holes has a diameter of 0.9 mm And add or subtract one of the 0.05 mm variants.

2 shows a graph of the DERO value DV as a function of one of the azimuth angles AA of one of the wafers processed on the test susceptor of FIG. 1 with the above-described holes added at positions 1A to 1D. The angle shown in Figure 2 corresponds to the angle measured by the WS tool. In Fig. 2, the DERO value DV is measured in units of nanometers. The peak value of the DRO value DV at 40 degrees, 130 degrees, 220 degrees, and 310 degrees may be the result of adding one of the holes 35 at the outer positions 1A to 1D of the wafer radius. These peaks do not exist for wafers processed on conventional pedestals. The peak value of the DERO values at 0, 90, 180, and 270 degrees is due to the <110> effect. The DERO value DV is measured at a 148 mm wafer radius. These results indicate that the DERO increases by approximately 15 nm with the pores spaced approximately 1.5 degrees apart. Therefore, in order to make the DERO at the <110> position away from the wafer substantially match the DERO at the <110> position, apply 22.5 nm. One of the response coefficients calculates a hole density for the angle between the <110> directions. The calculation results are shown in Table 1:

3 shows another illustrative embodiment of a susceptor 20 having one of the hole spacings of Table 1. In this embodiment, the aperture 35 is arranged at a radius RH of approximately 150.6 mm for a wafer radius RW of 150 mm. In this embodiment, the hole 35 outside the wafer radius at a position plus or minus 9 degrees from the <110> direction of the wafer is omitted. The aperture 35 has a diameter of about 0.9 mm, although other diameters and radii may be used. Figure 3A shows one of the areas 3A of the susceptor 10 Section view. FIG. 3B shows a detailed view of a region 3B of the base 10.

In the embodiment of Figure 4, the aperture 35 is arranged for a radius RW of about 150.6 mm for one of the 150 mm wafer radii RW. In this embodiment, the aperture 35 outside the wafer radius at the orientation plus or minus 10 degrees of the <110> direction of the wafer is omitted. In contrast, in the test pedestal of Figure 1, the angle range of the omitted holes is different for each of the four <110> directions. In this embodiment, as shown in detail 4A (Fig. 4A), the holes are positioned at the following angular positions: 45.0 degrees, 43.9 degrees, 42.8 degrees, 41.7 degrees, 40.6 degrees, 39.5 degrees, 38.4 degrees, 37.3 degrees, 36.2. Degree, 35.1, 34.0, 32.9, 31.8, 30.7, 29.6, 28.4, 27.2, 26.0, 24.8, 23.6, 22.4, 21.1, 19.8, 18.4, 17.0, 15.5 degrees, 14.0 degrees, 12.3 degrees and 10 degrees. The aperture pattern can be reflected (ie, symmetric) with respect to a 45 degree line and repeated up to four times (ie, the same in each quadrant). Detail 4B (Fig. 4B) shows that the holes are omitted within 10 degrees of the <110> position 50.

In an epitaxial CVD reactor of one embodiment, there are two processing chambers, chamber A and chamber B. In one mode of operation, the wafer processed in chamber A is rotated such that the wafer notch is 7 degrees counterclockwise from the reference C position. The wafer processed in chamber B rotates the wafer notch 7 degrees clockwise along the reference C position. In one embodiment, in order to accommodate the difference in alignment between the wafer and the pedestal, the wafer is pre-aligned in a cassette such that the notch corresponds to the chamber (the wafer will be processed therein (ie, the cavity) Room A or chamber B)) in one direction. In another embodiment, the pattern of the through holes 30 may be rotated corresponding to the chamber A or the chamber B. In yet another embodiment, the misalignment of the wafer crystal direction plus or minus 7 degrees and the pattern of holes added outside the wafer diameter can be ignored.

FIG. 5 shows a cross section of the susceptor 10. The base 10 has a thickness T. The aperture 35 outside the wafer radius RW extends completely through the thickness T of the body 20 of the base 10.

In other embodiments, the wafer may have a notch positioned in one of the directions other than the <110> direction, such as the <100> direction. As shown in FIG. 3, for a wafer having a recess of <100> direction, the wafer can be loaded on the susceptor 20 such that the recess is approximately 45 degrees from the reference C position, 135 Degree, 225 degrees, or 315 degrees. However, other wafer notch locations are contemplated in accordance with the present invention.

The articles "a", "an" and "the" are intended to mean the presence of one or more of the elements. The terms "including", "comprising" and "having" are intended to include and mean that there may be additional elements other than the listed elements.

Since many changes can be made in the above-described apparatus and methods without departing from the scope of the invention, it is intended that all matters contained in the above description and illustrated in the drawings should be construed as illustrative rather than Limit meaning.

Claims (10)

A method of processing a wafer in an epitaxial chemical vapor deposition process, the method comprising: providing a susceptor having a plurality of holes, the plurality of holes being larger than a diameter of one of the wafers to be processed One diameter circumferentially disposed; the unprocessed wafer is placed on the susceptor in a predetermined orientation such that the <110> direction of the wafer and the pedestal are not from the unprocessed wafer The portion of the diameter of the outer hole is aligned; and the wafer is chemically processed. The method of claim 1, further comprising measuring a delta edge roll off at a predetermined diameter of the wafer. The method of claim 1, wherein the placing the unprocessed wafer on the pedestal comprises: placing the wafer on the pedestal such that the holes having no holes outside the wafer diameter are <110 > The direction is approximately plus or minus 9 degrees. The method of claim 1, wherein placing the unprocessed wafer on the pedestal comprises: placing the wafer on the pedestal such that the hole has no holes outside the wafer diameter of the wafer <110> The direction is approximately plus or minus 10 degrees. The method of claim 1, wherein providing the base comprises providing the plurality of holes in groups, each of the groups being arranged at an interval of 90 degrees from an adjacent group. The method of claim 1, wherein providing the pedestal comprises providing the plurality of apertures with an interval between about 1 and 4 degrees between the apertures. The method of claim 1, wherein the wafer diameter is between about 150 millimeters (mm) and about 300 millimeters. The method of claim 1, wherein each of the holes has a diameter of between about 0.8 mm and about 1.0 mm. The method of claim 1, wherein providing the pedestal comprises providing the plurality of holes by circumferentially varying a hole density around the diameter of the pedestal. The method of claim 9, wherein the pore density varies from about 0.25 pores per degree to about 1.0 pores per degree.