TWI627732B - Twin-bit flash memory cell structure and fabrication thereof - Google Patents

Abstract

A two-bit flash memory structure includes a selection gate oxide layer on a substrate, a selection gate contained in the selection gate oxide layer, and a set of composite gate layers on each side of the selection gate. . Each composite gate layer includes a floating gate oxide layer, a floating gate electrode, a composite material layer, a control gate electrode and a partition wall. Floating silica is on the substrate. The floating gate is located on the floating oxide layer. The composite material layer is located on the floating gate. The control gate is located on the composite layer. The gap wall is located on the control gate.

Description

Double-bit flash memory memory structure and manufacturing method thereof

The present invention generally relates to a memory structure and a manufacturing method thereof. In particular, the present invention is directed to a flash memory structure capable of storing double bits in a single memory cell and a method for manufacturing the same.

Generally speaking, memory can be divided into random access memory (RAM-Random Access Memory) and read-only memory (ROM-Read Only Memory), and read-only memory can also be called nonvolatile memory (nonvolatile memory) memory). Non-volatile memory retains stored information even when power is not supplied. In addition, some non-volatile memory can be programmed and erasable. Non-volatile memory is a memory component used to store structural data, program data, and the like in various electronic devices today. Flash memory has non-volatile, programmable, and erasable information storage capabilities, so it has a wide range of applications.

Flash memory is widely used in personal computers or electronic devices because it has the advantages of multiple operations such as writing, reading, erasing, etc., and the stored data will not disappear after power failure. A non-volatile memory element is used. Generally speaking, flash memory is divided into two types: coded flash memory (Nor Flash) and storage type flash memory (Nand Flash).

In a single memory cell structure of flash memory, information is stored in the form of electron clusters in a floating gate between the source and the drain. The control gate is used to control the memory cell. Conventional flash memory devices have stacked gates. With the development of various electronic products toward miniaturization and the process of semiconductor processes entering the deep sub-micron, the design of memory cells It must also meet the requirements of high accumulation and high density, so the semiconductor industry is committed to reducing the size of the memory cell. At the same time, with the increase in the amount of information and electronic product processing and storage, the semiconductor industry needs to take into account the above requirements to reduce the memory cell size and increase the accumulation degree. On the one hand, it is necessary to increase the memory capacity of the memory elements and ensure the Reliability. Therefore, it is known that there is still a need for a flash memory structure and a manufacturing method thereof that can meet the above requirements.

In view of the above needs, the present invention provides a memory structure and a method for manufacturing the same. law. The memory structure of the present invention can store double bits in a single memory cell, and specifically realizes the demand for high-density memory capacity of the memory. In addition, the self-aligned floating gate can reduce the channel length to about 20 nanometers. In addition, traditionally, the manufacturing process of the floating gate and the control gate is changed to a damascene process and a self-alignment process to control the gate.

In a first aspect, the invention provides a method for forming a memory structure. First, a laminated substrate is provided. The laminated substrate includes a substrate, a floating gate oxide, and a plurality of pieces of floating gate material. The active area is defined and filled into the trench. The trench oxide is embedded in the substrate. The function of the trench oxide is to isolate the floating gate. A plurality of pieces of floating gate material are respectively placed between the trench oxides and rise above the surface of the trench oxides. Second, a composite material layer is formed to cover a plurality of floating gate material pieces and trench oxides in a conformal manner. Then, a control gate material layer is formed, covering the composite material layer and extending between the plurality of floating gate material sheets. Then, a protective layer is formed to cover the control gate material layer. Then, the protective layer, the control gate material layer, the composite material layer, the plurality of floating gate material sheets and the substrate are etched at one time, and the substrate is exposed and a plurality of stacked material columns are formed. Then, a selective gate oxide layer is formed to cover the plurality of stacked material columns and the substrate in a conformal manner. Adjacent columns of laminated material define the space between them to accommodate the selection gate. Then, the selected gate material is filled into the space accommodating the selected gate. The selected gate material is sandwiched between the selected gate oxide layers. Then, the protective layer is removed, and a vertical portion of the control gate material layer is exposed. Then, a set of partition walls is formed on each of the stacked material columns, and the vertical portion is attached. A set of gap walls defines a gap space. Continue to use this set of gap walls as an etch mask to pass through the gap space The gate material layer, the composite material layer, and the plurality of floating gate material pieces are etched and controlled in a self-aligned manner at a time to form a plurality of double-bit memory structures.

In one embodiment of the present invention, the method for forming a memory structure further includes the following: Steps to obtain a laminated substrate. First, a substrate is provided. Next, a gate oxide layer is formed to cover the substrate. Then, a floating gate material layer is formed to cover the gate oxide layer. Then, a patterned hard mask is formed to cover the floating gate material layer. Then, a patterned hard mask is used to etch the floating gate material layer, the gate oxide layer and the substrate to form a plurality of unidirectionally extending trenches and a plurality of floating gate material sheets. The trench is then filled with oxide to form a trench oxide. Then, the patterned hard mask is removed, exposing a plurality of pieces of floating gate material under the previously patterned hard mask. Continue to reduce the height of the oxide by wet etching, so that the respective pieces of floating gate material are not only embedded between the trench oxides, but also protruded from the surface of the trench oxides to form a laminated substrate.

In another embodiment of the present invention, the unidirectionally extending trenches and the floating gate material pieces are staggered.

In another embodiment of the present invention, the method for forming a memory structure can adjust an etching recipe and use a gate oxide layer as an etch stop layer to etch a protective layer, control a gate material layer, a composite material layer, and a plurality of floating layers. A gate electrode material sheet and a floating gate oxide layer.

In another embodiment of the present invention, a single etch of the etching recipe allows the plurality of stacked material columns to have vertical sidewalls.

In another embodiment of the present invention, the selected gate oxide layer includes a selected gate oxide and a sidewall oxide.

In another embodiment of the present invention, the selective gate covering oxide covers the selected gate region.

In another embodiment of the present invention, the gate material is selected to have approximately the same height as the top surface of the sidewall oxide.

In another embodiment of the present invention, the bottom width of a group of partition walls is between 20 and 40 nanometers.

In another embodiment of the present invention, the distance between the individual double-bit memory structures is between 30-40 nanometers.

In a second aspect, the present invention further provides a double-bit memory structure. Double of the invention The bit memory structure includes a substrate, a selected gate oxide layer, a selected gate and a group of composite gate layers. The selected gate oxide layer is located on the substrate and includes a selected gate oxide and a side wall oxide. The gate oxide and sidewall oxide are selected together to define an accommodation space. Selecting the gate is embedded in this accommodation space. A group of composite gate layers are located on the floating gate oxide and are attached to the side wall oxides, respectively. Each composite gate layer includes a floating gate oxide, a floating gate, a composite material layer, a control gate and a gap wall on the control gate. The floating gate is located on the floating gate oxide and is attached to the sidewall oxide. The composite material layer is located on the floating gate and adheres to the sidewall oxide. The control gate is located on the composite material layer and adheres to the sidewall oxide. The spacer is located on the control gate and adheres to the side wall oxide.

In an embodiment of the present invention, the double-bit memory structure further includes a plurality of double-bit memories. Memory structure. Adjacent double-bit memory structures are electrically isolated from each other by a shallow trench isolation embedded in the substrate, so that the distance between adjacent double-bit memory structures is between 30-40 nanometers.

In another embodiment of the present invention, the width of the bottom of the dual-bit memory structure is not greater than 100 nanometers.

In another embodiment of the present invention, the sidewall oxide of the dual-bit memory structure is vertical Straight insulating wall.

In another embodiment of the present invention, the dual-bit memory structure further includes an overlay selection gate. Side oxide.

In another embodiment of the present invention, each group of composite gate layers of the dual-bit memory structure Contains a pair of layers of composite material that are insulated from each other, thus becoming a two-bit memory structure.

In another embodiment of the present invention, the floating gate of the double-bit memory structure is self-aligned. Accurate to control the gate.

The invention further proposes a double-bit memory structure. Double-bit memory node of the present invention The structure includes a substrate, a selected gate oxide layer, a selected gate and a group of composite gate layers. Select gate The oxide layer is located on the substrate and is composed of a selected gate oxide and a side wall oxide. The gate oxide and sidewall oxide are selected together to define an accommodation space. Selecting the gate is embedded in the accommodation space, and the top surface of the selection gate is approximately the same height as the top surface of the sidewall oxide. A set of composite gate layers are located on the floating gate oxide and are attached to two sides of the side wall oxide, respectively. Each composite gate layer includes a floating gate oxide, a floating gate, a composite material layer, a control gate and a gap wall on the control gate. The floating gate is located on the selected gate oxide and is attached to the first or second sidewall oxide. The composite material layer is located on the floating gate and adheres to the first or second sidewall oxide. The control gate is located on the composite material layer and adheres to the first or second sidewall oxide. The partition wall is located on the control gate and adheres to the first or second sidewall oxide.

100‧‧‧ double bit memory structure

101‧‧‧ substrate

102‧‧‧ laminated substrate

103‧‧‧hard mask layer

104‧‧‧protective layer

105‧‧‧Laminated material column

110‧‧‧Floating gate oxide

111‧‧‧ trench 112 trench oxide

120‧‧‧Floating gate material sheet, floating gate

121‧‧‧Floating gate material layer

130‧‧‧ Composite

131‧‧‧ composite material layer

140‧‧‧Control gate material, control gate

141‧‧‧Control gate material layer

151‧‧‧Select gate oxide layer

152‧‧‧Select gate material

155‧‧‧accommodation space

156, 158‧‧‧ sidewall oxide

157‧‧‧Select gate oxide

159‧‧‧Select gate oxide

160‧‧‧wall

161‧‧‧a group of partition walls

162‧‧‧Gap space

170‧‧‧a group of composite gate layers

171, 172‧‧‧ composite gate layer

1 to 10 are top views of a feasible method for forming a memory structure of the present invention.

A series of FIGS. 1A to 10A are cross-sectional views corresponding to the upper views of FIGS. 1 to 10.

FIG. 1B, FIG. 2B, FIG. 3B, FIG. 4B, FIG. 6B, FIG. 7B, FIG. 8B, FIG. 9B to FIG. 10B are sectional views corresponding to the top views of FIG. .

7C and 9C show cross-sectional views of alternative embodiments corresponding to FIGS. 7 and 9.

FIG. 11, FIG. 11B and FIG. 11C are schematic diagrams showing the structure of the dual-bit flash memory of the present invention.

The invention proposes a memory for manufacturing a gate electrode using a mosaic process and a self-alignment process. 体 结构。 Body structure. Since each single memory cell includes a pair of floating gates that are electrically insulated from each other, the memory structure of the present invention becomes a two-bit memory structure. In addition, because the floating gate is aligned with the control gate by itself, the process of yellow light alignment can be omitted, and the dual-bit memory structure of the present invention can be established by an etching control method.

The invention first proposes a method for forming a memory structure. Figures 1 to 10 A top view showing a possible method of forming the memory structure of the present invention. A series of diagrams in FIGS. 1A to 10A are cross-sectional views corresponding to the upper views in FIGS. 1 to 10, which are developed along a first direction, such as a word line (WL) direction. Figures 1B, 2B, 3B, 4B, 6B, 7B, 8B, 9B to 10B are the B series diagrams corresponding to FIGS. 1 to The cross-sectional view of the top view in FIG. 10 is unfolded along a second direction, such as the bit line (BL) direction.

First, please refer to FIG. 5, FIG. 5A and FIG. 5B to provide a laminated substrate 102. The laminated substrate 102 includes a substrate 101, a floating gate oxide 110 and a plurality of floating gate material sheets 120. The floating gate oxide 110 is embedded in the trench oxide 112. The plurality of floating gate material pieces 120 are respectively embedded between the trench oxides 112 filled in the plurality of trenches 111. Since the bottoms of the plurality of floating gate material pieces 120 are located above the floating gate oxide 110, respectively, the tops of the plurality of floating gate material pieces 120 may be raised or may be regarded as protruding from the floating The gate oxide 110 is on the surface.

The substrate 101 may be a doped or undoped semiconductor substrate such as silicon. through The doped substrate 101 has a suitable dopant. The trench oxide 112 and the floating gate oxide 110 are usually silicon oxides, which can be prepared by furnace tube oxidation of the substrate 101 or plasma method. For example, trench oxide 112 is filled in a plurality of trenches 111 to form shallow trench isolation (STI). When the surface of the trench oxide 112 is uneven, a chemical mechanical polishing (CMP) planarization step may be performed. The plurality of floating gate material sheets 120 on the floating gate oxide 110 may be doped polycrystalline silicon material.

The laminated substrate 102 can be obtained using a conventional process. For example, refer to Figure 1, In FIGS. 1A and 1B, a floating gate oxide 110 is first formed by the furnace tube oxidation method to cover the substrate 101 as a whole, and then a floating gate material layer 121 is formed to cover the floating gate oxide 110 as a whole. Continue to cover the floating gate material layer 121 with the patterned hard mask 103 as a whole to obtain a stacked substrate 102, a floating gate oxide 110, a floating gate material layer 121, and a hard mask layer. 103. The hard mask layer 103 may be a silicon nitride material layer. Next, please refer to Figure 2, Figure 2A and Figure 2B. For example, the hard mask 103 is patterned with a traditional yellow light and an etching process, and then the patterned hard mask 103 is used to etch the floating gate material layer 121, the floating gate oxide 110, and the substrate 101. A plurality of unidirectionally extending trenches 111 and a plurality of floating gate material pieces 120 are formed in the substrate 101 between the plurality of unidirectionally extending trenches 111. In one embodiment of the present invention, the unidirectionally extending trenches 111 and the floating gate material sheets 120 are arranged in a staggered manner.

Then, please refer to Fig. 3, Fig. 3A and Fig. 3B, for example, the high-density plasma method (HDP) Fill oxide 112 into trench 111 and merge with previous floating gate oxide 110, and then use patterned hard mask 103 as a stop layer, using a planarization such as chemical mechanical polishing (CMP) Step to remove the excess oxide 112, and the dotted area indicates the removed excess oxide 112. Although the trench oxide 112 is merged with the floating gate oxide 110, each oxide is of a different quality. Next, please refer to FIG. 4, FIG. 4A, and FIG. 4B. For example, the patterned hard mask 103 is completely removed by a wet etching method of phosphoric acid, and a plurality of floats under the patterned hard mask 103 are exposed.放 测 极 材料 片 120。 Position gate material sheet 120. Continuing, please refer to FIG. 5 and FIG. 5A. For example, the height of the oxide 112 is reduced by wet etching with hydrofluoric acid, so that the lower half of each floating gate material sheet 120 is embedded with trench oxide. 112, and the upper half is raised / projected from the surface of the oxide 112 to form a laminated substrate 102. Incidentally, because the steps shown by reducing the height of the oxide 112 have no effect on the drawing of FIG. 5B, FIG. 4B can be used instead of FIG. 5B.

Next, please refer to FIG. 6A, and then form a composite material on the laminated substrate 102. The layer 131, the control gate material layer 141, and the protective layer 104. For example, the composite material layer 131 first covers a plurality of floating gate material sheets 120 and trench oxides 112 in a conformal manner, and then the control gate material layer 141 covers the composite material layer 131 and makes the control gate material layer 141 extends in the strip-shaped recesses between the plurality of floating gate material pieces 120. Then, a protective layer 104 is formed to cover the control gate material layer 141, for example, silicon nitride generated in a furnace tube at 700 ° C-800 ° C as a hard mask. The composite material layer 131 may be a laminated structure in which a nitride is compounded with an oxide. For example, the composite material layer 131 may be an oxide-nitride-oxide (O-N-O) type composite structure. complex The thickness of each layer in the material layer 131 may be an oxide (~ 50Å)-a nitride (~ 70Å)-an oxide (~ 50Å). The control gate material layer 141 may also be a doped polycrystalline silicon material. If the surface of the control gate material layer 141 formed is uneven, a chemical mechanical polishing (CMP) planarization step may be performed. The protective layer 104 temporarily covers the control gate material layer 141, and can protect the control gate material layer 141 in a subsequent one-time etching step. The material of the protective layer 104 may be silicon nitride.

Next, please refer to Figure 6 and Figure 6B, and then perform a one-time etching step to build A plurality of stacked material columns 105 are formed. The one-time etching step may be to adjust the etching formula and use the floating gate oxide 110 as an etching stop layer to directly etch the protective layer 104, the control gate material layer 141, the composite material layer 131, and a plurality of floating gate materials. The sheet 120 and the floating gate oxide 110 expose the substrate 101 and form a plurality of stacked material pillars 105. In other words, in the stacked material column 105, there are a floating gate oxide 110, a floating gate material sheet 120, a composite material 130, a control gate material 140, and a protective layer 104. In a preferred embodiment of the present invention, the formulation of the one-time etching step can be adjusted so that the plurality of stacked material pillars 105 have vertical sidewalls instead of tapered sidewalls.

Next, referring to FIG. 7 and FIG. 7B, a selective gate oxide layer 151 is first formed. The selection gate material 152 is formed again, so that the selection gate material 152 is embedded in the selection gate oxide layer 151. The space between the adjacent plurality of stacked material pillars 105 defines a space for accommodating the selected gate material 152. The selective gate oxide layer 151 may be formed first to cover the plurality of stacked material pillars 105 and the substrate 101 in a conformal manner. A method of forming the selective gate oxide layer 151 may be a chemical vapor deposition (CVD) method. In one embodiment of the present invention, the selected gate oxide layer 151 includes a sidewall oxide 158 and a selected gate oxide 157. The wider sidewall oxide 158 facilitates the electrical insulation between the subsequent selection gate (not shown) and the floating gate and the control gate. The thinner selection gate oxide 157 is suitable for matching the selection gate. Therefore, the parameters of the chemical vapor deposition method can be adjusted, and the thicknesses of the gate oxide 157 and the side wall oxide 158 can be adjusted. If necessary, pre-cleaning can be arranged before the step of forming the gate oxide layer 151 is selected. A step of.

Then, the selection gate material 152 is formed again, so that the selection gate material 152 is entirely formed. The selective gate oxide layer 151 is covered. The selection gate material layer 152 may also be a doped polycrystalline silicon material. In order for the selection gate material 152 to be embedded in the selection gate oxide layer 151, an etch back step is performed to remove the excess selection gate material 152 and the protective layer 104 on the stacked material pillar 105. The selective gate oxide layer 151 on the top is then obtained as shown in FIG. 7B. The dotted area indicates that the excess selective gate material 152 and the selective gate oxide layer 151 are removed. Please note that, as shown in FIG. 7B, the height of the top surface of the selected gate material 152 may be lower than the height of the top surface of the protective layer 104. Alternatively, as shown in FIG. 7C, the etch-back step may be controlled so that the height of the top surface of the selected gate material 152 is substantially the same as the height of the top surface of the protective layer 104. It can also be considered that the height of the top surface of the selected gate material 152 is substantially the same as the top surface of the sidewall oxide 158.

After that, please refer to Figure 8 and Figure 8B. If you choose the top surface of the gate material 152 The height of the protective layer 104 is lower than the height of the top surface of the protective layer 104, and then the oxide material, for example, in the form of a selective gate covering oxide 159, covers the exposed top surface of the selective gate material 152, and the deposited selective gate The gate covering oxide 159 is also merged with the selective gate oxide layer 151, and is commonly referred to as the selective gate oxide layer 151, so it can also be regarded as the selective gate covering oxide 159 covering the selective gate material 152. If the surface of the deposited selective gate covering oxide 159 is uneven, a chemical mechanical polishing (CMP) planarization step may be performed, and the result shown in FIG. 8B is obtained.

Then, please refer to FIG. 9, FIG. 9A, and FIG. 9B. After the etch-back step is completed, the protective layer 104 can be removed. After the protective layer 104 is removed, not only the side wall oxide 158 of the control gate material layer 151 is exposed, but only the floating gate oxide 110, the floating gate material sheet 120, and the composite material are left in the stacked material column 105. Material 130 and control gate material 140. If the material of the protective layer 104 is silicon nitride, the protective layer 104 can be completely removed by using a wet etching method such as phosphoric acid. FIG. 9C illustrates the selection gate material 152 with the top surface exposed.

Then, please refer to Fig. 10, Fig. 10A and Fig. 10B. A spacer 160 is formed on the pillar 105, and each spacer 160 is attached to the nearest sidewall oxide 158. On the one hand, each spacer 160 covers the top surface of the laminated material column 105. On the other hand, a set of spacer walls 161 on each laminated material column 105 are separated from each other by a gap distance, thereby exposing the top surface of the laminated material column 105 portion. In other words, a set of partition walls 161 on each laminated material column 105 defines a clearance space 162. Each of the spacers 160 can be formed by a conventional method, such as a deposition method and anisotropic etching. The thickness of the spacer material before etching may be between 20-40 nanometers, and the width of the bottom of the spacer wall 160 after etching may be between 20-40 nanometers. The dotted line shows the spacer material layer deposited before the etching.

Continuing, please refer to FIG. 11, FIG. 11B and FIG. As an etching mask, the stacked material column 105 is etched at one time through the gap space 162, that is, the gate material layer 140, the composite material layer 130, the plurality of floating gate material sheets 120 and the floating gate are oxidized The object 110 forms a plurality of double-bit memory structures 100, and converts the control gate material layer 140 into a control gate 140, a composite material 130, and a floating gate 120. The function of the spacer 160 is used as an etching mask in this one-step etching step. Therefore, this one-step etching step, with the assistance of the spacer 160, has a self-aligning property, so that the floating gate 120 can perform its own function Aligned to the control gate 140. FIG. 11C illustrates an embodiment without the cover layer 159. Incidentally, because the one-time etching steps shown in FIGS. 11 and 11B and the step of forming the spacer 160 shown in FIGS. 10 and 10B have no effect on the drawing of FIG. 11A, Fig. 10A replaces Fig. 11A.

On the other hand, the width of the bottom of the partition wall 160 can be used to control dual bit memory. The body structure 100 controls the widths of the gate 140 and the floating gate 120. For example, when the width of the bottom of the spacer 160 before etching is 25 nanometers, the formula of one etching can be adjusted so that the width of the bottom of the spacer 160 after etching is reduced to 20 nanometers, so the dual-bit memory structure is also made The channel length of 100 can be reduced to about 20 nm. In addition, the width of the bottom of the gap wall 160 can also be used to control the gap width between adjacent memory structures. For example, if the bottom of the stacked material column 105 before etching When the width of the part is about 70 nanometers to 80 nanometers, the formula of one etching can be adjusted so that the gap width between adjacent two-bit memory structures 100 after etching becomes about 30 nanometers to 40 nanometers. The small gap width is conducive to achieving high-density memory capacity of the memory.

After the above steps, a double-bit memory structure of the present invention is obtained. 100. FIG. 11B and FIG. 11C are schematic diagrams showing the structure of the dual-bit memory of the present invention, and other drawings can be referred to together. The dual-bit memory structure 100 of the present invention includes a substrate 101, a selected gate oxide layer 151, a selected gate material 152, and a group of composite gate layers 170. Preferably, the width of the bottom of the dual-bit memory structure 100 is not more than about 100 nanometers. The substrate 101 may be a doped or undoped semiconductor substrate, such as silicon. The doped substrate 101 has a suitable dopant. Preferably, there will be a plurality of double-bit memory structures 100 on the substrate.

The selection gate material 152 may also be a doped polycrystalline silicon material, and the In the gate oxide layer 151. The gate oxide layer 151 is selected, which can be a high-quality silicon oxide layer and is located on the substrate. The selected gate oxide layer 151 generally has three parts, that is, a gate oxide 157, a first sidewall oxide 156, and a second sidewall oxide 158. The gate oxide 157 defines the accommodating space 155 together with the first sidewall oxide 156 and the second sidewall oxide 158 located on the left and right sides. The selection gate material 152 is embedded on the selection gate oxide 157 in the accommodation space 155. FIG. 11B illustrates that the dual-bit memory structure 100 of the present invention further includes a selective gate covering oxide 159 covering the selected gate material 152. As shown in FIG. 11C, when the selective gate covering oxide 159 does not exist as required, the selective gate oxide layer 151 is composed of the selective gate oxide 157, the first sidewall oxide 156, and the second sidewall. Composed of oxide 158.

A set of composite gate layers 170 is located on the substrate 101 and is oxidized on the first sidewall. 物 156 或 第二 oleal oxide 158. The wider sidewall oxide facilitates the electrical insulation between the selected gate material 152, the floating gate 120, and the control gate 140 that are subsequently established, and the thinner selected gate oxide is suitable for matching the selected gate, so The parameters of the sidewall oxide and the selected gate oxide can be adjusted so that the width of the sidewall oxide is greater than the thickness of the selected gate oxide. For example, the width of at least one of the first sidewall oxide 156 or the second sidewall oxide 158 is greater than the selection gate oxide 157 thickness of. In one embodiment of the present invention, the first sidewall oxide 156 and the second sidewall oxide 158 are vertical insulating walls.

A group of composite gate layers 170 includes a composite gate layer 171 and a composite gate layer 172. Each composite gate layer includes a floating gate oxide 110, a floating gate 120, a composite material layer 130, a control gate 140, and a spacer 160, respectively. The floating gate oxide 110 may be an oxide of silicon and has an ideal thickness to cooperate with the electronic writing and erasing of the dual-bit memory. The dual-bit memory structure 100 of the present invention is suitable for a coded flash memory, and can be operated by using Channel Hot Electron Injection (CHEI) or F-N tunneling (Fowler-Nordheim tunneling). The floating gate 120 preferably includes a doped polycrystalline silicon material, which is located on the selective gate oxide 157 and is attached to the first sidewall oxide 156 or the second sidewall oxide 158 according to its relative position. The floating gate 120 is the location where the memory structure 100 stores charges.

The composite material layer 130 is located on the floating gate 120 and is also attached according to its relative position On the first sidewall oxide 156 or the second sidewall oxide 158. The composite material layer 130 may be a laminated structure in which a nitride and an oxide are composited. For example, the composite material layer 130 may be an oxide-nitride-oxide (O-N-O) type composite structure. The thickness of each layer in the composite material layer 130 may be an oxide (~ 50Å)-a nitride (~ 70Å)-an oxide (~ 50Å). Preferably, a group of composite gate layers 170 has a pair of composite material layers 130. The pair of composite material layers 130 are insulated from each other, thus making the memory structure of the present invention a two-bit memory structure. The control gate 140 preferably also includes a doped polycrystalline silicon material and is located on the composite material layer 130. Similarly, the control gate 140 is attached to the first sidewall oxide 156 or the second sidewall oxide 158 according to its relative position. The partition wall 160 is located on the control gate 140 and is a protective top layer of the composite gate layer 170. The partition wall 160 is attached to the first sidewall oxide 156 or the second sidewall oxide 158 according to its relative position. The partition wall 160 helps the floating gate 120 of the two-bit memory structure 100 to align itself with the control gate 140.

Please refer to FIG. 10A. In one embodiment of the present invention, trench oxide 112 The bottom trenches 111 are embedded in the plurality of shallow trenches 111 for isolation of the shallow trenches. Adjacent double-bit memory structures 100 are electrically isolated from each other by this shallow trench isolation. Better, Adjacent Double Bits The distance between the memory structure 110 is about 30-40 nanometers.

The above description is only a preferred embodiment of the present invention, and all equivalent changes and modifications made in accordance with the scope of patent application of the present invention shall fall within the scope of the present invention.

Claims (16)

A method of forming a memory structure includes: providing a laminated substrate including: a substrate; a floating gate oxide located on the substrate and embedded in the substrate; and a plurality of floating gates The material sheet is located on the floating gate oxide, which is embedded between the trench oxides and rises above the surface of the trench oxides; a composite material layer is formed to cover the plurality of floats in a conformal manner A gate material sheet and the trench oxide; forming a control gate material layer covering the composite material layer and extending between the plurality of floating gate material sheets; forming a protective layer to cover the control gate material Layer; etch the protective layer, the control gate material layer, the composite material layer, the plurality of floating gate material pieces and the floating gate oxide at one time, and expose the substrate and form a plurality of stacks Material column; forming a selective gate oxide layer, covering the plurality of laminated material columns and the substrate in a conformal manner, wherein the adjacent plurality of laminated material columns define a selective gate accommodation space at In the meantime Fill the selection gate accommodation space and sandwich it between the selection gate oxide layers; remove the protective layer and expose a vertical portion of the control gate material layer; at each of the stacks A set of gap walls is formed on the layer material column to attach to the vertical part, wherein the set of gap walls defines a gap space; and the set of gap walls is used as an etching mask, and the etching is performed in a self-aligned manner through the gap space at one time The control gate material layer, the composite material layer, the plurality of floating gate material pieces and the floating gate oxide form a plurality of double-bit memory structures. The method for forming a memory structure according to claim 1, further comprising: providing a substrate; forming a floating gate oxide layer to cover the substrate; forming a floating gate material layer to cover the floating gate oxide Forming a patterned hard mask to cover the floating gate material layer; using the patterned hard mask to etch the floating gate material layer, the floating gate oxide, and the substrate to Forming a plurality of unidirectionally extending trenches and a plurality of floating gate material pieces; using an oxide to fill the trenches; removing the patterned hard mask, and exposing the patterned hard mask underneath the patterned hard mask A plurality of floating gate material pieces; the height of the oxide is reduced so that each of the floating gate material pieces is embedded between the oxides and rises above the surface of the oxides to form the laminated substrate . The method for forming a memory structure according to claim 1, wherein the unidirectionally extending trenches and the floating gate material pieces are staggered. For example, the method for forming a memory structure according to claim 1, wherein an etching recipe is adjusted and the floating gate oxide layer is used as an etch stop layer to etch the protective layer, the control gate material layer, and the composite material layer at one time. The plurality of floating gate material pieces, the floating gate oxide and the substrate. The method for forming a memory structure as claimed in claim 4, wherein a single etching of the etching recipe causes a plurality of the stacked material columns to have vertical sidewalls. The method of claim 1, wherein the selected gate oxide layer includes a selected gate oxide and a sidewall oxide. A method of forming a memory structure as claimed in claim 6, wherein the selected gate oxide is located below the selected gate material. The method for forming a memory structure according to claim 6, wherein the selected gate material has the same height as the top surface of the sidewall oxide. The method for forming a memory structure according to claim 1, wherein the width of the bottom of the group of partition walls is 20-40 nanometers. For example, the method for forming a memory structure according to claim 1, wherein the distance between the individual bit memory structures is between 20 and 40 nanometers. A two-bit memory structure includes: a substrate; a selective gate oxide layer located on the substrate and including a selective gate oxide, a first sidewall oxide, and a second sidewall oxide, The selective gate oxide, the first sidewall oxide, and the second sidewall oxide together define an accommodation space; a selection gate is embedded in the accommodation space; and a set of composite gate layers is located on the base The first and second sidewall oxides are attached to the material, and the respective composite gate layers include: a floating gate oxide layer on the substrate; and a floating gate on the substrate. One of the first sidewall oxide and the second sidewall oxide is attached to the floating gate oxide layer; and a composite material layer is located on the floating gate oxide and adheres to the first sidewall oxide and the second sidewall oxide. One of the side wall oxides; a control gate located on the composite material layer and attached to one of the first side wall oxide and the second side wall oxide; and a gap wall located on the control gate and attached to the First sidewall oxide and the first One of the sidewall oxides; further comprising a plurality of two-bit memory structures, and the adjacent two-bit memory structures are electrically isolated from each other by a shallow trench isolation embedded in the substrate, so that the adjacent two-bit memory structures The distance between meta-memory structures is between 30-40 nanometers. For example, the double-bit memory structure of claim 11 has a width at the bottom of not more than 100 nanometers. For example, the dual-bit memory structure of claim 11, wherein the first sidewall oxide and the second sidewall oxide are vertical insulating walls. For example, the dual-bit memory structure of claim 11 further includes a selective gate covering oxide to cover the selective gate. For example, the dual-bit memory structure of claim 11, wherein the group of composite gate layers includes a pair of composite material layers insulated from each other, and thus becomes a dual-bit memory structure. For example, the dual-bit memory structure of claim 11, wherein the floating gate is aligned with the control gate by itself.