TWI626726B - High density chip-to-chip connection - Google Patents

High density chip-to-chip connection Download PDF

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Publication number
TWI626726B
TWI626726B TW104117980A TW104117980A TWI626726B TW I626726 B TWI626726 B TW I626726B TW 104117980 A TW104117980 A TW 104117980A TW 104117980 A TW104117980 A TW 104117980A TW I626726 B TWI626726 B TW I626726B
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Taiwan
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die
layer
conductive
conductive material
top surface
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TW104117980A
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Chinese (zh)
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TW201606975A (en
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特羅斯登 梅耶爾
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英特爾Ｉｐ公司
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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

一種裝置包括至少一第一IC晶粒及一第二IC晶粒。該第一IC晶粒及該第二IC晶粒之底表面包括第一多個連接襯墊，且該第一IC晶粒及該第二IC晶粒之頂表面包括第二多個連接襯墊。該裝置亦包括：一非傳導材料層，其覆蓋該第一IC晶粒及該第二IC晶粒之該等頂表面；多個通孔；在該等第一多個連接襯墊之至少一部分與至少一個通孔之間的第一傳導性互連件；以及在該非傳導材料層之一頂表面上的第二傳導性互連件，其提供該等第二多個連接襯墊之至少一部分與該等多個通孔中之至少一個通孔之間的電氣連續性。 A device includes at least one first IC die and a second IC die. a bottom surface of the first IC die and the second IC die includes a first plurality of connection pads, and a top surface of the first IC die and the second IC die includes a second plurality of connection pads . The device also includes a non-conductive material layer covering the top surfaces of the first IC die and the second IC die, a plurality of vias, and at least a portion of the first plurality of connection pads a first conductive interconnect between the at least one via; and a second conductive interconnect on a top surface of the non-conductive material layer providing at least a portion of the second plurality of connection pads Electrical continuity between at least one of the plurality of through holes.

Description

高密度晶片對晶片連接技術 High-density wafer-to-wafer connection technology 發明領域 Field of invention

實施例係關於積體電路(IC)之封裝。一些實施例係關於積體電路之IC封裝互連。 The embodiment relates to a package of an integrated circuit (IC). Some embodiments relate to IC package interconnections for integrated circuits.

發明背景 Background of the invention

電子系統常包括連接到諸如基體或主機板之子總成的積體電路(IC)。該等IC可經封裝且插入到設置於子總成上之IC封裝內。隨著電子系統設計變得更複雜，符合系統之所要的大小約束係一個難題。影響設計之總大小的一個態樣為對於IC封裝之接點之互連所需的間隔。隨著間隔減小，封裝之IC可變得不夠穩固且符合間距要求之成本可能增加。因此，存在對於解決針對IC之接點的間隔難題卻又提供穩固且具成本效益的設計之裝置、系統及方法的一般需求。 Electronic systems often include integrated circuits (ICs) that are connected to sub-assemblies such as a base or motherboard. The ICs can be packaged and inserted into an IC package disposed on a subassembly. As electronic system design becomes more complex, conforming to the size constraints of the system is a challenge. One aspect that affects the overall size of the design is the spacing required for the interconnection of the contacts of the IC package. As the spacing decreases, the packaged IC can become less robust and the cost of meeting the spacing requirements can increase. Accordingly, there is a general need for devices, systems, and methods that address the problem of spacing for IC contacts while providing a robust and cost effective design.

依據本發明之一實施例，係特地提出一種裝置，其包含：至少一第一積體電路(IC)晶粒及一第二IC晶粒，其中該第一IC晶粒及該第二IC晶粒之底表面包括第一多個連 接襯墊，且該第一IC晶粒及該第二IC晶粒之頂表面包括第二多個連接襯墊；一非傳導材料層，其覆蓋該第一IC晶粒及該第二IC晶粒之該等頂表面；多個通孔，其包括在該第一IC晶粒中之至少一個通孔及在該第二IC晶粒中之至少一個通孔；在該等第一多個連接襯墊之至少一部分與該等多個通孔中之至少一個通孔之間的第一傳導性互連件；以及在該非傳導材料層之一頂表面上的第二傳導性互連件，其提供該等第二多個連接襯墊之至少一部分與該等多個通孔中之至少一個通孔之間的電氣連續性。 According to an embodiment of the present invention, a device is specifically provided, including: at least a first integrated circuit (IC) die and a second IC die, wherein the first IC die and the second IC die The bottom surface of the grain includes the first plurality of links a pad, and the top surface of the first IC die and the second IC die includes a second plurality of connection pads; a non-conductive material layer covering the first IC die and the second IC crystal The top surfaces of the particles; a plurality of vias including at least one via in the first IC die and at least one via in the second IC die; at the first plurality of connections a first conductive interconnect between at least a portion of the spacer and at least one of the plurality of vias; and a second conductive interconnect on a top surface of the non-conductive material layer, Electrical continuity between at least a portion of the second plurality of connection pads and at least one of the plurality of through holes is provided.

100、600、700‧‧‧裝置 100, 600, 700‧‧‧ devices

105、205、405‧‧‧第一IC晶粒 105, 205, 405‧‧‧ first IC die

110、210、410‧‧‧第二IC晶粒 110, 210, 410‧‧‧ second IC die

115A、115B、115C、115D、215A、215B、215C、215D、415A、415B、415C、415D、715A、715C‧‧‧連接襯墊 115A, 115B, 115C, 115D, 215A, 215B, 215C, 215D, 415A, 415B, 415C, 415D, 715A, 715C‧‧‧ connection pads

120、220、320、720‧‧‧非傳導材料層 120, 220, 320, 720‧‧‧ non-conductive material layers

125、225A、225B、425A、425B、665、765‧‧‧矽穿孔(TSV) 125, 225A, 225B, 425A, 425B, 665, 765‧‧ ‧ Perforated (TSV)

135、735‧‧‧傳導性互連件 135, 735‧‧‧ Conductive interconnects

240‧‧‧薄金屬箔 240‧‧‧Thin metal foil

245A‧‧‧第一導電互連件 245A‧‧‧First Conductive Interconnect

245B‧‧‧第二導電互連件 245B‧‧‧Second conductive interconnect

250A、250B‧‧‧箭頭 250A, 250B‧‧‧ arrows

255、455‧‧‧焊料阻流劑層 255, 455‧‧‧ solder barrier layer

260、760‧‧‧焊料凸塊 260, 760‧‧‧ solder bumps

270、470‧‧‧開口 270, 470‧‧‧ openings

345A‧‧‧底側上之傳導性互連件 345A‧‧‧ Conductive interconnects on the bottom side

345B‧‧‧頂表面上之傳導性互連件 345B‧‧‧ Conductive interconnects on the top surface

365、767‧‧‧模穿孔(TMV) 365, 767‧‧ ‧ die piercing (TMV)

420、520‧‧‧模製層 420, 520‧‧‧ moulding layer

445B、450B‧‧‧導電互連件 445B, 450B‧‧‧ conductive interconnects

460‧‧‧焊球 460‧‧‧ solder balls

475、482、775‧‧‧再分佈層 475, 482, 775‧‧ ‧ redistribution layer

480‧‧‧介電層 480‧‧‧ dielectric layer

565‧‧‧通孔 565‧‧‧through hole

605、610、705‧‧‧IC晶粒 605, 610, 705‧‧‧ IC die

685、780‧‧‧基體 685, 780‧‧‧ base

690‧‧‧橋接組件 690‧‧‧Bridge components

800‧‧‧電子系統 800‧‧‧Electronic system

802‧‧‧系統匯流排 802‧‧‧ system bus

810‧‧‧電子總成 810‧‧‧Electronic assembly

812‧‧‧處理器 812‧‧‧ processor

814‧‧‧通訊電路 814‧‧‧Communication circuit

816‧‧‧顯示裝置 816‧‧‧ display device

818‧‧‧揚聲器 818‧‧‧Speaker

820‧‧‧外部記憶體 820‧‧‧External memory

822‧‧‧主記憶體 822‧‧‧ main memory

824‧‧‧硬碟機 824‧‧‧ Hard disk drive

826‧‧‧抽取式媒體 826‧‧‧Removable media

830‧‧‧鍵盤及/或控制器 830‧‧‧Keyboard and / or controller

d‧‧‧距離 D‧‧‧distance

圖1說明根據一些實施例的包括系統級電子封裝之電子裝置之一實例之部分；圖2A至圖2E說明根據一些實施例的形成用於電子裝置的系統級封裝的方法之一實例之部分；圖3說明根據一些實施例的包括系統級封裝之電子裝置之另一實例之部分；圖4A至圖4G說明根據一些實施例的形成用於電子裝置的系統級電子封裝的方法之一實例之部分；圖5說明根據一些實施例的包括系統級封裝之電子裝置之另一實例之部分；圖6說明根據一些實施例的包括在系統級封裝中之覆晶技術的電子裝置之另一實例之部分；圖7說明根據一些實施例的用於電子裝置之封裝之一實例；及 圖8為根據一些實施例的電子系統之一實例之方塊圖。 1 illustrates a portion of one example of an electronic device including a system level electronic package in accordance with some embodiments; FIGS. 2A-2E illustrate portions of one example of a method of forming a system level package for an electronic device, in accordance with some embodiments; 3 illustrates a portion of another example of an electronic device including a system-in-package in accordance with some embodiments; FIGS. 4A-4G illustrate portions of one example of a method of forming a system-level electronic package for an electronic device, in accordance with some embodiments. Figure 5 illustrates a portion of another example of an electronic device including a system-in-package in accordance with some embodiments; Figure 6 illustrates a portion of another example of an electronic device including flip chip technology in a system-in-package, in accordance with some embodiments. FIG. 7 illustrates an example of a package for an electronic device in accordance with some embodiments; and 8 is a block diagram of one example of an electronic system in accordance with some embodiments.

較佳實施例之詳細說明 Detailed description of the preferred embodiment

以下描述及圖式充分說明具體實施例，以使得熟習此項技術者能夠實踐該等實施例。其他實施例可併有結構、邏輯、電氣、過程及其他改變。一些實施例之部分及特徵可包括於其他實施例之部分及特徵中或取代其他實施例之部分及特徵。申請專利範圍中所闡述之實施例涵蓋彼等申請專利範圍之所有可用等效物。 The detailed description and the drawings are to be considered as a Other embodiments may be combined with structural, logical, electrical, process, and other changes. Portions and features of some embodiments may be included in or substituted for parts and features of other embodiments. The examples set forth in the scope of the patent application cover all available equivalents of the scope of the patent application.

對於較小裝置中之增大的計算能力之需求已導致對系統級封裝之增大的使用以符合系統整合之需求。舉例而言，可使用兩個不同技術節點來分開及建置電子系統之數位與類比部分：針對數位部分之高端複雜積體電路(IC)製造製程及針對類比部分之低端製程。兩個部分可包括於兩個不同IC晶粒中，該等兩個不同IC晶粒可按封裝級整合至並排SiP內。然而，此整合方案可能需要兩個IC晶粒之間的許多連接。IC晶粒之間的此互連可能需要非常細的金屬行距及間隔，且可能需要多個佈線層。亦可能存在晶片間信號速度與減小的實體尺寸之間的電氣效能取捨。 The need for increased computing power in smaller devices has led to increased use of system level packaging to meet system integration requirements. For example, two different technology nodes can be used to separate and construct the digital and analog portions of an electronic system: a high-end complex integrated circuit (IC) manufacturing process for the digital portion and a low-end process for the analog portion. The two sections can be included in two different IC dies that can be integrated into the side-by-side SiP at the package level. However, this integration scheme may require many connections between the two IC dies. This interconnection between IC dies may require very fine metal pitch and spacing and may require multiple wiring layers. There may also be electrical performance trade-offs between inter-wafer signal speeds and reduced physical size.

另外，使用較細間距容納增大的積體電路輸入/輸出(I/O)可導致代價大的封裝製程來適應與互連線之寬度相關聯的較細幾何尺寸、互連之間的間隔及保護免遭互連件之間的電子遷移的間隔。此可導致與對下部成本之需求衝突的封裝要求。 In addition, the use of finer pitch to accommodate increased integrated circuit input/output (I/O) can result in costly packaging processes to accommodate the finer geometry associated with the width of the interconnect, the spacing between interconnects. And to protect against the separation of electrons between interconnects. This can result in packaging requirements that conflict with the need for lower cost.

通常，IC晶粒之僅一側用於I/O。當製造IC晶粒時，IC連接襯墊形成於晶圓之表面上。個別晶粒經分開及設置(例如，以覆晶組配)，其中連接襯墊側或前側在陶瓷基體或印刷電路板(PCB)上面向下以用於連接至其他裝置。除了前側之外，亦將IC晶粒之後側用於互連及佈線可大大增大可用於I/O佈線之空間量。此允許以較小侵略性間隔及較少佈線要求實施用於IC的佈線。 Typically, only one side of the IC die is used for I/O. When an IC die is fabricated, an IC connection pad is formed on the surface of the wafer. The individual dies are separated and disposed (e.g., in a flip chip configuration) with the pad side or front side being over the ceramic substrate or printed circuit board (PCB) for connection to other devices. In addition to the front side, the use of the back side of the IC die for interconnection and routing can greatly increase the amount of space available for I/O wiring. This allows wiring for the IC to be implemented with less aggressive spacing and less routing requirements.

圖1說明包括系統級電子封裝的電子裝置之一實例之部分。裝置100包括第一IC晶粒105及第二IC晶粒110。在某些變化中，該等IC晶粒中之一者包括數位電路，且另一晶粒包括類比電路或主要為類比電路。在一些變化中，裝置100包括兩個以上IC晶粒。該等IC晶粒中之兩者皆包括一頂表面及一底表面。一IC晶粒在其於晶圓上製造時可具有自該IC晶粒之定向翻轉或倒轉的定向，使得圖1中展示之頂表面對應於形成該IC晶粒的晶圓之後側。 Figure 1 illustrates a portion of one example of an electronic device including a system level electronic package. The device 100 includes a first IC die 105 and a second IC die 110. In some variations, one of the IC dies includes a digital circuit and the other dies include analog circuits or primarily analog circuits. In some variations, device 100 includes more than two IC dies. Both of the IC dies include a top surface and a bottom surface. An IC die may have an orientation that is flipped or inverted from the orientation of the IC die as it is fabricated on the wafer such that the top surface shown in Figure 1 corresponds to the back side of the wafer from which the IC die is formed.

裝置100包括多個通孔。在該圖中展示之實例中，該等通孔包括至少一個矽穿孔125(TSV)。在某些實例中，該等晶粒中之兩者皆包括至少一個TSV。TSV通常形成於IC晶粒中以自IC晶粒之底表面延伸穿過IC晶粒至頂表面。可在形成IC之製程期間形成TSV，或可在形成IC之後添加TSV(例如，藉由在IC晶粒中鑽出開口及用傳導材料填充該開口)。TSV可提供IC晶粒之底表面與頂表面之間的電氣連續性。在圖1之實例中，藉由在非傳導材料層120中形成至IC晶粒之頂表面的開口進行至TSV之頂部的電接觸。 Device 100 includes a plurality of through holes. In the example shown in the figure, the through holes include at least one turn perforation 125 (TSV). In some examples, both of the dies include at least one TSV. The TSV is typically formed in the IC die to extend from the bottom surface of the IC die through the IC die to the top surface. The TSV can be formed during the process of forming the IC, or the TSV can be added after the IC is formed (eg, by drilling an opening in the IC die and filling the opening with a conductive material). The TSV provides electrical continuity between the bottom and top surfaces of the IC die. In the example of FIG. 1, electrical contact to the top of the TSV is made by forming an opening in the non-conductive material layer 120 to the top surface of the IC die.

IC之頂表面包括第一多個連接襯墊(例如，115A、115B)。IC之底表面包括第二多個連接襯墊(例如，115C、115D)。在圖1之實例中，該等第一多個連接襯墊接觸通孔之頂端。該等第二多個連接襯墊接觸通孔之底端且接觸IC晶粒之主動電路。非傳導材料層120覆蓋該第一IC晶粒及該第二IC晶粒之頂表面。傳導材料亦可覆蓋如圖1之實例中所展示的該第一IC晶粒及該第二IC晶粒之側。 The top surface of the IC includes a first plurality of connection pads (e.g., 115A, 115B). The bottom surface of the IC includes a second plurality of connection pads (e.g., 115C, 115D). In the example of Figure 1, the first plurality of connection pads contact the top end of the via. The second plurality of connection pads contact the bottom end of the via and contact the active circuitry of the IC die. The non-conductive material layer 120 covers the top surface of the first IC die and the second IC die. The conductive material may also cover the side of the first IC die and the second IC die as shown in the example of FIG.

裝置100亦包括導電互連件130以提供在IC晶粒之底表面上的連接襯墊之至少一部分之間的電氣連續性，包括第一IC晶粒之一或多個連接襯墊與第二IC晶粒之一或多個連接襯墊之間的連續性。傳導性互連件亦可提供在IC晶粒之底表面處的一或多個TSV之電氣連續性。 The device 100 also includes a conductive interconnect 130 to provide electrical continuity between at least a portion of the bond pads on the bottom surface of the IC die, including one or more of the first IC die and the second Continuity between one or more of the IC pads. The conductive interconnects can also provide electrical continuity of one or more TSVs at the bottom surface of the IC die.

裝置100進一步包括在非傳導材料層之頂表面上的傳導性互連件135。傳導性互連件135可提供在第一IC晶粒之頂表面上的連接襯墊之至少一部分與在第二IC晶粒之頂表面上的連接襯墊之至少一部分之間的電氣連續性。傳導性互連件135可提供在IC晶粒之頂表面處的TSV中之一或多者的電氣連續性。以此方式，可提供自第一IC晶粒之底表面上的連接襯墊至通孔及至第二IC晶粒之頂表面上的連接襯墊之電氣連續性。類似地，可提供自第一IC晶粒之頂表面上的連接襯墊至通孔及至第二IC晶粒之底表面上的連接襯墊之電氣連續性。 Device 100 further includes a conductive interconnect 135 on a top surface of the layer of non-conductive material. The conductive interconnect 135 can provide electrical continuity between at least a portion of the bond pads on the top surface of the first IC die and at least a portion of the bond pads on the top surface of the second IC die. Conductive interconnect 135 can provide electrical continuity of one or more of the TSVs at the top surface of the IC die. In this manner, electrical continuity can be provided from the connection pads on the bottom surface of the first IC die to the vias and to the connection pads on the top surface of the second IC die. Similarly, electrical continuity can be provided from the connection pads on the top surface of the first IC die to the vias and to the connection pads on the bottom surface of the second IC die.

圖2A至圖2E說明形成用於電子裝置之系統級封裝的方法之一實例之部分。第一IC晶粒205及第二IC晶粒 210經形成以包括連接襯墊。在某些變化中，IC晶粒包括在連接襯墊位置處之銅襯墊修飾面層。連接襯墊(例如，215A、215C)形成於第一IC晶粒之頂表面及底表面兩者上，及第二IC晶粒之頂表面及底表面兩者上(例如，215B、215D)。在圖2A之實例中，IC晶粒各包括TSV 225A、225B。展示頂表面之連接襯墊連接至TSV，但IC晶粒可包括未連接到TSV之其頂表面上的連接襯墊。在圖2A之實例中，IC晶粒膠合至薄金屬箔240。 2A-2E illustrate portions of an example of a method of forming a system in package for an electronic device. First IC die 205 and second IC die 210 is formed to include a connection pad. In some variations, the IC die includes a copper liner modifying finish at the location of the bond pads. A connection pad (e.g., 215A, 215C) is formed on both the top and bottom surfaces of the first IC die and on both the top and bottom surfaces of the second IC die (e.g., 215B, 215D). In the example of FIG. 2A, the IC dies each include TSVs 225A, 225B. The connection pads showing the top surface are connected to the TSV, but the IC die may include a connection pad that is not attached to the top surface of the TSV. In the example of FIG. 2A, the IC die is glued to the thin metal foil 240.

在圖2B中，使用非傳導材料層220覆蓋該第一IC晶粒及該第二IC晶粒之至少頂表面以形成子總成。非傳導材料之一些實例可尤其包括可模製塑膠材料、環氧樹脂、層壓材料或預浸染或「預浸」材料。在展示之實例中，非傳導層亦覆蓋IC晶粒之側，且非傳導材料可由多個經層壓或按壓之層組成。 In FIG. 2B, the first IC die and at least the top surface of the second IC die are covered with a non-conductive material layer 220 to form a sub-assembly. Some examples of non-conductive materials may include, in particular, moldable plastic materials, epoxies, laminates, or pre-dip or "prepreg" materials. In the example shown, the non-conductive layer also covers the side of the IC die, and the non-conductive material can be composed of a plurality of laminated or pressed layers.

在圖2C中，通孔形成於子總成中。在展示之實例中，通孔包括IC晶粒之TSV。藉由形成至非傳導層中之TSV的開口270或通孔且用傳導材料(例如，金屬)填充開口來形成至非傳導層之頂表面的通孔。可藉由機械鑽孔或雷射鑽孔形成非傳導層中之開口270。連接襯墊中的銅之使用可有助於雷射鑽孔。銅襯墊通常比其他材料(例如，鋁)之襯墊厚，且較厚之連接襯墊可使雷射鑽孔更易於控制。亦可形成至其他連接襯墊之通孔。在圖2C之實例中，經由圖2A之薄金屬箔及黏著劑或膠形成至IC之底表面上的連接襯墊之至少一部分之通孔。在某些變化中，同時在IC晶粒之頂 表面及底表面上形成至連接襯墊之通孔。 In Figure 2C, a through hole is formed in the subassembly. In the example shown, the vias include the TSV of the IC die. A via to the top surface of the non-conductive layer is formed by forming an opening 270 or via of the TSV into the non-conductive layer and filling the opening with a conductive material (eg, metal). The opening 270 in the non-conductive layer can be formed by mechanical drilling or laser drilling. The use of copper in the connection pads can aid in laser drilling. Copper pads are typically thicker than pads of other materials (eg, aluminum), and thicker connection pads make laser drilling easier to control. It is also possible to form through holes to other connection pads. In the example of FIG. 2C, vias of at least a portion of the connection pads on the bottom surface of the IC are formed via the thin metal foil of FIG. 2A and an adhesive or glue. In some variations, at the same time at the top of the IC die Through holes are formed in the surface and the bottom surface to the connection pads.

在圖2D中，進行至頂表面及底表面上之連接襯墊的電氣連接。第一導電互連件245A(例如，金屬跡線)形成於在該第一與該第二IC晶粒之底表面上的連接襯墊之至少一部分之間。傳導性互連件245A之至少一部分用於晶粒對晶粒連接，且傳導性互連件245A之至少一部分用以形成至至少一個TSV之電氣連接。在一些實例中，經由薄金屬箔之圖案化來形成傳導性互連件245A。 In Figure 2D, electrical connections are made to the connection pads on the top and bottom surfaces. A first conductive interconnect 245A (eg, a metal trace) is formed between at least a portion of the connection pads on the bottom surfaces of the first and second IC dies. At least a portion of the conductive interconnects 245A are for die-to-die connections, and at least a portion of the conductive interconnects 245A are used to form electrical connections to the at least one TSV. In some examples, the conductive interconnect 245A is formed via patterning of a thin metal foil.

第二導電互連件245B形成於非傳導材料層之頂表面上以提供第一IC晶粒與第二IC晶粒之頂表面上的連接襯墊之至少一部分之間的電氣互連件。傳導性互連件之至少一部分用於晶粒對晶粒連接，且該傳導性互連件之至少一部分用以形成至至少一個TSV之電連接。箭頭250A、250B指示藉由傳導性互連件之電氣連接，其可存在，但在圖2D中之橫截面說明中不可見。可包括額外層以提供用於傳導性互連件之跨接或以提供用於焊球之著陸襯墊。額外頂表面佈線自若佈線僅限於底表面則將有的密度減小佈線密度。 A second conductive interconnect 245B is formed on a top surface of the layer of non-conductive material to provide an electrical interconnection between the first IC die and at least a portion of the bond pads on the top surface of the second IC die. At least a portion of the conductive interconnects are for die-to-die connections, and at least a portion of the conductive interconnects are used to form electrical connections to the at least one TSV. Arrows 250A, 250B indicate electrical connections by conductive interconnects, which may be present, but are not visible in the cross-sectional illustration in Figure 2D. Additional layers may be included to provide a jumper for the conductive interconnect or to provide a landing pad for the solder ball. The extra top surface wiring freely is limited to the bottom surface and the density will be reduced by the density.

圖2E展示可將焊料凸塊或焊球添加至裝置。為了容納焊料凸塊，可將焊料阻流劑層255添加該底表面。焊料阻流劑層255包括絕緣材料層，且亦包括用於設置焊料凸塊260之開口。焊料凸塊260接著經設置至焊料阻流劑層。經由傳導性互連件及通孔之使用，可提供至少一個著陸襯墊與在該第一IC晶粒及該第二IC晶粒中之至少一者之頂側上 的至少一個連接襯墊之間的電氣連續性。焊料阻流劑層255可配置於在連接襯墊與著陸襯墊及焊料凸塊之間導引傳導性互連件的再分佈層(例如，連同電氣連接245A及250A一起塗覆)上。在一些實例中，可存在同時形成且共享同一平台(例如，共享一基體)之若干系統級封裝。可將個別系統級封裝分開，諸如，藉由鋸切。 Figure 2E shows that solder bumps or solder balls can be added to the device. To accommodate the solder bumps, a solder flow inhibitor layer 255 can be added to the bottom surface. The solder flow inhibitor layer 255 includes a layer of insulating material and also includes openings for providing solder bumps 260. Solder bumps 260 are then disposed to the solder flow inhibitor layer. Providing at least one landing pad and a top side of at least one of the first IC die and the second IC die via the use of a conductive interconnect and a via Electrical continuity between at least one of the connection pads. The solder baffer layer 255 can be disposed on a redistribution layer (eg, coated with electrical connections 245A and 250A) that guides the conductive interconnect between the landing pads and the landing pads and solder bumps. In some instances, there may be several system level packages that are simultaneously formed and share the same platform (eg, share a base). Individual system level packages can be separated, such as by sawing.

圖3說明包括系統級封裝的電子裝置之另一實例之部分。圖1及圖2A至圖2E展示通孔包括TSV之實例。然而，在給定IC製程中，TSV可能不可用，或不選擇具有TSV能力之製程(例如，為了成本之原因)。在圖3中展示之實例中，使用形成於非傳導材料層320中之通孔實施在IC晶粒之底表面與頂表面之間的電氣連續性。若非傳導材料經模製層壓，則可將通孔叫作模穿孔365或TMV。可藉由鑽孔(例如，雷射鑽孔或機械鑽孔)以形成開口來形成TMV，接著用導電材料填充開口。其亦可為一塊包括垂直連接的經內嵌、預形成之矽、PCB、層壓物或陶瓷。在某些變化中，系統級封裝包括TSV及TMV兩者。底側上之傳導性互連件345A及頂表面上之傳導性互連件345B可用以形成通孔之電氣連續性。舉例而言，傳導性互連件可形成在IC晶粒之頂表面之連接襯墊、通孔與同一或不同IC晶粒之底表面上之連接襯墊之間的電氣連續性。因為至通孔之佈線短，所以使用非TSV通孔可仍減小系統級封裝之佈線密度。 Figure 3 illustrates a portion of another example of an electronic device including a system in package. 1 and 2A to 2E show an example in which a through hole includes a TSV. However, in a given IC process, the TSV may not be available, or a TSV capable process may not be selected (eg, for cost reasons). In the example shown in FIG. 3, electrical continuity between the bottom surface and the top surface of the IC die is performed using vias formed in the non-conductive material layer 320. If the non-conductive material is molded and laminated, the through hole can be referred to as a die hole 365 or TMV. The TMV can be formed by drilling (eg, laser drilling or mechanical drilling) to form an opening, followed by filling the opening with a conductive material. It can also be an in-line, preformed crucible, PCB, laminate or ceramic comprising vertical connections. In some variations, system level packages include both TSV and TMV. The conductive interconnects 345A on the bottom side and the conductive interconnects 345B on the top surface can be used to form electrical continuity of the vias. For example, the conductive interconnects can form electrical continuity between the bond pads on the top surface of the IC die, the vias, and the bond pads on the bottom surface of the same or different IC die. Because the wiring to the vias is short, the use of non-TSV vias can still reduce the wiring density of the system-in-package.

圖4A至圖4H說明形成用於電子裝置之系統級封裝的方法之一實例之部分。在該實例中，應用圖2A至圖2E 之實例方法以改良扇出晶圓級封裝。第一IC晶粒405及第二IC晶粒410經形成以包括連接襯墊。連接襯墊(例如，415A、415C)形成於第一IC晶粒之頂表面及底表面兩者上，及第二IC晶粒之頂表面及底表面兩者上(例如，415B、415D)。在圖4A之實例中，IC晶粒各包括TSV 425A、425B。可將IC晶粒置放於模載體上。 4A-4H illustrate portions of one example of a method of forming a system in package for an electronic device. In this example, the application of Figures 2A to 2E is applied. Example methods for improved fan-out wafer level packaging. The first IC die 405 and the second IC die 410 are formed to include a connection pad. A connection pad (e.g., 415A, 415C) is formed on both the top and bottom surfaces of the first IC die and on both the top and bottom surfaces of the second IC die (e.g., 415B, 415D). In the example of FIG. 4A, the IC dies each include TSVs 425A, 425B. The IC die can be placed on a mold carrier.

在圖4B中，模製層420形成於該第一IC晶粒及該第二IC晶粒上以形成子總成。模製層420通常為非傳導的。在一些變化中，模製層420係藉由壓縮模製而形成，且在某些變化中，模製層420包括環氧樹脂。在圖4C中，開口470形成於模製層420中以接觸TSV。非傳導層中之開口可藉由雷射鑽孔或蝕刻而形成。 In FIG. 4B, a mold layer 420 is formed on the first IC die and the second IC die to form a sub-assembly. Molded layer 420 is typically non-conductive. In some variations, the mold layer 420 is formed by compression molding, and in some variations, the mold layer 420 includes epoxy. In FIG. 4C, an opening 470 is formed in the mold layer 420 to contact the TSV. The openings in the non-conductive layer can be formed by laser drilling or etching.

在圖4D中，展示開口填充有導電材料。再分佈層475形成於包括導電互連件445B、450B的模製層420之上。傳導性互連件之至少一部分包括晶粒對晶粒連接。可使用薄膜技術(例如，濺鍍及電鍍)、PCB技術、其他技術或技術之組合形成連接。再分佈層475可包括保護傳導性互連件之鈍化層或鈍化塗層。 In Figure 4D, the display opening is filled with a conductive material. Redistribution layer 475 is formed over molding layer 420 that includes conductive interconnects 445B, 450B. At least a portion of the conductive interconnects include die-to-die connections. The connections can be formed using thin film techniques (eg, sputtering and plating), PCB technology, other techniques, or a combination of techniques. The redistribution layer 475 can include a passivation layer or a passivation coating that protects the conductive interconnects.

在圖4E中，一可選介電層480形成於IC晶粒之底表面上。開口可形成於介電層中以接取IC晶粒之底表面上的連接襯墊。連接襯墊之間的一些傳導性互連件可在形成介電層480之前形成，且接著由介電層480覆蓋。 In Figure 4E, an optional dielectric layer 480 is formed on the bottom surface of the IC die. An opening may be formed in the dielectric layer to interface the connection pads on the bottom surface of the IC die. Some of the conductive interconnects between the connection pads may be formed prior to forming the dielectric layer 480 and then covered by the dielectric layer 480.

在圖4F中，將另一再分佈層482塗覆至可選介電層480上。再分佈層482可用於晶粒對晶粒連接及至用於焊 料凸塊之著陸襯墊的連接。在圖4G中，將焊料阻流劑層455添加至底表面。焊料阻流劑層455包括用於襯墊之開口，以用於設置焊球460。在一些實例中，圖4D至圖4G中展示之製程實例可同時在頂側及底側上執行。 In FIG. 4F, another redistribution layer 482 is applied to the optional dielectric layer 480. Redistribution layer 482 can be used for die-to-die bonding and for soldering The connection of the landing pad of the bump. In Figure 4G, a solder flow inhibitor layer 455 is added to the bottom surface. Solder blocker layer 455 includes openings for the pads for providing solder balls 460. In some examples, the process examples shown in Figures 4D-4G can be performed on both the top and bottom sides.

圖5說明包括系統級封裝的電子裝置之另一實例之部分。當TSV在IC製程中不可用時，此方法可為有用的。如在圖3之實例中，通孔565可形成於模製層520中。在一些變化中，通孔565係藉由形成開口(藉由雷射鑽孔)且接著用導電材料填充開口來製造。在一些變化中，使用印刷電路板材料或矽材料預先製造通孔565。 Figure 5 illustrates a portion of another example of an electronic device including a system in package. This method can be useful when the TSV is not available in the IC process. As in the example of FIG. 3, a via 565 can be formed in the mold layer 520. In some variations, the vias 565 are fabricated by forming openings (by laser drilling) and then filling the openings with a conductive material. In some variations, the vias 565 are pre-fabricated using a printed circuit board material or a tantalum material.

圖6說明包括系統級封裝中之覆晶技術的電子裝置之再一實例之部分。在展示之實例中，兩個IC晶粒605、610經配置(例如，並排)於基體685(例如，覆晶基體)上。當設置IC晶粒時，可使其間之距離d儘可能地小。 Figure 6 illustrates a portion of yet another example of an electronic device including flip chip technology in a system in package. In the illustrated example, two IC dies 605, 610 are configured (eg, side by side) on a substrate 685 (eg, a flip-chip substrate). When the IC die is set, the distance d between them can be made as small as possible.

裝置600包括多個結合層。在第一IC晶粒及第二IC晶粒之底表面與基體685之第一側(在圖6之實例中，頂側)之間存在第一結合層。第一IC晶粒之底表面及第二IC晶粒之底表面各包括一或多個結合襯墊以提供焊料凸塊或銅柱至底表面的附著。可藉由(連同其他者)質量回流製程或藉由熱壓縮結合來使IC晶粒附著至基體685。熱壓縮結合方法可提供對基體685之更準確結合。 Device 600 includes a plurality of bonding layers. A first bonding layer is present between the bottom surface of the first IC die and the second IC die and the first side of the substrate 685 (in the example of FIG. 6, the top side). The bottom surface of the first IC die and the bottom surface of the second IC die each include one or more bond pads to provide adhesion of the solder bumps or copper posts to the bottom surface. The IC die can be attached to the substrate 685 by (along with other) mass reflow processes or by thermal compression bonding. The thermocompression bonding method provides a more accurate bond to the substrate 685.

裝置600包括在橋接組件690與第一IC晶粒605及第二IC晶粒610之頂表面之間的第二結合層。IC晶粒之頂表面包括用於焊料凸塊(例如，微焊球)之著陸襯墊，以用於橋 接組件690之附著。橋接組件690可為主動型或被動型裝置，且可包括矽、PCB、陶瓷或另一IC晶粒，且包括導電互連件佈線。橋接組件在IC晶粒之頂表面處形成第二導電互連件(例如，晶粒對晶粒)之部分。橋接組件690電氣連接至IC晶粒之連接襯墊。傳導性互連件提供自第一IC晶粒之結合襯墊經由橋接組件至第二IC晶粒之結合襯墊之電氣連續性。在展示之實例中，IC晶粒包括TSV 665。在一些實例中，橋接組件690提供IC晶粒之TSV 665之間的電氣連續性。 Device 600 includes a second bonding layer between bridge assembly 690 and a top surface of first IC die 605 and second IC die 610. The top surface of the IC die includes a landing pad for solder bumps (eg, micro solder balls) for use in the bridge Attachment of the assembly 690. The bridge assembly 690 can be an active or passive type device and can include germanium, PCB, ceramic, or another IC die, and includes conductive interconnect wiring. The bridging assembly forms a portion of the second conductive interconnect (eg, die to die) at the top surface of the IC die. The bridge assembly 690 is electrically connected to the connection pads of the IC die. The conductive interconnect provides electrical continuity from the bond pads of the first IC die via the bridge assembly to the bond pads of the second IC die. In the example shown, the IC die includes TSV 665. In some examples, the bridging assembly 690 provides electrical continuity between the TSVs 665 of the IC die.

裝置600包括配置在基體之第二側(在圖6之實例中，底側)上的多個結合襯墊，且可將焊料凸塊配置於結合襯墊之至少一部分上。此提供第三結合層，用於將裝置600結合至系統級PCB(例如，主機板)或陶瓷基體。 Device 600 includes a plurality of bond pads disposed on a second side of the substrate (in the example of FIG. 6, the bottom side), and the solder bumps can be disposed on at least a portion of the bond pads. This provides a third bonding layer for bonding device 600 to a system level PCB (eg, a motherboard) or a ceramic substrate.

在IC晶粒之兩側上提供佈線可允許較細間距之佈線用於IC晶粒之間的連接。在IC晶粒之兩側上的佈線亦可有用於具有大量I/O且將通常具有高接觸襯墊密度之一IC晶粒封裝。至所有襯墊及至焊料凸塊位置之佈線可能困難(當其排他性地配置在IC下方時)，且該佈線可能需要用於多層分佈之代價大的製程，且該製程可導致降低的電氣效能。 Providing wiring on both sides of the IC die allows finer pitch wiring for the connection between the IC dies. Wiring on both sides of the IC die can also be used for IC die packages that have a large amount of I/O and will typically have a high contact pad density. Wiring to all pads and to solder bump locations can be difficult (when it is exclusively placed under the IC), and the routing may require a costly process for multilayer distribution, and the process can result in reduced electrical performance.

圖7說明用於電子裝置的封裝之另一實例。裝置700包括具有頂表面及底表面之IC晶粒705，且頂表面及底表面中之每一者包括多個連接襯墊715A、715C。非傳導材料層720覆蓋頂表面，且實質上覆蓋IC晶粒705之側表面。非傳導材料可包括模製層壓物或重組晶圓。 Figure 7 illustrates another example of a package for an electronic device. Device 700 includes an IC die 705 having a top surface and a bottom surface, and each of the top surface and the bottom surface includes a plurality of connection pads 715A, 715C. The non-conductive material layer 720 covers the top surface and substantially covers the side surfaces of the IC die 705. Non-conductive materials can include molded laminates or reconstituted wafers.

該裝置包括多個通孔。通孔可形成於IC晶粒705及非傳導材料層720中之一或兩者中，且通孔可包括TMV 767及TSV 765中之一或兩者。裝置700包括傳導性互連件，其提供IC晶粒之底表面上的連接襯墊之至少一部分及至通孔之至少一部分的電氣連續性。在展示之實例中，IC晶粒之底表面配置於基體780之第一側上。通孔可自非傳導材料層720之頂表面延伸至基體780。 The device includes a plurality of through holes. The vias may be formed in one or both of the IC die 705 and the non-conductive material layer 720, and the vias may include one or both of the TMV 767 and the TSV 765. Device 700 includes a conductive interconnect that provides electrical continuity to at least a portion of the connection pads on the bottom surface of the IC die and to at least a portion of the vias. In the illustrated example, the bottom surface of the IC die is disposed on a first side of the substrate 780. The vias may extend from the top surface of the non-conductive material layer 720 to the substrate 780.

裝置700包括在非傳導材料層720之頂表面上的傳導性互連件735。在頂表面上之傳導性互連件提供IC晶粒705之頂表面上的連接襯墊之至少一部分及至通孔之至少一部分的電氣連續性。在一些變化中，非傳導材料層720之頂表面包括一再分佈層775。傳導性互連件之至少一部分可包括於再分佈層中。 Device 700 includes a conductive interconnect 735 on a top surface of non-conductive material layer 720. The conductive interconnect on the top surface provides electrical continuity to at least a portion of the bond pads on the top surface of the IC die 705 and to at least a portion of the via. In some variations, the top surface of the layer of non-conductive material 720 includes a redistribution layer 775. At least a portion of the conductive interconnect can be included in the redistribution layer.

基體780之第二側可包括結合襯墊或著陸襯墊(例如，在焊料阻流劑層中)。基體780可包括一再分佈層以提供IC之底表面上的連接襯墊至著陸襯墊及形成於著陸襯墊上之焊料凸塊760的電氣連續性。在一些實例中，底表面上之傳導性互連件提供在通孔之至少一部分與結合襯墊之間的電氣連續性。以此方式，至IC晶粒705之頂表面的連接可在於IC晶粒705下方不添加至佈線之情況下導引至著陸襯墊。 The second side of the base 780 can include a bond pad or landing pad (eg, in a solder flow inhibitor layer). The substrate 780 can include a redistribution layer to provide electrical continuity of the bond pads on the bottom surface of the IC to the landing pads and solder bumps 760 formed on the landing pads. In some examples, the conductive interconnect on the bottom surface provides electrical continuity between at least a portion of the via and the bond pad. In this manner, the connection to the top surface of the IC die 705 can be directed to the landing pad without the underlying IC die 705 being added to the routing.

包括使用具有如本發明中描述之系統級封裝之總成的電子裝置之一實例以展示較高級裝置應用之實例。圖8為根據至少一個實施例的併有一IC裝置封裝之電子系 統800及/或方法之一實例之方塊圖。電子系統800僅為可使用實施例的電子系統之一個實例。電子系統之實例包括(但不限於)個人電腦、平板電腦、行動電話、遊戲裝置、MP3或其他數位音樂播放器等。在此實例中，電子系統800包含一資料處理系統，其包括一系統匯流排802以耦接系統之各種組件。系統匯流排802提供電子系統800之各種組件間的通訊鏈路，且可實施為單一匯流排、實施為匯流排之組合或以任一其他合適方式來實施。 An example of an electronic device using an assembly having a system in package as described in this disclosure is included to demonstrate an example of a higher level device application. 8 is an electronic system with an IC device package in accordance with at least one embodiment. A block diagram of an example of a system 800 and/or method. Electronic system 800 is but one example of an electronic system in which embodiments may be used. Examples of electronic systems include, but are not limited to, personal computers, tablets, mobile phones, gaming devices, MP3 or other digital music players, and the like. In this example, electronic system 800 includes a data processing system that includes a system bus 802 to couple various components of the system. System bus 802 provides communication links between various components of electronic system 800 and can be implemented as a single bus, as a combination of busses, or in any other suitable manner.

電子總成810耦接至系統匯流排802。電子總成810可包括任何電路或電路之組合。在一個實施例中，電子總成810包括可屬於任一類型之處理器812。如本文中所使用，“處理器”意謂任一類型之計算電路，諸如(但不限於)，微處理器、微控制器、複雜指令集計算(CISC)微處理器、精簡指令集計算(RISC)微處理器、超長指令字(VLIW)微處理器、圖形處理器、數位信號處理器(DSP)、多核處理器或任一其他類型之處理器或處理電路。 The electronics assembly 810 is coupled to the system bus 802. The electronics assembly 810 can include any circuit or combination of circuits. In one embodiment, the electronics assembly 810 includes a processor 812 that can be of any type. As used herein, "processor" means any type of computing circuit such as, but not limited to, a microprocessor, a microcontroller, a complex instruction set computing (CISC) microprocessor, a reduced instruction set calculation ( RISC) microprocessor, very long instruction word (VLIW) microprocessor, graphics processor, digital signal processor (DSP), multi-core processor or any other type of processor or processing circuit.

可包括於電子總成810中的其他類型之電路為定製電路、特殊應用積體電路(ASIC)或類似者，諸如，用於在如行動電話、個人數位助理、攜帶型電腦、雙向無線電及類似電子系統之無線裝置中使用的一或多個電路(諸如，通訊電路814)。IC可執行任一其他類型之功能。 Other types of circuits that may be included in the electronics assembly 810 are custom circuits, special application integrated circuits (ASICs), or the like, such as for use in, for example, mobile phones, personal digital assistants, portable computers, two-way radios, and the like. One or more circuits (such as communication circuit 814) used in wireless devices like electronic systems. The IC can perform any other type of function.

電子系統800亦可包括一外部記憶體820，其又可包括適合於特定應用之一或多個記憶體元件，諸如，呈隨機存取記憶體(RAM)之形式的主記憶體822、一或多個硬碟 機824和/或處置抽取式媒體826之一或多個碟機(諸如，光碟(CD)、快閃記憶體卡、數位視訊碟(DVD)及類似者)。 The electronic system 800 can also include an external memory 820, which in turn can include one or more memory elements suitable for a particular application, such as main memory 822 in the form of random access memory (RAM), or Multiple hard drives The machine 824 and/or one or more of the removable media 826 (such as a compact disc (CD), a flash memory card, a digital video disc (DVD), and the like).

電子系統800亦可包括一顯示裝置816、一或多個揚聲器818及一鍵盤及/或控制器830，鍵盤及/或控制器可包括滑鼠、軌跡球、觸控式螢幕、語音辨識裝置或准許系統使用者將資訊輸入至電子系統800內及自電子系統800接收資訊的任一其他裝置。 The electronic system 800 can also include a display device 816, one or more speakers 818, and a keyboard and/or controller 830. The keyboard and/or controller can include a mouse, a trackball, a touch screen, a voice recognition device, or Any other device that allows the system user to enter information into and receive information from electronic system 800.

與習知多晶片封裝方法相比，所描述之裝置、系統及方法可顯著減小用於多晶片封裝之IC之間的互連之佈線密度。為簡單起見，本文中描述之實例包括兩個IC晶粒，但熟習此項技術者將認識到，在閱讀了此描述後，實例可包括兩個以上IC晶粒。所描述之裝置、系統及方法亦可減小用於包括大量I/O連接的單一晶片封裝之佈線密度。 The described devices, systems, and methods can significantly reduce the wiring density of interconnects between ICs for multi-chip packages as compared to conventional multi-die packaging methods. For simplicity, the examples described herein include two IC dies, but those skilled in the art will recognize that the examples may include more than two IC dies after reading this description. The described devices, systems, and methods also reduce the wiring density for a single wafer package that includes a large number of I/O connections.

提供「摘要」以遵守需要將允許讀者確定技術揭示內容之本質及要點的摘要的37 C.F.R.章節1.72(b)。應理解，其將不用以限制或解釋申請專利範圍之範疇或意義。以下申請專利範圍在此併入至實施方式內，其中每一技術方案獨立地作為單獨實施例。 The Abstract is provided to comply with 37 C.F.R. Section 1.72(b) of the abstract that will allow the reader to determine the nature and key points of the technical disclosure. It will be understood that it is not intended to limit or explain the scope or meaning of the scope of the claims. The scope of the following patent application is hereby incorporated by reference in its entirety in its entirety herein in its entirety in its entirety in its entirety in its entirety

Claims (25)

一種電子裝置，其包含：至少一第一積體電路(IC)晶粒及一第二IC晶粒，其中該第一及第二IC晶粒之底表面包括第一多個連接襯墊，且該第一及第二IC晶粒之頂表面包括第二多個連接襯墊；一非傳導材料層，其覆蓋該第一IC及第二IC晶粒之該等頂表面，該非傳導材料層具有接觸該第一及第二IC晶粒之一底表面，以及具有相對該底表面之一頂表面；多個通孔，其包括在該第一IC晶粒中之至少一個通孔延伸至該非傳導材料層之該頂表面，以及在該第二IC晶粒中之至少一個通孔延伸至該非傳導材料層之該頂表面；在該等第一多個連接襯墊之至少一部分與該等多個通孔中之至少一個通孔之間的第一傳導性互連件；以及在該非傳導材料層之該頂表面上的第二傳導性互連件，其提供該等第二多個連接襯墊之至少一部分與該第一IC與第二IC中之該等通孔之間的電氣連續性。 An electronic device comprising: at least one first integrated circuit (IC) die and a second IC die, wherein bottom surfaces of the first and second IC die comprise a first plurality of connection pads, and The top surface of the first and second IC dies includes a second plurality of connection pads; a non-conductive material layer covering the top surfaces of the first IC and the second IC die, the non-conductive material layer having Contacting a bottom surface of one of the first and second IC dies, and having a top surface opposite the bottom surface; a plurality of vias including at least one via in the first IC die extending to the non-conducting The top surface of the material layer, and the at least one via in the second IC die extending to the top surface of the layer of non-conductive material; at least a portion of the first plurality of connection pads and the plurality a first conductive interconnect between the at least one of the through holes; and a second conductive interconnect on the top surface of the layer of non-conductive material that provides the second plurality of connection pads Electrical continuity between at least a portion of the vias in the first IC and the second IC 如請求項1之裝置，其中該等多個通孔中之至少一個通孔包括於該非傳導材料層中且延伸至該非傳導材料層之該頂表面，且該第二傳導性互連件提供包括於該非傳導材料層中之該至少一個通孔的電氣連續性。 The device of claim 1, wherein at least one of the plurality of vias is included in the non-conductive material layer and extends to the top surface of the non-conductive material layer, and the second conductive interconnect is provided Electrical continuity of the at least one via in the layer of non-conductive material. 如請求項1之裝置，其中該非傳導材料層包括在該第一及該第二IC晶粒上的層壓材料之一模製層。 The device of claim 1 wherein the layer of non-conductive material comprises a molded layer of a laminate on the first and second IC dies. 如請求項1之裝置，其中該非傳導材料層包括在該第一及該第二IC晶粒上的重組晶圓之一模製層。 The device of claim 1, wherein the layer of non-conductive material comprises one of the layers of the reconstituted wafer on the first and second IC dies. 如請求項4之裝置，其包括在該第一IC及第二IC晶粒之該頂表面及該底表面中之至少一者上的一再分佈層，其中該第一傳導性互連件之一部分或該第二傳導性互連件之一部分中的至少一者包括於該再分佈層中。 The device of claim 4, comprising a redistribution layer on at least one of the top surface and the bottom surface of the first IC and the second IC die, wherein a portion of the first conductive interconnect Or at least one of the portions of the second conductive interconnect is included in the redistribution layer. 如請求項1之裝置，其包括在該等IC晶粒之一底側上的一或多個著陸襯墊，且該等多個通孔中之至少一個通孔提供在至少一個著陸襯墊與該第二傳導性互連件之間的電氣連續性。 A device as claimed in claim 1, comprising one or more landing pads on one of the bottom sides of the IC dies, and at least one of the plurality of through holes is provided in at least one landing pad Electrical continuity between the second conductive interconnects. 如請求項1之裝置，其中該第二傳導性互連件包括配置於該第一及第二IC晶粒之該等頂表面上的一橋接組件。 The device of claim 1, wherein the second conductive interconnect comprises a bridge assembly disposed on the top surfaces of the first and second IC dies. 如請求項7之裝置，其包括：一基體，其中該第一及第二IC晶粒配置於該基體上；在該第一IC及該第二IC晶粒之該等底表面與該基體之一第一側之間的一第一結合層；在該橋接組件與該第一及第二IC晶粒之該等頂表面之間的一第二結合層；以及配置在該基體之第二側上的多個結合襯墊及配置在該等結合襯墊之至少一部分上的焊料凸塊。 The device of claim 7, comprising: a substrate, wherein the first and second IC dies are disposed on the substrate; and the bottom surfaces of the first IC and the second IC die and the substrate a first bonding layer between the first sides; a second bonding layer between the bridging component and the top surfaces of the first and second IC dies; and a second side disposed on the substrate a plurality of bonding pads thereon and solder bumps disposed on at least a portion of the bonding pads. 如請求項7之裝置，其包括在該第一IC及第二IC晶粒之 該等底表面中之每一者上的一或多個結合襯墊，且該第一傳導性互連件提供該第一IC晶粒之一結合襯墊與該第一IC晶粒之該至少一個通孔之間的電氣連續性及該第二IC晶粒之一結合襯墊與該第二IC晶粒之該至少一個通孔之間的電氣連續性，且該第二傳導性互連件提供該第一IC晶粒之該至少一個通孔與該第二IC晶粒之該至少一個通孔之間的電氣連續性。 The device of claim 7, which is included in the first IC and the second IC die One or more bonding pads on each of the bottom surfaces, and the first conductive interconnects provide one of the first IC die bond pads and the first IC die Electrical continuity between a via and electrical continuity between one of the second IC die bond pads and the at least one via of the second IC die, and the second conductive interconnect Providing electrical continuity between the at least one via of the first IC die and the at least one via of the second IC die. 如請求項1之裝置，其中該第一IC晶粒僅包括數位電路，且該第二IC晶粒包括類比電路。 The device of claim 1, wherein the first IC die comprises only a digital circuit, and the second IC die comprises an analog circuit. 一種用於積體電路晶粒封裝之方法，其包含：形成一第一積體電路(IC)晶粒及一第二IC晶粒以包括在該第一及第二IC晶粒中之每一者之一底表面上的第一多個連接襯墊及在該第一IC及第二IC晶粒中之每一者之頂表面上的第二多個連接襯墊；用一非傳導材料層覆蓋該第一及第二IC晶粒之至少該等頂表面以形成一子總成；在該子總成中形成多個通孔；在該非傳導材料中形成至該等第二多個連接襯墊之至少一部分的開口；以及在該等第一多個連接襯墊之至少一部分之間形成第一傳導性互連件；以及在該非傳導材料層之一頂表面上形成第二傳導性互連件，該第二傳導性互連件提供該等第二多個連接襯墊之至少一部分與該等多個通孔中之至少一個通孔之 間的電氣連續性。 A method for integrated circuit die package, comprising: forming a first integrated circuit (IC) die and a second IC die to be included in each of the first and second IC die a first plurality of connection pads on a bottom surface and a second plurality of connection pads on a top surface of each of the first IC and the second IC die; using a layer of non-conductive material Covering at least the top surfaces of the first and second IC dies to form a subassembly; forming a plurality of vias in the subassembly; forming the second plurality of linings in the non-conductive material An opening of at least a portion of the pad; and forming a first conductive interconnect between at least a portion of the first plurality of bond pads; and forming a second conductive interconnect on a top surface of the non-conductive material layer The second conductive interconnect provides at least a portion of the second plurality of connection pads and at least one of the plurality of through holes Electrical continuity between. 如請求項11之方法，其中形成該至少一個通孔包括在該第一及第二IC晶粒中之一或兩者中形成至少一個矽穿孔(TSV)或在該非傳導材料層中形成該通孔。 The method of claim 11, wherein the forming the at least one via comprises forming at least one turns (TSV) in one or both of the first and second IC dies or forming the pass in the layer of non-conductive material hole. 如請求項11之方法，其中覆蓋該第一IC及第二IC晶粒之至少該等頂表面包括在該第一IC及第二IC晶粒上模製一層壓材料層。 The method of claim 11, wherein covering at least the top surfaces of the first IC and the second IC die comprises molding a laminate layer on the first IC and the second IC die. 如請求項11之方法，其中覆蓋該第一及第二IC晶粒之至少該等頂表面包括在該第一及第二IC晶粒上模製一重組晶圓層。 The method of claim 11, wherein covering at least the top surfaces of the first and second IC dies comprises molding a reconstituted wafer layer on the first and second IC dies. 如請求項14之方法，其包括在一再分佈層中形成該第一傳導性互連件之一部分或該第二傳導性互連件之一部分中的至少一者及在該子總成之一頂側或一底側中之至少一者上配置該再分佈層。 The method of claim 14, comprising forming at least one of a portion of the first conductive interconnect or a portion of the second conductive interconnect in a redistribution layer and at a top of the sub-assembly The redistribution layer is disposed on at least one of a side or a bottom side. 如請求項11之方法，其中形成電氣互連包括在用該非傳導材料覆蓋該第一IC及第二IC晶粒之該等頂表面之前在該第一IC及第二IC晶粒之該等頂表面上配置一橋接組件，其中該橋接組件包括該第二傳導性互連件之至少一部分。 The method of claim 11, wherein forming the electrical interconnect includes the top of the first IC and the second IC die before covering the top surfaces of the first IC and the second IC die with the non-conductive material A bridge assembly is disposed on the surface, wherein the bridge assembly includes at least a portion of the second conductive interconnect. 如請求項16之方法，其包括：使用一第一結合層將該第一及第二IC晶粒之該等底表面設置於一基體之一第一側，其中該第一結合層包括焊料凸塊或銅柱中之至少一者；以及將一第二結合層配置於該基體之一第二側上，其中 該第二層包括焊料凸塊，且其中該基體包括第三傳導性互連件以提供該第一結合層之至少一部分與該第二結合層之間的電氣連續性。 The method of claim 16, comprising: disposing the bottom surfaces of the first and second IC dies on a first side of a substrate using a first bonding layer, wherein the first bonding layer comprises a solder bump At least one of a block or a copper post; and disposing a second bonding layer on a second side of the substrate, wherein The second layer includes a solder bump, and wherein the substrate includes a third conductive interconnect to provide electrical continuity between at least a portion of the first bonding layer and the second bonding layer. 如請求項11之方法，其中該第一傳導性互連件包括提供該第一IC晶粒之該底表面上的一連接襯墊與該等多個通孔中之至少一個通孔之間的電氣連續性，且形成第二傳導性互連件包括提供該至少一個通孔與該第二IC晶粒之該頂表面上的一連接襯墊之間的電氣連續性。 The method of claim 11, wherein the first conductive interconnect comprises between a connection pad on the bottom surface of the first IC die and at least one of the plurality of vias Electrical continuity, and forming the second conductive interconnect includes providing electrical continuity between the at least one via and a connection pad on the top surface of the second IC die. 一種電子裝置，其包含：一IC晶粒，其包括一頂表面及一底表面，其中該底表面包括第一多個連接襯墊，且該頂表面包括第二多個連接襯墊；一非傳導材料層，其覆蓋該頂表面且實質上覆蓋該IC晶粒之側表面；多個通孔；第一傳導性互連件，其提供該等第一多個連接襯墊之至少一部分及該等多個通孔中之至少一個通孔的電氣連續性；以及在該非傳導材料層之一頂表面上的第二傳導性互連件，其提供該等第二多個連接襯墊之至少一部分及對該等多個通孔中之至少一個通孔的電氣連續性。 An electronic device comprising: an IC die comprising a top surface and a bottom surface, wherein the bottom surface comprises a first plurality of connection pads, and the top surface comprises a second plurality of connection pads; a layer of conductive material covering the top surface and substantially covering a side surface of the IC die; a plurality of vias; a first conductive interconnect providing at least a portion of the first plurality of connection pads and the Electrical continuity of at least one of the plurality of through holes; and a second conductive interconnect on a top surface of the non-conductive material layer providing at least a portion of the second plurality of connection pads And electrical continuity of at least one of the plurality of vias. 如請求項19之裝置，其中該等多個通孔包括形成於該非傳導材料層中且延伸至該非傳導材料層之一頂表面的至少一個模穿孔(TMV)，且包括形成於該IC晶粒中之至 少一個矽穿孔(TSV)，該矽穿孔提供該等第一多個連接襯墊中之一連接襯墊與該等第二多個連接襯墊中之一連接襯墊之間的電氣連續性，且該第二傳導性互連件自該非傳導材料層之該頂表面延伸至該TSV。 The device of claim 19, wherein the plurality of vias comprise at least one die via (TMV) formed in the non-conductive material layer and extending to a top surface of the non-conductive material layer, and comprising the IC die formed Medium to One less perforation (TSV) that provides electrical continuity between one of the first plurality of connection pads and one of the second plurality of connection pads And the second conductive interconnect extends from the top surface of the layer of non-conductive material to the TSV. 如請求項19之裝置，其包括一基體，其中該IC晶粒之該底表面配置於該基體之一第一側上，且其中該裝置包括自該非傳導材料層之一頂表面延伸至該基體之多個通孔。 The device of claim 19, comprising a substrate, wherein the bottom surface of the IC die is disposed on a first side of the substrate, and wherein the device comprises extending from a top surface of the non-conductive material layer to the substrate Multiple through holes. 如請求項21之裝置，其中該基體之第二側包括結合襯墊，且其中該裝置包括在該等通孔之至少一部分與該等結合襯墊之間的傳導性互連件。 The device of claim 21, wherein the second side of the substrate comprises a bond pad, and wherein the device comprises a conductive interconnect between at least a portion of the vias and the bond pads. 如請求項19之裝置，其包括配置於該非傳導材料層之頂表面上的一再分佈層，其中該第二傳導性互連件之至少一部分包括於該再分佈層中。 The device of claim 19, comprising a redistribution layer disposed on a top surface of the layer of non-conductive material, wherein at least a portion of the second conductive interconnect is included in the redistribution layer. 如請求項19之裝置，其中該非傳導層包括一模製層壓材料層或重組晶圓之一模製層中的至少一者。 The device of claim 19, wherein the non-conductive layer comprises at least one of a molded laminate layer or a molded layer of a reconstituted wafer. 如請求項19之裝置，其中該IC晶粒包括一處理器。 The device of claim 19, wherein the IC die comprises a processor.
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